Department of Electronic Engineering

FPGA LAB 2&3

(LAB REPORT)

SUBMITTED BY:

WARDAH BATOOL
20-ENC-07

SUBMITTED TO:

SIR TAHIR KHAN

 LAB N0 2

TASK NO1:FULLADDER
module fulladder (
input [3:0] a,
input [3:0] b,
input c_in,
output reg c_out,
output reg [3:0] sum);
always @(a or b or c_in)
begin
{c_out, sum} = a + b + c_in;
end
endmodule

TESTBENCH:
module tb_fulladd;
reg [3:0] a, b;
reg c_in;
wire [3:0] sum;
wire c_out;
fulladder uut (
.a(a),
.b(b),
.c_in(c_in),
.sum(sum),
.c_out(c_out)
);

initial begin
a = 4'b1101;
b = 4'b1010;
c_in = 1'b0;
#10 a = 4'b0011; b = 4'b0101; c_in = 1'b1;
#10 a = 4'b1111; b = 4'b0001; c_in = 1'b0;
#10 a = 4'b0100; b = 4'b0010; c_in = 1'b1;
#10 $finish;
end
endmodule
SIMULATION:

TRUTH TABLE:

INPUTS OUTPUTS
A B Cin SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

TASK NO 2:4TO1 MUX

module mux2to1 (
input A,
input B,
input S,
output Y);
assign Y = (S == 1'b0) ? A : B;
endmodule
module mux4to1 (
input [3:0] A, B, C, D, // Data inputs
 input [1:0] S, // Select inputs
output Y // Mux output);

wire Y1, Y2, Y3;

mux2to1 Mux1 (.A(A), .B(B), .S(S[0]), .Y(Y1));
mux2to1 Mux2 (.A(C), .B(D), .S(S[0]), .Y(Y2));
mux2to1 Mux3 (.A(Y1), .B(Y2), .S(S[1]), .Y(Y3));
assign Y = Y3;
endmodule

TESTBENCH:
module mux4to1_tb;
reg [3:0] A, B, C, D;
reg [1:0] S;
wire Y;
mux4to1 uut (
.A(A),
.B(B),
.C(C),
.D(D),
.S(S),
.Y(Y) );
initial begin
A = 4'b0101;
B = 4'b1010;
C = 4'b1100;
D = 4'b0011;
S = 2'b00;
#10 S = 2'b01; // Select input 1
#10 S = 2'b10; // Select input 2
#10 S = 2'b11; // Select input 3
$finish;
end
endmodule

CIRCUIT DIAGRAM:
SIMULATION:
 LAB N0 3

QUESTION NO 1: DECODER
PART A: WITH DELAYS
module decode( input A0, A00, A1, output D0,D1,D2,D3);
assign #5 A00=~A0;
assign #6 D0= A00 & ~A1;
assign D1= A0 & ~A1;
assign D2= A00 & A1;
assign D3= A0 & A1;
endmodule

TEST BENCH:
module mydec_tb();
reg A0,A00, A1;
wire D0,D1,D2,D3;
decode uu(.A0(A0), .A00(A00), .A1(A1), .D0(D0), .D1(D1), .D2(D2), .D3(D3));
initial
begin
A0=1'b0;
A00 =1'b0;
A1=1'b0;
#5
A0=1'b0;
A00 =1'b1;
A1=1'b1;
#5
A0=1'b1;
A00 =1'b0;
A1=1'b0;
#5
A0=1'b1;
A00 =1'b0;
A1=1'b1;
#5
$stop;
end
endmodule
SIMULATION:

PART B: WITHOUT DELAYS

module decode( input A0, A1, output D0,D1,D2,D3);
assign D0= ~A0 & ~A1;
assign D1= A0 & ~A1;
assign D2= ~A0 & A1;
assign D3= A0 & A1;
endmodule

TEST BENCH:
`timescale 1ns / 1ps
/////////////////////
module dectb();
reg A0, A1;
wire D0,D1,D2,D3;
decode uu(.A0(A0), .A1(A1), .D0(D0), .D1(D1), .D2(D2), .D3(D3));
initial
begin
A0=1'b0;
A1=1'b0;
#5
A0=1'b0;
A1=1'b1;
#5
A0=1'b1;
A1=1'b0;
#5
A0=1'b1;
A1=1'b1;
#5
$stop;
end
endmodule

SIMULATION:

QUESTION NO 2 . 8 to 1 MUX:
module mymux(input [2:0] sel, [7:0] data, output out);
assign out = (sel == 3'b000) ? data[0]:
(sel == 3'b001) ? data[1]:
(sel == 3'b010) ? data[2] :
(sel == 3'b011) ? data[3] :
(sel == 3'b100) ? data[4] :
(sel == 3'b101) ? data[5] :
(sel == 3'b110) ? data[6] :
(sel == 3'b111) ? data[7] :
8'b00000000;
Endmodule

TEST BENCH:
module mux_tb();
// Inputs
reg [7:0] data; // 8 input data lines
reg [2:0] sel; // 3-bit select input
// Output
wire out; // Output
mymux mux(.sel(sel), .data(data), .out(out));
initial
begin
sel = 3'b000;
data = 8'b00000001;
#10;
data = 8'b00000010;
sel = 3'b001;
#10;
data= 8'b00000100;
sel = 3'b010;
#10;
data = 8'b00001000;
sel = 3'b011;
#10;
data = 8'b00010000;
sel = 3'b100;
#10;
data = 8'b00100000;
sel = 3'b101;
#10;
data = 8'b01000000;
sel = 3'b110;
#10;
data = 8'b10000000;
sel = 3'b111;
//out= 1'b1;
#10;
$stop;
end
endmodule

SIMULATION:
TRUTH TABLE:

S2 S1 S0 D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
CIRCUIT DIAGRAM:

QUESTION 3: ADDER
module myadd(input [1:0] a,b,cin, output sum, carry);
wire c,c1,s;
halfadder ha0(a,b,s,c);
halfadder ha1(cin,s,sum,c1);
assign carry = c | c1 ;
endmodule
module halfadder(input [1:0] a,b, output s, c);
assign s = a ^ b;
assign c = a & b;
endmodule

TEST BENCH:
module myadd_tb();
reg a,b,cin;
wire sum,carry;
myadd uut(a,b,cin,sum,carry);
initial
begin
a = 0; b = 0; cin = 0;
#10
a = 0; b = 0; cin = 1;
#10
a = 3; b = 1; cin = 0;
#10
a = 0; b = 3; cin = 1;
#10
a = 1; b = 0; cin = 0;
#10
a = 1; b = 0; cin = 1;
#10
a = 1; b = 1; cin = 0;
#10
a = 1; b = 1; cin = 1;
#10
$stop;
end
endmodule

SIMULATION:

QUESTION NO 4: COMPARATOR
module mycomp( A,B, R, S,T);
input [3:0] A,B;
output R,S,T;
assign R = (A==B) ? 1 : 0;
assign S = (A>B) ? 1 : 0;
assign T = (A<B) ? 1 : 0;
endmodule

TEST BENCH:
module comptb();
reg [3:0] A,B;
wire R,S,T;
comp2 cc(.A(A), .B(B), .R(R), .S(S), .T(T));
initial
begin
A=4'b0000;
B= 4'b0000;
#10
A=4'b0010;
B= 4'b0001;
#10
A=4'b1111;
B= 4'b1010;
#10
A=4'b1001;
B= 4'b1110;
#10
A=4'b0001;
B= 4'b0101;
#10
A=4'b1000;
B= 4'b1000;
#10
$stop;
end
endmodule

SIMULATION:
CIRCUIT DIAGRAM:

TRUTH TABLE:

A1 A0 B1 B0 EQ A>B A<B
0 0 0 0 1 0 0
0 0 0 1 0 0 1
0 0 1 0 0 1 0
0 0 1 1 0 0 1
0 1 0 0 0 1 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 0 1 0
1 0 0 1 0 1 0
1 0 1 0 0 1 0
1 0 1 1 0 1 0
1 1 0 0 0 1 0
1 1 0 1 0 1 0
1 1 1 0 0 1 0
1 1 1 1 1 0 0
QUESTION NO 5:SUBTRACTOR
module sub4bit(input [3:0] A, // 2-bit input A
input [3:0] B, // 2-bit input B
output [3:0] Y // 2-bit output Y);
assign Y = A - B;
endmodule

TEST BENCH:
`timescale 1ns / 1ps
Module mysub_tb();
reg [3:0] A,B;
wire [3:0] Y;
mysub u(.A(A), .B(B), .Y(Y));
initial
begin
A=4'b1111; B=4'b1010;
#10
A=4'b1000; B=4'b0101;
#10
A=4'b0111; B=4'b0110;
#10
A=4'b1011; B=4'b0000;
#10
$stop;
end
endmodule

SIMULATION:
TRUTH TABLE:

A1 A0 B1 B0 D1 D0
0 0 0 0 0 0
0 0 0 1 1 1
0 0 1 0 1 1
0 0 1 1 0 0
0 1 0 0 0 1
0 1 0 1 0 0
0 1 1 0 1 1
0 1 1 1 1 0
1 0 0 0 1 0
1 0 0 1 0 1
1 0 1 0 0 0
1 0 1 1 1 1
1 1 0 0 0 0
1 1 0 1 0 1
1 1 1 0 0 0
1 1 1 1 1 1
CIRCUIT DIAGRAM:

QUESTION NO 6:
module labckt(input A,B,C,D, output y) ;
// DATA FLOW LEVEL MODELLING
assign y = (~A & ~B & ~C & ~D) |(~A&~B&C&D)|(~A&B&C&~D)|(A&~B&~C&D)|(A&B&~C&~D)|
(A&B&C&D);
endmodule

TEST BENCH:
module tb();

reg A,B,C,D;
wire y;

labckt u(.A(A), .B(B), .C(C), .D(D), .y(y));

initial
begin
A=1'b0;
B=1'b0;
C=1'b0;
D=1'b0;

#10
A=1'b0;
B=1'b0;
C=1'b1;
D=1'b1;
#10
A=1'b0;
B=1'b1;
C=1'b1;
D=1'b0;
#10
A=1'b1;
B=1'b0;
C=1'b0;
D=1'b1;
#10
A=1'b1;
B=1'b1;
C=1'b0;
D=1'b0;
#10
A=1'b1;
B=1'b1;
C=1'b0;
D=1'b1;
#10
A=1'b1;
B=1'b1;
C=1'b1;
D=1'b1;
#10
$stop;

end
endmodule

SIMULATION: