CoreUSXGMII HB
CoreUSXGMII HB
CoreUSXGMII HB
Handbook
CoreUSXGMII v2.1
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1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Revision 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Revision 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2.1 Features Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2.2 Features Not Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.3 Core Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.4 Supported Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.5 Utilization and Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 XGMII Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1.1 XGMII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2 Data Rate Adaptation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2.1 Tx Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2.2 Rx Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.3 Auto-negotiation Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.4 BaseR_PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.5 Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.6 Transceiver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.7 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.7.1 Core Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.7.2 System-side (MAC) Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.7.3 Transceiver Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1 XGMII Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.2 Transceiver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7 Tool Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.1 License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.1.1 Obfuscated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.1.2 Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.2 SmartDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.3 Configuring CoreUSXGMII in SmartDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.4 Simulation Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.5 Synthesis in Libero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.6 Place-and-Route in Libero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8 Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1 Revision History
The revision history describes the changes that were implemented in the document. The changes are
listed by revision, starting with the most current publication.
2 Introduction
2.1 Overview
The CoreUSXGMII (Universal Serial Media Independent Interface) IP is used to carry single network port
over a single SERDES between the MAC and the PHY for Multi-Gigabit technology at 1G/ 2.5G/ 5G/ 10G
data rate.
2.2 Features
The following topics describes the various features of CoreUSXGMII.
Combinatorial
Device Family Sequential (DFF) (4-LUT) Total % RAM 1K20 CORE_TX_CLK CORE_RX_CLK
PolarFire 6065 4165 10230 2.12 12 180 245
(MPF500T)
Note: The data in this table is achieved using typical synthesis and layout settings. Frequency (MHz) was set to
175 and the speed grade was -1.
Note: FPGA resources and performance data for the PolarFire SoC family is similar to PolarFire family.
3 Functional Description
BaseR-to-GBX
AN Block To / From Transceiver
(configured in PCS 64b66b mode)
From / to XGMII
Note: Scaling factor is /10, /4, /2, /1 for 1G, 2.5G, 5G and 10G respectively.
Note: The clock description is provided in the Clocking, page 5 section.
After the EOP is transmitted, the remaining 1/ 3/ 9 bytes are Idles. This is compatible with the checks of
the Tx PCS state machine that back to back EOPs are not allowed.
Each idle byte is replicated 2/ 4/ 10 times. This ensures that the data rate in case of 2/ 4/ 10 does not
exceed the frame rate.
All other sequence ordered sets and control sets are replicated 2/ 4/ 10 times for 5G/ 2.5G/ 1G
respectively.
3.2.2 Rx Path
In the Rx path, the received SOP samples every 2nd, 4th, and 10th words to form RX data for 5G/ 2.5G/
1G respectively. This is then passed to Receive XGMII control block and to the MAC subsequently.
The Data rate adaptation block works on CORE_TX_CLK and CORE_RX_CLK in the transmit and
receive path respectively.
TXC [3:0] Lane0 [31:24] Lane1 [23:16] Lane2 [15:8] Lane3 [7:0]
0x1 Character Control Code = 0x9C Config [15:8] Config [7:0] Opcode for auto-neg = 0x03 (Cisco
Specific)
3.4 BaseR_PHY
The BaseR_PHY converts the XGMII signaling to gearbox signaling and interfaces with Microchip's
transceiver. Refer to Figure 2 and Figure 3 for the timing information.
The BaseR_PHY block works on CORE_TX_CLK/ CORE_RX_CLK and XCVR_TX_CK/
XCVR_RX_CLK in the transmit and receive path respectively. It contains the CDC FIFO to synchronize
the signals for the clock rate change between the transceiver and the IP BaseR_PHY block.
3.7 Clocking
Refer to Figure 1 for information on the clocking scheme used in the IP.
Table 3 • IP Clocking
The following registers are accessed through the APB slave interface.
The register block contains the management registers specified in IEEE 802.3, Clause 37 – Control,
Status, Auto Negotiation Advertisement, and Link Partner Ability.
5 Interface
5.1 Parameters
There are no parameters required for the CoreUSXGMII IP.
5.2 Ports
The following table describes the input/output ports:
6 Timing Diagrams
XCVR_TX_CLK
32 cycles 33rd
O_PMA49_TX_SOS
O_PMA49_TX_HDR [3:0] 01 10 01 10 01
O_PMA49_TX_DATA [63:0] a b c d e f g h i j p aa
dead
cycle
The following timing diagram shows the behavior of RXD and RXC frame reception:
Figure 3 • 64B66B Receive Sequence for the 64-Bit Interface
XCVR_RX_CLK
I_PMA49_RX_HDR [3:0] 01 10 01 10 01
I_PMA49_RX_DATA [63:0] a b c d e f g h i j p aa
dead
cycle
I_PMA49_RX_HDR_VAL
I_PMA49_RX_DATA_VAL
7 Tool Flow
7.1 License
CoreUSXGMII is licensed with obfuscated RTL. Evaluation is free with Libero SoC software.
7.1.1 Obfuscated
Complete RTL code is provided for the core, enabling the core to be instantiated with SmartDesign.
Simulation, Synthesis, and Layout can be performed with Libero software. The RTL code for the core is
obfuscated using the IP encryption (encryptP1735.pl) solution.
7.1.2 Evaluation
Complete RTL code is provided for the core, enabling the core to be instantiated with SmartDesign.
Simulation, Synthesis, and Layout can be performed with Libero software. The RTL code for the core is
obfuscated using the IP encryption (encryptP1735.pl) solution and has a self-destruct feature which will
stop functioning after 4 hours at 10 Gbps data rate using 64bit at 156.25 MHz.
7.2 SmartDesign
CoreUSXGMII is pre-installed in the SmartDesign IP Deployment design environment. Figure 4 shows
an example of instantiated CoreUSXGMII IP. The core can be configured using the configuration window
in the SmartDesign, as shown in Figure 5.
To know how to create SmartDesign project using the IP cores, refer to Libero SoC documents page and
use the latest SmartDesign user guide.
Figure 4 • SmartDesign CoreUSXGMII Instance View
8 Testbench
There is no User Test bench provided with this release of the IP.
9 System Integration
XCVR_TX_CLK CLKS_FROM_TXPLL
50MHz XTAL I_SYS_CLK
CORE_TX_CLK 161.133MHz
CCC 156.25MHz CDR_REFCLK
I_CORE_TX_CLK
SYS_TX_CLK
SYSCLK_IN
PF_XVCR
Packet generator CORE10GMAC COREUSXGMII
checker 161.133MHz
SYS_RX_CLK
I_CORE_RX _CLK
CORE_RX_CLK
XCVR_RX_CLK
156.25MHz
CCC
156.25÷N
User_RST EXT_RST_N
PLL_LOCK CLK
Reset_PF
MiV
FABRIC_RESET_N RESETN
INIT_DONE AQR107 PHY RSTN
DEVICE_INIT_DONE
EXT_RESETN
PF_INIT_MONITOR
Note: N indicates the scaling factor and depends on the speed data rate. The scaling factor N = 10, 4, 2, and 1
for 1G, 2.5G, 5G and 10G respectively. Refer to Table 7, page 20.
N (Scaling
Speed Data Rate Factor)
10G 1
5G 2
2.5G 4
1G 10