E1121 Digital LOGIC (a)

Fall 2020

Lecture 4
 Boolean Algebra
01
Agenda
Logic Gates
02

Logic Families
03
Boolean Algebra
 Boolean Agenda
Algebra Style
❑ When we learned numbers like 1, 2, 3, we also then learned how to add,
multiply, etc. with them. Boolean Algebra covers operations that we can do
with 0’s and 1’s. Computers do these operations ALL THE TIME and they
are basic building blocks of computation inside your computer program.

❑ A Boolean algebra is a system consisting of a set of elements, binary

operators (+,’ and ● ), parentheses to indicate the nested order of evaluation
and an = operator to perform assignment of an expression. The algebra
must further obey six fundamental postulates, or axioms.
 Boolean Agenda
Operators Style
• A binary operator defined on a set S of elements is a rule that assigns a unique element from S to
each pair of elements from S.
– an example, consider the relation a *b = c. * can be considered as a binary operator if it defines a rule to c
ompute c from the pair (a, b) and if a, b, c ∈ S. However, * is not a binary operator if a, b ∈ S, and if c ∉ S.

• There are three basic operators in Boolean Algebra which are called logical operators or Boolean
operators.

OR - logical addition
Binary
AND – logical multiplication

NOT – Logical negation Unary

• The Boolean operators are used to combine Boolean variables and Boolean constants to form
Boolean Expressions.
 Basic Boolean
Agendaoperations
Style
 There are three basic operations for logical values.
Operation: OR (sum) of AND (product) NOT(complement)
two inputs of two inputs on one input
Expression: x+y xy, or x•y x’ or 𝑥ҧ

Output: =1 if either input =1 if all input are =1 if input = 0

equal to 1 equal to 1 =0 if input =1

Truth table: x y x+y x y xy x x’

0 0 0 0 0 0 0 1
▪Note: The statement: 0 1 1 0 1 0 1 0
1 + 1 = 2 (read “one plus one
equals two”) 1 0 1 1 0 0
is not the same as 1 1 1 1 1 1
1 + 1 = 1 (read “1 or 1 equals 1”).
Logic Gates
 Logic Gates
Agenda Style
❑ There are three basic logical operations from which it is possible
to derive all other Boolean functions regardless of how complex.

❑ These operations are implemented by three basic gates: AND, OR,

and NOT.

❑ Four other derived gates NAND, NOR, XOR, and XNOR are also
used to construct logic functions.
 LOGIC GATES (cont.)
Agenda Style
❑ A logic gate takes one or more inputs and only one output is produced.

❑ Logic gates are the building blocks that build most of the digital systems.

❑ It must be understood that there are two different voltages levels that used

to represent the logic `1 ` and logic `0’, which are fed as input to the gates.

❑ Moreover the output, which has the logic `1’ or `0’ values, is represented

by two different voltage levels.

 LogicIn Gates(cont.)
Agenda Style
x out
Inverter (NOT)
A x x 0 1 NAND:
B 1 0

x y out x y out
AND
x
A x•y 0 0 0 NOR:x 0 0 1
y NAND y x•y 0 1 1
B 0 1 0
1 0 0 1 0 1
1 1 1 1 1 0
x y out x y out
OR
x x+y 0 0 0 x
y NOR y x+y 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 1 1 1 0
 Logic Gates(cont.)
Agenda Style
XOR (Exclusive-OR) x y XOR
0 0 0
x xÅ y 0 1 1
y xy+xy 1 0 1
1 1 0

x y XNOR
XNOR (Exclusive-NOR) (Equivalence) 0 0 1
0 1 0
1 0 0
1 1 1
 Timing Diagram
Agenda Style
• Timing Diagram is a graph that accurately depicts the relation of
two or more waveforms on a time basis with respect to each other.

• t1: A =1 , B=1 →x=1

• t2: A =0 , B=1 →x=0

• t3: A =1 , B=1 →x=1

• t4: A =1 , B=0 →x=0

• t5: A =0 , B=0 →x=0

Timing Behavior
Agenda Style
 Universal Gates
Agenda Style
❑ The NAND and NOR gates can be easily used to implement all
the basic logic gates like AND,OR and NOT.

❑ NAND and NOR gates less expensive and easier to design which
makes them more popular.

❑ They are referred as Universal gates because of their versatility.

Universality of NANDStyle
Agenda Gates
Universality of NOR Style
Agenda Gates
Combinational
Agenda Gates
Style
Name Symbol Function Truth Table
A B X
A X=A•B 0 0 0
AND X or 0 1
1 0
0
0
B X = AB
1 1 1
A B X
A
OR X X=A+B 0 0
0 1
0
1
B 1 0 1
1A1 1
X
NOT A X X = A’ 0
1
1
0
A X
Buffer A X X=A 0 0
1 1
A B X
A 0 0 1
NAND X X = (AB)’ 0 1
1 0
1
1
B 1 1 0
A B X
A 0 0 1
NOR X X = (A + B)’ 0 1 0
B 1 0 0
1 1 0
A B X
A X=AÅB
XOR X or
0 0 0
Exclusive OR 0 1 1
B X = A’B + AB’ 1 0 1
1 1 0
A B X
XNOR A X = (A Å B)’ 0 0 1
Exclusive NOR X or 0 1 0
or Equivalence B X = A’B’+ AB 1 0 0
1 1 1
 Applications
Agenda Style
1- Application of using AND Gate 2- Application of using OR Gate
 ExerciseAgenda Style
• What the type of gate that can replace the box?
• Explain your choice?

?
 Logic Function
Agenda Implementation
Style
 Using Switches Switches in parallel => OR
 For inputs:
◼ logic 1 is switch closed
◼ logic 0 is switch open

Switches in series => AND

 For outputs:
◼ logic 1 is light on
◼ logic 0 is light off.

 NOT uses a switch such that: Normally-closed switch => NOT

◼ logic 1 is switch open C
◼ logic 0 is switch closed
 Boolean Agenda
Expressions
Style
• We can use these basic operations to form more complex expressions:

f(x,y,z) = (x + y’)z + x

• Some terminology and notation:

– f is the name of the function.
– (x,y,z) are the input variables, each representing 1 or 0. Listing the inputs is optional, but
sometimes helpful.
– A literal is any occurrence of an input variable or its complement. The function above has
four literals: x, y’, z, and x.
• Precedencies are important, but not too difficult.
– NOT has the highest precedence, followed by AND, and then OR.
– Fully parenthesized, the function above would be kind of messy:

f(x,y,z) = (((x +(y’))z) + x’)

Logic Function
Agenda Implementation
Style

F = A’ + B•C’ + A’•B’

A F

B
 Agenda
Logic Function Style
Implementation
• Example: Logic Using Switches
A

• Light is on (L = 1) for
L(A, B, C, D) = A ( BCത + D)
and off (L = 0), otherwise.
• Useful model for relay circuits and for CMOS gate circuits,
the foundation of current digital logic technology
Logic Families
 Logic Families
Agenda Style
 Logic families classified based on manufacturing technologies to:
 “Diode Logic”(DL)
 “Resistor Transistor Logic”(RTL)

 “Diode Transistor Logic”(DTL)

 “High threshold Logic”(HTL)

 “Transistor Transistor Logic”(TTL)

 “Integrated Injection Logic”(I2L)

 “Emitter coupled logic”(ECL)

 “Metal Oxide Semiconductor Logic”(MOS)

 “Complementary Metal Oxide Semiconductor Logic”( CMOS)

 Types ofAgenda
integrated circuits
Style (IC)
❑ The various sizes of IC chips integration are usually specified in terms of the number
of logic gates in a single IC or package. They are categorized to one of the following
1. Small-scale integration (SSI) device contains less than 10 gates in a single package,
such as logic gates.
2. Medium scale integration (MSI) device contains 10 -100 gates in a single package,
such as adders.
3. Large-scale integration (LSI) device contains 100 to 10000 gates in a single package,
such as processors.
4. Very large-scale integration (VLSI) device contains more than 10000 gates in a singl
e package, such as complex microprocessors chips.
 Some characteristics
Agenda Style of the TTL family

• Power dissipation: It is the amount of power delivered from the power

supply which required by the gate . It is equal to 20 mw per gate.
𝐼𝐶𝐶𝐻 +𝐼𝐶𝐶𝐿
– 𝑃𝑑 = 𝑉𝑐𝑐 ( )
2

– 𝑉𝑐𝑐 : Dc Supply Voltage, 𝐼𝐶𝐶𝐻 , 𝐼𝐶𝐶𝐿 : the supply current for the high and LOW
output respectively

• Propagation/time delay 𝒕𝒑 : it is the amount of delay between applying

the input and the response of the output of the gate. Generally, the
propagation delay is between 0.5 and 50 nanoseconds.
 Some characteristics
Agenda Style of the TTL family (Cont.)

• Fan-out: it is the maximum number of inputs that can be connected to the

output of the gate without affecting its normal operation.

𝐼𝑂𝐿
– fan-out = 𝐼𝐼𝐿

– 𝐼𝑂𝐿 : LOW Level Output Current , 𝐼𝐼𝐿 : LOW Level Input Current
• Example: Determine the number of units loads that 74LS00 (NAND gate)
can derive if 𝐼𝑂𝐿 = 8.0 mA and 𝐼𝐼𝐿 = 0.4 mA
– Fan-out = 8 / 0.4 = 20
Thank you