SSRG International Journal of Electronics and Communication Engineering ( SSRG – IJECE ) – Volume 3 Issue 3–March

2016

A Survey on Different Multiplier

Techniques
Y.RamaLakshmanna#1, G.V.S.Padma Rao#2, N . Udaya Kumar#3, K. Bala Sindhuri#4
#1
PG Student, SRKR Engineering College, Bhimavaram, India.
#2
Professor, SRKR Engineering College, Bhimavaram, India.
#3
Professor, SRKR Engineering College, Bhimavaram, India.
#4
Assistant Professor, SRKR Engineering College, Bhimavaram, India

Abstract – Section II deals with literature survey. In this section an

A multiplier has a significant role in introduction to serial multiplier, Shift and Add
various arithmetic operations in digital processing multiplier, Array multiplier, Booth Multiplier, Constant
applications which include digital filtering, digital coefficient multiplier, Vedic multiplier and Wallace
communications and spectral analysis. With the tree multiplier is presented. A conclusion is given in
advancement in semiconductor technology, chip section III.
density and operating frequency are increasing, so
the power consumption in VLSI circuits has become a II. LITERATURE SURVEY
major problem of consideration. Rapidly growing
technology has raised demands for fast and efficient A. Serial Multiplier
real time digital signal processing applications. A The serial multiplier is used where the area and
large number of multiplier designs have been power is most important and delay can be tolerated. In
developed to enhance their speed. This paper this one adder is used to add partial products. The
presents a study on some important multiplier multiplier and multiplicand inputs are arranged such
techniques. that they synchronized with the circuit behavior.
Depending on the length of the multiplier and
Keywords: Multiplier, Vedic Mathematics; Wallace multiplicand, the inputs can be presented at different
Tree rates. Here two clock signals are used. One for data and
I. INTRODUCTION another for reset operation. The main drawback of
In the design of systems using digital signal serial multiplier algorithm is not suitable for large
processing and other applications multiplier is an values of multiplier and multiplicand.
important basic building block. Many researchers are
continuously trying to design multiplier with high B. Shift and Add Multiplier
speed, low power consumption, regular structure, For standard add shift algorithm, every
such that it occupies less area for compact VLSI multiplier bit gives one multiple of the multiplicand
implementation. which is added to partial products. A more number of
multiplicands are added, if multiplier is very large. In
Many algorithms are proposed in the past to this situation the number of additions to be performed
perform multiplication process. Every algorithm determines the delay of multipliers. The performance
offerings its own advantages and having tradeoff will get better, if the number of additions are minimum.
between themselves by means of their speed area,
power consumption and circuit complexity. The value of multiplicand to be accumulated
and added depends on the value of multiplier LSB. At
Add and shift multiplication process is the each clock cycle the multiplier is shifted one bit to the
common method. The main parameter in parallel right and its value is tested. If it is a 0, then only a shift
multipliers that determines the performance of the operation is performed. If the value is a 1, then the
multiplier is the number of products to be added. By multiplicand is added to the accumulator and is shifted
the use of increased parallelism, the amount of by one bit to the right. After all the multiplier bits have
shifts between intermediate sums and the partial been tested the product is in the accumulator. The
products to be added will increase which may gives accumulator is 2Q (P+Q) in size and initially the Q,
in reduction in speed. Due to irregularity of structure LSBs contains the Multiplier. The delay is Q cycles
silicon area increases and also due to increase in maximum. Serial multipliers consume more power. So
interconnect resulting from complex routing power power is an important criterion there we should prefer
consumption increased. Depends on the nature of parallel multipliers like booth multipliers to serial
application, the selection of a parallel or serial multipliers.
multiplier is made.
The parallel multipliers like booth multiplier
The organization of this paper is as follows: perform the computations using very few adders and

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SSRG International Journal of Electronics and Communication Engineering ( SSRG – IJECE ) – Volume 3 Issue 3–March 2016

very few iterative steps. As a result of which they the booth algorithm. Booth algorithm reduces the
cover minimum space as compared to the serial number of partial products. Here, the multiplier
multiplier. considers two number of bits at a time for the
multiplication process. The multiplication process for
C. Array Multipliers both signed and unsigned numbers can be done in this
Laxman S, Darshan Prabhu R, Mahesh S booth multiplier. This multiplier considers the 2's
Shetty ,Mrs. Manjula BM, Dr. Chirag Sharma have compliment of the given multiplicand and multiplier. It
presented this algorithm. The detailed study of is based on radix-2 computation. In add-shift operation
different multipliers based on Array Multiplier, each multiplier bit multiply with the multiplicand and to
Constant coefficient multiplication (KCM) and be added to the partial product.
multiplication based on vedic mathematics is
introduced in this work[1]. For very large multiplier, a large number of
multiplicands to be added. In this multiplier, number of
With an array multiplier two binary numbers additions can decide the multiplier delay. Booth
will be multiplied by using of an array of half adders algorithm can easily reduce the no.of multiplicand
and full adders. Simultaneously addition of the multiplies.For a n-bit number can be represented as n/2-
different product terms is done in this array. By digit radix 4 number, a n/3- digit radix 8 number and so
using an array of AND gates, the partial product on.
terms are formed..Following this an array of AND
gates, the adder array is used. The hardware structure Major limitation of array multiplier is its size.
for an pxq bit multiplier is described as (pxq) AND As operand sizes increase, arrays grow in size at a rate
gates (p-1)q adders .Here q Half adders and (p-2).q equal to the square of the operand size ,hence speed of
Full adders. Array multiplier doing the multiplication multiplier reduces .In order to increase the speed of
process in traditional way. It looks like regular multiplier booth algorithm is used. The Booth
structure. Hence wiring and the layout are done in multiplier makes use of Booth encoding algorithm in
a much simplified manner. Add and shift algorithm order to reduce the number of partial products by
is employed in an array multiplier. Implementation of considering two bits of the multiplier at a time, thereby
this multiplier is simple but it requires larger area, achieving a speed advantage over other multiplier
with considerable delay also[2]. architectures. This algorithm is valid for both signed
and unsigned numbers. It accepts the number in 2's
Instead of Ripple Carry Adder (RCA), in complement form, based on radix-2 computation[4,10]
this multiplier Carry Save Adder (CSA) is used
for adding each group of partial product terms, The low power consumption quality of booth
because RCA is the slowest adder among all other multiplier makes it a preferred choice in designing
types of adders available. In case of multiplier with different circuits. By implementing both Radix-2 &
CSA , partial product addition is carried out in Radix -4 multiplier using booth algorithm their
Carry save form and RCA is used only in final computation speed increases so much.
addition. In this algorithm , no waiting is necessary
until all the partial products have been formed before E. Constant Coefficinet Multiplier
summing them. As soon as the partial products Mohammed Hasmat Ali, Anil Kumar Sahani
formed immediately the addition of partial product have presented this algorithm. In this work[5]
can be done[3]. introduces the multiplier is based on an algorithm
Urdhva Tiryakbhyam (Vertical & Crosswise) of ancient
The major advantage of the array multiplier Indian Vedic Mathematics. This method is based on
is that it has a regular structure. Another advantage of ROM approach. In conventional KCM, one input is
the array multiplier is its ease of design for a fixed but here, both the inputs for the multiplier can be
pipelined architecture. Major limitation of array variables. ROM approach is employed in this method.
multiplier is its size. As operand sizes increase, The two inputs are variables for this multiplier. By
arrays grow in size at a rate equal to the square of the averaging, squaring and subtraction this two variables
operand size. It comes under conventional multiplier. multiplication is performed. The averaging process is
done by right shifting the sum by one bit. Here ROM
D. Booth Multiplier stores the squares of the numbers, finally the result will
Ruchi Sharma have presented this be calculated instantaneously.
algorithm. In this work[4] different multiplier
architectures are implemented in Xilinx FPGA and In KCM, the multiples are stored in ROM. In
compared for their performance It is a powerful this method, the difference of two given numbers is
algorithm for signed-number multiplication, which decided as even or odd. For even difference, the two
treats both positive and negative numbers uniformly. variable multiplication is performed by averaging
To overcome the limitation of array squaring and subtraction. For odd difference, the
multiplier the speed of the multiplier is increased by average is a floating point number,the square of

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SSRG International Journal of Electronics and Communication Engineering ( SSRG – IJECE ) – Volume 3 Issue 3–March 2016

numbers end with 5 is found by the Vedic sutra – (KCM) in terms of execution time. The main
Ekadikena purvena.These squares of averages and Disadvantage of this multiplier is system becomes
difference is stored in two port memory complex for complex multiplications[8].
simultaneously to reduce memory accessing time[6].
G. Wallace Tree Multiplier
Thus, division and multiplication operations Vidhi Gupta1, J. S. Ubhi21Scholar have
are effectively converted to subtraction and addition presented this algorithm. In this work[7,9] introduces
operations using Vedic Maths. Square of both the Analysis And Comparison Of Various Parameters
Average and Deviation is read out simultaneously by For Different Multiplier Designs. Wallace tree is an
using a two port memory to reduce memory access efficient hardware implementation of a digital circuit
time. that multiplies two integers. Wallace trees are irregular
structure in that the informal description does not
F. Vedic Multiplier specify a systematic method for the compressor
Mohammed Hasmat Ali, Anil Kumar Sahani interconnections. But still it is an efficient
have presented this algorithm. In this work[7,11] implementation of adding partial products in parallel.
introduces the multiplier is based on an algorithm Using this method, a three step process is used to
Urdhva Tiryakbhyam (Vertical & Crosswise) of multiply two integer numbers. First step is to multiply
ancient Indian Vedic Mathematics. In Vedic each bit of one of the arguments, by each bit of the
mathematics, two of sixteen sutras are mainly used other, yielding n2 results. Based on the position of the
for multiplication process. One is Urdhva- multiplied bits, the wires carry different weights. The
tiryagbhyam sutra and other is Nikhilam second step is to reduce the number of partial products
Navatascaramam dasatahs. Urdhva – Tiryagbyam to two by layers of full and half adders. The third step
performs the operation of two decimal numbers is to group the wires in two numbers, and then add
multiplication. It is applicable ao all types of them with conventional adder . There are two different
multiplication between two large numbers. It is also architectures of Wallace tree multiplier are available.
referred as “Vertically and crosswise algorithm”. First one is designed using only half adder and full
This can solve the multiplication of larger number (N adder, while the second one uses a more sophisticated
X N bits) by breaking it into smaller sizes. Vedic carry skip adder (CSA).
multiplier gives the improved speed than the
conventional multiplier and reduces the system Wallace Tree Multiplier using only Full and
memory. Very small area is needed for this Half Adders is employed. With this idea of Wallace tree
multiplier. For binary and decimal number method is to reduce the number of adders by minimizing
multiplication this multiplier is used exclusively. To the number of the half adder in any multiplier. The first
solve complex calculations by simple techniques partial product is the least significant bit in the output of
Vedic Mathematics is used. The strategy applied for the multiplier result. After that, moving to the next column
developing a 64 x 64-bit Vedic multiplier is to design of the partial product if there are any adders from the
a 2 x 2- bit Vedic multiplier as a basic building previous product, the full Adder is used otherwise a half
module for the system. The development a 4 x 4-bit adder is used and so on[13].
multiplier is designed using 2 x 2-bit Vedic
multiplier. Further in the same manner 8 x 8, 16 x 16 Wallace Tree Multiplier using Carry Skip
and 32 x 32- bit Vedic multiplier is designed. This Adder is also employed. A carry-skip adder consists of
type of Multiplier plays a very important role in a simple ripple carry-adder with a special speed up
today's digital circuits[12]. carry chain called a skip chain. The purpose of using
the CSA is to improve the worst case path delay. A 4 -
The first step in multiplication is vertical bit CSA is used for implementing the Wallace tree
multiplication of LSB of both multiplicands, and then multiplier. The carry output from the first addition is the
carry input in the second addition. The advantage of using
second step is crosswise multiplication and additions
CSA is to increase the maximum frequency.
of the partial products. Third step involves vertical
multiplication of MSB of the multiplicand and
The Wallace tree multiplier using CSA
addition with the carry propagated from step 2.
occupies smallest area while the Vedic multiplier using
KSA consumes large area. The power consumption of
Vedic multiplier gives the improved speed
the four multipliers is convergent. In the parallel FIR
than the conventional multiplier and reduces the
filter architecture, Wallace tree multiplier using CSA
system memory. Very small area is needed for this
has the minimum critical path whereas the Vedic
multiplier as compared to other multiplier
multiplier using conventional adder has the maximum
architecture. For binary and decimal number
delay.
multiplication this multiplier is used and also it is
III. CONCLUSION
used in unsigned and signed number multiplication.
It is concluded that the parallel multipliers
The Vedic Urdhva multiplier is much more efficient
are much option than the serial multiplier. In case of
than Array and Constant Coefficient Multiplier

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SSRG International Journal of Electronics and Communication Engineering ( SSRG – IJECE ) – Volume 3 Issue 3–March 2016

parallel multipliers, the total area is much less than international conference on engineering trends and
science & humanities (icetsh-2015) issn: 2348 – 8549
that of serial multipliers. Hence the power www.internationaljournalssrg.org page 1
consumption is also less. [11] S Muneer Ahamed 1, V Madhuri”Implementation Of High
Wallace tree multiplier exhibits good Speed 8-Bit Vedic Multiplier Using Barrel Shifter” SSRG
features as compared to Array multiplier. It has lower International Journal of Electronics and Communication
Engineering (SSRG-IJECE) – volume1 issue10 Dec 2014
power dissipation both static and dynamic. It has ISSN: 2348 – 8549 www.internationaljournalssrg.org
lesser delay and good noise immunity Page 20
[12] Sulakshna Thakur#1, Pardeep Kumar”Area-Efficient &
The performance of both sequential and High Speed Ripple Carry based Vedic Multiplier” SSRG
parallel micro programmed FIR filters using Wallace International Journal of Electronics and Communication
Engineering (SSRG-IJECE) – EFES April 2015 ISSN:
tree and Vedic multipliers for different number of taps. 2348 - 8549 http://www.internationaljournalssrg.org Page 6
Wallace tree multiplier delivers better performance than [13] M.Rohini, M.Madhumetha, S.Ranjith”An Survey on Adders &
Vedic multiplier for both the FIR filter architectures. Multiplier For High Speed & Low Power Application”
International Conference on Futuristic Trends in Computing
The Wallace tree multiplier using regular and Communication (ICFTCC-2015) ISSN: 2348 – 8549
www.internationaljournalssrg.org Page 55
full and half adder has minimum area while Vedic
using KSA has maximum area. In terms of power
consumption, the four multiplier architectures are
very close. The Wallace tree multiplier has the
smallest critical path delay as compared to Vedic
multiplier.

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