Tutorial

LABORATORY 0 – BASIC TOOL SETUP AND USAGE
LABORATORY 0
BASIC TOOL SETUP AND USAGE
OBJECTIVES
No. Objectives Requirements
1 Install and Setup enviroment for ▪ Install VM-Ware and Import virtual
Cadence Virtuoso machine with Cadence Virtuoso enviroment.
2 Simulation a working of Inverter ▪ Fimiliar with linux command.
▪ Create library, schematic and testbench.
▪ Using ADE-L to simulation.
LAB 0 INFORMATION
- Download and install VM-Ware tool version 16 Pro.
- Download Cadence Virtuoso enviroment virtual machine (your laptop need ~80GB empty
space).
- Link download tools (VM-Ware and Cadence Virtuoso enviroment): AMS Design
- PDK usage is tsmc65 technology.
- Device usge for LAB0, LAB1, LAB2, LAB3, LAB4: nch_lvt and pch_lvt devices.
❖ Open virtual machine
Figure 1. Import Cadence_IC_Design_Virtuoso_CentOS to WM-Ware

▪ Open VM-Ware Station.
▪ Import and open virtual machine as Figure 1.
▪ User name: hoangtrang, Password: hoangtrang
Department of Electronics Page | 1

Analog and Mixed Signal IC Design Laboratory
▪ Open Terminal by the step in Figure 2
Figure 2. Open Terminal

▪ Go to ALL_PDK directory and using virtuoso& command to open tool. Choose Library
Manager to view PDK library and your defined library as Figure 3.
cd /home/hoangtrang/Thu_vien_PDK/ALL_PDK/
virtuoso&
Figure 3. Open virtuoso tool

▪ Basic Linux Command

❖ Create Library, Cell and Testbench

✓ Create Library
Figure 4. Create library

o Create a new library with username as Figure 4.

o Attach tsmcN65 technology to your library.
✓ Create schematic of inverter
o Create a new inverter cell as Figure 5.
o Cell inv has created.
Figure 5. Create schematic

o Common shotcut
f Fit to screen. Autozoom the schematic to the size of your window
i Insert an instance from the library
w Add a wire
m Move instance
c Copy instance
q Edit parameters of the selected instance
l Label a wire

p Create pin
r Rotate device
Shift + r Take symmetry of an element
e Descend to an inner level only read
ESC Unselect the actual tool / unselect the currently selected device
u Undo an action
Shift + x Check + Save the schematic
Shift + e Descend to an inner level
o Press i to insert a device → Define the type cell and view of device → Hide
▪ Library: tsmcN65
▪ Cell: nch/nch_lvt/nch_hvt 1
▪ View: symbol
Figure 6. Insert NMOS nch_lvt device
1
There are many types of NMOS/PMOS device, with NMOS core device has 3 type nch (normal threshold
voltage), nch_lvt (low threshold voltage) and nch_hvt (high threshold voltage).

o Select device M0 > Press q to view the properties of MMOS. You can change the
length, width, finger and multiplier of MOS.
▪ L (M): Length of MOS
▪ W (M): Width of MOS
▪ Number of Fingers: Number of devices (Share OD in layout)
▪ Multiplier: Number of devices (Not share OD in layout)
Figure 7. Edit the properties of NMOS

o Similarly, insert a pch_lvt PMOS device to create an inverter.
o Press w to add wire for connecting → Press l to label a name for each net as Figure 8
Figure 8. Add wire to connect and label

o Create pin for schematic to contact with another block in top cell or testbench
connection, following the step in Figure 9.
Figure 9. Create pin for inverter schematic

o Finally, you must check warning/error and save schematic design. There are 3 ways:
▪ At File tab > Choose Check and Save.
▪ Choose Check and Save icon in TabBar.
▪ Press Shift + X.
✓ Create Symbol
o At Create tab → Choose Cellview → Choose From Cellview as Figure 10

Figure 10. Create symbol

o Generate the symbol shape and pin by following the step in Figure 11.
Figure 11. Setup creating symbol

o Finally, you draw the shape for design as Figure 12, instead of the regtangle default
shape.

Figure 12. Symbol of inverter

✓ Create testbench
o Create a new cell view with name inv_tb as Figure 13.
Figure 13. Create testbench

o Press i → Choose library username, cell inv, view symbol to get the inverter as Figure
14.
Figure 14. Insert inverter to testbench

o Insert power supply and ground in Library analogLib as Figure 15.
Figure 15. Insert vdc cell to testbench

o Some common usage cell in library
Cell Library Detail
vdc analogLib DC voltage
gnd analogLib Ground
vsin analogLib SIN voltage
vpulse analogLib PULSE voltage
vpwl analogLib RAMP custom voltage
idc analogLib DC current
isin analogLib SIN current
ipusle analogLib PULSE current
res analogLib Ideal resistor
cap analogLib Ideal capacitor
ind analogLib Ideal inducttor
noConn basic For floating net, ignore warning
o Insert supply voltage and capacitor to create a testbench for inverter as Figure 16.

Figure 16. Inverter testbench for DC analysis

o Note: Must be clean all error and warning after Check and Save schematic and
testbench.
o Some common error:
▪ No connect bulk. NMOS bulk connect to VSS, PMOS bulk connect to VDD
(not connect to source of MOS). Why?
▪ No connect to gnd!
o The parameter of cell can be a variable (can be changed value while simulating). For
example, in Figure 16, V1 source set the value of DC voltage parameter equal 𝒗𝒅𝒅.
Figure 17. Set variable for cell parameter

❖ Simulation with ADE-L and Spectre

▪ At Launch tab, choose ADE-L
Figure 18. Open ADE-L

▪ Setup Variable
o At Variables tab, choose Copy from Cellview
o Define value for all variable
Figure 19. Define variable

▪ Setup Model files
o At Setup tab, choose Model Libraries
o Choose TT model file
Figure 20. Model files setup

▪ Define the Temperature = 25℃
Figure 21. Temperature setup

▪ Setup Analyses
▪ At Analyses tab > Choose. Setup DC analyses with 6 steps in Figure 22.
Figure 22. DC analyses setup
Figure 23. Result after analyses setup

▪ You can investigate three common usage analyses: DC, AC and TRAN. How to setup the
testbench and what analyses uses for?
▪ Setup Output
▪ At tab Outputs, choose To be plotted > Select On Design
Figure 24. Output plot setup

▪ Choose important signal need to be plotted from schematic design.
Figure 25. Result after output setup
▪ At tab Simulation, choose Netlist and Run. Or click on to running testbench

Figure 26. Netlist and run setup

▪ The output waveform is similar Figure 27.
Figure 27. Result after simulation

❖ Practices:
o Explain the output waveform of inverter with DC analysis in Figure 27.
o Build a testbench for transient analysis. Hint: Replace input voltage from vdc to
vpulse. Setup TRAN analysis instead of DC analysis.
Figure 28. Setup TRAN analyses


Tutorial

Uploaded by

Copyright:

Available Formats

Tutorial

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Tutorial

Uploaded by

Copyright:

Available Formats

LABORATORY 0 – BASIC TOOL SETUP AND USAGE

Figure 1. Import Cadence_IC_Design_Virtuoso_CentOS to WM-Ware

Department of Electronics Page | 1

▪ Open Terminal by the step in Figure 2

Figure 2. Open Terminal

Figure 3. Open virtuoso tool

Department of Electronics Page | 2

❖ Create Library, Cell and Testbench

Figure 4. Create library

Department of Electronics Page | 3

o Create a new library with username as Figure 4.

Figure 5. Create schematic

Department of Electronics Page | 4

Figure 6. Insert NMOS nch_lvt device

Department of Electronics Page | 5

Figure 7. Edit the properties of NMOS

Figure 8. Add wire to connect and label

Department of Electronics Page | 6

Figure 9. Create pin for inverter schematic

Department of Electronics Page | 7

Figure 10. Create symbol

Figure 11. Setup creating symbol

Department of Electronics Page | 8

Figure 12. Symbol of inverter

Figure 13. Create testbench

Figure 14. Insert inverter to testbench

Department of Electronics Page | 9

o Insert power supply and ground in Library analogLib as Figure 15.

Figure 15. Insert vdc cell to testbench

Department of Electronics Page | 10

Figure 16. Inverter testbench for DC analysis

Figure 17. Set variable for cell parameter

Department of Electronics Page | 11

❖ Simulation with ADE-L and Spectre

Figure 18. Open ADE-L

Figure 19. Define variable

Figure 20. Model files setup

Department of Electronics Page | 12

▪ Define the Temperature = 25℃

Figure 21. Temperature setup

Figure 22. DC analyses setup

Figure 23. Result after analyses setup

Department of Electronics Page | 13

Figure 24. Output plot setup

Figure 25. Result after output setup

▪ At tab Simulation, choose Netlist and Run. Or click on to running testbench

Department of Electronics Page | 14

Figure 26. Netlist and run setup

Figure 27. Result after simulation

Figure 28. Setup TRAN analyses

Department of Electronics Page | 15

You might also like