SG3525A

Pulse Width
Modulator Control Circuit
The SG3525A pulse width modulator control circuit offers
improved performance and lower external parts count when
implemented for controlling all types of switching power supplies.
The on–chip +5.1 V reference is trimmed to ±1% and the error http://onsemi.com
amplifier has an input common–mode voltage range that includes the
reference voltage, thus eliminating the need for external divider MARKING
resistors. A sync input to the oscillator enables multiple units to be DIAGRAM
slaved or a single unit to be synchronized to an external system clock. 16
A wide range of deadtime can be programmed by a single resistor
PDIP–16 SG3525AN
connected between the CT and Discharge pins. This device also
N SUFFIX AWLYYWW
features built–in soft–start circuitry, requiring only an external timing CASE 648
capacitor. A shutdown pin controls both the soft–start circuitry and the 16 1
output stages, providing instantaneous turn off through the PWM latch 1
with pulsed shutdown, as well as soft–start recycle with longer
A = Assembly Location
shutdown commands. The under voltage lockout inhibits the outputs WL = Wafer Lot
and the changing of the soft–start capacitor when VCC is below YY = Year
nominal. The output stages are totem–pole design capable of sinking WW = Work Week
and sourcing in excess of 200 mA. The output stage of the SG3525A
features NOR logic resulting in a low output for an off–state.
• 8.0 V to 35 V Operation PIN CONNECTIONS
• 5.1 V ± 1.0% Trimmed Reference
• 100 Hz to 400 kHz Oscillator Range Inv. Input 1 16 Vref
• Separate Oscillator Sync Pin
Noninv. Input 2 15 VCC
• Adjustable Deadtime Control
• Input Undervoltage Lockout Sync 3 14 Output B
• Latching PWM to Prevent Multiple Pulses OSC. Output 4 13 VC
• Pulse–by–Pulse Shutdown
CT 5 12 Ground
• Dual Source/Sink Outputs: ±400 mA Peak
RT 6 11 Output A
Discharge 7 10 Shutdown
16 VC
Vref To Internal 13 Soft-Start 8 9 Compensation
15 Circuitry
Reference Under-
VCC Output A
Regulator Voltage
12 Lockout 11
(Top View)
Ground NOR
4
OSC Output
3 Q
Sync
6 Oscillator F/F ORDERING INFORMATION
RT Q NOR 14
5 Output B
CT Device Package Shipping
7
Discharge R
9 + S SG3525AN PDIP–16 25 Units/Rail
Compensation - PWM Latch SG3525A Output Stage
1 -
INV. Input -
Error 50µA S
2 Amp
Noninv. Input + VREF
8
CSoft-Start
10 5.0k
Shutdown 5.0k

Figure 1. Representative Block Diagram

 Semiconductor Components Industries, LLC, 2001 1 Publication Order Number:

July, 2001 – Rev. 3 SG3525A/D

This datasheet has been downloaded from http://www.digchip.com at this page

 SG3525A

MAXIMUM RATINGS (Note 1)

Rating Symbol Value Unit
Supply Voltage VCC +40 Vdc
Collector Supply Voltage VC +40 Vdc
Logic Inputs –0.3 to +5.5 V
Analog Inputs –0.3 to VCC V
Output Current, Source or Sink IO ±500 mA
Reference Output Current Iref 50 mA
Oscillator Charging Current 5.0 mA
Power Dissipation (Plastic & Ceramic Package) PD mW
TA = +25°C (Note 2) 1000
TC = +25°C (Note 3) 2000
Thermal Resistance Junction–to–Air RθJA 100 °C/W
Thermal Resistance Junction–to–Case RθJC 60 °C/W
Operating Junction Temperature TJ +150 °C
Storage Temperature Range Tstg –55 to +125 °C
Lead Temperature (Soldering, 10 seconds) TSolder +300 °C

RECOMMENDED OPERATING CONDITIONS

Characteristics Symbol Min Max Unit
Supply Voltage VCC 8.0 35 Vdc
Collector Supply Voltage VC 4.5 35 Vdc
Output Sink/Source Current IO mA
(Steady State) 0 ±100
(Peak) 0 ±400
Reference Load Current Iref 0 20 mA
Oscillator Frequency Range fosc 0.1 400 kHz
Oscillator Timing Resistor RT 2.0 150 kΩ
Oscillator Timing Capacitor CT 0.001 0.2 µF
Deadtime Resistor Range RD 0 500 Ω
Operating Ambient Temperature Range TA 0 +70 °C
1. Values beyond which damage may occur.
2. Derate at 10 mW/°C for ambient temperatures above +50°C.
3. Derate at 16 mW/°C for case temperatures above +25°C.

APPLICATION INFORMATION
Shutdown Options (See Block Diagram, front page) latch is immediately set providing the fastest turn–off signal
Since both the compensation and soft–start terminals to the outputs; and a 150 µA current sink begins to discharge
(Pins 9 and 8) have current source pull–ups, either can the external soft–start capacitor. If the shutdown command
readily accept a pull–down signal which only has to sink a is short, the PWM signal is terminated without significant
maximum of 100 µA to turn off the outputs. This is subject discharge of the soft–start capacitor, thus, allowing, for
to the added requirement of discharging whatever external example, a convenient implementation of pulse–by–pulse
capacitance may be attached to these pins. current limiting. Holding Pin 10 high for a longer duration,
An alternate approach is the use of the shutdown circuitry however, will ultimately discharge this external capacitor,
of Pin 10 which has been improved to enhance the available recycling slow turn–on upon release.
shutdown options. Activating this circuit by applying a Pin 10 should not be left floating as noise pickup could
positive signal on Pin 10 performs two functions: the PWM conceivably interrupt normal operation.

http://onsemi.com
2
 SG3525A

ELECTRICAL CHARACTERISTICS (VCC = +20 Vdc, TA = Tlow to Thigh [Note 4], unless otherwise noted.)
Characteristics Symbol Min Typ Max Unit
REFERENCE SECTION
Reference Output Voltage (TJ = +25°C) Vref 5.00 5.10 5.20 Vdc
Line Regulation (+8.0 V ≤ VCC ≤ +35 V) Regline – 10 20 mV
Load Regulation (0 mA ≤ IL ≤ 20 mA) Regload – 20 50 mV
Temperature Stability ∆Vref/∆T – 20 – mV
Total Output Variation ∆Vref 4.95 – 5.25 Vdc
Includes Line and Load Regulation over Temperature

Short Circuit Current ISC – 80 100 mA

(Vref = 0 V, TJ = +25°C)

Output Noise Voltage (10 Hz ≤ f ≤ 10 kHz, TJ = +25°C) Vn – 40 200 µVrms

Long Term Stability (TJ = +125°C) (Note 5) S – 20 50 mV/khr

OSCILLATOR SECTION (Note 6, unless otherwise noted.)

Initial Accuracy (TJ = +25°C) – ±2.0 ±6.0 %
Frequency Stability with Voltage ∆fosc – ±1.0 ±2.0 %
(+8.0 V ≤ VCC ≤ +35 V) D VCC

Frequency Stability with Temperature ∆fosc – ±0.3 – %

D T

Minimum Frequency (RT = 150 kΩ, CT = 0.2 µF) fmin – 50 – Hz

Maximum Frequency (RT = 2.0 kΩ, CT = 1.0 nF) fmax 400 – – kHz
Current Mirror (IRT = 2.0 mA) 1.7 2.0 2.2 mA
Clock Amplitude 3.0 3.5 – V
Clock Width (TJ = +25°C) 0.3 0.5 1.0 µs
Sync Threshold 1.2 2.0 2.8 V
Sync Input Current (Sync Voltage = +3.5 V) – 1.0 2.5 mA
ERROR AMPLIFIER SECTION (VCM = +5.1 V)
Input Offset Voltage VIO – 2.0 10 mV
Input Bias Current IIB – 1.0 10 µA
Input Offset Current IIO – – 1.0 µA
DC Open Loop Gain (RL ≥ 10 MΩ) AVOL 60 75 – dB
Low Level Output Voltage VOL – 0.2 0.5 V
High Level Output Voltage VOH 3.8 5.6 – V
Common Mode Rejection Ratio (+1.5 V ≤ VCM ≤ +5.2 V) CMRR 60 75 – dB
Power Supply Rejection Ratio (+8.0 V ≤ VCC ≤ +35 V) PSRR 50 60 – dB
PWM COMPARATOR SECTION
Minimum Duty Cycle DCmin – – 0 %
Maximum Duty Cycle DCmax 45 49 – %
Input Threshold, Zero Duty Cycle (Note 6) Vth 0.6 0.9 – V
Input Threshold, Maximum Duty Cycle (Note 6) Vth – 3.3 3.6 V
Input Bias Current IIB – 0.05 1.0 µA
4. Tlow = 0° Thigh = +70°C
5. Since long term stability cannot be measured on each device before shipment, this specification is an engineering estimate of average
stability from lot to lot.
6. Tested at fosc = 40 kHz (RT = 3.6 kΩ, CT = 0.01 µF, RD = 0 Ω).

http://onsemi.com
3
 SG3525A

ELECTRICAL CHARACTERISTICS (Continued)

Characteristics Symbol Min Typ Max Unit
SOFT–START SECTION
Soft–Start Current (Vshutdown = 0 V) 25 50 80 µA
Soft–Start Voltage (Vshutdown = 2.0 V) – 0.4 0.6 V
Shutdown Input Current (Vshutdown = 2.5 V) – 0.4 1.0 mA
OUTPUT DRIVERS (Each Output, VCC = +20 V)
Output Low Level VOL V
(Isink = 20 mA) – 0.2 0.4
(Isink = 100 mA) – 1.0 2.0
Output High Level VOH V
(Isource = 20 mA) 18 19 –
(Isource = 100 mA) 17 18 –
Under Voltage Lockout (V8 and V9 = High) VUL 6.0 7.0 8.0 V
Collector Leakage, VC = +35 V (Note 7) IC(leak) – – 200 µA
Rise Time (CL = 1.0 nF, TJ = 25°C) tr – 100 600 ns
Fall Time (CL = 1.0 nF, TJ = 25°C) tf – 50 300 ns
Shutdown Delay (VDS = +3.0 V, CS = 0, TJ = +25°C) tds – 0.2 0.5 µs
Supply Current (VCC = +35 V) ICC – 14 20 mA
7. Applies to SG3525A only, due to polarity of output pulses.

Vref
16 15 VCC
Reference Regulator
Clock 0.1 0.1
4 Flip/ 13 VC
Flop
3.0k 0.1
Sync
3 O Out A
PWM
ADJ. s 11
RT c A
1.0k
6 i
l
Deadtime l
1.5k 1.0k, 1.0W
a
0.009 Ramp 7 (2)
t
100Ω 5 o
r
14
0.1 0.001 B
Out B
Comp

10k 9 12
PWM Gnd
1 = VIO
2 = 1(+) 0.01
3 = 1(-) 50µA 8 Softstart
1 1
+
2 2 1 5.0µF
- -
3 3 E/A 5.0k 10
2 5.0k Vref
V/I Meter +
1 1 2.0k
+ 2 2
3 3 DUT
Shutdown

Figure 2. Lab Test Fixture

http://onsemi.com
4
 SG3525A

200 500

R D , DEAD TIME RESISTOR ()

100

Ω
400
RT, TIMING RESISTOR (k Ω )

50
300
* RD = 0 Ω
20
200
10
6 5 7
RD * 100
5.0
RT CT

2.0 0
2.0 5.0 10 20 50 100 200 500 1000 2000 5000 10,000 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200
CHARGE TIME (µs) DISCHARGE TIME (µs)

Figure 3. Oscillator Charge Time versus RT Figure 4. Oscillator Discharge Time versus RD

1 - 9

VCC = +20 V
V sat , SATURATION VOLTAGE (V)
2 +
CP 4.0
TJ = +25°C
A VOL, VOLTAGE GAIN (dB)

100 RZ 3.5
80 3.0
60 2.5
RZ = 20 k 2.0
40
1.5 Source Sat, (VC-VOH)
20
1.0
0 Sink Sat, (VOL)
0.5
-20 0
1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M 0.01 0.02 0.03 0.05 0.07 0.1 0.2 0.3 0.5 0.7 1.0
f, FREQUENCY (Hz) IO, OUTPUT SOURCE OR SINK CURRENT (A)

Figure 5. Error Amplifier Open Loop Figure 6. Output Saturation

Frequency Response Characteristics

Vref 15
16 VCC
Q1 Q5 Q8
7.4k
Q3
RT Q3
6
CT Q6 Q9
5 Ramp Q4
Inverting
2.0k 14k To PWM Q1 Q2
Input
3 2.0k Q10 Q11 25k 1
Sync Blanking To PWM
5.0pF Noninverting
7 Q14 To Output Input Comparator
Discharge 400µA 2
Q4 5.8V 30
Q2 23k 200µA 100µA
Q7 1.0k Q12 Q13 250
12 1.0k 3.0k 9 Compensation
Gnd 4
OSC Output

Figure 7. Oscillator Schematic Figure 8. Error Amplifier Schematic

http://onsemi.com
5
 SG3525A

13
VCC VC
Q5 Q7
Q9
Q10
Q4
5.0k

11, 14
Vref Q8
Q11 Output
Q6
2.0k

Q1 Q2 Q3 Q6 Omitted
in SG3527A

5.0k 10k 10k

Clock F/F PWM

Figure 9. Output Circuit

(1/2 Circuit Shown)

Q1
+Vsupply
+Vsupply To Output Filter
R1
R1
C1
R2 13
11 T1
VC A Q1
13 R2
VC 11 C2
A SG3525A
SG3525A 14
14 B Q2
B Gnd R3
Gnd
12
12

For single-ended supplies, the driver outputs are grounded. In conventional push-pull bipolar designs, forward base drive is
The VC terminal is switched to ground by the totem-pole controlled by R1-R3. Rapid turn-off times for the power devices
source transistors on alternate oscillator cycles. are achieved with speed-up capacitors C1 and C2.
Figure 10. Single–Ended Supply Figure 11. Push–Pull Configuration

+Vsupply +Vsupply
R1
Q1
T1 C1
13 Q1 T1
11 13 R1 T2
VC A 11
VC A

SG3525A SG3525A Q2
Q2 14
14
Gnd B Gnd B C2
12 R2
12

The low source impedance of the output drivers provides Low power transformers can be driven directly by the SG3525A.
rapid charging of power FET input capacitance while Automatic reset occurs during deadtime, when both ends of the
minimizing external components. primary winding are switched to ground.
Figure 12. Driving Power FETS Figure 13. Driving Transformers in a
Half–Bridge Configuration

http://onsemi.com
6
 SG3525A

PACKAGE DIMENSIONS

PDIP–16
N SUFFIX
CASE 648–08
ISSUE R

NOTES:
–A– 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
16 9 3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
B 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 8 5. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
F C A 0.740 0.770 18.80 19.55
L
B 0.250 0.270 6.35 6.85
S C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
SEATING F 0.040 0.70 1.02 1.77
–T– PLANE G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
H K M J 0.008 0.015 0.21 0.38
J K 0.110 0.130 2.80 3.30
G L 0.295 0.305 7.50 7.74
D 16 PL
M 0
10
0
10

0.25 (0.010) M T A M S 0.020 0.040 0.51 1.01

http://onsemi.com
7
 SG3525A

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

Literature Fulfillment: JAPAN: ON Semiconductor, Japan Customer Focus Center
Literature Distribution Center for ON Semiconductor 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031
P.O. Box 5163, Denver, Colorado 80217 USA Phone: 81–3–5740–2700
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada Email: r14525@onsemi.com
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada
ON Semiconductor Website: http://onsemi.com
Email: ONlit@hibbertco.com
For additional information, please contact your local
N. American Technical Support: 800–282–9855 Toll Free USA/Canada
Sales Representative.

http://onsemi.com SG3525A/D
8