COMPUTER

ORGANIZATION
SEMESTER 3
UNIT - 2

HI COLLEGE
SYLLABUS
UNIT - 2

HI COLLEGE
 COMBINATIONAL CIRCUITS
MULTIPLEXERS

Selects one of many input lines and routes it to a single output.

Controlled by a set of select lines.

Multiplexers are mainly used to increase amount of the data that can be sent
over the network within certain amount of time and bandwidth.

Now the implementation of 4:1 Multiplexer using truth table and gates.

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Multiplexer can act as universal combinational circuit. All the standard logic
gates can be implemented with multiplexers.

IMPLEMENTATION OF NOT GATE USING 2 : 1 MUX

NOT Gate :

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We can analyze it Y = x’.1 + x.0 = x’
It is NOT Gate using 2:1 MUX.
The implementation of NOT gate is done using “n” selection lines. It cannot be
implemented using “n-1” selection lines. Only NOT gate cannot be implemented
using “n-1” selection lines.

IMPLEMENTATION OF AND GATE USING 2 : 1 MUX

AND GATE :

This implementation is done using “n-1” selection lines.

IMPLEMENTATION OF OR GATE USING 2 : 1 MUX USING “N-1”

SELECTION LINES.
OR GATE :

Implementation of NAND, NOR, XOR and XNOR gates requires two 2:1 Mux.
First multiplexer will act as NOT gate which will provide complemented
input to the second multiplexer.

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IMPLEMENTATION OF NAND GATE USING 2 : 1 MUX

NAND GATE :

IMPLEMENTATION OF NOR GATE USING 2 : 1 MUX

NOR GATE :

IMPLEMENTATION OF EX-OR GATE USING 2 : 1 MUX

EX-OR GATE :

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IMPLEMENTATION OF EX-NOR GATE USING 2 : 1 MUX
EX-NOR GATE :

IMPLEMENTATION OF HIGHER ORDER MUX USING LOWER ORDER

MUX

4 : 1 MUX using 2 : 1 MUX

Three(3) ​2 : 1 MUX are required to implement 4 : 1 MUX.

Similarly,
While 8 : 1 MUX require seven(7) ​2 : 1 MUX, 16 : 1 MUX require fifteen(15) ​2 :1
MUX, 64 : 1 MUX requires sixty three(63)​2 : 1 MUX.
Hence, we can draw a conclusion, 2n : 1 MUX requires (2^n – 1) 2 : 1 MUX.

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16 : 1 MUX using 4 : 1 MUX

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Similarly,
While 8 : 1 MUX require seven(7) ​2 : 1 MUX, 16 : 1 MUX require fifteen(15) ​2 :1 MUX,
64 : 1 MUX requires sixty three(63)​ 2 : 1 MUX. Hence, we can draw a conclusion,
2n : 1 MUX requires (2^n – 1) 2 : 1 MUX.

For example, to implement a 64 : 1 MUX using a 4 : 1 MUX:

64 / 4 = 16
16 / 4 = 4
4 / 4 = 1 (continue until you obtain 1 count of MUX)

Hence, the total number of 4 : 1 MUX required to implement a 64 : 1 MUX

is 16 + 4 + 1 = 21.
Now, let's briefly discuss implementing a boolean function using a MUX.
For the boolean function: f(A, B, C) = Σ(1, 2, 3, 5, 6)

With don't care term (7), using a 4 : 1 MUX with AB as the select input:

1. Expand the minterms to their boolean form.

2. Determine if they have a 0 or 1 value in the Cth place.
3. Place them accordingly in the MUX.

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ADVANTAGES OF MULTIPLEXERS IN DIGITAL LOGIC:
1. Space-saving: They consolidate multiple signals into a single channel,
reducing circuit space requirements.
2. Cost-effective: Fewer components are needed, lowering overall circuit
costs.
3. Time-saving: Simplify circuitry and reduce wiring complexity, saving
time in digital design.
4. Flexibility: Multiplexers are versatile and widely applicable.

DISADVANTAGES OF MULTIPLEXERS IN DIGITAL LOGIC:

1. Limited inputs: Multiplexer input capacity is restricted by control
lines.
2. Delay: Introduce signal delays that can impact circuit performance.
3. Complex control logic: Larger multiplexers require intricate control
logic.
4. Power consumption: They may consume more power, especially with
many inputs.

DE-MULTIPLEXERS:
Distributes a single input to one of many output lines.
Controlled by select lines.

DECODERS:
Converts binary inputs into multiple output lines, one of which is
active based on the input.
Commonly used in memory addressing.

ENCODERS:
Converts multiple input lines into a smaller set of output lines.
Inverse operation of a decoder

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 FLIP-FLOPS
Flip-flop is a circuit that maintains a state until directed by input to change the
state. A basic flip-flop can be constructed using four-NAND or four-NOR gates.

Types of flip-flops:
SR Flip Flop
JK Flip Flop
D Flip Flop
T Flip Flop

Logic diagrams and truth tables of the different types of flip-flops are as
follows:

S-R Flip Flop :

Characteristics Equation for SR Flip Flop: QN+1 = QNR’ + SR’

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J-K Flip Flop:

Characteristics Equation for JK Flip Flop: QN+1 = JQ’N + K’QN

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D Flip Flop:

Characteristics Equation for D Flip Flop: QN+1 = D

T Flip Flop:

Characteristics Equation for T Flip Flop: QN+1 = Q’NT + QNT’ = QN XOR T

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Conversion for Flip Flops:
EXCITATION TABLE:

Steps To Convert from One Flip Flop to Other :

Let there be required flipflop to be constructed using sub-flipflop:

1. Draw the truth table of the required flip-flop.

2. Write the corresponding outputs of sub-flipflop to be used from the
excitation table.
3. Draw K-Maps using required flipflop inputs and obtain excitation
functions for sub-flipflop inputs.
4. Construct a logic diagram according to the functions obtained.

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Convert SR To JK Flip Flop

Excitation Functions

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CONVERT SR TO D FLIP FLOP

Excitation Functions: S = D, R = D‘

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APPLICATIONS OF FLIP-FLOPS
These are the various types of flip-flops being used in digital electronic circuits
and the applications of Flip-flops are as specified below.

Counters
Frequency Dividers
Shift Registers
Storage Registers
Bounce elimination switch
Data storage
Data transfer
Latch
Registers
Memory

Clocked Flip-flop:
Synchronization of flip-flop operations using a clock signal.

Race Around Condition:

Hazardous situation in flip-flop operation due to clock skew.
Resolved using clocked flip-flops.

Master-Slave Flip-Flop:
Race Around Condition in JK Flip-Flop:
Occurs when J=K=1 and CLK is continuously high, leading to unstable Q
output.
Avoided by brief clock pulses.
Solution: Master-Slave JK Flip-Flop.
Master-Slave JK Flip-Flop:
Combines two JK flip-flops: master and slave.
Master drives slave via an inverter.
Inverted clock pulse controls slave (CP).
Master transfers data during CP low, and slave operates during CP high.
flip-flops working in tandem to eliminate race conditions.

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Applications of Flip-Flops

1.Latch:
Latches in Digital Circuits:
Latches store a single bit of information until updated by new input signals.
Two main types: S-R (Set-Reset) Latches and D (Data) Latches.
Latches operate at signal levels, not transitions.

S-R (Set-Reset) Latch:

Simplest latch, uses S (Set) and R (Reset) inputs.
When S is set to 1, the output becomes 1; when R is set to 1, output becomes
0.
Both S and R at 1 result in an undefined state.
Form the basis of other flip-flops.

D (Data) Latch:
Also called transparent latches.
Uses D (Data) input and a clock signal.
Output follows D when the clock is high.
Output holds its state until the next clock rising edge.

Applications of Latches:
Widely used in digital systems for data storage, control circuits, and flip-flop
circuits.
Used in combination with other circuits for sequential systems like state
machines and memory elements.

Key Characteristics:
Latches are level-sensitive and not edge-triggered like flip-flops.
Useful for asynchronous sequential circuits.
Have two stable states and respond to input voltage.

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Under normal conditions, both the input remains 0. The following is the RS
Latch with NAND gates:

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Case-1: S’=R’=1 (S=R=0) –
If Q = 1, Q and R’ inputs for 2nd NAND gate are both 1.
If Q = 0, Q and R’ inputs for 2nd NAND gate are 0 and 1 respectively.

Case-2: S’=0, R’=1 (S=1, R=0) –

As S’=0, the output of 1st NAND gate, Q = 1(SET state). In 2nd NAND gate, as Q
and R’ inputs are 1, Q’=0.

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Case-3: S’= 1, R’= 0 (S=0, R=1) –
As R’=0, the output of 2nd NAND gate, Q’ = 1. In 1st NAND gate, as Q and S’ inputs
are 1, Q=0(RESET state).

Case-4: S’= R’= 0 (S=R=1) –

When S=R=1, both Q and Q’ becomes 1 which is not allowed. So, the input
condition is prohibited.

The SR Latch using NOR gate is shown below:

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Gated SR Latch –
A Gated SR latch is a SR latch with enable input which works when enable is 1
and retain the previous state when enable is 0.

Gated D Latch –
D latch is similar to SR latch with some modifications made. Here, the inputs
are complements of each other. The letter in the D latch stands for “data” as this
latch stores single bit temporarily.
The design of D latch with Enable signal is given below:

The truth table for the D-Latch is shown below:

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As the output is same as the input D, D latch is also called as Transparent
Latch. Considering the truth table, the characteristic equation for D latch
with enable input can be given as:

Q(n+1) = EN.D + EN'.Q(n)

ADVANTAGES OF LATCHES:
1. Easy Implementation: Latches are straightforward to design and construct
using basic digital logic gates.
2. Low Power Consumption: They consume less power compared to more
complex sequential circuits like flip-flops.
3. High-Speed Operation: Latches can operate at high speeds, making them
suitable for high-performance digital systems.
4. Cost-Effective: Latches are cost-effective to manufacture, making them
suitable for low-cost digital systems.
5. Versatility: Latches find application in various scenarios, including data
storage, control circuits, and flip-flop circuits.

DISADVANTAGES OF LATCHES:
1. Lack of Clock: Latches lack a clock signal, making their behavior
unpredictable and less suitable for synchronous systems.
2. Unstable State: In certain situations, latches can enter an unstable state
when both inputs are set to 1, leading to unexpected system behavior.
3. Complex Timing: Specifying the timing characteristics of latches can be
complex, which may limit their use in real-time control applications.

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REGISTERS
A collection of flip-flops used to store data.
Registers are essential components in digital computer systems that play a
crucial role in data storage, manipulation, and transfer. Here are some key
points about registers:

Data Storage: Registers are small, high-speed storage elements within the CPU
(Central Processing Unit) or other parts of a computer's architecture. They store
binary data in the form of bits or bytes.

Purpose: Registers are used for various purposes, including storing data
temporarily during computation, holding operands for arithmetic and logic
operations, and serving as input/output buffers.

Size and Types: Registers come in different sizes, typically defined by the
number of bits they can store (e.g., 8-bit, 16-bit, 32-bit, or 64-bit registers).
Common types of registers include:

General-Purpose Registers: Used for general data storage and manipulation

within the CPU.

Special-Purpose Registers: Designed for specific tasks, such as the program

counter (PC), instruction register (IR), and status registers (flags).
Stack Pointer (SP) Register: Manages the stack in memory for subroutine calls
and returns.

Memory Address Register (MAR): Holds the address of the memory location
being read from or written to.

Memory Buffer Register (MBR): Temporarily stores data read from or written to
memory.

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 Speed: Registers are the fastest type of storage in a computer, with access
times measured in nanoseconds. This speed is crucial for high-performance
computation.

Data Transfer: Registers facilitate the transfer of data within the CPU and
between the CPU and other parts of the computer, such as memory and I/O
devices.

Processor Registers: The CPU typically contains several registers, including

those for arithmetic and logic operations, data movement, and control flow
management.

Instruction Execution: Registers are involved in the execution of machine

instructions. Data is loaded from memory into registers for processing, and
results are often stored back in registers.

Register Renaming: In advanced microarchitectures, register renaming

techniques are used to optimize instruction execution by dynamically
mapping architectural registers to physical registers.

Pipeline Stages: Modern CPUs often use pipeline architectures where

different stages of instruction execution are performed in parallel. Registers
are used to hold data as it progresses through these stages.

Cache Registers: High-speed cache memory in modern CPUs also uses

registers to temporarily store frequently accessed data.

Counters (Elementary Treatment):

Using flip-flops to count events or sequences of binary numbers.

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