VLSI SYSTEM DESIGN (20BT50405)

By
Prof.Avireni Srinivasulu, SM-IEEE
B.Tech., M.E., M.S., Ph.D (Birla Inst. of Tech., Mesra)
Dean (R & I)

MOHAN BABU UNIVERSITY

TIRUPATI – 517102, A.P.
 Dr. Avireni.S
Syllabus

UNIT-2: Fabrication and Electrical Properties of MOS

Fabrication Process for NMOS and CMOS Technology, Basic Electrical
Properties of MOS: Ids-Vds Relationship, Threshold Voltage VT, gm and
ωo; Pass Transistor, nMOS Inverter, CMOS Inverter.
 Dr. Avireni.S
Power Supply Voltage

• GND = 0 V
• In 1980’s, VDD = 5V
• VDD has decreased in modern processes
– High VDD would damage modern tiny transistors
– Lower VDD saves power
• VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0,
• Effective power supply voltage can be lower due to IR
drop across the power grid.

3
 Dr. Avireni.S
MOS Transistors
• Four terminal device: gate, source, drain, body
• Gate – oxide – body stack looks like a capacitor
– Gate and body are conductors (body is also called the substrate)
– SiO2 (oxide) is a “good” insulator (separates the gate from the body
– Called metal–oxide–semiconductor (MOS) capacitor, even though gate is
mostly made of poly-crystalline silicon (polysilicon)

Source Gate Drain Source Gate Drain

Polysilicon Polysilicon
SiO 2 SiO 2

n+ n+ p+ p+

p bulk Si n bulk Si

NMOS PMOS 4
 Dr. Avireni.S
Transistors as Switches
• In Digital circuits, MOS transistors are electrically controlled
switches
• Voltage at gate controls path from source to drain

g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s
5
 Dr. Avireni.S
A Y CMOS Inverter

VDD
VDD VDD

OFF A Y ON A Y
A Y
A Y A=1 Y=0 0 A=0 Y=1 0 1
0
ON 1 0 OFF 1 0
1
GND GND GND
Fig. (a) Fig. (b) Fig. (c)
Y is pulled low by the turned on Y is pulled high by the turned on
NMOS Device. Hence NMOS is PMOS Device. Hence PMOS is
the pull-down device. the pull-up device.

6
 Dr. Avireni.S
CMOS Fabrication

• CMOS transistors are fabricated on silicon wafer

• Wafers diameters (200-300 mm)
• Lithography process similar to printing press
• On each step, different materials are deposited, or
patterned or etched
• Easiest to understand by viewing both top and cross-
section of wafer in a simplified manufacturing process

7
 Dr. Avireni.S
Inverter Cross-section

• Typically use p-type substrate for nMOS transistors

• Requires to make an n-well for body of pMOS transistors

A
GND VDD
Y SiO 2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

 Dr. Avireni.S
Well and Substrate Taps
• Substrate must be tied to GND and n-well to VDD
• Metal to lightly-doped semiconductor forms poor connection
called Schottky Diode
• Use heavily doped well and substrate contacts/taps (or ties)

A
GND VDD
Y

p+ n+ n+ p+ p+ n+

n well
p substrate

substrate tap well tap

 Dr. Avireni.S
Inverter Mask Set
• Top view
• Transistors and wires are defined by masks
• Cross-section taken along dashed line

GND VDD

nMOS transistor pMOS transistor

substrate tap well tap
 Dr. Avireni.S

In 1978-79, when approximately 20,000 transistors could be

fabricated in a single chip, Carver Mead and Lynn Conway wrote the
text book Introduction to VLSI System Design which became a best
seller.
The Mead & Conway revolution was a very-large-scale integration
(VLSI) design revolution which resulted in a world-wide restructuring
of academic education, and was paramount for the development of
industries based on the application of Microelectronics.
Dr. Avireni.S

12
 Dr. Avireni.S

Layer Color Representation

Well (p, n) Yellow
Active Area (n+,p+) Green
Select (p+,n+) Green
Polysilicon Red
Metal-1 Blue
Metal-2 Magenta
Contact To Poly Black
Contact To Diffusion Black
Via Black

13
Dr. Avireni.S

14
Dr. Avireni.S

15
 Dr. Avireni.S
Detailed Mask Views
• Six masks
– n-well n well

– Polysilicon
Polysilicon

– n+ diffusion
n+ Diffusion

– p+ diffusion p+ Diffusion

– Contact Contact

In – Metal
Metal

In reality > 40 masks may be needed

16
 Dr. Avireni.S
Fabrication Steps

Start with blank wafer (typically p-type where NMOS is created)

Build inverter from the bottom up
First step will be to form the n-well (where PMOS would reside)
 Cover wafer with protective layer of SiO2 (oxide)
 Remove oxide layer where n-well should be built
 Implant or diffuse n dopants into exposed wafer to form n-well
 Strip off SiO2

17
 Dr. Avireni.S
Oxidation

• Grow SiO2 on top of Si wafer

– 900 – 1200 C with H2O or O2 in oxidation furnace

18
 Dr. Avireni.S
Photoresist
Spin on photoresist
 Photoresist is a light-sensitive organic polymer
 Property changes where exposed to light

Two types of photoresists (positive or negative)

 Positive resists can be removed if exposed to UV light
 Negative resists cannot be removed if exposed to UV light
 Dr. Avireni.S
Lithography

• Expose photoresist to Ultra-violate (UV) light through

the n-well mask
• Strip off exposed photoresist with chemicals
 Dr. Avireni.S
Etch

• Etch oxide with hydrofluoric acid (HF)

– Seeps through skin and eats bone; nasty stuff!!!
• Only attacks oxide where resist has been exposed
• N-well pattern is transferred from the mask to silicon-di-
oxide surface; creates an opening to the silicon surface

21
 Dr. Avireni.S
Strip Photoresist

• Strip off remaining photoresist

– Use mixture of acids called piranah etch
• Necessary so resist doesn’t melt in next step

22
 Dr. Avireni.S
n-well
• n-well is formed with diffusion or ion implantation
• Diffusion
– Place wafer in furnace with arsenic-rich gas
– Heat until As atoms diffuse into exposed Si
• Ion Implanatation
– Blast wafer with beam of As ions
– Ions blocked by SiO2, only enter exposed Si
• SiO2 shields (or masks) areas which remain p-type

23
 Dr. Avireni.S
Strip Oxide

• Strip off the remaining oxide using HF (Hafnium (IV) oxide is the
inorganic compound with the formula HfO₂).
• Back to bare wafer with n-well
• Subsequent steps involve similar series of steps

24
 Dr. Avireni.S
Polysilicon
(self-aligned gate technology)

• Deposit very thin layer of gate oxide

– < 20 Å (6-7 atomic layers)
• Chemical Vapour Deposition (CVD) of silicon layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon
– Heavily doped to be good conductor

25
 Dr. Avireni.S
Polysilicon Patterning

• Use same lithography process discussed earlier to pattern

polysilicon

Polysilicon

26
 Dr. Avireni.S
Self-Aligned Process

• Use gate-oxide/polysilicon and masking to expose where n+

dopants should be diffused or implanted
• N-diffusion forms nMOS source, drain, and n-well contact

27
 Dr. Avireni.S
N-diffusion/implantation
• Pattern oxide and form n+ regions
• Self-aligned process where gate blocks n-dopants
• Polysilicon is better than metal for self-aligned gates because it
doesn’t melt during later processing

n+ Diffusion

28
 Dr. Avireni.S

• Historically dopants were diffused

• Usually high energy ion-implantation used today
• But n+ regions are still called diffusion

29
 Dr. Avireni.S

• Strip off oxide to complete patterning step

30
 Dr. Avireni.S
P-Diffusion/implantation

• Similar set of steps form p+ “diffusion” regions for

PMOS source and drain and substrate contact

p+ Diffusion
 Dr. Avireni.S
Contacts

Now we need to wire together the devices

Cover chip with thick field oxide (FO)
Etch oxide where contact cuts are needed

Contact
 Dr. Avireni.S
Metalization
• Sputter on aluminum over whole wafer
• Copper is used in newer technology
• Pattern to remove excess metal, leaving wires

Metal
 Dr. Avireni.S
Metallization: Contact to devices,
interconnections between devices and to external

34
 Dr. Avireni.S
Multi-level Metallization

Lower levels: fine

connections to
individual devices

Upper levels:
thicker/wider common
connections

Copper versus Aluminum

~ 40% lower resistivity
~ 10× less electromigration
 Dr. Avireni.S
Simple MOS process

(a) Source & drain p+ diffusion

(b) Wet oxidation for field oxide

(c) Dry oxidation for gate oxide

(d) Al metallization for gate and

contacts to S & D
 Dr. Avireni.S
CMOS Technology

Simple CMOS process

CMOS inverter
 Dr. Avireni.S
Poly-Si Gate NMOS Process

Field oxide growth and

opening etching

Gate oxide growth and poly-Si

deposit

Gate, source & drain n+

diffusion

PSG CVD, lithography and

metallization
Angstrom (Å) = 0.1 nanometer
38
 Dr. Avireni.S
Bonding & Packaging
Wafer with IC Chips

Thin film pads for

wire bonding
Encapsulation Processes Dr. Avireni.S
 Dr. Avireni.S
Plastic-encapsulated
Package

Back side of IC chip bond to a

metallized ceramic substrate

Aurum (Au ) wires

connecting the IC and pins
 Dr. Avireni.S
DIMENSIONS OF A MOS TRANSISTOR
Electrical Properties of MOS: IDS -VDS Relationship
 Dr. Avireni.S

ID versus VDS Relationship

44
 Dr. Avireni.S

When the gate-source voltage VGS, is larger than Vtn, the channel is
present. As VGS is increased, the density of electrons in the channel
increases. Indeed, the carries density, and therefore the charge
density, is proportional to VGS-Vtn, which is often called the
effective gate-source voltage denoted Veff. Specifically, define
Veff ≡ VGS -Vtn → (1)
The charge density of electrons is then given by
Qn = Cox(VGS – Vtn) = Cox Veff → (2)
Here, Cox is the gate capacitance per unit area and is given by
Cox = Koxε0 / tox → (3)
where Kox is the relative permittivity of SiO2 ( ≈ 3.9) and tox is the
thickness of the thin oxide under the gate.
 Dr. Avireni.S

To obtain the total gate capacitance (3) should be multiplied by the

effective gate area. WL, where W is the gate width and L is the
effective gate length. Thus the total gate capacitance Cq, is given by
Cg = W L Cox → (4)
and the total charge of the channel, QT-n, is given by
QT-n = W L Cox(VGS – Vtn) = WLCoxVeff → (5)
If the grain voltage is increased above 0V, a drain source potential
difference exists. This difference results in current flowing from the
drain to the source. The relationship between VDS and the drain-
source current, ID is the same as for a resistor, assuming VDS is
small. This relationship is given by
ID = µnQnVDS(W/L) → (6)
 Dr. Avireni.S

where µn is the mobility of electrons near the silicon surface, and

Qn is the charge concentration of the channel per unit area. Using
(5) and (6) results in

 (7)

where it should be emphasized that this relationship is only valid

for drain-source voltage near zero.
The triode region equation for a MOS transistor relates the drain
current to the gate-source and drain-source voltages. It can be
shown that this relationship is given by

 (8)
 Dr. Avireni.S

When VDS is increased so that VGD < Vtn, the channel becomes
pinched-off at the drain end.
 Dr. Avireni.S

As VDS increases, ID increases until the drain end of the channel

becomes pinched off, and then ID no longer increases. This pinch-
off occurs for VDG = -Vtn or approximately,
VDS = VGS – Vtn = Veff  (9)
Right at the edge of pinch-off, the drain current resulting from (8)
and the drain current in the active region must have the same
value. Therefore, the active region equation can be found by
substituting (9) in (8), resulting

 (10)

49
 Dr. Avireni.S
ID versus VDS curve for an ideal MOS transistor

The ID vs VDS curve for an ideal MOS transistor

Dr. Avireni.S
 Dr. Avireni.S
MOS Transistor Circuit T-Model
 Dr. Avireni.S
MOS Transistor Circuit ᴨ -Model
 Dr. Avireni.S
Pass Transistor

The output (Y) is logic high when the input (A) is logic high and
the switch-control signal (B) is logic high, and it is not logic high
for all other combinations.

54
Transmission Gate (or) Complementary Pass Transistor Logic
 Dr. Avireni.S
nMOS Inverter

56
 Dr. Avireni.S

• Dissipation is high since current flows when Vin = 1

• Vout can never reach Vdd (effect of channel)
• VGG can be derived from a switching source (i.e. one phase of a
clock, so that dissipation can be significantly reduced
• If VGG is higher than Vdd, and extra supply rail is required

V0
Vdd
Vt (pull up)

Non zero output

Vin
Vt (pull down)
Dr. Avireni.S
Dr. Avireni.S
(1)

60
 Dr. Avireni.S

This gives Zpu/Zpd = 4:1 for an nMOS inverter directly driven by another
inverter
 Dr. Avireni.S
CMOS Inverter
Complimentary Transistor Pull – Up (CMOS)
Vout Vtn Vtp 1: Logic 0 : p on ; n off

5: Logic 1: p off ; n on
P on N on
N off P off
Both On 2: Vin > Vtn.
Vdsn large – n in saturation
Vdsp small – p in resistive
Vin
Small current from Vdd to Vss
Vss Vdd
4: same as 2 except reversed p and n
1 2 3 4 5
3: Both transistors are in saturation
Large instantaneous current flows
 Dr. Avireni.S
References

1. Principles of CMOS VLSI Design: A system Perspective, By

Neil H.E. Weste and Kamaran Eshraghian, 2 Ed, Addison-
Wesley.
2. CMOS Circuit Design, Layout, and Simulation, By R. Jacob
Baker, Harry W. Li, and David E. Boyce, PHI Publications.
3. Introduction to VLSI Circuits And Systems, John P.
Uyemura, John Wiley & Sons
4. Images: amazon.com
5. http://www.intel.com/
Thank you
Prof. Avireni Srinivasulu.