Logic Synthesis with Verilog HDL

Logic Synthesis
• Synthesis is the process of converting a high-level description of the
design into an optimized gate-level representation, given a standard
cell library and certain design constraints
• A standard cell library can have simple cells, such as basic logic gates
(and, or, not) or macro cells, such as adders, multiplexers and flip-
flops.
• A standard cell library is also known as the technology library.
• The advent of computer-aided logic synthesis tools has automated
the process of converting the high-level description to logic gates.
• Logic synthesis tools cut design cycle times significantly. Designers can
design at a high level of abstraction and thus reduce design time.
Synthesis Process
Synthesis Design Flow
RTL description
• The designer describes the design at a high level by using RTL constructs.
• The designer spends time in functional verification to ensure that the RTL
description functions correctly.
• After the functionality is verified, the RTL description is input to the logic
synthesis tool.
Translation
• The RTL description is converted by the logic synthesis tool to an
unoptimized, intermediate, internal representation. The translator
understands the basic primitives and operators in the Verilog RTL
description.
• Design constraints such as area, timing, and power are not considered in
the translation process.
Technology mapping and optimization
• Until this step, the design description is independent of a specific target
technology.
• The synthesis tool takes the internal representation and implements the
representation in gates, using the cells provided in the technology library.
• The design is mapped to the desired target technology.
Technology library
• The technology library contains library cells provided by vendor.
• The library cells are the basic building blocks that will be used for IC fabrication.
• Library cells can be basic logic gates or macro cells such as adders, ALUs,
multiplexers, and flip-flops.
• Physical layout of library cells is done first. Then, the area of each cell is
computed from the cell layout. Next, modeling techniques are used to estimate
the timing and power characteristics of each library cell. This process is called cell
characterization
The cell description contains information about the following:
• Functionality of the cell
• Area of the cell layout
• Timing information about the cell
• Power information about the cell
Design constraints
Design constraints typically include the following:
Timing? The circuit must meet certain timing requirements. An internal static
timing analyzer checks timing.
Area? The area of the final layout must not exceed a limit.
Power? The power dissipation in the circuit must not exceed a threshold
In general, there is an inverse relationship between area and timing
constraints.

operating environment factors, such as input and output delays, drive

strengths, and loads will affect the optimization for the target technology
Optimized gate-level description
After the technology mapping is complete, an optimized gate-level
netlist described in terms of target technology components is
produced.
Synthesis information from Module

module system1 (a,b,d);

input a,b;
output d;
--
--
endmodule
module system3 (a,b,d);
input [3:0] a,b;
output [7:0]d;
--
--
endmodule
module system7 (a,b,d);
Parameter N=4;
Parameter M=3;
input [N:0]a,b;
output [M:0]d;
--
--
endmodule
Interpretation of a Few Verilog Constructs
The assign statement
assign out = (a & b) | c;

If a, b, c, and out are 2-bit vectors [1:0], then the above assign
statement will frequently translate to two identical circuits for each bit.
assign {c_out, sum} = a + b + c_in;

If a conditional operator ? is used, a multiplexer circuit is inferred.

assign out = (s) ? i1 : i0;

for loops
The for loops can be used to build cascaded combinational logic.
For example, the following for loop builds an 8-bit full adder:
c = c_in;
for(i=0; i <=7; i = i + 1)
{c, sum[i]} = a[i] + b[i] + c; // builds an 8-bit ripple adder
c_out = c;
The always statement
The always statement can be used to infer sequential and combinational logic.
For sequential logic, the always statement must be controlled by the change in the value of
a clock signal clk.

always @(posedge clk) q <= d;

This is inferred as a positive edge-triggered D-flip flop with d as input, q as output, and clk
as the clocking signal.

The following Verilog description creates a level-sensitive latch:

always @(clk or d)
if (clk) q <= d;
Mapping Always statement in the hardware domain
module system5 (x,y);
input x;
output y;
reg y;
always@(x)
begin
y=x;
end
endmodule
Mapping IF-ELSE statement

always @ (a, X)
begin
if (a == 1'b1)
Y = X;
else
Y = 1'b0;
end
Multiplexer
always @ (a, X, X1)
begin
if (a == 1'b1)
Y = X;
else
Y = X1;
end
 Signal Assignment
module example (x,y);
input[1:0]x;
output[3:0]y;
reg[3:0]y;
always@(x)
begin
Y=2*x+3;
end
endmodule
Truth table Logic Diagram

Simplified Expressions:
module IF_st (a, Y);
input [2:0] a;
output Y;
reg Y;
always @ (a)
begin
if (a < 3'b101)
Y = 1'b1;
else
Y = 1'b0;
end
endmodule
IF statement with storage
module If_store (a, X, Y);
input a, X;
output Y;
reg Y;
always @ (a, X)
begin
if (a == 1'b1)
Y = X;
end
endmodule
Mapping the case statement

module case_adder (a, b, ct, d);

input [3:0] a, b;
input ct;
output [4:0] d;
reg [4:0] d;
always @ (a, b, ct)
begin
case (ct)
1'b0 : d = a + b;

1'b1 : d = a - b;
endcase

end

endmodule
 Case statement with storage
module case_str (a, b, ct, d);
input [3:0] a, b;
input ct;
output [4:0] d;
reg [4:0] d;
always @ (a, b, ct)
begin
case (ct)
1'b0: d = a + b;
1'b1: ; /* This is a blank statement with
no operation */
endcase

end

endmodule
SYNTHESIS
module syn (ip,op);
input [3:0]ip;
output [2:0] op;
reg [2:0] op;
always@(ip)
begin
if (ip[0]=1’b1)
op=3’d7;
else if (ip[1]==1’b1)
op=3’d6;
else if (ip[2]==1’b1)
op=3’d5;
else
op=3’d0;
end
endmodule
Synthesis Example
module synthesisckt (x,y);
input [2:0]x;
output reg [3:0]y;
always@(x)
begin
if (x<=4)
y = 2*x + 5;
end
endmodule
X(2) X(1) X(0) clk X(2) X(1) X(0) Y(3) Y(2) Y(1) Y(0)
0 0 0 1 0 0 0 0 1 0 1
0 0 1 1 0 0 1 0 1 1 1
0 1 0 1 0 1 0 1 0 0 1
0 1 1 1 0 1 1 1 0 1 1
1 0 0 1 1 0 0 1 1 0 1
1 0 1 0 1 0 1 d d d d
1 1 0 0 1 1 0 d d d d
1 1 1 0 1 1 1 d d d d

Y(0)=1
Clk=x(2)’ + X(0)’ x(1)’ Y(1)=x(0)
Y(2)=x(1)’
Y(3)=x(1) + x(2)
Synthesis Example
module ckt(X, CLK, Z); nand G2(A2,Q1, Q3N, XN);
input X, CLK; nand G3(A3,X, Q1N, Q2N);
output Z; nand G4(D3,A1, A2, A3);
wire A1,A2, A3, A5, A6; DFF FF1(Q2N, CLK, Q1, Q1N);
wire D3; DFF FF2(Q1, CLK, Q2, Q2N);
wire Q1, Q2, Q3; DFF FF3(D3, CLK, Q3, Q3N);
wire Q1N, Q2N, Q3N, XN; nand G5(A5,X, Q3);
not I1(XN,X); nand G6(A6,XN, Q3N);
nand G1(A1,Q1, Q2, Q3); nand G7(Z,A5, A6);
endmodule
FSM
module fsm(A,clr,clk,z);
s1 : if (A==0) s3 : if (A==0)
input A,clr,clk; begin
output reg z; s<= s3; z<=0; begin

reg [1:0]s; end

else if (A==1) s<= s2; z<=1;
parameter s0=2'b00,s1=2'b01,s2=2'b10,s3=2'b11; begin
end
always@(negedge clr,negedge clk,s)
s<=s2; z<=0; else if (A==1)
begin
if (clr==0) s<=s0; end begin
else if (~clk) s2 : if (A==0)
s<=s0; z<=1;
case (s) begin
s0 :if (A==0) s<= s0; z<=0; end
end
begin endcase
s<= s0; z<=1; else if (A==1)
begin end
end s<=s3; z<=1; endmodule
else if (A==1) end
begin
s<=s1; z<=0;
end
Function Table
Present state Input Next state Output Flip-flop inputs
Q1 Q0 A Q1 Q0 Z D1 D0
0 0 0 0 0 1 0 0
0 0 1 0 1 0 0 1
0 1 0 1 1 0 1 1
0 1 1 1 0 0 1 0
1 0 0 0 0 1 0 0
1 0 1 1 1 1 1 1
1 1 0 1 0 1 1 0
1 1 1 0 0 1 0 0
Equations
Circuit diagram
module state_machine (A, clk, pres_st, Z); else else
input A, clk; begin begin
present = state0; present = state0;
output [1:0] reg pres_st;
Z = 1’b1; Z = 1’b0;
output reg Z; end
parameter state0=2’b00,state1 end
end end
=2’b01,state2=2’b10,state3=2’b11; state3 : begin if (A == 1)
state1 : begin if (A == 1)
reg [1:0] present; begin
begin
initial present = state2; present = state0;
begin Z = 1’b0; Z = 1’b0;
end end
pres_st = 2’b00;
else else
end begin
begin
always @ (posedge clk) present = state2;
present = state3;
begin Z = 1’b0; Z = 1’b0;
case (pres_st) end end
end end
state0 : begin if (A == 1)
state2 : begin if (A == 1) endcase
begin pres_st = present;
begin
present = state1; end
present = state3;
Z = 1’b0; Z = 1’b1; endmodule
end end
FSM
Modeling tips for logic synthesis
• Use meaningful names for signals and variables
• Do not use reserved keywords from Verilog as identifiers
• Do not use delays
• Do not use initial blocks.
• If possible, use concurrent assignments (assign) to design
combinational logic
• It is possible to use procedural assignments (always blocks) to design
either combinational logic or sequential logic.
• When procedural assignments (always blocks) are used for
combinational logic, use blocking assignments
• Combinatorial procedural blocks should be fully specified
• Specify complete sensitivity lists
• Do not make assignments to the same variable from more than one
always block.
• Avoid combinational feedback
• Use parentheses to optimize logic structures
Out = a + b + c + d; //3 adders in series
Out = (a + b) + (c + d); //2 adders in parallel and one final
adder to sum results
• Instantiate multiplexers instead of if-else or case statements
• Use case over if-then-else whenever priority structure not required
• Avoid latches (including else clauses for if statements, specifying all
cases for case statements or have a default clause at the end)
❑if (control)
out <= a; //latch is inferred, incomplete specification
❑ if (control)
out <= a;
else
out <= b; //complete specification for all values of control
• When procedural assignments (always block) are used for sequential
logic, use non-blocking assignments
• Do not mix blocking and non-blocking statements in an always block.
• Avoid mixing positive and negative edge-triggered flops-flops
• Use separate processes for sequential state register and
combinational logic
always@(posedge clk)
a <= b + c;
always@(b or c)
a_st = b + c;
always@(posedge clk)
a <= a_st;
JKFF
module jkff(
input j,k,clk,
output reg q,
output qb );
initial q=0;
always@(negedge clk)
begin
if (j==0 & k==0) q<=q;
else if (j==0 & k==1) q<=1'b0;
else if (j==1 & k==0) q<=1'b1;
else if (j==1 & k==1) q<=~q;
end
assign qb = ~q;
endmodule
Write a synthesizable code for JKFF
module jkff(
input j,k,clk,clr,pre,
output reg q,
output qb);
always@(negedge clk,negedge clr,negedge pre)
begin
if (clr==0) q<=1'b0;
else if (pre==0) q<=1'b1;
else if (~clk)
begin
if (j==0 & k==0) q<=q;
else if (j==0 & k==1) q<=1'b0;
else if (j==1 & k==0) q<=1'b1;
else if (j==1 & k==1) q<=~q;
end
end
assign qb = ~q;
endmodule