CH 7updated Unit 6 Computer Arithmetic

CHAPTER -05
COMPUTER ARITHMETIC
Magnitude Comparator:
A magnitude digital Comparator is a combinational circuit that compares
two digital or binary numbers in order to find out whether one binary
number is equal, less than, or greater than the other binary number.
The circuit is logically design for which we will have two inputs one for A
and the other for B and have three output terminals, one for A > B
condition, one for A = B condition, and one for A < B condition.
The circuit works by comparing the bits of the two numbers starting from
the most significant bit (MSB) and moving toward the least significant bit
(LSB).
At each bit position, the two corresponding bits of the numbers are
compared.
If the bit in the first number is greater than the corresponding bit in the
second number, the A>B output is set to 1, and the circuit immediately
determines that the first number is greater than the second.
Similarly, if the bit in the second number is greater than the
corresponding bit in the first number, the A<B output is set to 1, and the
circuit immediately determines that the first number is less than the
second.
If the two corresponding bits are equal, the circuit moves to the next bit
position and compares the next pair of bits. This process continues until
all the bits have been compared.
If at any point in the comparison, the circuit determines that the first
number is greater or less than the second number, the comparison is
terminated, and the appropriate output is generated.
If all the bits are equal, the circuit generates an A=B output, indicating
that the two numbers are equal.
A) 1-Bit Magnitude Comparator

A comparator used to compare two bits is called a single-bit comparator.
It consists of two inputs each for two single-bit numbers and three
outputs to generate less than, equal to, and greater than between two
binary numbers.
A>B: AB'
A<B: A'B
A=B: A'B' + AB
Arithmetic operations:
The four basic arithmetic operations are addition, subtraction,
multiplication and division.
Arithmetic processor is the part of processor to perform arithmetic
operation.
Algorithm is the finite number of well-defined procedural steps that

give solution to any problem.
Addition and subtraction algorithm:
1) Addition and subtraction of two signed magnitude binary numbers.
➔ Let us consider the two numbers A and B
a) When the sign of A and B are identical then add the two magnitudes
and attach the sign of A to the result.
b) When the sign of A and B are different then, compare the
magnitudes and subtract smaller number from larger number.
i) if A> B, Choose sign of A to be sign of result
ii) if A< B, complement the sign of A.
iii) if A=B, subtract B from A and make sign of result positive.
Example1 : perform the addition. (+5 ) + (-3)
Let A = +5
B = -3
Solutions: Sign of A = As = 0, Magnitude of A = 101

Sign of B = Bs = 1, Magnitude of B = 011
Computing As Xor Bs = As’Bs + AsBs’

= 1*1 + 0*0
=1
So, As not equal to Bs
Then EA = A+ B’ +1
= 101+ 100 + 1
= 1010
Here , E =1
Since A not equal to 0, Result is in A = 010 and As =0 so, +2
2) Addition and subtraction of two signed 2’s complement numbers.
Example:
Let A =10
B = -5
1) Perform subtraction (A – B)
Solution: Here , A =10 =1010

B = -5 = 1011
5 = 0101 in 4 bit
And -5 = 2’s complement of 5 = 1010 +1 = 1011

-5=1011
1011 complement = 0100
Now A-B = A +B’ +1

= 1010 + 0100 + 1 =1111
= 1111
2) Perform A + B
Solution: Here, A =10 =1010

B = -5 = 1011
A + B = 1010 + 1011
= 1 0101
V = 1 and Result = 0101
Multiplication Algorithms
- Shift- addition multiplication algorithm (unsigned Binary

Multiplication)
- Booth Multiplication algorithm (signed multiplication)
Booth Multiplication Algorithm
Figure: Hardware implementation of Unsigned Binary multiplication
Figure: Hardware implementation of Booth multiplication
Division algorithm
1) Restoring Division Algorithm

2) Non-Restoring Division Algorithm
Figure: Hardware implementation of Division algorithms
1) Restoring Division Algorithm

2) Non-Restoring Division Algorithm
A<-A- M A<-A+M
Result:
Quotient in Q = 0100 = 4
Remainder in A = 00010 = 2
Divide Overflow:
A divide overflow occurs when the result of a division operation exceeds
the representable range for the data type being used. In computer
systems, data types have a finite number of bits to represent values, and
if the result of a division operation cannot be accommodated within
those bits, a divide overflow occurs.
A) Data Type Limits: Each data type in a computer system has a specific
range of representable values. For example, an 8-bit unsigned integer
can represent values from 0 to 255. A 32-bit signed integer has a range
from -2,147,483,648 to 2,147,483,647.
B) Division Operation: When you perform a division operation, the result
may include a quotient and a remainder. The quotient is what you get
when you divide one number by another.
C) Overflow Condition: A divide overflow happens when the result of the

division (including the quotient and remainder) cannot be accurately
represented within the available bits for the data type. This can occur in
a few scenarios:
a) Dividing by Zero: Division by zero is undefined in mathematics and
computing. Attempting to divide by zero can result in a divide overflow
or trigger an error.
b)Result Exceeding Representable Range: If the result of the division
operation is too large (positive or negative) to fit within the allowed
range of the data type, a divide overflow occurs.
Example of divide overflow:
When you try to divide 00876002h by the contents of BX ( 10h ), the
result is 87600h and the remainder is 2. Now you should see why it
triggers an error: quotient 87600h is too big to fit into 16-bit register AX.
Divide overflow (alias division by zero) happens when the divisor is too
small.
Handling divide overflow:

Modern computer architectures typically include mechanisms to detect
and handle divide overflows. This might involve setting flags or triggering
exceptions. Programmers can then implement error-handling routines to
manage these exceptional conditions.
The condition of divide-overflow is checked by subtracting the divisor in
B from half of the bits of the dividend stored in A. If A ≥ B, the Divide
overflow flag(DVF) is set and the operation is terminated before time. If
A < B, no overflow condition occurs and so the value of the dividend is
reinstated by adding B to A.

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CHAPTER -05

A) 1-Bit Magnitude Comparator

Algorithm is the finite number of well-defined procedural steps that

Addition and subtraction algorithm:

1) Addition and subtraction of two signed magnitude binary numbers.

➔ Let us consider the two numbers A and B

Solutions: Sign of A = As = 0, Magnitude of A = 101

Computing As Xor Bs = As’Bs + AsBs’

So, As not equal to Bs

Solution: Here , A =10 =1010

And -5 = 2’s complement of 5 = 1010 +1 = 1011

Now A-B = A +B’ +1

Solution: Here, A =10 =1010

- Shift- addition multiplication algorithm (unsigned Binary

1) Restoring Division Algorithm

1) Restoring Division Algorithm

C) Overflow Condition: A divide overflow happens when the result of the

Handling divide overflow:

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