Grafic Rlink2

Product Sample & Technical Tools & Support & Reference
Folder Buy Documents Software Community Design
DS90UB926Q-Q1
SNLS422B – JULY 2012 – REVISED JANUARY 2015
DS90UB926Q-Q1 5- to 85-MHz 24-Bit Color FPD-Link III Deserializer With Bidirectional

Control Channel
1 Features 3 Description
1• Bidirectional Control Interface Channel Interface The DS90UB926Q-Q1 deserializer, in conjunction
With I2C Compatible Serial Control Bus with the DS90UB925Q-Q1 serializer, provides a
complete digital interface for concurrent transmission
• Supports High-Definition (720p) Digital Video of high-speed video, audio, and control data for
Format automotive display and image-sensing applications.
• RGB888 + VS, HS, DE and Synchronized I2S
This chipset translates a parallel RGB video interface
Audio Supported into a single-pair high-speed serialized interface. The
• 5- to 85-MHz PCLK Supported serial bus scheme, FPD-Link III, supports full duplex
• Single 3.3-V Operation With 1.8-V or 3.3-V of high-speed forward data transmission and low-
Compatible LVCMOS I/O Interface speed backchannel communication over a single
differential link. Consolidation of video data and
• AC-Coupled STP Interconnect up to 10 Meters control over a single differential pair reduces the
• Parallel LVCMOS Video Outputs interconnect size and weight, while also eliminating
• I2C Compatible Serial Control Bus for skew issues and simplifying system design.
Configuration The DS90UB926Q-Q1 deserializer recovers the RGB
• DC-balanced and Scrambled Data With data, three video control signals, and four
Embedded Clock synchronized I2S audio signals. The device extracts
• Adaptive Cable Equalization the clock from a high-speed serial stream. An output
LOCK pin provides the link status if the incoming data
• Supports Repeater Application stream is locked, without the use of a training
• @ SPEED Link BIST Mode and LOCK Status Pin sequence or special SYNC patterns, as well as a
• Image Enhancement (White Balance and reference clock.
Dithering) and Internal Pattern Generation The DS90UB926Q-Q1 deserializer has a 31-bit
• EMI Minimization (SSCG and EPTO) parallel LVCMOS output interface to accommodate
• Low Power Modes Minimize Power Dissipation the RGB, video control, and audio data.
• Automotive-Grade Product: AEC-Q100 Grade 2 An adaptive equalizer optimizes the maximum cable
Qualified reach. EMI is minimized by output SSC generation
(SSCG) and enhanced progressive turnon (EPTO)
• Greater than 8 kV HBM and ISO 10605 ESD
features.
Rating
• Backward Compatible to FPD-Link II Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
2 Applications DS90UB926Q-Q1 WQFN (60) 9.00 mm x 9.00 mm
• Automotive Display for Navigation (1) For all available packages, see the orderable addendum at
• Rear Seat Entertainment Systems the end of the data sheet.
• Automotive Drive Assistance

• Automotive Megapixel Camera Systems
VDDIO VDD33 VDD33 VDDIO
(1.8V or 3.3V) (3.3V) (3.3V) (1.8V or 3.3V)
RGB Digital Display Interface
R[7:0] FPD-Link III R[7:0]

G[7:0] 1 Pair / AC Coupled G[7:0]
HOST B[7:0] 0.1 PF 0.1 PF B[7:0]
HS HS RGB Display
Graphics DOUT+ RIN+ 720p
VS VS
Processor DE 24-bit color depth
DE
PCLK DOUT- RIN- PCLK
100: STP Cable
DS90UB925Q-Q1 PDB DS90UB926Q-Q1 LOCK
PDB
Serializer Deserializer PASS
OSS_SEL
3
I2S AUDIO OEN 3 I2S AUDIO
(STEREO) MODE_SEL MODE_SEL
(STEREO)
INTB INTB_IN MCLK
SCL SCL
SDA SDA
IDx DAP IDx DAP
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS90UB926Q-Q1
SNLS422B – JULY 2012 – REVISED JANUARY 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 7.2 Functional Block Diagram ....................................... 16
2 Applications ........................................................... 1 7.3 Feature Description................................................. 16
3 Description ............................................................. 1 7.4 Device Functional Modes........................................ 28
7.5 Programming........................................................... 31
4 Revision History..................................................... 2
7.6 Register Maps ......................................................... 33
5 Pin Configuration and Functions ......................... 3
8 Application and Implementation ........................ 45
6 Specifications......................................................... 6
8.1 Application Information............................................ 45
6.1 Absolute Maximum Ratings ..................................... 6
8.2 Typical Application .................................................. 46
6.2 ESD Ratings.............................................................. 6
6.3 Recommended Operating Conditions....................... 6 9 Power Supply Recommendations...................... 48
6.4 Thermal Information .................................................. 7 10 Layout................................................................... 48
6.5 DC Electrical Characteristics .................................... 7 10.1 Layout Guidelines ................................................. 48
6.6 AC Electrical Characteristics..................................... 9 10.2 Layout Example .................................................... 50
6.7 DC and AC Serial Control Bus Characteristics....... 10 11 Device and Documentation Support ................. 51
6.8 Timing Requirements .............................................. 10 11.1 Documentation Support ........................................ 51
6.9 Timing Requirements for the Serial Control Bus .... 11 11.2 Trademarks ........................................................... 51
6.10 Switching Characteristics ...................................... 11 11.3 Electrostatic Discharge Caution ............................ 51
6.11 Typical Characteristics .......................................... 15 11.4 Glossary ................................................................ 51
7 Detailed Description ............................................ 16 12 Mechanical, Packaging, and Orderable
7.1 Overview ................................................................. 16 Information ........................................................... 51
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (April 2013) to Revision B Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................... 1
Changes from Original (July 2012) to Revision A Page
• Corrected typo in table “DC and AC Serial Control Bus Characteristics” from VDDIO to VDD33, added “Note: BIST
is not available in backwards compatible mode.”, added Recommended FRC settings table, changed entire layout
of Data Sheet to TI format, added to Absolute Maximum Rating section, note (3): The maximum limit (VDDIO +0.3V)
does not apply to the PDB pin during the transition to the power down state (PDB transitioning from HIGH to LOW),
deleted derate from Maximum Power Dissipation Capacity at 25°C...................................................................................... 1
• Added "Note: BIST is not available in backwards compatible mode." ................................................................................. 23
2 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DS90UB926Q-Q1

DS90UB926Q-Q1
www.ti.com SNLS422B – JULY 2012 – REVISED JANUARY 2015
5 Pin Configuration and Functions
NKB Package
60-Pin WQFN With Exposed Thermal Pad
I2S_DA / GPO_REG6
Top View
ROUT0 / R0 / GPIO0
ROUT1 / R1 / GPIO1
ROUT2 / R2
ROUT4 / R4
ROUT5 / R5
ROUT6 / R6
ROUT7 / R7
ROUT3 / R3
BISTEN
VDDIO
LOCK
PASS
RES1
OEN
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
OSS_SEL 46 30 I2S_WC / GPO_REG7
RES0 47 29 VDD33_B
VDD33_A 48 28 ROUT8 / G0 / GPIO2
RIN+ 49 27 ROUT9 / G1 / GPIO3
RIN- 50 26 ROUT10 / G2
CMF 51 25 ROUT11 / G3
CMLOUTP 52 DS90UB926Q-Q1 24 VDDIO
CMLOUTN 53
TOP VIEW 23 ROUT12 / G4
NC 54 DAP = GND 22 ROUT13 / G5
CAPR12 55 21 ROUT14 / G6
IDx 56 20 ROUT15 / G7
CAPP12 57 19 ROUT16 / B0 / GPO_REG4
CAPI2S 58 18 ROUT17 / B1 / GPO_REG5 / I2S_DB
PDB 59 17 ROUT18 / B2
MCLK 60 16 BISTC / INTB_IN

10
11
12
13
14
15
1
9
VS
GPO_REG8 / I2S_CLK
SDA
SCL
CAPL12
PCLK
DE
HS
B7 / ROUT23
MODE_SEL
VDDIO
B5 / ROUT21
B6 / ROUT22
B3 / ROUT19
B4 / ROUT20
Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 3

DS90UB926Q-Q1
Pin Functions
PIN
I/O, TYPE DESCRIPTION
NAME NO.
LVCMOS PARALLEL INTERFACE
ROUT[23:0] / 41, 40, 39, 37, O, LVCMOS Parallel Interface Data Output Pins.
R[7:0], 36, 35, 34, 33, with pulldown Leave open if unused.
G[7:0], B[7:0] 28, 27, 26, 25, ROUT0 / R0 can optionally be used as GPIO0 and ROUT1 / R1 can optionally be used as
23, 22, 21, 20, GPIO1.
19, 18, 17, 14, ROUT8 / G0 can optionally be used as GPIO2 and ROUT9 / G1 can optionally be used as
12, 11, 10, 9 GPIO3.
ROUT16 / B0 can optionally be used as GPO_REG4 and ROUT17/ B1 can optionally be
used as I2S_DB / GPO_REG5.
HS 8 O, LVCMOS Horizontal Sync Output Pin
with pulldown Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
Control Signal Filter is enabled. There is no restriction on the minimum transition pulse
when the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130
PCLKs.
See Table 11
VS 7 O, LVCMOS Vertical Sync Output Pin
with pulldown Video control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width
is 130 PCLKs.
DE 6 O, LVCMOS Data Enable Output Pin
with pulldown Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
Control Signal Filter is enabled. There is no restriction on the minimum transition pulse
when the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130
PCLKs.
See Table 11
PCLK 5 O, LVCMOS Pixel Clock Output Pin. Strobe edge set by RFB configuration register. See Table 11
with pulldown
I2S_CLK, 1, 30, 45 O, LVCMOS Digital Audio Interface Data Output Pins
I2S_WC, with pulldown Leave open if unused
I2S_DA I2S_CLK can optionally be used as GPO_REG8, I2S_WC can optionally be used as
GPO_REG7, and I2S_DA can optionally be used as GPO_REG6.
MCLK 60 O, LVCMOS I2S Master Clock Output. x1, x2, or x4 of I2S_CLK Frequency.
with pulldown
OPTIONAL PARALLEL INTERFACE
I2S_DB 18 O, LVCMOS Second Channel Digital Audio Interface Data Output pin at 18–bit color mode and set by
with pulldown MODE_SEL or configuration register
Leave open if unused
I2S_B can optionally be used as BI or GPO_REG5.
GPIO[3:0] 27, 28, 40, 41 I/O, Standard General Purpose IOs.
LVCMOS Available only in 18-bit color mode, and set by MODE_SEL or configuration register. See
with pulldown Table 11
Leave open if unused
Shared with G1, G0, R1 and R0.
GPO_REG[8: 1, 30, 45, 18, O, LVCMOS General Purpose Outputs and set by configuration register. See Table 11
4] 19 with pulldown Shared with I2S_CLK, I2S_WC, I2S_DA, I2S_DB or B1, B0.
INTB_IN 16 Input, Interrupt Input
LVCMOS Shared with BISTC
with pulldown
OPTIONAL PARALLEL INTERFACE
PDB 59 I, LVCMOS Power-down Mode Input Pin
with pulldown PDB = H, device is enabled (normal operation)
Refer to Power Supply Recommendations.
PDB = L, device is powered down.
When the device is in the POWER DOWN state, the LVCMOS Outputs are in TRI-STATE,
the PLL is shutdown and IDD is minimized. .
OEN 31 Input, Output Enable Pin.
LVCMOS See Table 8
with pulldown
OSS_SEL 46 Input, Output Sleep State Select Pin.
LVCMOS See Table 8
with pulldown

DS90UB926Q-Q1
Pin Functions (continued)

PIN
I/O, TYPE DESCRIPTION
NAME NO.
MODE_SEL 15 I, Analog Device Configuration Select. See Table 9
IDx 56 I, Analog I2C Serial Control Bus Device ID Address Select
External pullup to VDD33 is required under all conditions, DO NOT FLOAT.
Connect to external pullup and pulldown resistor to create a voltage divider.
See Figure 23
SCL 3 I/O, I2C Clock Input / Output Interface
LVCMOS Must have an external pullup to VDD33, DO NOT FLOAT.
Open-Drain Recommended pullup: 4.7 kΩ.
SDA 2 I/O, I2C Data Input / Output Interface
LVCMOS Must have an external pullup to VDD33, DO NOT FLOAT.
Open-Drain Recommended pullup: 4.7 kΩ.
BISTEN 44 I, LVCMOS BIST Enable Pin.
with pulldown 0: BIST Mode is disabled.
1: BIST Mode is enabled.
BISTC 16 I, LVCMOS BIST Clock Select.
with pulldown Shared with INTB_IN
0: PCLK; 1: 33 MHz
STATUS
LOCK 32 O, LVCMOS LOCK Status Output Pin
with pulldown 0: PLL is unlocked, ROUT[23:0]/RGB[7:0], I2S[2:0], HS, VS, DE and PCLK output states
are controlled by OEN. May be used as Link Status or Display Enable
1: PLL is Locked, outputs are active
PASS 42 O, LVCMOS PASS Output Pin
with pulldown 0: One or more errors were detected in the received payload
1: ERROR FREE Transmission
Leave Open if unused. Route to test point (pad) recommended
FPD-LINK III SERIAL INTERFACE
RIN+ 49 I, LVDS True Input.
The interconnection should be AC-coupled to this pin with a 0.1-μF capacitor.
RIN- 50 I, LVDS Inverting Input.
The interconnection should be AC-coupled to this pin with a 0.1-μF capacitor.
CMLOUTP 52 O, LVDS True CML Output
Monitor point for equalized differential signal
CMLOUTN 53 O, LVDS Inverting CML Output
Monitor point for equalized differential signal
CMF 51 Analog Common Mode Filter. Connect 0.1-μF capacitor to GND
(1)
POWER AND GROUND
VDD33_A, 48, 29 Power Power to on-chip regulator 3.0 V – 3.6 V. Requires 4.7 uF to GND at each VDD pin.
VDD33_B
VDDIO 13, 24, 38 Power LVCMOS I/O Power 1.8 V ±5% OR 3.0 V – 3.6 V. Requires 4.7 uF to GND at each VDDIO
pin.
GND DAP Ground DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connect to the ground plane (GND) with at least 9 vias.
REGULATOR CAPACITOR
CAPR12, 55, 57, 58 CAP Decoupling capacitor connection for on-chip regulator. Requires a 4.7uF to GND at each
CAPP12, CAP pin.
CAPI2S
CAPL12 4 CAP Decoupling capacitor connection for on-chip regulator. Requires two 4.7uF to GND at this
CAP pin.
OTHERS
NC 54 NC No connect. This pin may be left open or tied to any level.
RES[1:0] 43.47 GND Reserved. Tie to Ground.
(1) The VDD (VDD33 and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise.

DS90UB926Q-Q1
6 Specifications
6.1 Absolute Maximum Ratings
See (1) (2) (3) (4).
MIN MAX UNIT
Supply Voltage – VDD33 −0.3 4.0 V
Supply Voltage – VDDIO −0.3 4.0 V
LVCMOS I/O Voltage (VDDIO +
−0.3 V
0.3)
Deserializer Input Voltage −0.3 2.75 V
Junction Temperature 150 °C
Storage temperature, Tstg −65 150 °C
Maximum Power Dissipation RθJA 31 °C/W
Capacity at 25°C
RθJC 2.4 °C/W
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) The maximum limit (VDDIO +0.3V) does not apply to the PDB pin during the transition to the power down state (PDB transitioning from
HIGH to LOW).
(4) For soldering specifications: see product folder at www.ti.com and SNOA549.
6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per AEC Q100-002 (1) ±8000
Charged-device model (CDM), per AEC Q100-011 ±1250
Machine model ±250
(IEC, powered-up only) Air Discharge (Pin 49 and 50) ±15000
Electrostatic RD = 330 Ω, CS = 150 pF
V(ESD) Contact Discharge (Pin 49 and 50) ±8000 V
discharge
(ISO1060SN5), RD = 330 Ω Air Discharge (Pin 49 and 50) ±15000
CS = 150 pF Contact Discharge (Pin 49 and 50) ±8000
(ISO10605), RD = 2 kΩ Air Discharge (Pin 49 and 50) ±15000
CS = 150 and 330 pF Contact Discharge (Pin 49 and 50) ±8000
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
Supply Voltage (VDD33) 3 3.3 3.6 V
Connect VDDIO to 3.3 V and use 3.3-V IOs 3 3.3 3.6 V
LVCMOS Supply Voltage (VDDIO)
Connect VDDIO to 1.8 V and use 1.8-V IOs 1.71 1.8 1.89 V
Operating Free Air Temperature (TA) −40 +25 +105 °C
PCLK Frequency 5 85 MHz
Supply Noise (1) 100 mVP-P
(1) Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the VDD33 and VDDIOsupplies
with amplitude = 100 mVp-p measured at the device VDD33 and VDDIO pins. Bit error rate testing of input to the Ser and output of the
Des with 10 meter cable shows no error when the noise frequency on the Ser is less than 50MHz. The Des on the other hand shows no
error when the noise frequency is less than 50 MHz.

DS90UB926Q-Q1
6.4 Thermal Information

DS90UB926Q-Q1
THERMAL METRIC (1) NKB (WQFN) UNIT
60 PINS
RθJA Junction-to-ambient thermal resistance 26.2
RθJC(top) Junction-to-case (top) thermal resistance 8.1
RθJB Junction-to-board thermal resistance 5.2
°C/W
ψJT Junction-to-top characterization parameter 0.1
ψJB Junction-to-board characterization parameter 5.2
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.1
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 DC Electrical Characteristics

over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3)
PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT

LVCMOS I/O DC SPECIFICATIONS
VIH High Level Voltage VDDIO = 3.0 to 3.6 V 2.0 VDDIO V
VIL Low Level Input VDDIO = 3.0 to 3.6 V GND 0.8 V
PDB
VIN = 0 V or VDDIO = 3.0 to
IIN Input Current –10 ±1 +10 uA
3.6 V
VDDIO = 3.0 to 3.6 V 2.0 VDDIO
VIH High Level Input Voltage 0.65 ×
VDDIO = 1.71 to 1.89 V VDDIO
VDDIO
V
VDDIO = 3.0 to 3.6 V GND 0.8
VIL Low Level Input Voltage OEN, OSS_SEL, 0.35 ×
VDDIO = 1.71 to 1.89 V BISTEN, BISTC / GND
VDDIO
INTB_IN,
VDDIO = GPIO[3:0]
3.0 −10 ±1 +10
VIN = 0 V or to 3.6 V
IIN Input Current μA
VDDIO VDDIO =
1.7 −10 ±1 +10
to 1.89 V
VDDIO =
3.0 to 3.6 2.4 VDDIO
V
VOH High Level Output Voltage IOH = −4mA
VDDIO =
VDDIO-
1.7 VDDIO
ROUT[23:0], HS, 0.45
to 1.89 V
VS, DE, PCLK, V
VDDIO = LOCK, PASS,
3.0 to 3.6 MCLK, I2S_CLK, GND 0.4
V I2S_WC, I2S_DA,
VOL Low Level Output Voltage IOL = +4mA
VDDIO = I2S_DB,
1.7 GPO_REG[8:4] GND 0.35
to 1.89 V
IOS Output Short Circuit Current VOUT = 0 V −60 mA
VOUT = 0 V or VDDIO, PDB =
IOZ Tri-state Output Current −10 +10 μA
L
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) Typical values represent most likely parametric norms at VDD = 3.3 V, TA = 25°C, and at the Recommended Operation Conditions at the
time of product characterization and are not ensured.
(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD, which are differential voltages.

DS90UB926Q-Q1
DC Electrical Characteristics (continued)

over recommended operating supply and temperature ranges unless otherwise specified.(1) (2) (3)
FPD-LINK III CML RECEIVER INPUT DC SPECIFICATIONS
Differential Threshold High
VTH +50 mV
Voltage VCM = 2.5 V
Differential Threshold Low (Internal VBIAS)
VTL −50 mV
Voltage
RIN+, RIN-
Differential Common-mode
VCM 1.8 V
Voltage
Internal Termination Resistor -
RT 80 100 120 Ω
Differential
CML MONITOR DRIVER OUTPUT DC SPECIFICATIONS
CMLOUTP,
VODp-p Differential Output Voltage RL = 100Ω 360 mVp-p
CMLOUTN
SUPPLY CURRENT
VDD33=
IDD1 VDD33 125 145
3.6 V
CL = 12pF,
Supply Current
Checker Board VDDIO=
(includes load current) 110 118
Pattern 3.6 V
IDDIO1 f = 85MHz VDDIO
(Figure 1)
VDDIO =
60 75
1.89 V
VDD33 =
IDD2 VDD33 125 145
3.6 V
CL = 4pF
Supply Current
Checker Board VDDIO =
(includes load current) 75 85
Pattern 3.6 V
IDDIO2 f = 85MHz VDDIO
(Figure 1)
VDDIO =
50 65
1.89 V
mA
VDD33 =
IDDS VDD33 90 115
3.6 V
Without Input VDDIO =
Supply Current Sleep Mode 3 5
Serial Stream 3.6 V
IDDIOS VDDIO
VDDIO =
2 3
1.89 V
VDD33 =
IDDZ VDD33 2 10
3.6 V
PDB = L, All
LVCMOS inputs VDDIO =
Supply Current Power Down 0.05 10
are floating or 3.6 V
IDDIOZ tied to GND VDDIO
VDDIO =
0.05 10
1.89 V

DS90UB926Q-Q1
6.6 AC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3)

GPIO BIT RATE
Forward Channel Bit Rate f = 5 – 85MHz, 0.25 × f Mbps
BR See (4) (5)
Back Channel Bit Rate GPIO[3:0] >50 >75 kbps
CML MONITOR DRIVER OUTPUT AC SPECIFICATIONS
Differential Output Eye Opening CMLOUTP,
EW RL = 100Ω, 0.3 0.4 UI
Width (6) CMLOUTN,
Jitter Freq >f / 40 (Figure 2) (4) (5)
EH Differential Output Eye Height f = 85MHz 200 300 mV
BIST MODE
tPASS BIST PASS Valid Time 800 ns
PASS
BISTEN = H (Figure 8) (4) (5)
SSCG MODE
Spread Spectrum Clocking ±0.5% ±2.5%
fDEV
Deviation Frequency See Figure 14, Table 1, Table 2 f = 85MHz,
(4) (5)
Spread Spectrum Clocking SSCG = ON 8 100 kHz
fMOD
Modulation Frequency
are not ensured.
(2) Typical values represent most likely parametric norms at VDD = 3.3V, TA = 25°C, and at the Recommended Operation Conditions at the
(4) Specification is ensured by characterization and is not tested in production.
(5) Specification is ensured by design and is not tested in production.
(6) UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / 35*PCLK). The UI scales with PCLK frequency.

DS90UB926Q-Q1
6.7 DC and AC Serial Control Bus Characteristics

Over 3.3-V supply and temperature ranges unless otherwise specified. (1) (2) (3)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VIH Input High Level SDA and SCL 0.7 ×
VDD33 V
VDD33
VIL Input Low Level Voltage SDA and SCL 0.3 ×
GND V
VDD33
VHY Input Hysteresis >50 mV
VOL SDA, IOL = 1.25mA 0 0.36 V
Iin SDA or SCL, Vin = VDD33 or GND –10 +10 µA
tR SDA RiseTime – READ 430 ns
SDA, RPU = 10kΩ, Cb ≤ 400pF (Figure 9)
tF SDA Fall Time – READ 20 ns
tSU;DAT Set Up Time — READ See Figure 9 560 ns
tHD;DAT Hold Up Time — READ See Figure 9 615 ns
tSP Input Filter 50 ns
Cin Input Capacitance SDA or SCL <5 pF
are not ensured.
(2) Typical values represent most likely parametric norms at VDD = 3.3 V, TA = 25°C, and at the Recommended Operation Conditions at the
6.8 Timing Requirements

MIN NOM MAX UNIT
tR SDA RiseTime – READ SDA, RPU = 10kΩ, Cb ≤ 430 ns
tF SDA Fall Time – READ 400pF (Figure 9) 20 ns
tSU;DAT Set Up Time — READ See Figure 9 560 ns
tHD;DAT Hold Up Time — READ See Figure 9 615 ns
tSP Input Filter 50 ns

DS90UB926Q-Q1
6.9 Timing Requirements for the Serial Control Bus

Over 3.3-V supply and temperature ranges unless otherwise specified.
MIN NOM MAX UNIT
fSCL Standard Mode 0 100 kHz
SCL Clock Frequency
Fast Mode 0 400 kHz
tLOW Standard Mode 4.7 µs
SCL Low Period
Fast Mode 1.3 µs
tHIGH Standard Mode 4.0 µs
SCL High Period
Fast Mode 0.6 µs
tHD;STA Hold time for a start or a Standard Mode 4.0 µs
repeated start condition
(Figure 9) Fast Mode 0.6 µs
tSU:STA Set Up time for a start or a Standard Mode 4.7 µs
repeated start condition
(Figure 9) Fast Mode 0.6 µs
tHD;DAT Standard Mode 0 3.45 µs
Data Hold Time (Figure 9)
Fast Mode 0 0.9 µs
tSU;DAT Standard Mode 250 ns
Data Set Up Time (Figure 9)
Fast Mode 100 ns
tSU;STO Set Up Time for STOP Standard Mode 4.0 µs
Condition (Figure 9) Fast Mode 0.6 µs
tBUF Bus Free Time between STOP Standard Mode 4.7 µs
and START (Figure 9)
Fast Mode 1.3 µs
tr SCL & SDA Rise Time Standard Mode 1000 ns
(Figure 9) Fast Mode 300 ns
tf SCL & SDA Fall Time Standard Mode 300 ns
(Figure 9) Fast mode 300 ns
6.10 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
tRCP PCLK Output Period tRCP = tTCP 11.76 T 200 ns
PCLK
tRDC PCLK Output Duty Cycle 45% 50% 55%
VDDIO = 1.71 - 1.89 V,
2 3 ns
LVCMOS Low-to-High CL = 12pF
tCLH
Transition Time (Figure 3) VDDIO = 3.0 – 3.6 V,
2 3 ns
CL = 12pF
VDDIO = 1.71 - 1.89 V,
2 3 ns
LVCMOS High-to-Low CL = 12pF
tCHL
Transition Time (Figure 3) VDDIO = 3.0 – 3.6 V, ROUT[23:0], HS, VS,
DE, PCLK, LOCK, 2 3 ns
CL = 12pF
PASS, MCLK,
VDDIO = 1.71 - 1.89 V, I2S_CLK, I2S_WC,
Data Valid before PCLK – 2.2 ns
CL = 12pF I2S_DA, I2S_DB
tROS Setup Time
SSCG = OFF (Figure 6) VDDIO = 3.0 – 3.6 V,
2.2 ns
CL = 12pF
VDDIO = 1.71 - 1.89 V,
Data Valid after PCLK – Hold 3.0 ns
CL = 12pF
tROH Time
SSCG = OFF (Figure 6) VDDIO = 3.0 – 3.6 V,
3.0 ns
CL = 12pF

DS90UB926Q-Q1
Switching Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)
ROUT[23:0] 10 ns
HS, VS, DE, PCLK,
15 ns
Active to OFF Delay LOCK, PASS
tXZR OEN = L, OSS_SEL = H
(Figure 5) (1) (2)
MCLK, I2S_CLK,
I2S_WC, I2S_DA, 60 ns
I2S_DB
tDDLT Lock Time (Figure 5) (3) (1) (2)
SSCG = OFF f = 5 – 85MHz 5 40 ns
(1) (2)
tDD Delay – Latency f = 5 – 85MHz 147*T ns
f = 5 – <15 MHz 0.5 ns
(1) (2) f = 15 – 85 MHz 0.2 ns
tDCCJ Cycle-to-Cycle Jitter SSCG = OFF
I2S_CLK = 1 -
±2 ns
12.28MHz
VDDIO = 1.71 - 1.89 V,
50 ns
Data Valid After OEN = H CL = 12pF
tONS
SetupTime (Figure 7) (1) (2) VDDIO = 3.0 – 3.6 V,
50 ns
CL = 12pF
VDDIO = 1.71 - 1.89 V,
50 ns
Data Tri-State After OEN = L CL = 12pF
tONH
SetupTime (Figure 7) (1) (2) VDDIO = 3.0 – 3.6 V, ROUT[23:0], HS, VS, 50 ns
CL = 12pF DE, PCLK, MCLK,
VDDIO = 1.71 - 1.89 V, I2S_CLK, I2S_WC,
Data Tri-State after OSS_ I2S_DA, I2S_DB 5 ns
CL = 12pF
tSES SEL = H, Setup Time
(Figure 7) (1) (2) VDDIO = 3.0 – 3.6 V,
5 ns
CL = 12pF
VDDIO = 1.71 - 1.89 V,
Data to Low after OSS_SEL 5 ns
CL = 12pF
tSEH = L Setup Time (Figure 7) (1)
(2) VDDIO = 3.0 – 3.6 V,
5 ns
CL = 12pF
(1) Specification is ensured by characterization and is not tested in production.

(2) Specification is ensured by design and is not tested in production.
(3) tDDLT is the time required by the device to obtain lock when exiting power-down state with an active serial stream.
VDDIO
PCLK
GND
VDDIO
ROUT[n] (odd),
VS, HS
GND
VDDIO
ROUT[n] (even),
DE
GND
Figure 1. Checker Board Data Pattern
EW
VOD (+)
CMLOUT
EH 0V
(Diff.)
EH
VOD (-)
tBIT (1 UI)
Figure 2. CML Output Driver


DS90UB926Q-Q1
VDDIO
80%
20%
GND
tCLH tCHL
Figure 3. LVCMOS Transition Times
START STOP START STOP

BIT BIT BIT BIT
RIN 3 3
0 1 2 0 1 2
(Diff.) 3 3
SYMBOL N SYMBOL N+1
tDD
PCLK
(RFB = L)
ROUT[23:0],
I2S[2:0], SYMBOL N-2 SYMBOL N-1 SYMBOL N
HS, VS, DE
Figure 4. Delay - Latency
PDB 2.0V
0.8V
RIN }v[
(Diff.)
tDDLT
TRI-STATE
LOCK or LOW
Z or L
tXZR
ROUT[23:0],
HS, VS, DE, TRI-STATE or LOW or Pulled Up Z or L or PU
I2S
PCLK TRI-STATE or LOW Z or L

(RFB = L)
OFF IN LOCK TIME ACTIVE OFF
Figure 5. PLL Lock Times and PDB TRI-STATE Delay
VDDIO
PCLK
1/2 VDDIO
w/ RFB = H
GND
ROUT[23:0], VDDIO
VOHmin
VS, HS, DE,
VOLmax
I2S GND
tROS tROH
Figure 6. Output Data Valid (Setup and Hold) Times With SSCG = Off

DS90UB926Q-Q1
PDB= H
VIH
OSS_SEL VIL
VIH
OEN
VIL
RIN }v[
(Diff.)
tSEH
tSES tONS tONH
LOCK
TRI-STATE
(HIGH)
PASS ACTIVE HIGH

HIGH
ROUT[23:0],
HS, VS, DE, LOW TRI-STATE ACTIVE TRI-STATE
LOW
I2S[2:0]
PCLK
LOW TRI-STATE ACTIVE TRI-STATE
(RFB = L) LOW
Figure 7. Output State (Setup and Hold) Times
SDA
SCL
S P
START condition, or STOP condition
START repeat condition
Figure 8. BIST PASS Waveform
tr
tf
tBUF
SDA
tSU;DAT tHD;STA tSU;STO

tLOW tSP
tf tSU;STA
tHD;DAT
SCL
tr tHIGH
tHD;STA
S Sr P S
Figure 9. Serial Control Bus Timing Diagram


DS90UB926Q-Q1
6.11 Typical Characteristics

CML Serializer Data Throughput
78 MHz TX
Pixel Clock
(200 mV/DIV)
Input
(2 V/DIV)
78 MHz RX
Pixel Clock
Output
(2 V/DIV)
Time (1.25 ns/DIV)
Time (10 ns/DIV)

Note: On the rising edge of each clock period, the CML driver
outputs a low Stop bit, high Start bit, and 33 DC-scrambled data
bits.
Figure 10. Serializer CML Driver Output Figure 11. Comparison of Deserializer LVCMOS RX PCLK
With 78-MHZ TX Pixel Clock Output Locked to a 78-MHz TX PCLK

DS90UB926Q-Q1
7 Detailed Description
7.1 Overview
The DS90UB926Q-Q1 deserializer receives a 35-bits symbol over a single serial FPD-Link III pair operating up to
2.975-Gbps application payload. The serial stream contains an embedded clock, video control signals and the
DC-balanced video data and audio data which enhance signal quality to support AC coupling.
The DS90UB926Q-Q1 deserializer attains lock to a data stream without the use of a separate reference clock
source, which greatly simplifies system complexity and overall cost. The deserializer also synchronizes to the
serializer regardless of the data pattern, delivering true automatic “plug and lock” performance. It can lock to the
incoming serial stream without the need of special training patterns or sync characters. The deserializer recovers
the clock and data by extracting the embedded clock information, validating then deserializing the incoming data
stream. The recovered parallel LVCMOS video bus is then provided to the display. The deserializer is intended
for use with the DS90UB925Q-Q1 serializer, but is also backward-compatible with DS90UR905Q or
DS90UR907Q FPD-Link II serializer.
7.2 Functional Block Diagram
REGULATOR SSCG
CMF DC Balance Decoder

24
Serial to Parallel
ROUT [23:0]
Output Latch HS
RIN+
VS
RIN- DE
4 I2S_CLK
CMLOUTP I2S_WC
CMLOUTN I2S_DA
MCLK
BISTEN Error PASS

BISTC Detector
PDB
SCL Clock and
Timing and PCLK
SCA Data
Control
IDx Recovery LOCK
MODE_SEL
DS90UB926Q-Q1 Deserializer
7.3 Feature Description

7.3.1 High-Speed Forward Channel Data Transfer
The High-Speed Forward Channel (HS_FC) is composed of 35 bits of data containing DIN[23:0] or RGB[7:0] or
YUV data, sync signals, I2C, and I2S audio transmitted from Serializer to Deserializer. Figure 12 illustrates the
serial stream per PCLK cycle. This data payload is optimized for signal transmission over an AC-coupled link.
Data is randomized, balanced and scrambled.
C1
C0
Figure 12. FPD-Link III Serial Stream

DS90UB926Q-Q1
Feature Description (continued)

The device supports clocks in the range of 5 MHz to 85 MHz. The application payload rate is 2.975 Gbps
maximum (175 Mbps minimum) with the actual line rate of 2.975 Gbps maximum and 525 Mbps Minimum.
7.3.2 Low-Speed Back Channel Data Transfer

The Low-Speed Backward Channel (LS_BC) of the DS90UB926Q-Q1 provides bidirectional communication
between the display and host processor. The information is carried back from the Deserializer to the Serializer
per serial symbol. The back channel control data is transferred over the single serial link along with the high-
speed forward data, DC balance coding and embedded clock information. This architecture provides a backward
path across the serial link together with a high-speed forward channel. The back channel contains the I2C, CRC
and 4 bits of standard GPIO information with 10-Mbps line rate.
7.3.3 Backward Compatible Mode

The DS90UB926Q-Q1 is also backward-compatible to DS90UR905Q and DS90UR907Q FPD Link II serializers
at 15 - 65 MHz pixel clock frequencies. It receives 28-bits of data over a single serial FPD-Link II pair operating
at the line rate of 420 Mbps to 1.82 Gbps. This backward compatible mode is provided through the MODE_SEL
pin (Table 9) or the configuration register (Table 11). In this mode, the minimum PCLK frequency is 15 MHz.
7.3.4 Input Equalization Gain

FPD-Link III input adaptive equalizer provides compensation for transmission medium losses and reduces the
medium-induced deterministic jitter. It equalizes up to 10-m STP cables with 3 connection breaks at maximum
serialized stream payload rate of 2.975 Gbps.
7.3.5 Common Mode Filter Pin (CMF)

The deserializer provides access to the center tap of the internal termination. A capacitor must be placed on this
pin for additional common-mode filtering of the differential pair. This can be useful in high noise environments for
additional noise rejection capability. A 0.1-μF capacitor has to be connected to this pin to Ground.
7.3.6 Video Control Signal Filter

When operating the devices in Normal Mode, the Video Control Signals (DE, HS, VS) have the following
restrictions:
• Normal Mode with Control Signal Filter Enabled: DE and HS — Only 2 transitions per 130 clock cycles are
transmitted, the transition pulse must be 3 PCLK or longer.
• Normal Mode with Control Signal Filter Disabled: DE and HS — Only 2 transitions per 130 clock cycles are
transmitted, no restriction on minimum transition pulse.
• VS — Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.
Video Control Signals are defined as low frequency signals with limited transitions. Glitches of a control signal
can cause a visual display error. This feature allows for the chipset to validate and filter out any high-frequency
noise on the control signals. See Figure 13.

DS90UB926Q-Q1
Feature Description (continued)
PCLK
IN
HS/VS/DE
IN
Latency
PCLK
OUT
HS/VS/DE Pulses 1 or 2
OUT PCLKs wide
Filetered OUT
Figure 13. Video Control Signal Filter Waveform
7.3.7 EMI Reduction Features
7.3.7.1 Spread Spectrum Clock Generation (SSCG)

The DS90UB926Q-Q1 provides an internally generated spread spectrum clock (SSCG) to modulate its outputs.
Both clock and data outputs are modulated. This will aid to lower system EMI. Output SSCG deviations to ±2.5%
(5% total) at up to 100-kHz modulations are available. This feature may be controlled by register. See Table 1,
Table 2, and Table 11.
Frequency
FPCLK+ fdev(max)
FPCLK
FPCLK- fdev(min)
Time
1/fmod
Figure 14. SSCG Waveform
Table 1. SSCG Configuration

LFMODE = L (15 - 85 MHz)
SSCG CONFIGURATION (0x2C) LFMODE = L (15 - 85 MHz) SPREAD SPECTRUM OUTPUT
SSC[2] SSC[1] SSC[0] Fdev (%) Fmod (kHz)
L L L ±0.9 PCLK / 2168
L L H ±1.2
L H L ±1.9
L H H ±2.5
H L L ±0.7 PCLK / 1300
H L H ±1.3
H H L ±2.0
H H H ±2.5

DS90UB926Q-Q1
Table 2. SSCG Configuration

LFMODE = H (5 - <15 MHz)
SSCG CONFIGURATION (0x2C) LFMODE = H (5 - <15 MHz) SPREAD SPECTRUM OUTPUT
SSC[2] SSC[1] SSC[0] Fdev (%) Fmod (kHz)
L L L ±0.5 PCLK / 628
L L H ±1.3
L H L ±1.8
L H H ±2.5
H L L ±0.7 PCLK / 388
H L H ±1.2
H H L ±2.0
H H H ±2.5
7.3.8 Enhanced Progressive Turn-On (EPTO)

The deserializer LVCMOS parallel outputs timing are delayed. Groups of 8-bit R, G and B outputs switch in a
different time. This minimizes the number of outputs switching simultaneously and helps to reduce supply noise.
In addition, it spreads the noise spectrum out reducing overall EMI.
7.3.9 LVCMOS VDDIO Option

The deserializer parallel bus can operate with 1.8 V or 3.3 V levels (VDDIO) for target (Display) compatibility.
The 1.8 V levels will offer a lower noise (EMI) and also a system power savings.
7.3.10 Power Down (PDB)

The Serializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin can be controlled by the
host or through the VDDIO, where VDDIO = 3 V to 3.6 V or VDD33. To save power disable the link when the display
is not needed (PDB = LOW). When the pin is driven by the host, make sure to release it after VDD33 and VDDIO
have reached final levels; no external components are required. In the case of driven by the VDDIO = 3 V to 3.6 V
or VDD33 directly, a 10-kΩ resistor to the VDDIO = 3.0V to 3.6V or VDD33 , and a >10-µF capacitor to the ground are
required (See Figure 24).
7.3.11 Stop Stream Sleep

The deserializer enters a low power SLEEP state when the input serial stream is stopped. A STOP condition is
detected when the embedded clock bits are not present. When the serial stream starts again, the deserializer will
then lock to the incoming signal and recover the data.
NOTE
In STOP STREAM SLEEP, the Serial Control Bus Registers values are retained.
7.3.12 Serial Link Fault Detect

The serial link fault detection is able to detect any of following 7 conditions
1. cable open
2. + to - short
3. + short to GND
4. - short to GND
5. + short to battery
6. - short to battery
7. cable is linked incorrectly
If any one of the fault conditions occurs, The Link Detect Status is 0 (cable is not detected) on the Serial Control
Bus Register bit 0 of address 0x1C Table 11. The link errors can be monitored though Link Error Count of the
Serial Control Bus Register bit [4:0] of address 0x41 Table 11.

DS90UB926Q-Q1
7.3.13 Oscillator Output

The deserializer provides an optional PCLK output when the input clock (serial stream) has been lost. This is
based on an internal oscillator. The frequency of the oscillator may be selected. This feature is controlled by
register Address 0x02, bit 5 (OSC Clock Enable). See Table 11.
7.3.14 Pixel Clock Edge Select (RFB)

The RFB determines the edge that the data is strobed on. If RFB is High (‘1’), output data is strobed on the
Rising edge of the PCLK. If RFB is Low (‘0’), data is strobed on the Falling edge of the PCLK. This allows for
inter-operability with downstream devices. The deserializer output does not need to use the same edge as the
Ser input. This feature may be controlled by register. See Table 11.
7.3.15 Image Enhancement Features

Several image enhancement features are provided. White balance LUTs allow the user to define and target the
color temperature of the display. Adaptive Hi-FRC dithering enables the presentation of “true-color” images on an
18–bit color display.
7.3.15.1 White Balance

The White Balance feature enables similar display appearance when using LCDs from different vendors. It
compensates for native color temperature of the display, and adjusts relative intensities of R, G, B to maintain
specified color temperature. Programmable control registers are used to define the contents of three LUTs (8-bit
color value for Red, Green and Blue) for the white balance feature. The LUTs map input RGB values to new
output RGB values. There are three LUTs, one LUT for each color. Each LUT contains 256 entries, 8-bits per
entry with a total size of 6144 bits (3 x 256 x 8). All entries are readable and writable. Calibrated values are
loaded into registers through the I2C interface (deserializer is a slave device). This feature may also be applied
to lower color depth applications such as 18–bit (666) and 16–bit (565). White balance is enabled and configured
through the serial control bus register.
7.3.15.1.1 LUT Contents

The user must define and load the contents of the LUT for each color (R,G,B). Regardless of the color depth
being driven (888, 666, 656), the user must always provide contents for 3 complete LUTs - 256 colors x 8 bits x 3
tables. Unused bits - LSBs -shall be set to “0” by the user.
When 24-bit (888) input data is being driven to a 24-bit display, each LUT (R, G and B) must contain 256 unique
8-bit entries. The 8-bit white balanced data is then available at the output of the DS90UB926Q-Q1 deserializer,
and driven to the display.
When 18-bit (666) input data is being driven to an 18-bit display, the white balance feature may be used in one of
two ways. First, simply load each LUT with 256, 8-bit entries. Each 8-bit entry is a 6-bit value (6 MSBs) with the 2
LSBs set to “00”. Thus as total of 64 unique 6-bit white balance output values are available for each color (R, G
and B). The 6-bit white balanced data is available at the output of the DS90UB926Q-Q1 deserializer, and driven
directly to the display.
Alternatively, with 6-bit input data the user may choose to load complete 8-bit values into each LUT. This mode
of operation provides the user with finer resolution at the LUT output to more closely achieve the desired white
point of the calibrated display. Although 8-bit data is loaded, only 64 unique 8-bit white balance output values are
available for each color (R, G and B). The result is 8-bit white balanced data. Before driving to the output of the
deserializer, the 8-bit data must be reduced to 6-bit with an FRC dithering function. To operate in this mode, the
user must configure the DS90UB926Q-Q1 to enable the FRC2 function.
Examples of the three types of LUT configurations described are shown in Figure 15
7.3.15.1.2 Enabling White Balance

The user must load all 3 LUTs prior to enabling the white balance feature. The following sequence must be
followed by the user.
To initialize white balance after power-on (Table 3):
1. Load contents of all 3 LUTs . This requires a sequential loading of LUTs - first RED, second GREEN, third
BLUE. 256, 8-bit entries must be loaded to each LUT. Page registers must be set to select each LUT.

DS90UB926Q-Q1
2. Enable white balance

By default, the LUT data may not be reloaded after initialization at power-on.
An option does exist to allow LUT reloading after power-on and initial LUT loading (as described above). This
option may only be used after enabling the white balance reload feature through the associated serial control bus
register. In this mode the LUTs may be reloaded by the master controller through the I2C. This provides the user
with the flexibility to refresh LUTs periodically , or upon system requirements to change to a new set of LUT
values. The host controller loads the updated LUT values through the serial bus interface. There is no need to
disable the white balance feature while reloading the LUT data. Refreshing the white balance to the new set of
LUT data will be seamless - no interruption of displayed data.
It is important to note that initial loading of LUT values requires that all 3 LUTs be loaded sequentially. When
reloading, partial LUT updates may be made.
8-bit in / 8 bit out 6-bit in / 6 bit out 6-bit in / 8 bit out
Gray level Data Out Gray level Data Out Gray level Data Out
Entry (8-bits) Entry (8-bits) Entry (8-bits)
0 00000000b 0 00000000b 0 00000001b
1 00000001b 1 N/A 1 N/A
2 00000011b 2 N/A 2 N/A
3 00000011b 3 N/A 3 N/A
4 00000110b 4 00000100b 4 00000110b
5 00000110b 5 N/A 5 N/A
6 00000111b 6 N/A 6 N/A
7 00000111b 7 N/A 7 N/A
8 00001000b 8 00001000b 8 00001011b
9 00001010b 9 N/A 9 N/A
10 00001001b 10 N/A 10 N/A
11 00001011b 11 N/A 11 N/A
«
«
«
«
«
248 11111010b 248 11111000b 248 11111010b

249 11111010b 249 N/A 249 N/A
250 11111011b 250 N/A 250 N/A
251 11111011b 251 N/A 251 N/A
252 11111110b 252 11111100b 252 11111111b
253 11111101b 253 N/A 253 N/A
254 11111101b 254 N/A 254 N/A
255 11111111b 255 N/A 255 N/A
Figure 15. White Balance LUT Configurations
Table 3. White Balance Register Table

PAGE ADD ADD Register Name Bit(s) Access Default Function Description
(dec) (hex) (hex)
0 42 0x2A White Balance 7:6 RW 0x00 Page Setting 00: Configuration Registers
Control 01: Red LUT
10: Green LUT
11: Blue LUT
5 RW White Balance 0: White Balance Disable
Enable 1: White Balance Enable
4 RW 0: Reload Disable
1: Reload Enable
3:0 Reserved
1 0– 00 – FF White Balance Red FF:0 RW N/A Red LUT 256 8–bit entries to be applied to the Red
255 LUT subpixel data
2 0– 00 – FF White Balance FF:0 RW N/A Green LUT 256 8–bit entries to be applied to the Green
255 Green LUT subpixel data
3 0– 00 – FF White Balance FF:0 RW N/A Blue LUT 256 8–bit entries to be applied to the Blue
255 Blue LUT subpixel data

DS90UB926Q-Q1
7.3.15.2 Adaptive HI-FRC Dithering

The Adaptive FRC Dithering Feature delivers product-differentiating image quality. It reduces 24-bit RGB (8 bits
per subpixel) to 18-bit RGB (6 bits per sub-pixel), smoothing color gradients, and allowing the flexibility to use
lower cost 18-bit displays. FRC (Frame Rate Control) dithering is a method to emulate “missing” colors on a
lower color depth LCD display by changing the pixel color slightly with every frame. FRC is achieved by
controlling on and off pixels over multiple frames (Temporal). Static dithering regulates the number of on and off
pixels in a small defined pixel group (Spatial). The FRC module includes both Temporal and Spatial methods and
also Hi-FRC. Conventional FRC can display only 16,194,277 colors with 6-bit RGB source. “Hi-FRC” enables full
(16,777,216) color on an 18-bit LCD panel. The “adaptive” FRC module also includes input pixel detection to
apply specific Spatial dithering methods for smoother gray level transitions. When enabled, the lower LSBs of
each RGB output are not active; only 18 bit data (6 bits per R,G and B) are driven to the display. This feature is
enabled through the serial control bus register.
Two FRC functional blocks are available, and may be independently enabled. FRC1 precedes the white balance
LUT, and is intended to be used when 24-bit data is being driven to an 18-bit display with a white balance LUT
that is calibrated for an 18-bit data source. The second FRC block, FRC2, follows the white balance block and is
intended to be used when fine adjustment of color temperature is required on an 18-bit color display, or when a
24-bit source drives an 18-bit display with a white balance LUT calibrated for 24-bit source data.
For proper operation of the FRC dithering feature, the user must provide a description of the display timing
control signals. The timing mode, “sync mode” (HS, VS) or “DE only” must be specified, along with the active
polarity of the timing control signals. All this information is entered to DS90UB926Q-Q1 control registers through
the serial bus interface.
Adaptive Hi-FRC dithering consists of several components. Initially, the incoming 8-bit data is expanded to 9-bit
data. This allows the effective dithered result to support a total of 16.7 million colors. The incoming 9-bit data is
evaluated, and one of four possible algorithms is selected. The majority of incoming data sequences are
supported by the default dithering algorithm. Certain incoming data patterns (black/white pixel, full on/off sub-
pixel) require special algorithms designed to eliminate visual artifacts associated with these specific gray level
transitions. Three algorithms are defined to support these critical transitions.
An example of the default dithering algorithm is illustrated in Figure 16. The 1 or 0 value shown in the table
describes whether the 6-bit value is increased by 1 (1) or left unchanged (0). In this case, the 3 truncated LSBs
are 001.

DS90UB926Q-Q1
F0L0 Frame = 0, Line = 0

PD1 Pixel Data one
Cell Value 010 R[7:2]+0, G[7:2]+1, B[7:2]+0
LSB=001 three lsb of 9 bit data (8 to 9 for Hi-Frc)
Pixel Index PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8
LSB=001
LSB = 001
F0L0 010 000 000 000 000 000 010 000
F0L1 101 000 000 000 101 000 000 000 R = 4/32
F0L2 000 000 010 000 010 000 000 000 G = 4/32
F0L3 000 000 101 000 000 000 101 000 B = 4/32
F1L0 000 000 000 000 000 000 000 000

F1L1 000 111 000 000 000 111 000 000 R = 4/32
F1L2 000 000 000 000 000 000 000 000 G = 4/32
F1L3 000 000 000 111 000 000 000 111 B = 4/32
F2L0 000 000 010 000 010 000 000 000

F2L1 000 000 101 000 000 000 101 000 R = 4/32
F2L2 010 000 000 000 000 000 010 000 G = 4/32
F2L3 101 000 000 000 101 000 000 000 B = 4/32
F3L0 000 000 000 000 000 000 000 000

F3L1 000 000 000 111 000 000 000 111 R = 4/32
F3L2 000 000 000 000 000 000 000 000 G = 4/32
F3L3 000 111 000 000 000 111 000 000 B = 4/32
Figure 16. Default FRC Algorithm
See Table 4 for recommended FRC settings dependant on 18/24–bit source, 18/24–bit white balance LUT, and
18/24–bit display.
Table 4. Recommended FRC settings

Source White Balance LUT Display FRC1 FRC2
24–bit 24–bit 24–bit Disabled Disabled
24–bit 24–bit 18–bit Disabled Enabled
24–bit 18–bit 18–bit Enabled Disabled
18–bit 24–bit 18–bit Disabled Enabled
7.3.16 Internal Pattern Generation

The DS90UB926Q-Q1 serializer supports the internal pattern generation feature. It allows basic testing and
debugging of an integrated panel. The test patterns are simple and repetitive and allow for a quick visual
verification of panel operation. As long as the device is not in power down mode, the test pattern will be
displayed even if no parallel input is applied. If no PCLK is received, the test pattern can be configured to use a
programmed oscillator frequency. For detailed information, refer to Application Note AN-2198 (SNLA132).
7.3.17 Built In Self Test (BIST)

An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high speed serial link and the
low- speed back channel. This is useful in the prototype stage, equipment production, in-system test and also for
system diagnostics.

DS90UB926Q-Q1
NOTE
BIST is not available in backward-compatible mode.
7.3.17.1 BIST Configuration and Status

The BIST mode is enabled at the deserializer by the Pin select (Pin 44 BISTEN and Pin 16 BISTC) or
configuration register (Table 11) through the deserializer. When LFMODE = 0, the pin based configuration
defaults to external PCLK or 33 MHz internal Oscillator clock (OSC) frequency. In the absence of PCLK, the user
can select the desired OSC frequency (default 33 MHz or 25MHz) through the register bit. When LFMODE = 1,
the pin based configuration defaults to external PCLK or 12.5MHz MHz internal Oscillator clock (OSC) frequency.
When BISTEN of the deserializer is high, the BIST mode enable information is sent to the serializer through the
Back Channel. The serializer outputs a test pattern and drives the link at speed. The deserializer detects the test
pattern and monitors it for errors. The PASS output pin toggles to flag any payloads that are received with 1 to
35 bit errors.
The BIST status is monitored real time on PASS pin. The result of the test is held on the PASS output until reset
(new BIST test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low on PASS
indicates one or more errors were detected. The duration of the test is controlled by the pulse width applied to
the deserializer BISTEN pin. This BIST feature also contains a Link Error Count and a Lock Status. If the
connection of the serial link is broken, then the link error count is shown in the register. When the PLL of the
deserializer is locked or unlocked, the lock status can be read in the register. See Table 11.
7.3.17.1.1 Sample BIST Sequence

See Figure 17 for the BIST mode flow diagram.
1. For the DS90UB925Q-Q1 and DS90UB926Q-Q1 FPD-Link III chipset, BIST Mode is enabled through the
BISTEN pin of DS90UB926Q-Q1 FPD-Link III deserializer. The desired clock source is selected through
BISTC pin.
2. The DS90UB925Q-Q1 serializer is woken up through the back channel if it is not already on. The all zero
pattern on the data pins is sent through the FPD-Link III to the deserializer. Once the serializer and the
deserializer are in BIST mode and the deserializer acquires Lock, the PASS pin of the deserializer goes high
and BIST starts checking the data stream. If an error in the payload (1 to 35) is detected, the PASS pin will
switch low for one half of the clock period. During the BIST test, the PASS output can be monitored and
counted to determine the payload error rate.
3. To Stop the BIST mode, the deserializer BISTEN pin is set Low. The deserializer stops checking the data.
The final test result is held on the PASS pin. If the test ran error free, the PASS output will be High. If there
was one or more errors detected, the PASS output will be Low. The PASS output state is held until a new
BIST is run, the device is RESET, or Powered Down. The BIST duration is user controlled by the duration of
the BISTEN signal.
4. The Link returns to normal operation after the deserializer BISTEN pin is low. Figure 18 shows the waveform
diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple errors.
In most cases it is difficult to generate errors due to the robustness of the link (differential data transmission
etc.), thus they may be introduced by greatly extending the cable length, faulting the interconnect, reducing
signal condition enhancements ( Rx Equalization).

DS90UB926Q-Q1
Normal
Step 1: DES in BIST
BIST
Wait
Step 2: Wait, SER in BIST
BIST
start
Step 3: DES in Normal Mode -

check PASS
BIST
stop
Step 4: DES/SER in Normal
Figure 17. Bist Mode Flow Diagram
7.3.17.2 Forward Channel And Back Channel Error Checking

While in BIST mode, the serializer stops sampling RGB input pins and switches over to an internal all-zero
pattern. The internal all-zeroes pattern goes through scrambler, dc-balancing etc. and goes over the serial link to
the deserializer. The deserializer on locking to the serial stream compares the recovered serial stream with all-
zeroes and records any errors in status registers and dynamically indicates the status on PASS pin. The
deserializer then outputs a SSO pattern on the RGB output pins.
The back-channel data is checked for CRC errors once the serializer locks onto back-channel serial stream as
indicated by link detect status (register bit 0x0C[0]). The CRC errors are recorded in an 8-bit register. The
register is cleared when the serializer enters the BIST mode. As soon as the serializer exits BIST mode, the
functional mode CRC register starts recording the CRC errors. The BIST mode CRC error register is active in
BIST mode only and keeps the record of last BIST run until cleared or enters BIST mode again.
BISTEN
DES Outputs
(DES)
PCLK
(RFB = L)
ROUT[23:0]
HS, VS, DE
Case 1 - Pass
DATA
(internal)
PASS Prior Result PASS
X = bit error(s)
Case 2 - Fail
DATA X X X
(internal)
PASS Prior Result FAIL
BIST
Normal SSO BIST Test Normal
Result
BIST Duration Held
Figure 18. Bist Waveforms

DS90UB926Q-Q1
7.3.18 I2S Receiving

In normal 24-bit RGB operation mode, the DS90UB926Q-Q1 provides up to 3-bit of I2S. They are I2S_CLK,
I2S_WC and I2S_DA, as well as the Master I2S Clock (MCLK). The audio is received through the forward video
frame, or can be configured to receive during video blanking periods. A jitter cleaning feature reduces I2S_CLK
output jitter to +/- 2ns.
7.3.18.1 I2S Jitter Cleaning

The DS90UB926Q-Q1 features a standalone PLL to clean the I2S data jitter supporting high end car audio
systems. If I2S CLK frequency is less than 1MHz, this feature has to be disabled through the register bit I2S
Control (0x2B) in Table 11.
7.3.18.2 Secondary I2S Channel

In 18-bit RGB operation mode, the secondary I2S data (I2S_DB) can be used as the additional I2S audio
channel in additional to the 3–bit of I2S. The I2S_DB is synchronized to the I2S_CLK. To enable this
synchronization feature on this bit, set the MODE_SEL (Table 9) or program through the register bit (Table 11).
7.3.18.3 MCLK
The deserializer has an I2S Master Clock Output. It supports x1, x2, or x4 of I2S CLK Frequency. When the I2S
PLL is disabled, the MCLK output is off. Table 5 below covers the range of I2S sample rates and MCLK
frequencies.
By default, all the MCLK output frequencies are x2 of the I2S CLK frequencies. The MCLK frequencies can also
be enabled through the register bit [7:4] (I2S MCLK Output) of 0x3A shown in Table 11. To select desired MCLK
frequency, write bit 7 (0x3A) = 1, then write to bit [6:4] accordingly.
Table 5. Audio Interface Frequencies

Sample Rate (kHz) I2S Data Word Size I2S CLK MCLK Output Bit [6:4]
(bits) (MHz) (MHz) (Address 0x3A)
32 16 1.024 x1 of I2S CLK 000
x2 of I2S CLK 001
x4 of I2S CLK 010
44.1 16 1.411 x1 of I2S CLK 000
x2 of I2S CLK 001
x4 of I2S CLK 010
48 16 1.536 x1 of I2S CLK 000
x2 of I2S CLK 001
x4 of I2S CLK 010
96 16 3.072 x1 of I2S CLK 001
x2 of I2S CLK 010
x4 of I2S CLK 011
192 16 6.144 x1 of I2S CLK 010
x2 of I2S CLK 011
x4 of I2S CLK 100
32 24 1.536 x1 of I2S CLK 000
x2 of I2S CLK 001
x4 of I2S CLK 010
44.1 24 2.117 x1 of I2S CLK 001
x2 of I2S CLK 010
x4 of I2S CLK 011
48 24 2.304 x1 of I2S CLK 001
x2 of I2S CLK 010
x4 of I2S CLK 011

DS90UB926Q-Q1
Table 5. Audio Interface Frequencies (continued)

Sample Rate (kHz) I2S Data Word Size I2S CLK MCLK Output Bit [6:4]
(bits) (MHz) (MHz) (Address 0x3A)
96 24 4.608 x1 of I2S CLK 010
x2 of I2S CLK 011
x4 of I2S CLK 100
192 24 9.216 x1 of I2S CLK 011
x2 of I2S CLK 100
x4 of I2S CLK 101
32 32 2.048 x1 of I2S CLK 001
x2 of I2S CLK 010
x4 of I2S CLK 011
44.1 32 2.822 x1 of I2S CLK 001
x2 of I2S CLK 010
x4 of I2S CLK 011
48 32 3.072 x1 of I2S CLK 001
x2 of I2S CLK 010
x4 of I2S CLK 011
96 32 6.144 x1 of I2S CLK 010
x2 of I2S CLK 011
x4 of I2S CLK 100
192 32 12.288 x1 of I2S CLK 011
x2 of I2S CLK 100
x4 of I2S CLK 110
7.3.19 Interrupt Pin — Functional Description and Usage (INTB)

1. On DS90UB925Q-Q1, set register 0xC6[5] = 1 and 0xC6[0] = 1
2. DS90UB926Q-Q1 deserializer INTB_IN (pin 16) is set LOW by some downstream device.
3. DS90UB925Q-Q1 serializer pulls INTB (pin 31) LOW. The signal is active low, so a LOW indicates an
interrupt condition.
4. External controller detects INTB = LOW; to determine interrupt source, read ISR register .
5. A read to ISR will clear the interrupt at the DS90UB925Q-Q1, releasing INTB.
6. The external controller typically must then access the remote device to determine downstream interrupt
source and clear the interrupt driving INTB_IN. This would be when the downstream device releases the
INTB_IN (pin 16) on the DS90UB926Q-Q1. The system is now ready to return to step (1) at next falling edge
of INTB_IN.
7.3.20 GPIO[3:0] and GPO_REG[8:4]

In 18-bit RGB operation mode, the optional R[1:0] and G[1:0] of the DS90UB926Q-Q1 can be used as the
general purpose IOs GPIO[3:0] in either forward channel (Outputs) or back channel (Inputs) application.
GPIO[3:0] Enable Sequence
See Table 6 for the GPIO enable sequencing.
1. Enable the 18-bit mode either through the configuration register bit Table 11 on DS90UB925Q-Q1 only.
DS90UB926Q-Q1 is automatically configured as in the 18-bit mode.
2. To enable GPIO3 forward channel, write 0x03 to address 0x0F on DS90UB925Q-Q1, then write 0x05 to
address 0x1F on DS90UB926Q-Q1.

DS90UB926Q-Q1
Table 6. GPIO Enable Sequencing Table

NO. Description Device Forward Channel Back Channel
1 Enable 18-bit DS90UB925Q-Q1 0x12 = 0x04 0x12 = 0x04
mode
DS90UB926Q-Q1 Auto Load from DS90UB925Q-Q1 Auto Load from DS90UB925Q-Q1
2 GPIO3 DS90UB925Q-Q1 0x0F = 0x03 0x0F = 0x05
DS90UB926Q-Q1 0x1F = 0x05 0x1F = 0x03
3 GPIO2 DS90UB925Q-Q1 0x0E = 0x30 0x0E = 0x50
DS90UB926Q-Q1 0x1E = 0x50 0x1E = 0x30
4 GPIO1 DS90UB925Q-Q1 0x0E = 0x03 0x0E = 0x05
DS90UB926Q-Q1 0x1E = 0x05 0x0E = 0x05
5 GPIO0 DS90UB925Q-Q1 0x0D = 0x93 0x0D = 0x95
DS90UB926Q-Q1 0x1D = 0x95 0x1D = 0x93
GPO_REG[8:4] Enable Sequence

GPO_REG[8:4] are the outputs only pins. They must be programmed through the local register bits. See Table 7
for the GPO_REG enable sequencing.
1. Enable the 18-bit mode either through the configuration register bit Table 11 on DS90UB925Q-Q1 only.
DS90UB926Q-Q1 is automatically configured as in the 18-bit mode.
2. To enable GPO_REG8 outputs an “1” , write 0x90 to address 0x21 on DS90UB926Q-Q1.
Table 7. GPO_REG Enable Sequencing Table

NO. Description Device Local Access Local Output Value
1 Enable 18-bit mode DS90UB926Q-Q1 0x12 = 0x04
(on DS90UB925Q-Q1)
2 GPO_REG8 DS90UB926Q-Q1 0x21 = 0x90 “1”
0x21 = 0x10 “0”
3 GPO_REG7 DS90UB926Q-Q1 0x21 = 0x09 “1”
0x21 = 0x01 “0”
4 GPO_REG6 DS90UB926Q-Q1 0x20 = 0x90 “1”
0x20 = 0x10 “0”
5 GPO_REG5 DS90UB926Q-Q1 0x20 = 0x09 “1”
0x20 = 0x01 “0”
6 GPO_REG4 DS90UB926Q-Q1 0x1F = 0x90 “1”
0x1F = 0x10 “0”
7.4 Device Functional Modes

7.4.1 Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN) and Output State Select
(OSS_SEL)
When PDB is driven HIGH, the CDR PLL begins locking to the serial input and LOCK is TRI-STATE or LOW
(depending on the value of the OEN setting). After the DS90UB926Q-Q1 completes its lock sequence to the
input serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial input
is available on the parallel bus and PCLK outputs. The State of the outputs are based on the OEN and
OSS_SEL setting (Table 8) or register bit (Table 11). See Figure 7.
Table 8. Output States

INPUTS OUTPUTS
Serial PDB OEN OSS_SEL Lock Pass Data, GPIO, I2S CLK
input
X 0 X X Z Z Z Z
X 1 0 0 L or H L L L
X 1 0 1 L or H Z Z Z

DS90UB926Q-Q1
Device Functional Modes (continued)

Table 8. Output States (continued)
INPUTS OUTPUTS
Static 1 1 0 L L L L/OSC (Register bit
enable)
Static 1 1 1 L Previous Status L L
Active 1 1 0 H L L L
Active 1 1 1 H Valid Valid Valid
7.4.2 Low Frequency Optimization (LFMODE)

The LFMODE is set through the register (Table 11) or MODE_SEL Pin 24 (Table 9). It controls the operating
frequency of the deserializer. If LFMODE is Low (default), the PCLK frequency is between 15 MHz and 85 MHz.
If LFMODE is High, the PCLK frequency is between 5 MHz and <15 MHz. Please note when the device
LFMODE is changed, a PDB reset is required.
7.4.3 Configuration Select (MODE_SEL)

Configuration of the device may be done through the MODE_SEL input pin, or through the configuration register
bit. A pullup resistor and a pulldown resistor of suggested values may be used to set the voltage ratio of the
MODE_SEL input (VR4) and VDD33 to select one of the other 10 possible selected modes. See Figure 19 and
Table 9.
VDD33
R3
VR4 MODE_SEL
R4
DES
Figure 19. MODE_SEL Connection Diagram
Table 9. Configuration Select (MODE_SEL)

NO. Ideal Ratio Ideal VR4 Suggested Suggested LFMODE (1) Repeater (2) Backward I2S Channel B
VR4/VDD33 (V) Resistor R3 Resistor R4 Compatible (3) (18–bit
kΩ (1% tol) kΩ (1% tol) Mode) (4)
1 0 0 Open 40.2 or Any L L L L
2 0.121 0.399 294 40.2 L L L H
3 0.152 0.502 280 49.9 L H L L
4 0.242 0.799 240 76.8 L H L H
5 0.311 1.026 226 102 H L L L
6 0.402 1.327 196 130 H L L H
7 0.492 1.624 169 165 H H L L
8 0.583 1.924 137 191 H H L H
9 0.629 2.076 124 210 L L H L
(1) LFMODE: L = 15 – 85 MHz (Default); H = 5 – <15 MHz

(2) Repeater: L = Repeater Off (Default); H = Repeater On
(3) Backward Compatible: L = Backward Compatible Off (Default); H = Backward Compatible On to 905/907 (15 - 65MHz)
(4) I2S Channel B: L = I2S Channel B Off, Normal 24-bit RGB Mode (Default); H = I2S Channel B On, 18-bit RGB Mode with I2S_DB
Enabled.

DS90UB926Q-Q1
7.4.4 Repeater Application

The DS90UB925Q-Q1 and DS90UB926Q-Q1 can be configured to extend data transmission over multiple links
to multiple display devices. Setting the devices into repeater mode provides a mechanism for transmitting to all
receivers in the system.
In a repeater application, in this document, the DS90UB925Q-Q1 is referred to as the Transmitter or transmit port
(TX), and the DS90UB926Q-Q1 is referred to as the Receiver (RX). Figure 20 shows the maximum configuration
supported for Repeater implementations using the DS90UB925Q-Q1 (TX) and DS90UB926Q-Q1 (RX). Two
levels of Repeaters are supported with a maximum of three Transmitters per Receiver.
1:3 Repeater
1:3 Repeater
TX RX Display
TX RX
Source TX RX RX Display
TX
TX
TX RX Display
TX
1:3 Repeater
TX RX Display
RX
TX RX Display
TX RX Display
1:3 Repeater
TX RX Display
RX
TX RX Display
TX RX Display
Figure 20. Maximum Repeater Application
DS90UB925Q-Q1
Transmitter
downstream
I2C Receiver
I2C I2C
Slave or
Master
upstream Repeater
Transmitter Parallel
LVCMOS
DS90UB926Q-Q1 DS90UB925Q-Q1
Receiver I2S Audio Transmitter
downstream
I2C Receiver
Slave or
Repeater
FPD-Link III interfaces
Figure 21. 1:2 Repeater Configuration


DS90UB926Q-Q1
In a repeater application, the I2C interface at each TX and RX may be configured to transparently pass I2C
communications upstream or downstream to any I2C device within the system. This includes a mechanism for
assigning alternate IDs (Slave Aliases) to downstream devices in the case of duplicate addresses.
At each repeater node, the parallel LVCMOS interface fans out to up to three serializer devices, providing parallel
RGB video data, HS/VS/DE control signals and, optionally, packetized audio data (transported during video
blanking intervals). Alternatively, the I2S audio interface may be used to transport digital audio data between
receiver and transmitters in place of packetized audio. All audio and video data is transmitted at the output of the
Receiver and is received by the Transmitter..
Figure 21 provides more detailed block diagram of a 1:2 repeater configuration.
7.4.4.1 Repeater Connections

The Repeater requires the following connections between the Receiver and each Transmitter for Figure 22:
1. Video Data – Connect PCLK, RGB and control signals (DE, VS, HS).
2. I2C – Connect SCL and SDA signals. Both signals should be pulled up to VDD33 with 4.7 kΩ resistors.
3. Audio – Connect I2S_CLK, I2S_WC, and I2S_DA signals.
4. IDx pin – Each Transmitter and Receiver must have an unique I2C address.
5. MODE_SEL pin – All Transmitter and Receiver must be set into the Repeater Mode.
6. Interrupt pin– Connect DS90UB926Q-Q1 INTB_IN pin to DS90UB925Q-Q1 INTB pin. The signal must be
pulled up to VDDIO.
DS90UB926Q-Q1 DS90UB925Q-Q1
RGB[7:0) / ROUT[23:0] DIN[23:0] / RGB[7:0]
DE DE
VS VS
HS HS
I2S_CLK I2S_CLK
VDD33 I2S_WC I2S_WC VDD33
I2S_DA I2S_DA
MODE_SEL Optional MODE_SEL
VDDIO
Optional
INTB_IN INTB
VDD33 VDD33
VDD33
ID[x] ID[x]
SDA SDA
SCL SCL
Figure 22. Repeater Connection Diagram
7.5 Programming
7.5.1 Serial Control Bus
The DS90UB926Q-Q1 is configured by the use of a serial control bus that is I2C protocol compatible. . Multiple
deserializer devices may share the serial control bus since 16 device addresses are supported. Device address
is set through the R1 and R2 values on IDx pin. See Figure 23.

DS90UB926Q-Q1
Programming (continued)
The serial control bus consists of two signals and a configuration pin. The SCL is a Serial Bus Clock Input /
Output. The SDA is the Serial Bus Data Input / Output signal. Both SCL and SDA signals require an external
pullup resistor to VDD33. For most applications a 4.7-k pullup resistor to VDD33 may be used. The resistor value
may be adjusted for capacitive loading and data rate requirements. The signals are either pulled High, or driven
Low.
VDD33
R1
VDD33
VR2 IDx
4.7k 4.7k R2
HOST SER
or or
Salve SCL SCL DES
SDA SDA
To other
Devices
Figure 23. Serial Control Bus Connection
The configuration pin is the IDx pin. This pin sets one of 16 possible device addresses. A pullup resistor and a
pulldown resistor of suggested values may be used to set the voltage ratio of the IDx input (VR2) and VDD33 to
select one of the other 16 possible addresses. See Table 10.
Table 10. Serial Control Bus Addresses for IDx

Ideal Ratio Ideal VR2 Suggested Resistor Suggested Resistor Address 8'b
NO. Address 7'b
VR2 / VDD33 (V) R1 kΩ (1% tol) R2 kΩ (1% tol) Appended
1 0 0 Open 40.2 or Any 0x2C 0x58
2 0.121 0.399 294 40.2 0x2D 0x5A
3 0.152 0.502 280 49.9 0x2E 0x5C
4 0.182 0.601 270 60.4 0x2F 0x5E
5 0.212 0.700 267 71.5 0x30 0x60
6 0.242 0.799 240 76.8 0x31 0x62
7 0.273 0.901 243 90.9 0x32 0x64
8 0.310 1.023 226 102 0x33 0x66
9 0.356 1.175 210 115 0x34 0x68
10 0.402 1.327 196 130 0x35 0x6A
11 0.447 1.475 182 147 0x36 0x6C
12 0.492 1.624 169 165 0x37 0x6E
13 0.538 1.775 154 180 0x38 0x70
14 0.583 1.924 137 191 0x39 0x72
15 0.629 2.076 124 210 0x3A 0x74
16 0.727 2.399 90.9 243 0x3B 0x76

DS90UB926Q-Q1
7.6 Register Maps

Table 11. Serial Control Bus Registers
ADD ADD Register Bit(s) Register Default Function Descriptions
(dec) (hex) Name Type (hex)
0 0x00 I2C Device ID 7:1 RW Device ID 7–bit address of Deserializer
See Table 9
0 RW ID Setting I2C ID Setting
1: Register I2C Device ID (Overrides IDx pin)
0: Device ID is from IDx pin
1 0x01 Reset 7 RW 0x04 Remote Remote Auto Power Down
Auto Power 1: Power down when no forward channel link is detected
Down 0: Do not power down when no forward channel link is
detected
6:3 Reserved
2 RW BC Enable Back channel enable
1: Enable
0: Disable
1 RW Digital Reset the entire digital block including registers
RESET1 This bit is self-clearing.
1: Reset
0: Normal operation
0 RW Digital Reset the entire digital block except registers
RESET0 This bit is self-clearing
1: Reset
0: Normal operation
2 0x02 Configuration 7 RW 0x00 Output LVCMOS Output Enable.
[0] Enable 1: Enable
0: Disable. Tri-state Outputs
6 RW OEN and Overrides Output Enable Pin and Output State pin
OSS_SEL 1: Enable override
Override 0: Disable - no override
5 RW OSC Clock OSC Clock Output Enable
Enable If loss of lock OSC clock is output onto PCLK
0: Disable
1: Enable
4 RW Output OSS Select to Control Output State during Lock Low
Sleep State Period
Select 1: Enable
(OSS_SEL) 0: Disable
3 RW Backward Mode_Sel Backward compatible Mode Override Enable.
Compatible 1: Use register bit "reg_02[2]" to set BC Mode
Mode 0: Use MODE_SEL option.
Override
2 RW Backward Backward Compatible Mode Select to DS90UR905Q and
Compatible DS90UR907Q. If Reg_02[3] = 1
Mode 1: Backward Compatible is on
Select 0: Backward Compatible is off
1 RW LFMODE LFMODE Pin Override Enable
Pin 1: Use register bit "reg_02[0]" to set LFMODE
Override 0: Use LFMODE Pin
0 RW LFMODE Low Frequency Mode Select
1: PCLK = 5 - <15 MHz
0: PCLK = 15 - 85 MHz

DS90UB926Q-Q1
Register Maps (continued)

Table 11. Serial Control Bus Registers (continued)
3 0x03 Configuration 7 0xF0 Reserved
[1]
6 RW CRC CRC Generator Enable (Back Channel)
Generator 1: Enable
Enable 0: Disable
5 Reserved
4 RW Filter HS, VS, DE two clock filter When enabled, pulses less
Enable than two full PCLK cycles on the DE, HS, and VS inputs
will be rejected
1: Filtering enable
0: Filtering disable
3 RW I2C Pass- I2C Pass-Through Mode
through 1: Pass-Through Enabled
0: Pass-Through Disabled
2 RW Auto ACK ACK Select
1: Auto ACK enable
0: Self ACK
1 Reserved
0 RW RRFB Pixel Clock Edge Select
1: Parallel Interface Data is strobed on the Rising Clock
Edge.
0: Parallel Interface Data is strobed on the Falling Clock
Edge.
4 0x04 BCC 7:1 RW 0xFE BCC The watchdog timer allows termination of a control channel
Watchdog Watchdog transaction, if it fails to complete within a programmed
Control Timer amount of time. This field sets the Bidirectional Control
Channel Watchdog Timeout value in units of 2
milliseconds.
This field should not be set to 0
0 RW BCC Disable Bidirectional Control Channel Watchdog Timer
Watchdog 1: Disables BCC Watchdog Timer operation
Timer 0: Enables BCC Watchdog Timer operation"
Disable
5 0x05 I2C Control [1] 7 RW 0x2E I2C Pass I2C Pass-Through All Transactions
Through All 1: Enabled
0: Disabled
6:4 RW I2C SDA Internal I2C SDA Hold Time
Hold Time It configures the amount of internal hold time provided for
the SDA input relative to the SCL input. Units are 50 ns.
3:0 RW I2C Filter I2C Glitch Filter Depth
Depth It configures the maximum width of glitch pulses on the
SCL and SDA inputs that will be rejected. Units are 5 ns.

DS90UB926Q-Q1

6 0x06 I2C Control [2] 7 R 0x00 Forward Control Channel Sequence Error Detected It indicates a
Channel sequence error has been detected in forward control
Sequence channel. It this bit is set, an error may have occurred in the
Error control channel operation.
6 RW Clear It clears the Sequence Error Detect bit
Sequence This bit is not self-clearing.
Error
5 Reserved
4:3 RW SDA Output SDA Output Delay
Delay This field configures output delay on the SDA output.
Setting this value will increase output delay in units of 50
ns. Nominal output delay values for SCL to SDA are:
00 : 250ns
01: 300ns
10: 350ns
11: 400ns
2 RW Local Write Disable Remote Writes to Local Registers through
Serializer (Does not affect remote access to I2C slaves at
Deserializer)
1: Stop remote write to local device registers
0: remote write to local device registers
1 RW I2C Bus Speed up I2C Bus Watchdog Timer
Timer 1: Timer expires after approximately 50 ms
Speed 0: Timer expires after approximately 1s
0 RW I2C Bus Disable I2C Bus Timer When the I2C Timer may be used
Timer to detect when the I2C bus is free or hung up following an
Disable invalid termination of a transaction. If SDA is high and no
signalling occurs for approximately 1 s, the I2C bus is
assumed to be free. If SDA is low and no signaling occurs,
the device will try to clear the bus by driving 9 clocks on
SCL
7 0x07 Remote 7:1 RW 0x18 Remote ID Remote ID
Device ID Configures the I2C Slave ID of the remote Serializer. A
value of 0 in this field disables I2C access to remote
Serializer. This field is automatically configured through the
Serializer Forward Channel. Software may overwrite this
value, but should also set the FREEZE DEVICE ID bit to
prevent overwriting by the Forward Channel.
0 RW Freeze Freeze Serializer Device ID
Device ID 1: Prevent auto-loading of the Serializer Device ID from the
Forward Channel. The ID will be frozen at the value
written.
0: Update
8 0x08 SlaveID[0] 7:1 RW 0x00 Target 7-bit Remote Slave Device ID 0
Slave Configures the physical I2C address of the remote I2C
Device ID0 Slave device attached to the remote Serializer. If an I2C
transaction is addressed to the Slave Alias ID0, the
transaction will be remapped to this address before
passing the transaction across the Bidirectional Control
Channel to the Serializer.
0 Reserved
9 0x09 SlaveID[1] 7:1 RW 0x00 Target 7-bit Remote Slave Device ID 1
0 Reserved

DS90UB926Q-Q1

10 0x0A SlaveID[2] 7:1 RW 0x00 Target 7-bit Remote Slave Device ID 2
0 Reserved
11 0x0B SlaveID[3] 7:1 RW 0x00 Target 7-bit Remote Slave Device ID 3
0 Reserved
12 0x0C SlaveID[4] 7:1 RW 0x00 Target 7-bit Remote Slave Device ID 4
0 Reserved
13 0x0D SlaveID[5] 7:1 RW 0x00 Target 7-bit Remote Slave Device ID 5
0 Reserved
14 0x0E SlaveID[6] 7:1 RW 0x00 Target 7-bit Remote Slave Device ID 6
0 Reserved
15 0x0F SlaveID[7] 7:1 RW 0x00 Target 7-bit Remote Slave Device ID 7
0 Reserved
16 0x10 SlaveAlias[0] 7:1 RW 0x00 ID[0] Match 7-bit Remote Slave Device Alias ID 0
Configures the decoder for detecting transactions
designated for an I2C Slave device attached to the remote
Serializer. The transaction will be remapped to the address
specified in the Slave ID0 register.
A value of 0 in this field disables access to the remote I2C
Slave.
0 Reserved

DS90UB926Q-Q1

Slave.
0 Reserved
Slave.
0 Reserved
Slave.
0 Reserved
Slave.
0 Reserved
Slave.
0 Reserved
Slave.
0 RW Reserved
Slave.
0 Reserved

DS90UB926Q-Q1

28 0x1C General Status 7:4 RW 0x00 Reserved
3 R I2S Locked I2S Lock Status
0: I2S PLL controller not locked
1: I2S PLL controller locked to input I2S clock
2 Reserved
1 Reserved
0 R Lock Deserializer CDR, PLL's clock to recovered clock
frequency
1: Deserializer locked to recovered clock
0: Deserializer not locked
29 0x1D GPIO0 Config 7:4 R 0xA0 Rev-ID Revision ID: 1010: Production Device
3 RW GPIO0 Local GPIO Output Value
Output This value is output on the GPIO pin when the GPIO
Value function is enabled, the local GPIO direction is Output, and
remote GPIO control is disabled.
2 RW GPIO0 Remote GPIO0 Control
Remote 1: Enable GPIO control from remote Serializer. The GPIO
Enable pin will be an output, and the value is received from the
remote Deserializer.
0: Disable GPIO control from remote Serializer
1 RW GPIO0 Local GPIO Direction
Direction 1: Input
0: Output
0 RW GPIO0 GPIO Function Enable
Enable 1: Enable GPIO operation
0: Enable normal operation
30 0x1E GPIO2 and 7 RW 0x00 GPIO2 Local GPIO Output Value
GPIO1 Config Output This value is output on the GPIO when the GPIO function
Value is enabled, the local GPIO direction is Output, and remote
GPIO control is disabled.
0: Disable GPIO control from remote Serializer.
Direction 1: Input
0: Output
3 RW GPIO1 Local GPIO Output Value
Output This value is output on the GPIO when the GPIO function
Value is enabled, the local GPIO direction is Output, and remote
GPIO control is disabled.
Direction 1: Input
0: Output

DS90UB926Q-Q1

31 0x1F GPO_REG4 7 RW 0x00 GPO_REG4 Local GPO_REG4 Output Value
and GPO3 Output This value is output on the GPO when the GPO function is
Config Value enabled, the local GPO direction is Output, and remote
GPO control is disabled.
6:5 Reserved
4 RW GPO_REG4 GPO_REG4 Function Enable
Enable 1: Enable GPO operation
3 RW GPIO3 Local GPIO Output Value This value is output on the GPIO
Output when the GPIO function is enabled, the local GPIO
Value direction is Output, and remote GPIO control is disabled.
Direction 1: Input
0: Output
32 0x20 GPO_REG6 7 RW 0x00 GPO_REG6 Local GPO_REG6 Output Value
and Output This value is output on the GPO when the GPO function is
GPO_REG5 Value enabled, the local GPO direction is Output, and remote
Config GPO control is disabled.
6:5 Reserved
3 RW GPO_REG5 Local GPO_REG5 Output Value
Output This value is output on the GPO when the GPO function is
Value enabled, the local GPO direction is Output, and remote
2:1 Reserved
33 0x21 GPO8 and 7 RW 0x00 GPO_REG8 Local GPO_REG8 Output Value
GPO7 Config Output This value is output on the GPO when the GPO function is
6:5 Reserved
3 RW GPO_REG7 Local GPO_REG7 Output Value
Output This value is output on the GPO when the GPO function is
2:1 Reserved

DS90UB926Q-Q1

34 0x22 Data Path 7 RW 0x00 Override FC 1: Disable loading of this register from the forward channel,
Control Config keeping locally written values intact
0: Allow forward channel loading of this register
6 RW Pass RGB Setting this bit causes RGB data to be sent independent of
DE. This allows operation in systems which may not use
DE to frame video data or send other data when DE is
deasserted. Note that setting this bit blocks packetized
audio. This bit does not need to be set in DS90UB925 or in
Backward Compatibility mode.
1: Pass RGB independent of DE
0: Normal operation
Note: this bit is automatically loaded from the remote
serializer unless bit 7 of this register is set.
5 RW DE Polarity This bit indicates the polarity of the DE (Data Enable)
signal.
1: DE is inverted (active low, idle high)
0: DE is positive (active high, idle low)
4 RW I2S_Gen This bit controls whether the Receiver outputs packetized
Auxiliary/Audio data on the RGB video output pins.
1: Don't output packetized audio data on RGB video output
pins
0: Output packetized audio on RGB video output pins.
3 RW I2S Channel 1: Set I2S Channel B Enable from reg_22[0]
B Enable 0: Set I2S Channel B Enable from MODE_SEL pin
Override Note: this bit is automatically loaded from the remote
2 RW 18-bit Video 1: Select 18-bit video mode
Select 0: Select 24-bit video mode
1 RW I2S 1: Enable I2S Data Forward Channel Frame Transport
Transport 0: Enable I2S Data Island Transport
Select Note: this bit is automatically loaded from the remote
0 RW I2S Channel I2S Channel B Enable
B Enable 1: Enable I2S Channel B on B1 output
0: I2S Channel B disabled
35 0x23 General 7 RW 0x10 Rx RGB RX RGB Checksum Enable Setting this bit enables the
Purpose Checksum Receiver to validate a one-byte checksum following each
Control video line. Checksum failures are reported in the STS
register
6:5 Reserved
4 R Mode_Sel Mode Select is Done
3 R LFMODE Low Frequency Mode Status
2 R Repeater Repeater Mode Status
1 R Backward Backward Compatible Mode Status
0 R I2S Channel I2S Channel B Status
B

DS90UB926Q-Q1

36 0x24 BIST Control 7:4 0x08 Reserved
3 RW BIST Pin BIST Configured through Pin
Config 1: BIST configured through pin
0: BIST configured through register bit
2:1 RW BIST Clock BIST Clock Source
Source 00: External Pixel Clock
01: 33 MHz Oscillator
10: Reserved
11: 25 MHz Oscillator
0 RW BIST BIST Control
Enable 1: Enabled
0: Disabled
37 0x25 BIST Error 7:0 R 0x00 BIST Error BIST Error Count
Count
38 0x26 SCL High 7:0 RW 0x83 SCL High I2C Master SCL High Time
Time Time This field configures the high pulse width of the SCL output
when the Deserializer is the Master on the local I2C bus.
Units are 50 ns for the nominal oscillator clock frequency.
The default value is set to provide a minimum 5us SCL
high time with the internal oscillator clock running at
26MHz rather than the nominal 20MHz.
39 0x27 SCL Low Time 7:0 RW 0x84 SCL Low I2C SCL Low Time
Time This field configures the low pulse width of the SCL output
when the De-Serializer is the Master on the local I2C bus.
This value is also used as the SDA setup time by the I2C
Slave for providing data prior to releasing SCL during
accesses over the Bidirectional Control Channel. Units are
50 ns for the nominal oscillator clock frequency. The
default value is set to provide a minimum 5us SCL low
time with the internal oscillator clock running at 26MHz
rather than the nominal 20MHz.
41 0x29 FRC Control 7 RW 0x00 Timing Select display timing mode
Mode 0: DE only Mode
Select 1: Sync Mode (VS,HS)
6 RW VS Polarity 0: Active High
1: Active Low
5 RW HS Polarity 0: Active High
1: Active Low
4 RW DE Polarity 0: Active High
1: Active Low
3 RW FRC2 0: FRC2 Disable
Enable 1: FRC2 Enable
2 RW FRC1 0: FRC1 Disable
Enable 1: FRC1 Enable
1 RW Hi-FRC 2 0: Hi-FRC2 Enable
Disable 1: Hi-FRC2 Disable
0 RW Hi-FRC 1 0: Hi-FRC1 Enable
Disable 1: Hi-FRC1 Disable
42 0x2A White Balance 7:6 RW 0x00 Page 00: Configuration Registers
Control Setting 01: Red LUT
10: Green LUT
11: Blue LUT
5 RW White 0: White Balance Disable
Balance 1: White Balance Enable
Enable
4 RW LUT Reload 0: Reload Disable
Enable 1: Reload Enable
3:0 Reserved

DS90UB926Q-Q1

43 0x2B I2S Control 7 RW 0x00 I2S PLL I2S PLL Control
0: I2S PLL is on for I2S data jitter cleaning
1: I2S PLL is off. No jitter cleaning
6:1 Reserved
0 RW I2S Clock I2S Clock Edge Select
Edge 0: I2S Data is strobed on the Rising Clock Edge
1: I2S Data is strobed on the Falling Clock Edge
44 0x2C SSCG Control 7:4 0x00 Reserved
3 RW SSCG Enable Spread Spectrum Clock Generator
Enable 0: Disable
1: Enable
2:0 RW SSCG SSCG Frequency Deviation:
Selection When LFMODE = H
fdev fmod
000: ±0.7 CLK/628
001: ±1.3
010: ±1.8
011: ±2.5
100: ±0.7 CLK/388
101: ±1.2
110: ±2.0
111: ±2.5
When LFMODE = L
fdev fmod
000: ±0.9 CLK/2168
001: ±1.2
010: ±1.9
011: ±2.5
100: ±0.7 CLK/1300
101: ±1.3
110: ±2.0
111: ±2.5
58 0x3A I2S MCLK 7 RW 0x00 MCLK 1: Override divider select for MCLK
Output Override 0: No override for MCLK divider
6:4 RW MCLK See Table 5
Frequency
Slect
3:0 Reserved
65 0x41 Link Error 7:5 0x03 Reserved
Count
4 RW Link Error Enable serial link data integrity error count
Count 1: Enable error count
Enable 0: Disable
3:0 RW Link Error Link error count threshold.
Count Counter is pixel clock based. clk0, clk1 and DCA are
monitored for link errors, if error count is enabled,
deserializer loose lock once error count reaches threshold.
If disabled deserilizer loose lock with one error.

DS90UB926Q-Q1

68 0x44 Equalization 7:5 RW 0x60 EQ Stage 1 EQ select value.
Select Used if adaptive EQ is bypassed.
000 Min EQ 1st Stage
001
010
011
100
101
110
111 Max EQ 1st Stage
4 Reserved
3:1 RW EQ Stage 2 EQ select value.
Select Used if adaptive EQ is bypassed.
000 Min EQ 2nd Stage
001
010
011
100
101
110
111 Max EQ 2nd Stage
0 RW Adaptive 1: Disable adaptive EQ (to write EQ select values)
EQ 0: Enable adaptive EQ
86 0x56 CML Output 7:4 0x08 Reserved
3 RW CMLOUT+/- 1: Disabled (Default)
Enable 0: Enabled
2:0 Reserved
100 0x64 Pattern 7:4 RW 0x10 Pattern Fixed Pattern Select
Generator Generator This field selects the pattern to output when in Fixed
Control Select Pattern Mode. Scaled patterns are evenly distributed
across the horizontal or vertical active regions. This field is
ignored when Auto-Scrolling Mode is enabled. The
following table shows the color selections in non-inverted
followed by inverted color mode
0000: Reserved 0001: White/Black
0010: Black/White
0011: Red/Cyan
0100: Green/Magenta
0101: Blue/Yellow
0110: Horizontally Scaled Black to White/White to Black
0111: Horizontally Scaled Black to Red/Cyan to White
1000: Horizontally Scaled Black to Green/Magenta to
White
1001: Horizontally Scaled Black to Blue/Yellow to White
1010: Vertically Scaled Black to White/White to Black
1011: Vertically Scaled Black to Red/Cyan to White
1100: Vertically Scaled Black to Green/Magenta to White
1101: Vertically Scaled Black to Blue/Yellow to White
1110: Custom color (or its inversion) configured in PGRS,
PGGS, PGBS registers
1111: Reserved
3:1 Reserved
0 RW Pattern Pattern Generator Enable
Generator 1: Enable Pattern Generator
Enable 0: Disable Pattern Generator

DS90UB926Q-Q1

101 0x65 Pattern 7:5 0x00 Reserved
Generator
4 RW Pattern 18-bit Mode Select
Configuration
Generator 1: Enable 18-bit color pattern generation. Scaled patterns
18 Bits will have 64 levels of brightness and the R, G, and B
outputs use the six most significant color bits.
0: Enable 24-bit pattern generation. Scaled patterns use
256 levels of brightness.
3 RW Pattern Select External Clock Source
Generator 1: Selects the external pixel clock when using internal
External timing.
Clock 0: Selects the internal divided clock when using internal
timing
This bit has no effect in external timing mode
(PATGEN_TSEL = 0).
2 RW Pattern Timing Select Control
Generator 1: The Pattern Generator creates its own video timing as
Timing configured in the Pattern Generator Total Frame Size,
Select Active Frame Size. Horizontal Sync Width, Vertical Sync
Width, Horizontal Back Porch, Vertical Back Porch, and
Sync Configuration registers.
0: the Pattern Generator uses external video timing from
the pixel clock, Data Enable, Horizontal Sync, and Vertical
Sync signals.
1 RW Pattern Enable Inverted Color Patterns
Generator 1: Invert the color output.
Color Invert 0: Do not invert the color output.
0 RW Pattern Auto-Scroll Enable:
Generator 1: The Pattern Generator will automatically move to the
Auto-Scroll next enabled pattern after the number of frames specified
Enable in the Pattern Generator Frame Time (PGFT) register.
0: The Pattern Generator retains the current pattern.
102 0x66 Pattern 7:0 RW 0x00 Indirect This 8-bit field sets the indirect address for accesses to
Generator Address indirectly-mapped registers. It should be written prior to
Indirect reading or writing the Pattern Generator Indirect Data
Address register.
See AN-2198 (SNLA132)
103 0x67 Pattern 7:0 RW 0x00 Indirect When writing to indirect registers, this register contains the
Generator Data data to be written. When reading from indirect registers,
Indirect Data this register contains the read back value.
See AN-2198 (SNLA132
240 0xF0 RX ID 7:0 R 0x5F ID0 First byte ID code: _
241 0xF1 7:0 R 0x55 ID1 Second byte of ID code: U
242 0xF2 7:0 R 0x48 ID2 Third byte of ID code, Value will be either B.
243 0xF3 7:0 R 0x39 ID3 Fourth byte of ID code: 9
244 0xF4 7:0 R 0x32 ID4 Fifth byte of ID code: 2
245 0xF5 7:0 R 0x36 ID5 Sixth byte of ID code: 6

DS90UB926Q-Q1
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information

The DS90UB926Q-Q1, in conjunction with the DS90UB925Q-Q1, is intended for interface between a host
(graphics processor) and a Display. It supports an 24-bit color depth (RGB888) and high definition (720p) digital
video format. It allows to receive a three 8-bit RGB stream with a pixel rate up to 85 MHz together with three
control bits (VS, HS and DE) and three I2S-bus audio stream with an audio sampling rate up to 192 kHz.
8.1.1 Display Application

The deserializer is expected to be located close to its target device. The interconnect between the deserializer
and the target device is typically in the 1 to 3 inch separation range. The input capacitance of the target device is
expected to be in the 5 to 10 pF range. Care should be taken on the PCLK output trace as this signal is edge
sensitive and strobes the data. It is also assumed that the fanout of the deserializer is up to three in the repeater
mode. If additional loads need to be driven, a logic buffer or mux device is recommended.

DS90UB926Q-Q1
8.2 Typical Application

3.3V
DS90UB926Q-Q1 3.3V/1.8V
VDDIO
VDD33_A C6 FB2
FB1 C4
VDDIO
VDD33_B C7
C5
VDDIO
C8
CAPP12
C9
CAPR12
CAPI2S C13
C10 PASS
LOCK
CAPL12 ROUT0
ROUT1
C12 C11 ROUT2
C1 ROUT3
Serial ROUT4
RIN+ ROUT5
FPD-Link III
RIN- ROUT6
Interface
C2 ROUT7
CMF
ROUT8
C3
ROUT9
ROUT10
CMLOUTP ROUT11
VDD33_B*
100:
ROUT12
ROUT13
R5 CMLOUTN ROUT14
ROUT15 LVCMOS
Parallel
OSS_SEL Video / Audio
OEN ROUT16
Interface
Host Control BISTEN ROUT17
ROUT18
BISTC / INTB_IN
ROUT19
PDB ROUT20
C14
ROUT21
VDD33_B ROUT22
ROUT23
4.7k
4.7k
HS
VDD33_B VS
SDA
DE
SCL
R1 PCLK
I2S_CLK
ID[X]
I2S_WC
R2 VDD33_B I2S_DA
MCLK
R3 NC
RES 2
MODE_SEL
R4 DAP (GND)
FB1 ± FB2: Impedance = 1 k: @ 100 MHz,

Low DC resistance (<1:)
C1 ± C3 = 0.1 PF (50 WV; C1, C2: 0402; C3: 0603)
C4 ± C13 = 4.7 PF
C14 =>10 PF
R1 and R2 (see IDx Resistor Values Table 8)
R3 and R4 (see MODE_SEL Resistor Values Table 4)
R5 = 10 k:
* or VDDIO = 3.3V+0.3V
Figure 24. Typical Connection Diagram

DS90UB926Q-Q1
Typical Application (continued)
VDDIO VDD33 VDD33 VDDIO

RGB Digital Display Interface (1.8V or 3.3V) (3.3V) (3.3V) (1.8V or 3.3V)
R[7:0] FPD-Link III R[7:0]

G[7:0] 1 Pair / AC Coupled G[7:0]
HOST B[7:0] 0.1 PF 0.1 PF B[7:0]
HS HS RGB Display
Graphics DOUT+ RIN+ 720p
VS VS
Processor DE 24-bit color depth
DE
PCLK DOUT- RIN- PCLK
100: STP Cable
DS90UB925Q-Q1 PDB DS90UB926Q-Q1 LOCK
PDB
Serializer Deserializer PASS
OSS_SEL
3
I2S AUDIO OEN 3 I2S AUDIO
(STEREO) MODE_SEL MODE_SEL
(STEREO)
INTB INTB_IN MCLK
SCL SCL
SDA SDA
IDx DAP IDx DAP
Figure 25. Typical Display System Diagram
Figure 24 shows a typical application of the DS90UB926Q-Q1 deserializer for an 85-MHz, 24-bit Color Display
Application. Inputs use 0.1-μF coupling capacitors to the line and the deserializer provides internal termination.
Bypass capacitors are placed near the power supply pins. At a minimum, seven 0.1-μF capacitors and two 4.7-
μF capacitors should be used for local device bypassing. Ferrite beads are placed on the power lines for
effective noise suppression. Since the device in the Pin/STRAP mode, two 10-kΩ pullup resistors are used on
the parallel output bus to select the desired device features.
The interface to the target display is with 3.3-V LVCMOS levels, thus the VDDIO pins are connected to the 3.3-V
rail. A delay cap is placed on the PDB signal to delay the enabling of the device until power is stable.
8.2.1 Design Requirements

For the typical design application, use the following as input parameters.
Table 12. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
VDDIO 1.8 V or 3.3 V
VDD33 3.3 V
AC Coupling Capacitor for RIN± 100 nF
PCLK Frequency 78 MHz
8.2.2 Detailed Design Procedure
8.2.2.1 Transmission Media

The DS90UB925Q-Q1 and DS90UB926Q-Q1 chipset is intended to be used in a point-to-point configuration
through a shielded twisted pair cable. The serializer and deserializer provide internal termination to minimize
impedance discontinuities. The interconnect (cable and connector) between the serializer and deserializer should
have a differential impedance of 100 Ω. The maximum length of cable that can be used is dependant on the
quality of the cable (gauge, impedance), connector, board (discontinuities, power plane), the electrical
environment (e.g. power stability, ground noise, input clock jitter, PCLK frequency, etc.) and the application
environment.
The resulting signal quality at the receiving end of the transmission media may be assessed by monitoring the
differential eye opening of the serial data stream. The Receiver CML Monitor Driver Output Specifications define
the acceptable data eye-opening width and eye-opening height. A differential probe should be used to measure
across the termination resistor at the CMLOUTP/N pin Figure 2.

DS90UB926Q-Q1
8.2.3 Application Curves
CML Serializer Data Throughput
78 MHz TX Pixel Clock Input

Magnitude (80 mV/DIV)
(200 mV/DIV)
(500 mV/DIV)
Time (100 ps/DIV) Time (2.5 ns/DIV)
Figure 26. Deserializer CMLOUT Eye Diagram With 78-MHz Figure 27. Deserializer FPD-Link III Input With 78-MHz TX
TX Pixel Clock Pixel Clock
9 Power Supply Recommendations

This section describes the power-up requirements and the PDB pin. The VDDs (V33 and VDDIO) supply ramp
should be faster than 1.5 ms with a monotonic rise. A large capacitor on the PDB pin is needed to ensure PDB
arrives after all the VDDs have settled to the recommended operating voltage. When PDB pin is pulled to VDDIO =
3.0 V to 3.6 V or VDD33, it is recommended to use a 10-kΩ pullup and a >10-uF cap to GND to delay the PDB
input signal.
All inputs must not be driven until VDD33 and VDDIO has reached its steady-state value.
10 Layout
10.1 Layout Guidelines

Circuit board layout and stack-up for the FPD-Link III devices should be designed to provide low-noise power
feed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs to
minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly
improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane
capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at
high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 µF to 0.1 µF. Tantalum capacitors may be in the 2.2 µF to 10 µF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 50 µF to 100 µF range and will smooth low-frequency switching noise. It is
recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors
connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external
bypass capacitor will increase the inductance of the path.
A small body size X7R chip capacitor, such as 0603 or 0402, is recommended for external bypass. Its small body
size reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple
capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing
the impedance at high frequency.

DS90UB926Q-Q1
Layout Guidelines (continued)

Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power
pin pairs. In some cases, an external filter may be used to provide clean power to sensitive circuits such as
PLLs.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the CML
lines to prevent coupling from the LVCMOS lines to the CML lines. Closely-coupled differential lines of 100 Ω are
typically recommended for CML interconnect. The closely coupled lines help to ensure that coupled noise will
appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also radiate less.
Information on the WQFN style package is provided in TI Application Note: AN-1187 (SNOA401).
Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste
deposition. Inspection of the stencil prior to placement of the WQFN package is highly recommended to improve
board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow
unevenly through the DAP. Stencil parameters for aperture opening and via locations are shown below:
Table 13. No Pullback WQFN Stencil Aperture Summary

DEVICE PIN MKT Dwg PCB I/O PCB PCB DAP STENCIL I/O STENCIL DAP NUMBER of
COUNT Pad Size PITCH SIZE (mm) APERTURE Aperture (mm) DAP
(mm) (mm) (mm) APERTURE
OPENINGS
DS90UB926Q-
60 NKB0060B 0.25 x 0.6 0.5 6.3 x 6.3 0.25 x 0.8 6.3 x 6.3 1
Q1
Figure 28 shows the PCB layout example derived from the layout design of the DS90UB926QSEVB Evaluation
Board. The graphic and layout description are used to determine both proper routing and proper solder
techniques when designing the Serializer board.
10.1.1 CML Interconnect Guidelines

See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details.
• Use 100-Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
– S = space between the pair
– 2S = space between pairs
– 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above 500-Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the TI
web site at: www.ti.com/lvds.

DS90UB926Q-Q1
10.2 Layout Example
Length-Matched RGB
Output Traces
AC Capacitors
NKB0060B High-Speed Traces
Figure 28. DS90UB926Q-Q1 Serializer Example Layout
Figure 29. 60-Pin WQFN Stencil Example of Via and Opening Placement

DS90UB926Q-Q1
11 Device and Documentation Support
11.1 Documentation Support

11.1.1 Related Documentation
For related documentation see the following:
• AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (SNLA008)
• AN-905 Transmission Line RAPIDESIGNER Operation and Applications Guide (SNLA035)
• AN-1187 Leadless Leadframe Package (LLP) (SNOA401)
• LVDS Owner’s Manual (SNLA187)
11.2 Trademarks
All trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 8-Oct-2014
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
DS90UB926QSQ/NOPB ACTIVE WQFN NKB 60 1000 Green (RoHS CU SN Level-3-260C-168 HR -40 to 105 UB926QSQ
& no Sb/Br)
DS90UB926QSQE/NOPB ACTIVE WQFN NKB 60 250 Green (RoHS CU SN Level-3-260C-168 HR -40 to 105 UB926QSQ
& no Sb/Br)
DS90UB926QSQX/NOPB ACTIVE WQFN NKB 60 2000 Green (RoHS CU SN Level-3-260C-168 HR -40 to 105 UB926QSQ
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 8-Oct-2014
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Sep-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90UB926QSQ/NOPB WQFN NKB 60 1000 330.0 16.4 9.3 9.3 1.3 12.0 16.0 Q1
DS90UB926QSQE/NOPB WQFN NKB 60 250 178.0 16.4 9.3 9.3 1.3 12.0 16.0 Q1
DS90UB926QSQX/NOPB WQFN NKB 60 2000 330.0 16.4 9.3 9.3 1.3 12.0 16.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Sep-2016
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DS90UB926QSQ/NOPB WQFN NKB 60 1000 367.0 367.0 38.0
DS90UB926QSQE/NOPB WQFN NKB 60 250 210.0 185.0 35.0
DS90UB926QSQX/NOPB WQFN NKB 60 2000 367.0 367.0 38.0
Pack Materials-Page 2
MECHANICAL DATA
NKB0060B
SQA60B (Rev B)
www.ti.com
IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its
semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated
circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
services.
Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced
documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements
different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the
associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
compliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2017, Texas Instruments Incorporated

Grafic Rlink2

Uploaded by

Copyright:

Available Formats

Grafic Rlink2

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Grafic Rlink2

Uploaded by

Copyright:

Available Formats

Product Sample & Technical Tools & Support & Reference

Folder Buy Documents Software Community Design

DS90UB926Q-Q1 5- to 85-MHz 24-Bit Color FPD-Link III Deserializer With Bidirectional

• Automotive Drive Assistance

R[7:0] FPD-Link III R[7:0]

Changes from Revision A (April 2013) to Revision B Page

Changes from Original (July 2012) to Revision A Page

2 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated

Product Folder Links: DS90UB926Q-Q1

5 Pin Configuration and Functions

VDD33_A 48 28 ROUT8 / G0 / GPIO2

RIN+ 49 27 ROUT9 / G1 / GPIO3

CMLOUTP 52 DS90UB926Q-Q1 24 VDDIO

NC 54 DAP = GND 22 ROUT13 / G5

CAPP12 57 19 ROUT16 / B0 / GPO_REG4

CAPI2S 58 18 ROUT17 / B1 / GPO_REG5 / I2S_DB

MCLK 60 16 BISTC / INTB_IN

Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 3

4 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated

Product Folder Links: DS90UB926Q-Q1

Pin Functions (continued)

Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 5

6.2 ESD Ratings

6.3 Recommended Operating Conditions

6 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated

Product Folder Links: DS90UB926Q-Q1

6.4 Thermal Information

6.5 DC Electrical Characteristics

PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT

Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 7

DC Electrical Characteristics (continued)

8 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated

Product Folder Links: DS90UB926Q-Q1

6.6 AC Electrical Characteristics

PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT

Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 9

6.7 DC and AC Serial Control Bus Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

6.8 Timing Requirements

10 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated

Product Folder Links: DS90UB926Q-Q1

6.9 Timing Requirements for the Serial Control Bus

6.10 Switching Characteristics

Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 11

Switching Characteristics (continued)

(1) Specification is ensured by characterization and is not tested in production.

Figure 1. Checker Board Data Pattern

Figure 2. CML Output Driver

Product Folder Links: DS90UB926Q-Q1

Figure 3. LVCMOS Transition Times

START STOP START STOP

Figure 4. Delay - Latency

PCLK TRI-STATE or LOW Z or L

OFF IN LOCK TIME ACTIVE OFF

Figure 5. PLL Lock Times and PDB TRI-STATE Delay

Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 13

PASS ACTIVE HIGH

Figure 7. Output State (Setup and Hold) Times

Figure 8. BIST PASS Waveform