Can CTRL Usg

CAN-CTRL Core Users Guide
2.3.2 Receive Buffer

To reduce the load of received frames for the host controller, the core uses acceptance filters. The CAN-
CTRL core checks the message identifier during acceptance filtering. If the received frame matches the
filter criteria of one of the acceptance filters then it will be stored in the Receive Buffer (RB), which has
FIFO-like behavior.
Depending on the number of available message slots, the host controller does not need to read incoming
messages immediately. The CAN-CTRL core is able to generate interrupts upon every received
message, when the RB is full or filled to a user-selectable “almost full” limit. Because of the FIFO-like
behavior, the host controller always reads the oldest message from the RB.
2.3.3 Transmit Buffer

For frame transmission purposes, two Transmit Buffers (TB) are offered. The Primary TB (PTB) has a
higher priority, but is able to buffer only one frame. The Secondary TB (STB) has a lower priority. It can
act in FIFO or in priority mode. The priority decision between PTB and STB is fixed and fully independent
from the CAN bus arbitration. Bus arbitration is a priority decision based on the frame identifiers.
The STB can be commanded to transmit one or all stored frames. In FIFO mode with every transmission
the oldest frame inside this buffer is transmitted first. In priority mode the frame with the highest priority
inside this buffer (based on the frame identifier) is transmitted first.
A frame located in the PTB has always a higher priority for the CAN protocol machine than the frames in
the STB regardless of the frame identifiers. A PTB transmission stops and delays an STB transmission.
The STB transmission is automatically restarted after the PTB frame has been successfully transmitted.
A PTB transmission starts at the next transmit position that is possible by the CAN protocol (after the
next interframe space). Because of this, an STB transmission that has won the arbitration and is actually
transmitted, will be completed before.
Interrupting STB transmissions using a PTB transmission may happen in the following cases:
1. The STB is commanded to output all stored frames and the host controller decides to command
a PTB transmission before all STB transmissions are completed.
2. The STB is commanded to output a single frame and the host controller decides to command a
PTB transmission before the STB transmission is completed.
If the host controller waits until each commanded transmission is completed, then it can easily decide
which buffer shall transmit the next frame. As a drawback a message with a low-priority identifier may
block more important messages. Then the host could abort the message (chap. 2.3.5 ).
2.3.4 Transmit Buffer Application Example in FIFO Mode

In the example a CAN node is used for sensor measurements. The CAN system engineer has decided to
handle these sensor measurements with low priority. Therefore frame identifiers with low priority are
used for CAN frames carrying the sensor data.
The host controller automatically acquires measurement results and places them as CAN frames in the
STB. Because of high traffic at the CAN bus, it may happen that the sensor data frames cannot be
transmitted immediately and several frames remain in the STB for some time. Later, if there is less traffic
at the CAN bus, they will be transmitted.
In the situation where several frames remain in the STB, an event may happen that forces the host
controller to output an important high-priority frame. In such a situation, the host can use the PTB. A
frame in the PTB will be always transmitted before all frames in the STB.
The advantage of having two transmit buffers is the option to keep all messages. No message has to be
aborted (discarded) in case of a high-priority event.
CAST, Inc. CAN-CTRL–USG–6H(V)14N00S00–145 CONFIDENTIAL Page 14

Figure 2-2 Transmit Buffer Application Example (TSALL=1)
The given application example is explained step by step in Figure 2-2. In this figure, LPF_x is the
abbreviation of “low priority frame” and HPF means “high priority frame”. As can be seen, LPF_1 is
blocked by other higher priority frames from other CAN nodes in the first part of the figure. The host
controller puts a fourth frame into the STB (LPF_4) and then decides to output the HPF. Meanwhile, the
CAN bus was free to transmit LPF_1 which is followed by HPF, LPF_2 and so on.
The priority decision between the PTB and STB is done by the CAN protocol machine, but the CAN
protocol itself uses another independent priority decision mechanism which is called bus arbitration. For
bus arbitration the frame identifier defines the priority level.
In the example given above, it would be possible to place a frame with a very low-priority identifier in the
PTB while higher priority frames remain in the STB. For the decision between PTB and STB always the
PTB wins regardless of the frame identifier. It is the task of the host controller to place frames with
meaningful identifier priorities in the appropriate buffers.
2.3.5 Transmit Buffer Application Example in Priority Mode

In priority mode for the STB CAN-CTRL automatically changes the order of the frames inside the STB.
As a result the frame with the highest priority is transmitted first. The priority decision is the same as for
bus arbitration and therefore a frame identifier with a lower value has a higher priority. Regardless of that
the PTB has always the highest priority.
Reordering the frames inside the STB is done automatically as soon as new frame is prepared for
transmission and written to the STB. As a result the frame with the highest priority is selected for
transmission. For the host controller it is like fire-and-forget: it just needs to write a new frame into the
STB while priority mode is active.
In general a frame with a higher priority will never interrupt an active transmission. To give an example in
Figure 2-2 in the leftmost part the frame LPF_1 is currently under transmission while LPF_4 is written to
the STB. Even if LPF_4 has higher priority than LPF_1, still LPF_1 will be transmitted until it loses
arbitration on the bus. Then after the node has lost arbitration, LPF_4 will be selected for transmission
because of its priority.
Priority reordering is automatically done in background, but takes some time. During heavy load when a
lot of new frames with different priorities are written to the STB and the node loses arbitration or there
are errors on the bus, it may be that not the frame with the highest priority is selected. This may happen
if this frame has been written too shortly before the deadline for the decision which frame will be next.
But this is a very rare condition and in general the host should not care about this.
If two frames with the same priority are written to the STB, then the oldest frame will be transmitted first
regardless of any reordering with other lower- or higher-prioritized frames.
2.3.6 Aborting a Transmission

If the situation arises, where a message in a transmit buffer cannot be sent due to its low priority, this
would block the buffer for a long time. In order to avoid this, the host controller can withdraw the

transmission request and abort the message. Aborting is possible for PTB and STB as well as for single
or all frame transmission.

Table 2-1 CAN Bit Abbreviations
Abbreviation Description Comment

ID IDentifier
RTR Remote Transmission Request Remote or Data frame
SRR Substitute Remote Request
RRS Remote Request Substitution
IDE IDentifier Extension Standard or Extended frame
DLC Data Length Code Number of payload bytes
EDL Extended Data Length CAN 2.0 or CAN FD frame
FDF FD Format indicator (=EDL) CAN 2.0 or CAN FD frame
BRS Bit Rate Switch
ESI Error State Indicator
r1, r0, res Reserved bits
The CAN FD specification by Bosch (non-ISO) uses the name EDL while the CAN FD ISO specification
uses the name FDF for the same bit. Both names are synonyms. This document uses the name EDL.
For CAN FD ISO frames the stuff count is transmitted as a part of the CRC field. For CAN FD non-ISO
frames the stuff count is not part of the frame. Furthermore the CRC checkers have a different
initialization for non-ISO and ISO frames. Therefore ISO and non-ISO frames are incompatible.
The CAN protocol machine in the CAN-CTRL core automatically transmits and receives the frames and
embeds the appropriate control and status bits. The host controller is required to select the desired frame
type (IDE, RTR, EDL), chose the identifier and set the data payload.

Table 3-4 Register Map
Bit position Register name

7 6 5 4 3 2 1 0
0x00 Receive Buffer Registers
RBUF
to and
(and RTS)
0x4f Reception Time Stamp
0x50
to Transmit Buffer Registers TBUF
0x97
0x98
to Transmission Time Stamp TTS
0x9f
0xa0 RESET LBME LBMI TPSS TSSS RACTIVE TACTIVE BUSOFF CFG_STAT
0xa1 TBSEL LOM STBY TPE TPA TSONE TSALL TSA TCMD
*)
0xa2 FD_ISO TSNEXT TSMODE TTTBM - TSSTAT(1:0) TCTRL
0xa3 SACK ROM ROV RREL RBALL - RSTAT(1:0) RCTRL
0xa4 RIE ROIE RFIE RAFIE TPIE TSIE EIE TSFF RTIE
0xa5 RIF ROIF RFIF RAFIF TPIF TSIF EIF AIF RTIF
0xa6 EWARN EPASS EPIE EPIF ALIE ALIF BEIE BEIF ERRINT
0xa7 AFWL(3:0) EWL(3:0) LIMIT
*)
0xa8 S_Seg_1(7:0) S_Seg_1
*)
0xa9 - S_Seg_2(6:0) S_Seg_2
*)
0xaa - S_SJW(6:0) S_SJW
*)
0xab S_PRESC(7:0) S_PRESC
*)
0xac - F_Seg_1(4:0) F_Seg_1
*)
0xad - F_Seg_2(3:0) F_Seg_2
*)
0xae - F_SJW(3:0) F_SJW
*)
0xaf F_PRESC(7:0) F_PRESC
0xb0 KOER(2:0) ALC(4:0) EALCAP
*)
0xb1 TDCEN SSPOFF(6:0) TDC
0xb2 RECNT RECNT
0xb3 TECNT TECNT
*)
0xb4 - SELMASK - ACFADR ACFCTRL
0xb5 - TIMEPOS TIMEEN TIMECFG
0xb6 AE_7 AE_6 AE_5 AE_4 AE_3 AE_2 AE_1 AE_0 ACF_EN_0
0xb7 AE_15 AE_14 AE_13 AE_12 AE_11 AE_10 AE_9 AE_8 ACF_EN_1
*)
0xb8 ACODE_x or AMASK_x (7:0) ACF_0
*)
0xb9 ACODE_x or AMASK_x (15:8) ACF_1
*)
0xba ACODE_x or AMASK_x (23:16) ACF_2
*)
0xbb - AIDEE AIDE ACODE_x or AMASK_x (28:24) ACF_3
0xbc VERSION(7:0) VER_0
0xbd VERSION(15:8) VER_1
0xbe TBE TBF TBPTR(5:0) TBSLOT
0xbf WTIE WTIF TEIF TTIE TTIF T_PRESC(1:0) TTEN TTCFG
0xc0 REF_ID(7:0) REF_MSG_0
0xc3 REF_IDE - REF_ID(28:24) REF_MSG_3

Bit position Register name

0xc4 - TTPTR(5:0) TRIG_CFG_0
0xc5 TEW(3:0) - TTYPE(2:0) TRIG_CFG_1
0xc6 TT_TRIG(7:0) TT_TRIG_0
0xc7 TT_TRIG(15:8) TT_TRIG_1
0xc8 TT_WTRIG(7:0) TT_WTRIG_0
0xc9 TT_WTRIG(15:8) TT_WTRIG_1
0xca - -
0xcb - -
*)
register can only be written if bit RESET in register CFG_STAT is set.
An write access to an addressable location not shown in the register map (Table 3-4) results in no action
and a read access will result in the value 0x00.
Register addresses are given as an example. They can be selected using generic parameters before
synthesis. The example shows the default setting. The example for 8 / 16 / 32 hosts in Figure 3-3
assumes that every byte is addressable even if the host uses a wider native width.
Please mind the several gaps inside the register map. This is for better address segment alignment for a
wider host controller interface.
Please have in mind that configuration registers that are only for CAN FD cannot be used if the IP core is
reduced to only CAN 2.0B capability. Then these registers are tied to their reset values.

Figure 3-3 Memory Map for 8 / 16 / 32 Bit Interface

Table 3-5 Transmission Time Stamp TTS (0x98 to 0x9f)
Bits Name Access Function

Transmission Time Stamp
TTS holds the time stamp of the last transmitted frame for CiA 603 time stamping. Every new
63:0 TTS r-0 frame overwrites TTS if TTSEN=1. Depending on a generic parameter (chap. 3.2) the time-
stamp can be 32 or 64 wide. Unused bits are forced to 0. The TTS is intended to be used by
the time master to acquire the time-stamp of the SYNC message.
Table 3-6 Configuration and Status Register CFG_STAT (0xa0)

RESET request bit
1- The host controller performs a local reset of CAN-CTRL.
0- no local reset of CAN-CTRL
The some register (e.g for node configuration) can only be modified if RESET=1.
Bit RESET forces several components to a reset state. A detailed definition is given in chap.
3.6.11 . RESET is automatically set if the node enters “bus off” state (chap. 3.6.7 ).
7 RESET rw-1
Note that a CAN node will participate in CAN communication after RESET is switched to 0
after 11 CAN bit times. This delay is required by the CAN standard (bus idle time).
If RESET is set to 1 and immediately set to 0, then it takes some time until RESET can be
read as 0 and becomes inactive. The reason is clock domain crossing from host to CAN clock
domain. RESET is held active as long as needed depending on the relation between host and
CAN clock.
Loop Back Mode, External (chap. 3.6.10.4)
0- Disabled
6 LBME rw-0
1- Enabled
LBME should not be enabled while a transmission is active.
Loop Back Mode, Internal (chap. 3.6.10.4)
0- Disabled
5 LBMI rw-0
1- Enabled
LBMI should not be enabled while a transmission is active.
Transmission Primary Single Shot mode for PTB (chap. 3.6.10.1)
4 TPSS rw-0 0- Disabled
1- Enabled
Transmission Secondary Single Shot mode for STB (chap. 3.6.10.1)
3 TSSS rw-0 0- Disabled
1- Enabled
Reception ACTIVE (Receive Status bit)
2 RACTIVE r-0 1- The controller is currently receiving a frame.
0- No receive activity.
Transmission ACTIVE (Transmit Status bit)
1 TACTIVE r-0 1- The controller is currently transmitting a frame.
0- No transmit activity.
Bus Off (Bus Status bit, chap. 3.6.7 )
1- The controller status is “bus off”.
0 BUSOFF rw-0 0- The controller status is “bus on”.
Writing a 1 to BUSOFF will reset TECNT and RECNT. This should be done only for debugging.
See chap. 3.6.10.6 for details.
Table 3-7 Command Register TCMD (0xa1)

Transmit Buffer Select
Selects the transmit buffer to be loaded with a message. Use the TBUF registers for
access. TBSEL needs to be stable all the time the TBUF registers are written and when
7 TBSEL rw-0 TSNEXT is set.
0- PTB (high-priority buffer)
1- STB
The bit will be reset to the hardware reset value if (TTEN=1 and TTTBM=1).


Listen Only Mode (chap. 3.6.10.2)
0- Disabled
1- Enabled
LOM should not be enabled while a transmission is active. No transmission can be started
6 LOM rw-0
if LOM is enabled and LBME is disabled.
LOM=1 and LBME=0 disables all transmissions.
LOM=1 and LBME=1 disables the ACK for received frames and error frames, but enables
the transmission of own frames.
Transceiver Standby Mode (chap. 3.6.10.5)
0- Disabled
1- Enabled
This register bit is connected to the output signal stby which can be used to control a
5 STBY rw-0
standby mode of a transceiver.
STBY cannot be set to 1 if TPE=1, TSONE=1 or TSALL=1.
If the host sets STBY to 0 then the host needs to wait for the time required by the
transceiver to start up before the host requests a new transmission.
Transmit Primary Enable
1- Transmission enable for the message in the high-priority PTB
0- No transmission for the PTB
If TPE is set, the message from the PTB will be transmitted at the next possible transmit
position. A started transmission from the STB will be completed before, but pending new
messages are delayed until the PTB message has been transmitted.
TPE stays set until the message has been transmitted successfully or it is aborted using
4 TPE rw-0
TPA.
The host controller can set TPE to 1 but can not reset it to 0. This would only be possible
using TPA and aborting the message.
During the short time while the CAN-CTRL core resets the bit, it cannot be set by the
host.
The bit will be reset to the hardware reset value if RESET=1, BUSOFF=1, STBY=1,
(LOM=1 and LBME=0) or (TTEN=1 and TTTBM=1).
Transmit Primary Abort
1– Aborts a transmission from PTB which has been requested by TPE=1 but not
started yet. (The data bytes of the message remains in the PTB.)
0– no abort
The bit has to be set by the host controller and will be reset by CAN-CTRL. Setting TPA
automatically de-asserts TPE.
3 TPA rw-0
The host controller can set TPA to 1 but can not reset it to 0.
host.
The bit will be reset to the hardware reset value if RESET=1, BUSOFF=1 or (TTEN=1
and TTTBM=1).
TPA should not be set simultaneously with TPE.
Transmit Secondary ONE frame
1– Transmission enable of one in the STB. In FIFO mode this is the oldest message
and in priority mode this is the one with the highest priority.
TSONE in priority mode is difficult to handle, because it is not always clear which
message will be transmitted if new messages are written to the STB meanwhile.
The controller starts the transmission as soon as the bus becomes vacant and
no request of the PTB (bit TPE) is pending.
0– No transmission for the STB.
2 TSONE rw-0
TSONE stays set until the message has been transmitted successfully or it is aborted
using TSA.
The host controller can set TSONE to 1 but can not reset it to 0. This would only be
possible using TSA and aborting the message.
host.
Transmit Secondary ALL frames
1– Transmission enable of all messages in the STB.
The controller starts the transmission as soon as the bus becomes vacant and
1 TSALL rw-0
no request of the PTB (bit TPE) is pending.
0– No transmission for the STB.
TSALL stays set until all messages have been transmitted successfully or they are aborted


using TSA.
The host controller can set TSALL to 1 but can not reset it to 0. This would only be
possible using TSA and aborting the messages.
host.
If during a transmission the STB is loaded with a new frame then the new frame will be
transmitted too. In other words: a transmission initiated by TSALL is finished when the
STB becomes empty.
Transmit Secondary Abort
1– Aborts a transmission from STB which has been requested but not started yet.
For a TSONE transmission, only one frame is aborted while for a TSALL
Transmission, all frames are aborted.
One or all message slots will be released which updates TSSTAT.
All aborted messages are lost because they are not accessible any more.
If in priority mode a TSONE transmission is aborted, then it is not clear which
0 TSA rw-0
frame will be aborted if new frames are written to the STB meanwhile.
0– no abort
The bit has to be set by the host controller and will be reset by CAN-CTRL. Setting TSA,
automatically de-asserts TSONE or TSALL respectively.
The host controller can set TSA to 1 but can not reset it to 0.
The bit will be reset to the hardware reset value if RESET=1 or BUSOFF=1.
TSA should not be set simultaneously with TSONE or TSALL.
Setting both TSONE and TSALL is meaningless. While TSALL is already set, it is impossible to set
TSONE and vice versa. If both TSONE and TSALL are set simultaneously then TSALL wins and TSONE
is cleared by the CAN-CTRL core.
Table 3-8 Transmit Control Register TCTRL (0xa2)

CAN FD ISO mode
0- Bosch CAN FD (non-ISO) mode
1- ISO CAN FD mode (ISO 11898-1:2015)
7 FD_ISO rw-1 ISO CAN FD mode has a different CRC initialization value and an additional stuff bit count.
Both modes are incompatible and must not be mixed in one CAN network.
This bit has no impact to CAN 2.0B.
This bit is only writeable if RESET=1.
Transmit buffer Secondary NEXT
0- no action
1- STB slot filled, select next slot.
After all frame bytes are written to the TBUF registers, the host controller has to set
TSNEXT to signal that this slot has been filled. Then the CAN-CTRL core connects the TBUF
registers to the next slot. Once a slot is marked as filled a transmission can be started
using TSONE or TSALL.
6 TSNEXT rw-0
It is possible to set TSNEXT and TSONE or TSALL together in one write access.
TSNEXT has to be set by the host controller and is automatically reset by the CAN-CTRL
core immediately after it was set.
Setting TSNEXT is meaningless if TBSEL=0. In this case TSNEXT is ignored and
automatically cleared. It does not do any harm.
If all slots of the STB are filled, TSNEXT stays set until a slot becomes free (chap. 3.6.6 ).
TSNEXT has no meaning in TTCAN mode and is fixed to 0.
Transmit buffer Secondary operation MODE
0- FIFO mode
1- priority decision mode
In FIFO mode frames are transmitted in the order in that they are written into the STB.
5 TSMODE rw-0 In priority decision mode the frame with the highest priority in the STB is automatically
transmitted first. The ID of a frame is used for the priority decision. A lower ID means a
higher priority of a frame. A frame in the PTB has always the highest priority regardless of
the ID.
TSMODE shall be switched only if the STB if empty.


TTCAN Transmit Buffer Mode
If TTEN=0 then TTTBM is ignored, otherwise the following is valid:
0- separate PTB and STB, behavior defined by TSMODE
1- full TTCAN support: buffer slots selectable by TBPTR and TTPTR
For event-driven CAN communication (TTEN=0), the system provides PTB and STB and
the behavior of the STB is defined by TSMODE. Then TTTBM is ignored.
4 TTTBM rw-1 For time-triggered CAN communication (TTEN=1) with full support of all features including
time-triggered transmissions, TTTBM=1 needs to be chosen. Then the all TB slots are
addressable using TTPTR and TBPTR.
For time-triggered CAN communication (TTEN=1) with only support of reception time-
stamps, TTTBM=0 can be chosen. Then the transmit buffer acts as in event-driven mode
and the behavior can be selected by TSMODE.
TTTBM shall be switched only if the TBUF is empty.
3:2 - r-0 reserved
Transmission Secondary STATus bits
If TTEN=0 or TTTBM=0:
00 – STB is empty
01 – STB is less than or equal to half full
10 – STB is more than half full
1:0 TSSTAT r-0 11 – STB is full
If the STB is disabled using STB_DISABLE, then TSSTAT=00.
If TTEN=1 and TTTBM=1:
00 – PTB and STB are empty
01 – PTB and STB are not empty and not full
11 – PTB and STB are full
Table 3-9 Receive Control Register RCTRL (0xa3)

Self-ACKnowledge
7 SACK rw-0 0– no self-ACK
1– self-ACK when LBME=1
Receive buffer Overflow Mode
In case of a full RBUF when a new message is received, then ROM selects the following:
6 ROM rw-0
1– The new message will not be stored.
0– The oldest message will be overwritten.
Receive buffer OVerflow
1– Overflow. At least one message is lost.
5 ROV r-0
0– No Overflow.
ROV is cleared by setting RREL=1.
Receive buffer RELease
The host controller has read the actual RB slot and releases it. Afterwards the CAN-CTRL
4 RREL rw-0 core points to the next RB slot. RSTAT gets updated.
1– Release: The host has read the RB.
0– No release
Receive Buffer stores ALL data frames
3 RBALL rw-0 0– normal operation
1– RB stores correct data frames as well as data frames with error (chap. 3.6.9.4)
2 - r-0 Reserved
Receive buffer STATus
00 - empty
1:0 RSTAT r-0 01 - > empty and < almost full (AFWL)
10 -  almost full (programmable threshold by AFWL) but not full and no overflow
11 - full (stays set in case of overflow – for overflow signaling see ROV)
Table 3-10 Receive and Transmit Interrupt Enable Register RTIE (0xa4)

Receive Interrupt Enable
7 RIE rw-1
0 – Disabled, 1 – Enabled
RB Overrun Interrupt Enable
6 ROIE rw-1


RB Full Interrupt Enable
5 RFIE rw-1
RB Almost Full Interrupt Enable
4 RAFIE rw-1
Transmission Primary Interrupt Enable
3 TPIE rw-1
Transmission Secondary Interrupt Enable
2 TSIE rw-1
Error Interrupt Enable
1 EIE rw-1
If TTEN=0 or TTTBM=0: Transmit Secondary buffer Full Flag
1- The STB is filled with the maximal number of messages.
0- The STB is not filled with the maximal number of messages
0 TSFF r-0 If the STB is disabled using STB_DISABLE, then TSFF=0.
If TTEN=1 and TTTBM=1: Transmit buffer Slot Full Flag
1- The buffer slot selected by TBPTR is filled.
0- The buffer slot selected by TBPTR is empty.
Table 3-11 Receive and Transmit Interrupt Flag Register RTIF (0xa5)

Receive Interrupt Flag
7 RIF rw-0 1- Data or a remote frame has been received and is available in the receive buffer.
0- No frame has been received.
RB Overrun Interrupt Flag
1- At least one received message has been overwritten in the RB.
6 ROIF rw-0
0- No RB overwritten.
In case of an overrun both ROIF and RFIF will be set.
RB Full Interrupt Flag
1- All RBs are full. If no RB will be released until the next valid message is received,
5 RFIF rw-0
the oldest message will be lost.
0- The RB FIFO is not full.
RB Almost Full Interrupt Flag
4 RAFIF rw-0 1- number of filled RB slots  AFWL_i
0- number of filled RB slots < AFWL_i
Transmission Primary Interrupt Flag
1- The requested transmission of the PTB has been successfully completed.
3 TPIF rw-0
0- No transmission of the PTB has been completed.
In TTCAN mode, TPIF will never be set. Then only TSIF is valid.
Transmission Secondary Interrupt Flag
1- The requested transmission of the STB has been successfully completed.
2 TSIF rw-0 0- No transmission of the STB has been completed successfully.
In TTCAN mode TSIF will signal all successful transmissions, regardless of storage location of
the message.
Error Interrupt Flag
1- The border of the error warning limit has been crossed in either direction,
1 EIF rw-0
or the BUSOFF bit has been changed in either direction.
0- There has been no change.
Abort Interrupt Flag
1- After setting TPA or TSA the appropriated message(s) have been aborted.
It is recommended to not set both TPA and TSA simultaneously because both
0 AIF rw-0 source AIF.
0- No abort has been executed.
The AIF does not have an associated enable register.
See also chap. 3.6.5 for further information.
To reset an interrupt flag, the host controller needs to write an 1 to the flag. Writing a 0 has no effect. If a
new interrupt event occurs while the write access is active then this event will set the flag and override
the reset. This ensures that no interrupt event is lost.
Interrupt flags will only be set if the associated interrupt enable bit is set.

Table 3-12 ERRor INTerrupt Enable and Flag Register ERRINT (0xa6)

Error WARNing limit reached
7 EWARN r-0 1- One of the error counters RECNT or TECNT is equal or bigger than EWL
0- The values in both counters are less than EWL.
Error Passive mode active
6 EPASS r-0 0- not active (node is error active)
1- active (node is error passive)
5 EPIE rw-0 Error Passive Interrupt Enable
Error Passive Interrupt Flag. EPIF will be activated if the error status changes from error
4 EPIF rw-0
active to error passive or vice versa and if this interrupt is enabled.
3 ALIE rw-0 Arbitration Lost Interrupt Enable
2 ALIF rw-0 Arbitration Lost Interrupt Flag
1 BEIE rw-0 Bus Error Interrupt Enable
0 BEIF rw-0 Bus Error Interrupt Flag
Table 3-13 Warning Limits Register LIMIT (0xa7)

receive buffer Almost Full Warning Limit
AFWL defines the internal warning limit AFWL_i with n RB being the number of available
RB slots.
 AFWL nRB  16

2  AFWL 16  nRB  32
AFWL_i  
4  AFWL 32  n RB  64
7:4 AFWL(3:0) rw-0x1   
AFWL_i is compared to the number of filled RB slots and triggers RAFIF if equal. The
valid range of AFWL_i  1 n RB .
AFWL  0 is meaningless and automatically treated as 0x1.
(Note that AFWL is meant in this rule and not AFWL_i.)
AFWL_i  nRB is meaningless and automatically treated as n RB .
AFWL_i  nRB is a valid value, but note that RFIF also exists.
Programmable Error Warning Limit = (EWL+1)*8. Possible Limit values: 8, 16, … 128.
The value of EWL controls EIF.
3:0 EWL(3:0) rw-0xB
EWL needs to be transferred using CDC from host to CAN clock domain. During transfer
EWL register bits are write-locked for the host for a few clocks until CDC is complete.
Table 3-14 Bit Timing Register S_Seg_1 (0xa8)

Bit Timing Segment 1 (slow speed)
7:0 S_Seg_1(7:0) rw-0x3
The sample point will be set to t Seg_1  Seg_1  2  TQ after start of bit time.

Table 3-15 Bit Timing Register S_Seg_2 (0xa9)

7 - r-0 reserved
Bit Timing Segment 2 (slow speed)
6:0 S_Seg_2(6:0) rw-0x2 Time t Seg_2  Seg_2  1 TQ after the sample point.
Table 3-16 Bit Timing Register S_SJW (0xaa)

7 - r-0 reserved
Synchronization Jump Width (slow speed)
The Synchronization Jump Width t SJW  SJW  1 TQ is the maximum time for
6:0 S_SJW(6:0) rw-0x2
shortening or lengthening the Bit Time for resynchronization, where TQ is a time
quanta.
Table 3-17 Bit Timing Register F_Seg_1 (0xac)

7:5 - r-0 reserved
Bit Timing Segment 1 (fast speed)
4:0 F_Seg_1(4:0) rw-0x3
The sample point will be set to t Seg_1  Seg_1  2  TQ after start of bit time.
Table 3-18 Bit Timing Register F_Seg_2 (0xad)

7:4 - r-0 reserved
Bit Timing Segment 2 (fast speed)
3:0 F_Seg_2(3:0) rw-0x2 Time t Seg_2  Seg_2  1 TQ after the sample point.
Table 3-19 Bit Timing Register F_SJW (0xae)

7:4 - r-0 reserved
Synchronization Jump Width (fast speed)
3:0 F_SJW(3:0) rw-02

The Synchronization Jump Width t SJW  SJW  1 TQ is the maximum time for
shortening or lengthening the Bit Time for resynchronization, where TQ is a time
quanta.
Table 3-20 Prescaler Registers S_PRESC (0xab) and F_PRESC (0xaf)

Prescaler (slow and fast speed)
S_PRESC
7:0 rw-0x01 The prescaler divides the system clock to get the time quanta clock tq_clk.
F_PRESC
Valid range PRESC=[0x00, 0xff] results in divider values 1 to 256.

Table 3-21 Transmitter Delay Compensation Register TDC (0xb1)

Transmitter Delay Compensation ENable
7 TDCEN rw-0 TDC will be activated during the data phase of a CAN FD frame if BRS is active if TDCEN=1.
For more details about TDC see chap. 6.5.
Secondary Sample Point OFFset
6:0 SSPOFF rw-0x00 The transmitter delay plus SSPOFF defines the time of the secondary sample point for TDC.
SSPOFF is given as a number of TQ.
Writing to S_Seg_1, S_Seg_2, S_SJW, S_PRESC, F_Seg_1, F_Seg_2, F_SJW, F_PRESC and TDC is
only possible if RESET=1. A detailed description of the CAN bus bit timing is given in chap. 4. The reset
value sets the bit timing which is described in the example in chap. 6.3.
All timing parameters in are given for slow (prefix “S_”) and fast speed (prefix “F_”). Slow speed is used
for CAN 2.0 and the CAN FD arbitration phase. Fast speed is used for the CAN FD data phase.
Table 3-22 Error and Arbitration Lost Capture Register EALCAP (0xb0)
Reset
Bits Name Function
Value
Kind Of ERror (Error code)
000 - no error
001 - BIT ERROR
010 - FORM ERROR
011 - STUFF ERROR
100 - ACKNOWLEDGEMENT ERROR
7:5 KOER(2:0) r-0x0 101 - CRC ERROR
110 - OTHER ERROR
(dominant bits after own error flag, received active Error Flag too long,
dominant bit during Passive-Error-Flag after ACK error)
111 - not used
KOER is updated with each new error. Therefore it stays untouched when frames are
successfully transmitted or received.
4:0 ALC(4:0) r-0x0 Arbitration Lost Capture (bit position in the frame where the arbitration has been lost)
Table 3-23 Error Counter Registers RECNT (0xb2) and TECNT (0xb3)
Receive Error CouNT (number of errors during reception)
RECNT is incremented and decremented as defined in the CAN specification.
7:0 RECNT r-0x00
RECNT does not overflow. RECNT signals 0xff = 255 as maximum value. See chap. 3.6.7
for more details about RECNT and the “bus off” state.
Transmit Error CouNT (number of errors during transmission)
TECNT is incremented and decremented as defined in the CAN specification.
7:0 TECNT r-0x00
TECNT does not overflow. TECNT signals 0xff = 255 as maximum value. See chap. 3.6.7
for more details about TECNT and the “bus off” state.

Table 3-24 Acceptance Filter Control Register ACFCTRL (0xb4)

7:6 - r-0 reserved
SELect acceptance MASK
0- Registers ACF_x point to acceptance code
5 SELMASK rw-0
1- Registers ACF_x point to acceptance mask.
ACFADR selects one specific acceptance filter. (See Figure 3-4.)
4 - r-0 Reserved
acceptance filter address
ACFADR points to a specific acceptance filter. The selected filter is accessible using the
registers ACF_x. Bit SELMASK selects between acceptance code and mask for the
3:0 ACFADR rw-0
selected acceptance filter. (See Figure 3-4.)
A value of ACFADR>NR_OF_ACF-1 is meaningless and automatically treated as value
NR_OF_ACF-1. (See chap. 0 and Figure 3-4 for details about NR_OF_ACF.)
The acceptance filter registers ACF_x provide access to the acceptance filter codes ACODE_x and
acceptance filter masks AMASK_x depending on the setting of SELMASK. (See Figure 3-4 and also
Table 3-4). Read / Write access to ACF_x is only possible if RESET=1. If RESET=0 then reading from
ACF_x results in the value 0.
The acceptance filters are build using a true 32 bit wide memory and therefore a write access needs to
be performed as 32 bit write. See chap. 7.1.3 for further details.
Figure 3-4 Access to the Acceptance Filters
Table 3-25 Acceptance CODE ACODE_x (register ACF_x (0xb8 to 0xbb))

Acceptance CODE
1- ACC bit value to compare with ID bit of the received message
0- ACC bit value to compare with ID bit of the received message
ACODE_0 rw-0x00
7:0 ACODE_x(10:0) will be used for extended frames.
ACODE_x rw-u
ACODE_x(28:0) will be used for extended frames.
Only filter 0 is affected by the power-on reset. All other filters stay uninitialized.
See chap. 3.6.1 for further details.

Table 3-26 Acceptance MASK AMASK_x (register ACF_x (0xb8 to 0xbb))

Acceptance MASK
1- acceptance check for these bits of receive identifier disabled
0- acceptance check for these bits of receive identifier enable
AMASK_x(10:0) will be used for extended frames.
AMASK_0 rw-0xFF
7:0 AMASK_x(28:0) will be used for extended frames.
AMASK_x rw-u
Disabled bits result in accepting the message. Therefore the default configuration after
reset for filter 0 accepts all messages.
See chap. 3.6.1 for further details.
The AMASK_x includes additional bits in register ACF_3 (Table 3-27) which can be only accessed if
SELMASK=1. These bits can be used to accept only either standard or extended frames with the
selected ACODE / AMASK setting or to accept both frame types. Only acceptance filter 0 is affected by
the power-on reset and it is configured to accept both frame types after power-up.
Table 3-27 Bits in Register ACF_3, if SELMASK=1

Acceptance mask IDE bit check enable
rw-0 1- acceptance filter accepts either standard or extended as defined by AIDE
6 AIDEE
rw-u 0- acceptance filter accepts both standard or extended frames
Acceptance mask IDE bit value
If AIDEE=1 then:
rw-0
5 AIDE 1- acceptance filter accepts only extended frames
rw-u
0- acceptance filter accepts only standard frames
Table 3-28 Acceptance Filter Enable ACF_EN_0 (0xb6)

Acceptance filter Enable
1- acceptance filter enabled
0- acceptance filter disable
Each acceptance filter (AMASK / ACODE) can be individually enabled or disabled. Only
filter number 0 is enabled by default after hardware reset.
7:0 AE_x rw-0x01
Disabled filters reject a message. Only enabled filters can accept a message if the
appropriate AMASK / ACODE configuration matches.
To accept all messages one filter x has to be enabled by setting AE_x=1,
AMASK_x=0xff and ACODE_x=0x00. This is the default configuration after hardware
reset for filter x=0 while all other filters are disabled.
Table 3-29 Acceptance Filter Enable ACF_EN_1 (0xb7)

Acceptance filter Enable
1- acceptance filter enabled
0- acceptance filter disable
7:0 AE_x rw-0x00
Each acceptance filter (AMASK / ACODE) can be individually enabled or disabled.
Disabled filters reject a message. Only enabled filters can accept a message if the
appropriate AMASK / ACODE configuration matches.

Table 3-30 Version Information VER_0 (0xbc) and VER_1 (0xbd)

Version of CAN-CTRL, given as decimal value. VER_1 holds the major version and
VER_0
15:0 r VER_0 the minor version.
VER_1
Example: version 5x16N00S00 is represented by VER_1=5 and VER_0=16.
Table 3-31 CiA 603 Time-Stamping TIMECFG (0xb5)

7:2 - r-0 Reserved
TIME-stamping POSition
1 TIMEPOS rw-1 0 – SOF
1 – EOF (see chap. 5)
TIME-stamping ENable
0 TIMEEN rw-0 0 – disabled
1 – enabled
Table 3-32 TTCAN: TB Slot Pointer TBSLOT (0xbe)

set TB slot to “Empty”
1- slot selected by TBPTR shall be marked as “empty”
0- no action
TBE is automatically reset to 0 as soon as the slot is marked as empty and TSFF=0. If a
7 TBE rw-0
transmission from this slot is active, then TBE stays set as long as either the
transmission completes or after a transmission error or arbitration loss the transmission
is not active any more.
If both TBF and TBE are set, then TBE wins.
set TB slot to “Filled”
1- slot selected by TBPTR shall be marked as “filled”
6 TBF rw-0 0- no action
TBF is automatically reset to 0 as soon as the slot is marked as filled and TSFF=1.
If both TBF and TBE are set, then TBE wins.
Pointer to a TB message slot.
0x00 - Pointer to the PTB
others - Pointer to a slot in the STB
The message slot pointed to by TBPTR is readable / writable using the TBUF registers.
Write access is only possible if TSFF=0. Setting TBF to 1 marks the selected slot as
filled and setting TBE to 1 marks the selected slot as empty.
5:0 TBPTR rw-0x00 TBSEL and TSNEXT are unused in TTCAN mode and have no meaning.
TBPTR can only point to buffer slots, that exist in the hardware. Unusable bits of
TBPTR are fixed to 0.
TBPTR is limited to the PTB and 63 STB slots. More slots cannot be used in TTCAN
mode.
If TBPTR is too big and points to a slot that is not available, then TBF and TBE are
reset automatically and no action takes place.

Table 3-33 TTCAN: Time Trigger Configuration TTCFG (0xbf)

Time Trigger Enable
0 TTEN rw-0 1- TTCAN enabled, timer is running
0- disabled
TTCAN Timer PRESCaler
00b - 1
01b - 2
10b - 4
2:1 T_PRESC rw-0x0 11b - 8
The TTCAN time base is a CAN bittime defined by S_PRES, S_SEG_1 and S_SEG_2.
With T_PRESC an additional prescaling factor of 1, 2, 4 or 8 is defined.
T_PRESC can only be modified if TTEN=0, but it is possible to modify T_PRESC and set
TTEN simultaneously with one write access.
Time Trigger Interrupt Flag
TTIF will be set if TTIE is set and the cycle time is equal to the trigger time TT_TRIG.
3 TTIF rw-0 Writing an one to TTIF resets it. Writing a zero has no impact.
TTIF will be set only once. If TT_TRIG gets not updated, then TTIF will be not set
again in the next basic cycle.
Time Trigger Interrupt Enable
4 TTIE rw-1 If TTIE is set, then TTIF will be set if the cycle time is equal to the trigger time
TT_TRIG.
Trigger Error Interrupt Flag
5 TEIF rw-0 The conditions when TEIF will be set, are defined in chap. 4.4. There is no bit to enable
or disable the handling of TEIF.
Watch Trigger Interrupt Flag
6 WTIF rw-0 WTIF will be set if the cycle count reaches the limited defined by TT_WTRIG and WTIE
is set.
7 WTIE rw-1 Watch Trigger Interrupt Enable
Table 3-34 TTCAN: Reference Message REF_MSG_0 to REF_MSG_3 (0xc0 to 0xc3)

REFerence message IDentifier.
If REF_IDE is
1- REF_ID(28:0) is valid (extended ID)
0- REF_ID(10:0) is valid (standard ID)
REF_ID is used in TTCAN mode to detect a reference message. This holds for time
slaves (reception) as well as for the time master (transmission). If the reference
rw- message is detected and there are no errors, then the Sync_Mark of this frame will
28:0 REF_ID
0x0000 become the Ref_Mark.
REF_ID(2:0) is not tested and therefore the appropriate register bits are forced to 0.
These bits are used for up to 8 potential time masters.
CAN-CTRL recognizes the reference message only by ID. The payload is not tested.
Additional note: A time master will transmit a reference message in the same way as a
normal frame. REF_ID is intended for detection of a successful transmission of a
reference message.
31 REF_IDE rw-0 REFerence message IDE bit.
Table 3-4 gives a definition of the bit positions of REF_ID and REF_IDE inside REF_MSG_0 to
REF_MSG_2.
A write access to REF_MSG_3 starts a data transfer of the reference message to the CAN clock domain
(clock domain crossing). During this automatic transfer a write lock for all registers REF_MSG_0 to

REF_MSG_2 is active. The transfer takes up to 6 clocks in the CAN clock domain and up to 6 clocks in
the host clock domain. The write access to REF_MSG_2 is necessary to make a new reference
message active.
Table 3-35 TTCAN: Trigger Configuration TRIG_CFG_0 (0xc4)

Transmit Trigger TB slot Pointer
If TTPTR is too big and points to a slot that is not available, then TEIF is set and no
5:0 TTPTR rw-0x00 new trigger can be activated after a write access to TT_TRIG_1.
If TTPTR points to an empty slot, then TEIF will be set at the moment, when the
trigger time is reached.
7:6 - r-00 reserved
Table 3-36 TTCAN: Trigger Configuration TRIG_CFG_1 (0xc5)

Trigger Type
000b - Immediate Trigger for immediate transmission
001b - Time Trigger for receive triggers
010b - Single Shot Transmit Trigger for exclusive time windows
2:0 TTYPE(2:0) rw-0x0 011b - Transmit Start Trigger for merged arbitrating time windows
100b - Transmit Stop Trigger for merged arbitrating time windows
others - no action
The time of the trigger is defined by TT_TRIG. TTPTR selects the TB slot for the
transmit triggers. See chap. 4.4 for more details.
3 - r-0 reserved
Transmit Enable Window
For a single shot transmit trigger there is a time of up to 16 ticks of the cycle time
7:4 TEW(3:0) rw-0x0 where the frame is allowed to start. TWE+1 defines the number of ticks. See chap.
4.4.3 for further details.
TEW=0 is a valid setting and shortens the transmit enable window to 1 tick.
Table 3-37 TTCAN: Trigger Time TT_TRIG_0 and TT_TRIG_1 (0xc6 and 0xc7)
Trigger Time
7:0 TT_TRIG rw-0x00 TT_TRIG(15:0) defines the cycle time for a trigger. For a transmission trigger the
earliest point of transmission of the SOF of the appropriate frame will be TT_TRIG+1.
A write access to TT_TRIG_1 starts a data transfer of the trigger definition to the CAN clock domain
(clock domain crossing) and activates the trigger. If the trigger is active, then a write lock for all registers
TRIG_CFG_0, TRIG_CFG_1, TT_TRIG_0 and TT_TRIG_1 is active. The write lock becomes inactive
when the trigger time is reached (TTIF gets set is TTIE is enabled) or an error is detected (TEIF gets
set).
Table 3-38 TTCAN: Watch Trigger Time TT_WTRIG_0 and TT_WTRIG_1 (0xc8 and 0xc9)
Watch Trigger Time
7:0 TT_WTRIG rw-0xff TT_WTRIG(15:0) defines the cycle time for a watch trigger. The initial watch trigger is
the maximum cycle time 0xffff. See chap. 4.5 for more details.
A write access to TT_WTRIG_1 starts a data transfer of the trigger definition to the CAN clock domain
(clock domain crossing). During this automatic transfer a write lock for the registers TT_WTRIG_0 and
TT_WTRIG_1 is active. The transfer takes up to 6 clocks in the CAN clock domain and up to 6 clocks in
the host clock domain. The write access to TT_WTRIG_1 is necessary to make a new trigger active.

Table 3-39 Receive Buffer Registers RBUF – Standard Format (r-0)
Address Bit position Function

7 6 5 4 3 2 1 0
RBUF ID(7:0) Identifier
RBUF+1 - ID(10:8) Identifier
RBUF+2 - Identifier
RBUF+3 ESI - Identifier
RBUF+4 IDE=0 RTR EDL BRS DLC(3:0) Control
RBUF+5 KOER TX - Status
RBUF+6 CYCLE_TIME(7:0) TTCAN
RBUF+8 d1(7:0) Data byte 1
. … .
RBUF+72 RTS(7:0) CiA 603
. … .
RBUF+79 RTS(63:56) CiA 603
Table 3-40 Receive Buffer Registers RBUF – Extended Format (r-0)

7 6 5 4 3 2 1 0
RBUF ID(7:0) Identifier
RBUF+1 ID(15:8) Identifier
RBUF+2 ID(23:16) Identifier
RBUF+3 ESI - ID(28:24) Identifier
RBUF+4 IDE=1 RTR EDL BRS DLC(3:0) Control
RBUF+5 KOER TX - Status
. … .
RBUF+72 RTS(7:0) CiA 603
. … .
RBUF+79 RTS(63:56) CiA 603
The RBUF registers (0x00 to 0x47) point the message slot with the oldest received message in the RB
as can be seen in Figure 3-5. All RBUF registers can be read in any order.
KOER in RBUF has the same meaning as the bits KOER in register EALCAP. KOER in RBUF becomes
meaningful if RBALL=1 (chap. 3.6.9.4).
Status bit TX in RBUF is set to 1 if the loop back mode (chap. 3.6.10.4) is activated and the core has
received its own transmitted frame. This can be useful if LBME=1 and other nodes in the network do also
transmissions.
The time-stamp CYCLE_TIME will be stored in RBUF only in TTCAN mode. This is the cycle time at the
SOF of this frame. The cycle time of a reference message is always 0.
The Reception Time Stamps (RTS) for CiA 603 time-stamping are stored for each received message at
the end of the RBUF address range. Therefore in contrast to TTS, RTS is related to the actual selected
RBUF slot.

Figure 3-5 Schematic of the FIFO-like RB (example with 6 slots)
Table 3-41 Transmit Buffer Registers TBUF – Standard Format (rw-u)

7 6 5 4 3 2 1 0
TBUF ID(7:0) Identifier
TBUF+1 - ID(10:8) Identifier
TBUF+2 - Identifier
TBUF+3 TTSEN - Identifier
TBUF+4 IDE=0 RTR EDL BRS DLC(3:0) Control
TBUF+8 d1(7:0) Data byte 1
. … .
Table 3-42 Transmit Buffer Registers TBUF – Extended Format (rw-u)

7 6 5 4 3 2 1 0
TBUF ID(7:0) Identifier
TBUF+1 ID(15:8) Identifier
TBUF+2 ID(23:16) Identifier
TBUF+3 TTSEN - ID(28:24) Identifier
TBUF+4 IDE=1 RTR EDL BRS DLC(3:0) Control
. … .
The TBUF registers (0x48 to 0x8f) point the next empty message slot in the STB if TBSEL=1 or to the
PTB otherwise. Seen in Figure 3-6 for more details. All TBUF registers can be written in any order. For
the STB it is necessary to set TSNEXT to mark a slot filled and to jump to the next message slot.
Please mind the gap inside the addressing range of TBUF from TBUF+5 to TBUF+7. This is for better
address segment alignment. The memory cells in the gap can be read and written, but have no meaning
for the CAN protocol.
TBUF is build using a true 32 bit wide memory and therefore a write access needs to be performed as 32
bit write. See chap. 7.1.3 for further details.
Both RBUF and TBUF include some frame-individual control bits (Table 3-43). For RBUF these bits
signal the status of the appropriate CAN control field bits of the received CAN frame while for TBUF
these bits select the appropriate CAN control field bit for the frame that has to be transmitted.
In contrast to RTS, which is stored for every received frame, TTS is stored only for the last transmitted
frame if TTSEN=1. TTS is not related to the actual selected TBUF slot.

Table 3-43 Control bits in RBUF and TBUF

Bit Description
IDentifier Extension
IDE 0 – Standard Format: ID(10:0)
1 – Extended Format: ID(28:0)
Remote Transmission Request
0 – data frame
1 – remote frame
Only CAN 2.0 frames can be remote frames. There is no remote frame for CAN FD. Therefore RTR
RTR
is forced to 0 if EDL=1 in TBUF and RBUF.
If a CAN FD frame is received with bit RRS=1, then this is ignored, a data payload is expected for
reception instead and RTR in RBUF is overridden but the CRC of the frame is calculated with
RRS=1.
Extended Data Length
EDL 0 – CAN 2.0 frame (up to 8 bytes payload)
1 – CAN FD frame (up to 64 bytes payload)
Bit Rate Switch
0 – nominal / slow bit rate for the complete frame
BRS
1 – switch to data / fast bit rate for the data payload and the CRC
Only CAN FD frames can switch the bitrate. Therefore BRS is forced to 0 if EDL=0.
Error State Indicator
This is a read-only status bit for RBUF and is not available in TBUF.
The protocol machine automatically embeds the correct value of ESI into transmitted frames. ESI
is only included in CAN FD frames and does not exist in CAN 2.0 frames.
ESI
0 – CAN node is error active
1 – CAN node is error passive
ESI in RBUF is always low for CAN 2.0 frames.
The error state for transmission is shown with bit EPASS in register ERRINT.
Transmit Time-Stamp ENable
For CiA 603 time-stamping the acquisition of a transmit time stamp TTS can be selected in the
TTSEN TBUF:
0 – no acquisition of a transmit time stamp for this frame
1 – TTS update enabled
The Data Length Code (DLC) in RBUF and TBUF defines the length of the payload – the number of
payload bytes in a frame. See Table 3-44 for further details.
Remote frames (only for CAN 2.0 frames where EDL=0) are always transmitted with 0 payload bytes, but
the content of the DLC is transmitted in the frame header. Therefore it is possible to code some
information into the DLC bits for remote frames. But then care needs to be taken if different CAN nodes
are allowed to transmit a remote frame with the same ID. In this case all transmitters need to use the
same DLC because otherwise this would result in an unresolvable collision.

Table 3-44 Definition of the DLC (according to the CAN 2.0 / FD specification)
DLC (binary) Frame Type Payload in Bytes
0000 to 1000 CAN 2.0 and CAN FD 0 to 8
1001 to 1111 CAN 2.0 8
1001 CAN FD 12
1010 CAN FD 16
1011 CAN FD 20
1100 CAN FD 24
1101 CAN FD 32
1110 CAN FD 48
1111 CAN FD 64
Figure 3-6 Schematic of PTB and STB in FIFO mode (empty PTB and 6 STB slots)
The TBUF registers and readable and writable. Therefore a host controller may use TBUF to
successively prepare a message bit-by-bit if necessary.
3.6 General Operation

This chapter describes handling of CAN communication. Before communication is possible, the CAN-
CTRL core has to be configured to match the CAN bus timings. A detailed description of the CAN bus bit
timing is given in chap. 4.
3.6.1 Acceptance Filters

To reduce the load of received frames for the host controller, the core uses acceptance filters. The CAN-
CTRL core checks the message identifier during acceptance filtering. Therefore the length of each
acceptance filter is 29 bits.
If a message passes one of the filters then it will be accepted. If accepted, the message will be stored
into the RB and finally RIF is set if RIE is enabled. If the message is not accepted, RIF is not set and the
RB FIFO pointer is not increased. Messages that are not accepted will be discarded and overwritten by
the next message. No stored valid message will be overwritten by any not accepted message.
Independently of the result of acceptance filtering, the CAN-CTRL core checks every message on the
bus and sends an acknowledge or an error frame to the bus.

Figure 3-7 Example of acceptance filtering
The acceptance mask defines which bits shall be compared while the acceptance code defines the
appropriate values. Setting mask bits to 0 enables the comparison of the selected acceptance code bits
with the corresponding message identifier bits. Mask bits that are set to 1 are disabled for the
acceptance check and this results in accepting the message.
The identifier bits will be compared with the corresponding acceptance code bits ACODE as follows:
 standard: ID(10:0) with ACODE(10:0)
 extended: ID(28:0) with ACODE(28:0)
Example: If AMASK_x(0)=0 and all other AMASK_x bits are 1 then the value of the last ID bit has to be
equal to ACODE(0) for an accepted message. All other ID bits are ignored by the filter.
Figure 3-7 gives an example of acceptance filtering using several filters. In this example the filter 0 and 1
are enabled by the appropriate AE_x bits in the ACF_EN_x registers. All other filters are disabled and
therefore do not accept any message. For the enabled filters the combination of AMASX_x and
ACODE_x defines if a message is accepted (like in the example for filter 0) or not accepted (like in the
example for filter 1).
Note: Disabling a filter by setting AE_x=0 blocks messages. In contrast to this disabling a mask bit in
AMASK_x disables the check for this bit which results in accepting messages.
The definitions of AMASK and ACODE alone do not distinguish between standard or extended frames. If
bit AIDEE=1 then the value of AIDE defines with frame type is accepted. Otherwise if AIDE=0 both types
are accepted.
After power-on reset the CAN-CTRL core is configured to accept all messages. (Filter 0 is enabled by
AE_0=1, all bits in AMASK_0 are set to 1 and AIDEE=0. All other filters are disabled. Filter 0 is the only
filter that has defined reset values for AMASK / ACODE while all other filters have undefined reset
values.)
3.6.2 Message Reception

The received data will be stored in the RB as shown in Figure 3-8. The RB is configurable by a pre-
synthesis parameter and has FIFO-like behavior. Every received message that is valid and accepted sets
RIF=1 if RIE is enabled. RSTAT is set depending of the fill state. When the number of filled buffers is
equal to the programmable value AFWL then RAFIF is set if RAFIE is enabled. In case, when all buffers
are full, the RFIF is set if RFIE is enabled.

Figure 3-8 Schematic of the FIFO-like RB (example with 6 slots)
The RB always maps the message slot containing the oldest message to the RBUF registers.
The maximum payload length for CAN 2.0 messages is 8 bytes and for CAN FD messages 64 bytes.
The individual length of each message is defined by the DLC. Because of this the RB provides slots for
each message and the host controller is required to set RREL to jump to the next RB slot. All RBUF
bytes of the actual slot can be read in any order.
th
If the RB is full, the next incoming message will be stored temporarily until it passes for valid (6 EOF
bit). Then if ROM=0 the oldest message will be overwritten by the newest or if ROM=1 the newest
message will be discarded. In both cases ROIF is set if ROIE is enabled. If the host controller reads the
oldest message and sets RREL before a new incoming message becomes valid then no message will be
lost.
3.6.3 Handling message receptions

Without acceptance filtering the CAN-CTRL core would signal the reception of every frame and the host
would be required to decide if it was addressed. This would result in quite a big load on the host
controller.
It is possible to disable interrupts and use the acceptance filters to reduce the load for the host controller.
For a basic operation RIF is set to 1 if RIE is enabled and the CAN-CTRL core has received a valid
message. To reduce the number of reception interrupts it is possible to use RAIE / RAIF (RB Almost full
Interrupt) or RFIE / RFIF (RB Full Interrupt) instead of RIE / RIF (Reception Interrupt). The “almost full
limit” is programmable using AFWL.
The RB contains a number of RB slots which is selectable before synthesis using a generic parameter.
Reading the RB shall be done as follows:
1. Read the oldest message from the RB FIFO using the RBUF registers.
2. Release the RB slot with RREL=1. This selects the next message (the next FIFO slot). RBUF will
be updated automatically.
3. Repeat these actions until RSTAT signals an empty RB.
th
If the RB FIFO is full and a new received message is recognized as valid (6 EOF bit) then one message
will be lost (see bit ROM). Before this event, no message is lost. This should give enough time for the
host controller to read at least one frame from the RB after the RB FIFO has been filled and the selected
interrupt has occurred. To enable this behavior the RB includes one more (hidden) slot than specified by
the synthesis parameter RBUF_SLOTS. This hidden slot is used to receive a message, validate it and
check it if it matches the acceptance filters before an overflow occurs.
3.6.4 Message Transmission

Before starting any transmission, at least one of the transmit buffers (PTB or STB) has to be loaded with
a message (Figure 3-9). TPE signals if the PTB is locked and TSSTAT signals the fill state of the STB.
The TBUF registers provide access to both the PTB as well as to the STB. Below is the recommended
programming flow:
1. Set TBSEL to the desired value to select either the PTB or the STB.
2. Write the frame to the TBUF registers.
3. For the STB set TSNEXT=1 to finish loading of this STB slot.

Figure 3-9 Schematic of PTB and STB in FIFO mode (empty PTB and 6 STB slots)
The maximum payload length for CAN 2.0 messages is 8 bytes and for CAN FD messages 64 bytes.
The individual length of each message is defined by the DLC. For remote frames (bit RTR) the DLC
becomes meaningless, because remote frames always have a data length of 0 bytes. The host controller
is required to set TSNEXT to jump to the next STB slot. All TBUF bytes can be written in any order.
Setting TSNEXT=1 is meaningless if TBSEL=0 selects the PTB. In this case TSNEXT is automatically
cleared and does no harm.
Bit TPE should be set to start a transmission when using the PTB. To use the STB, TSONE has to be set
to start a transmission of a single message or TSALL to transmit all messages.
The PTB has always a higher priority than the STB. If both transmit buffers have the order to transmit,
the PTB message will be always sent first regardless of the frame identifiers. If a transmission from the
STB is already active, it will be completed before the message from the PTB is sent at the next possible
transmit position (the next interframe slot). After the PTB transmission is completed or aborted, the CAN-
CTRL core returns to process other pending messages from the STB. See also chap. 2.3.3 for further
details.
When the transmission is completed, the following transmission interrupts are set:
 For the PTB, TPIF is set if TPIE is enabled
 For the STB using TSONE, TSIF is set if one message has been completed and TSIE is
enabled.
 For the STB using TSALL, TSIF is set if all messages have been completed and if TSIE is
enabled. In other words: TSIE is set if the STB is empty. Therefore, if the host controller writes
an additional message to the STB after a TSALL transmission has been started then the
additional message will be also transmitted before TSIF will be set.
It is meaningless to set TSONE or TSALL while the STB is empty. In such a case TSONE respectively
TSALL will be reset automatically. No interrupt flag will be set and no frame will be transmitted.
3.6.5 Message transmission abort

If the situation arises, where a message in a transmit buffer cannot be sent due to its low priority, this
would block the buffer for a long time. In order to avoid this, the host controller can withdraw the
transmission request by setting TPA or TSA respectively, if the transmission has not yet been started.
Both TPA and TSA source a single interrupt flag: AIF. The CAN protocol machine executes an abort only
if it does not transmit anything to the CAN bus. Therefore the following is valid:
 There is no abort during bus arbitration.
o If the node loses arbitration, the abort will be executed afterwards.
o If the node wins arbitration, the frame will be transmitted.
 There is no abort while a frame is transmitted.

o If a frame is transmitted successfully then a successful transmission is signaled to the

host controller. In this case no abort is signaled. This is done by the appropriate
interrupt and status bits.
o After an unsuccessful transmission where the CAN node does not receive an
acknowledge, the error counter is incremented and the abort will be executed.
o If there is at least one frame left in the STB, while the host has commanded all frames
to be transmitted (TSALL=1), then both the completed frame as well as the abort is
signaled to the host.
Because of these facts aborting a transmission may take some time depending on the CAN
communication speed and frame length. If an abort is executed, this results in the following actions:
 TPA releases the PTB which results in TPE=0.
The frame data is still stored in the PTB after releasing the PTB.
 TSA releases one single message slot or all message slots of the STB. This depends on
whether TSONE or TSALL was used to start the transmission. TSSTAT will be updated
accordingly. Releasing a frame in the STB results in discarding the frame data because the host
cannot access it.
Setting both TPA and TSA simultaneously is not recommended. If a host controller decides to do it
anyway, then AIF will be set and both transmissions from PTB and STB will be aborted if possible. As
already stated if one transmission will be completed before the abort can be executed this will result in
signaling a successful transmission. Therefore the following interrupt flags may be set if enabled:
 AIF (once for both PTB and STB transmission abort)
 TPIF + AIF
 TSIF + AIF
 TPIF + TSIF (very seldom, will only happen if the host does not handle TPIF immediately)
 TPIF + TSIF + AIF (very seldom, will only happen if the host does not handle TPIF and TSIF
immediately)
To clear the entire STB both TSALL and TSA need to be set. In order to detect if a message cannot be
sent for a long time because it loses arbitration the host may use the ALIF / ALIE.
3.6.6 A Full STB

After writing a message to the STB, TSNEXT=1 marks a buffer slot filled and jumps to the next free
message slot. TSNEXT is automatically reset to 0 by the CAN-CTRL core after this operation.
If the last message slot has been filled and therefore all message slots are occupied then TSNEXT stays
set until a new message slot becomes free. While TSNEXT=1, then writing to TBUF is blocked by the
CAN-CTRL core.
When a slot becomes free, then the CAN-CTRL core automatically resets TSNEXT to 0. A slot becomes
free if a frame form the STB is transmitted successfully or if the host requests an abort (TSA=1). If a
TSALL transmission is aborted, then TSNEXT is also reset, but additionally the complete STB is marked
as empty.
3.6.7 Error Handling

On one hand CAN-CTRL does automatic error handling which means that in most cases the host
controller does not care about errors. This includes automatic message retransmission and automatic
deletion of received messages with errors. On the other hand if required by the host, CAN-CTRL may
optionally give detailed information about errors and signal every error to the host by interrupt. This
enables to run an application like a CAN bus monitor at the host.
Every CAN node has 3 states of error handling:
1. Error-Active: The node automatically transmits active error frames upon detection of an error.
2. Error-Passive: The node transmits passive error frame upon detection of an error. This means
that it does not transmit a dominant value to the but, but expects an error frame.

3. Bus Off: After too many errors a node goes “bus off” where it stops touching the bus.
To handle the 3 error states every CAN node has two error counters: the transmit and the receive error
counter. Both are incremented and decremented as defined by the CAN specification and the node
enters the appropriate error state upon reaching a counter level defined by the CAN specification.
The error counters are incremented if there are errors. Dangerous errors that are probably caused by
this node will result in incrementing the counter by 8, errors that are probably caused by other nodes will
result in incrementing the counter by 1. Valid frame transmission or valid receptions result in
decrementing the counters. All this is defined by the CAN specification and handled automatically by
CAN-CTRL.
An error frame (better: an error flag) is different to a data frame. It is a dominant pulse for at least 6
consecutive dominant bits, which is a stuff bit violation for other nodes. A host controller cannot
command to transmit an error frame. It is done fully automatically by CAN-CTRL.
If CAN-CTRL is commanded to transmit a frame then it automatically tries retransmissions as fast as
possible until the frame gets transmitted without error or the node goes bus off. If a frame is received and
CAN-CTRL detects an error, then the received data is discarded. Because of the automatically
transmitted error frame the sender of the frame will retransmit the frame. Frames in RBUF are never
overwritten by frames with errors. Only valid received frames may result in a RBUF overflow.
3.6.8 The Bus Off State

The “bus off” state is signaled using the status bit BUSOFF in register CFG_STAT (Table 3-6). A CAN
node enters the “bus off” state automatically if its transmit error counter becomes >255. Then it will not
take part in further communications until it returns into the error-active state again. Setting BUSOFF to 1
also sets the EIF interrupt if EIE is enabled. A CAN node returns to error-active state if it is reset by a
power-on reset or if it receives 128 sequences of 11 recessive bits (recovery sequences).
In the “bus off” state, RECNT is used to count the recovery sequences while TECNT stays unchanged.
Please note that while entering bus off state TECNT rolls over and therefore may hold a small value.
Therefore it is recommended to use TECNT before the node enters bus off state and status bit BUSOFF
afterwards.
If the node recovers from “bus off” state then RECNT and TECNT are automatically reset to 0.
When BUSOFF gets set then RESET is automatically set. See chap. 3.6.11 for details about this
software reset. Therefore both RECNT and TECNT are not affected by the software reset.
3.6.9 Extended Status and Error Report

During CAN bus communication transmission errors may occur. The following features support detection
and analysis of them. This can be used for extended bus monitoring.
3.6.9.1. Programmable Error Warning Limit
Errors during reception / transmission are counted by RECNT and TECNT. A programmable error
warning limit EWL, located in register LIMIT, can be used by the host controller for flexible reaction on
those events. The limit values can be chosen in steps of 8 errors from 8 to 128:
Limit of count of errors = (EWL+1)*8
The interrupt EIF will be set if enabled by EIE under the following conditions:
 the border of the error warning limit has been crossed in either direction by RECNT or TECNT or
 the BUSOFF bit has been changed in either direction.
3.6.9.2. Arbitration Lost Capture (ALC)
The core is able to detect the exact bit position in the Arbitration Field where the arbitration has been
lost. This event can be signaled by the ALIF interrupt if it is enabled. The value of ALC stays unchanged
if the node is able to win the arbitration. Then ALC holds the old value of the last loss of arbitration.
The value of ALC is defined as follows: A frame starts with the SOF bit and then the first bit of the ID is
transmitted. This first ID bit has ALC value 0, the second ID bit ALC value 1 and so on. See Figure 2-3
for the bit order in all types of CAN 2.0 and CAN FD frames.

Arbitration is only allowed in the arbitration field (Figure 2-3). Therefore the maximum value of ALC is 31
which is the RTR bit in extended frames.
Additional hint: If a standard remote frame arbitrates with an extended frame, then the extended frame
loses arbitration at the IDE bit and ALC will be 12. The node transmitting the standard remote frame will
not notice that an arbitration has been taken place, because this node has won.
It is impossible to get an arbitration loss outside of the arbitration field. Such an event is a bit error.
3.6.9.3. Kind Of Error (KOER)
The core recognizes errors on the CAN bus and stores the last error event in the KOER bits. A CAN bus
error can be signaled by the BEIF interrupt if it is enabled. Every new error event overwrites the previous
stored value of KOER. Therefore the host controller has to react quickly on the error event. The error
codes are described in the table 3-15.
KOER is updated with each new error. Therefore it stays untouched when frames are successfully
transmitted or received. This opens the opportunity for a delayed error investigation.
3.6.9.4. Reception of All Data Frames (RBALL)
If RBALL=1 then all received data frames are stored even those with error. This holds also for loop back
mode (chap. 3.6.10.4). Only data frames are stored in RBUF. Error frames or overload frames are not
stored.
If CiA 603 time-stamping (chap. 5) is enabled (TIMEEN=1) and the timestamp is configured for the EOF
(TIMEPOS=1) then in the case of an error the time-stamp is acquired at the start of the error frame.
Most of the possible errors can only occur if the node is the transmitter of the frame. In this case a frame
would only be stored in RBUF if a loop back mode is activated. Depending on the type of error parts of
the frame stored in an RBUF slot may be valid while other parts are unknown. Table 3-45 lists the
possibilities.
Table 3-45 RBALL and KOER
KOER Condition Description
no error All Successful reception.
Receiver Can only occur in the ACK slot. All stored data are valid.
The payload is always invalid. The header bits including the ID may be valid. In
the arbitration phase detection of a wrong bit is part of the arbitration and
BIT ERROR therefore not a BIT ERROR. But if a stuff bit in the arbitration phase is detected
Transmitter wrong by the transmitter of the frame, then this is a BIT ERROR and in this case
the header bits are invalid. Therefore the header bits cannot be trusted, but if the
header matches to an expected header of a frame, it can be used for further
investigation.
Only FORM ERRORs in a data frame are covered. This includes errors in the CRC
FORM ERROR All
delimiter, the ACK delimiter or the EOF bits. All stored data are valid.
Receiver The position of a STUFF ERROR is unknown. All stored data are invalid.
STUFF ERROR
Transmitter Can only happen during arbitration. All stored data are invalid.
Receiver Can only occur if the node is in LOM. All stored data are valid.
ACK ERROR
Transmitter Can only occur in loop back mode without self-ACK. All stored data are valid.
CRC ERROR Receiver All stored data are invalid.
Please note that even if Table 3-45 states that (parts of) the data are valid under certain conditions, then
care must be taken. There is no guarantee for this and it depends on the reason for the error if this
statement is correct. Example: if the node has a bad bit timing configuration then there is no correct
synchronization and therefore no valid data. Therefore the statement that (parts of) the data is valid
signals only the possibility that it is so.

3.6.10 Extended Features

3.6.10.1. Single Shot Transmission
Sometimes an automatic re-transmission is not desired. Therefore the order to transmit a message only
once can be set separately for the transmit buffers PTB by the bit TPSS and for the transmit buffer STB
by the bit TSSS. In this case no re-transmission will be performed in the event of an error or arbitration
lost if the selected transmission is active.
In the case of an immediate successful transmission there is no difference to normal transmission. But in
the case of an unsuccessful transmission the following will happen:
 TPIF gets set if enabled, the appropriate transmit buffer slot gets cleared
 In case of an error, KOER and the error counters get updated. BEIF gets set if BEIE is enabled
and the other error interrupt flags will act accordingly.
 In case of a lost arbitration, ALIF gets set if ALIE is enable.
Therefore for single shot transmission TPIF alone does not indicate if the frame has been successfully
transmitted. Therefore single shot transmission should only be used together with BEIF and ALIF.
If single shot transmission is used with TSALL and there is more than one frame in the STB then for each
frame a single shot transmission is done. Regardless if any of the frames is not successfully transmitted
(e.g. because of an ACK error) the CAN-CTRL advances to the next frame and stops if the STB is empty.
Therefore in this scenario only the error counters indicate what has happened. This can be quite
complex to evaluate because if one of two frames got errors the host cannot detect which one was the
successful one.
If the bus is occupied by another frame, if a single shot transmission is started, then CAN-CTRL waits till
the bus is idle and then tries to transmit the single shot frame.
3.6.10.2. Listen Only Mode (LOM)
LOM provides the ability of monitoring the CAN bus without any influence to the bus. LOM by CAN-CTRL
is compatible to the bus monitoring feature defined in the CAN FD specification.
Another application is the automatic bit rate detection where the host controller tries different timing
settings until no errors occur.
Errors will be monitored (KOER, BEIF) in LOM.
In LOM the core is not able to write dominant bits onto the bus (no active error flags or overload flags, no
acknowledge). This is done using the following rules:
 In LOM the protocol machine acts as if in error passive mode where only recessive error flags
are generated. Only the protocol machine acts as if in error passive mode. All other components
including the status registers are not touched.
 In LOM the protocol machine does not generate a dominant ACK.
 The error counters stay unchanged regardless of any error condition.
Important facts regarding ACKs for LOM:
 If a frame is transmitted by a node then an ACK visible at the bus will be only generated if at
least one additional node is attached to the bus that is not in LOM. Then there will be no error
and all nodes (also those in LOM) will receive the frame.
 If there is an active or passive error flag after an ACK error, then the node in LOM is able to
detect this as ACK error.
Activation of LOM should not be done while a transmission is active. The host controller has to take care
of this. There is not additional protection from CAN-CTRL.
If LOM is enabled then no transmission can be started.
The loop back mode (external) LBME (chap. 3.6.10.4) plays an important role for the behavior of LOM. If
LBME is disabled, then LOM acts as described above and the node cannot write any dominant bit to the
bus. But if LBME is activated, then the node is allowed to transmit a frame. LBME allows only the
transmission of an frame including the optional self-ACK (SACK), but the node will not respond with an

ACK to frames from other nodes and will not generate error or overload frames. In Summary the
combination of LOM and LBME is “a silent receiver, that is able to transmit if necessary”.
3.6.10.3. Bus Connection Test
To check if a node is connected to the bus the following steps shall be done:
 Transmit a frame. If the node is connected to the bus then its TX bits are visible on its RX input.
 If there are other nodes connected to the CAN bus, then a successful transmission (including an
acknowledge from the other nodes) is expected. No error will be signaled.
 If the node is the only node that is connected to the CAN bus (but the connection between the
bus, the transceiver and the CAN-CTRL core is fine) then the first regular error situation occurs
in the ACK slot because of no acknowledge from other nodes. Then a BEIF error interrupt will be
generated if enabled and KOER=“100” (ACK error).
 If the connection to the transceiver or the bus is broken then immediately after the SOF bit the
BEIF error interrupt will be set and KOER=“001” (BIT error).
3.6.10.4. Loop Back Mode (LBMI and LBME)
CAN-CTRL supports two Loop Back Modes: internal (LBMI) and external (LBME). Both modes result in
reception of the own transmitted frame which can be useful for self-tests. See Figure 3-10 for details.
In LBMI CAN-CTRL is disconnected from the CAN bus and the txd output is set to recessive. The output
data stream is internally fed back to the input. In LBMI the node generates a self-ACK to avoid an ACK
error.
In LBME CAN-CTRL stays connected to the transceiver and a transmitted frame will be visible on the
bus. With the help of the transceiver CAN-CTRL receives its own frame. In LBME the node does not
generate a self-ACK when SACK=0, but generates a self-ACK when SACK=1. Therefore in LBME with
SACK=0 there are two possible results upon a frame transmission:
1. Another node receives the frame too and generates an ACK. This will result in a successful
transmission and reception.
2. No other node is connected to the bus and this results in an ACK error. To avoid retransmissions
and incrementing the error counters it is recommended to use TPSS or TSSS if it is unknown if
other nodes are connected.
Figure 3-10 Loop Back Mode: Internal and External
In Loop Back Mode the core receives its own message, stores it in the RBUF and sets the appropriate
receive and transmit interrupt flags if enabled.
LBMI can be useful for chip-internal and software tests while LBME can test the transceiver and the
connections to it.
Activation of LBMI or LBME should not be done while a transmission is active. The host controller has to
take care of this. There is not additional protection from CAN-CTRL.
If the node is connected to a CAN bus then switching back from LBMI to normal operation must not be
done by simply setting LBMI to 0, because then it may be that this occurs just at the moment while
another CAN node is transmitting. In this case switching back to normal operation shall be done by

setting bit RESET to 1. This automatically clears LBMI to 0. Finally RESET can be disabled and the core
returns back to normal operation. In contrast to this LBME can be disabled every time.
LBME can be used in combination with LOM. Details are given in chap. 3.6.10.2.
3.6.10.5. Transceiver Standby Mode
Using the register bit STBY the output signal stby is driven. It can be used to activate a standby mode for
a transceiver. The behavior is compatible to the NXP TJA1049 transceiver.
Once standby is activated no transmission is possible and therefore TPE, TSONE and TSALL cannot be
set. On the other hand CAN-CTRL does not allow STBY to be set if a transmission is already active
(TPE, TSONE or TSALL is set).
If STBY is set the transceiver enters a low-power mode. In this mode it is unable to receive a frame at full
speed but monitors the CAN bus for a dominant state. If the dominant state is active for a time which is
defined in the transceivers data sheet the transceiver will pull the rxd signal low. If rxd is low CAN-CTRL
automatically clears STBY to 0 which disables standby mode for the transceiver. This is done silently
without an interrupt to the host controller.
Switching from standby mode to active mode takes some time for the transceiver and therefore the initial
wakeup frame cannot be received successfully. Therefore the node recently being in standby will not
respond with an ACK. If no CAN node at the bus responds to the wakeup frame with an ACK then this
results in an ACK error for the transmitter of the wakeup frame. Then the transmitter will automatically
repeat the frame. During the repetition the transceiver will be back in active mode and CAN-CTRL will
receive the frame and will respond with an ACK.
In summary: One node transmits a frame for wakeup. If all others nodes are in standby mode, then the
transmitter gets an ACK error and will automatically repeat the frame. During the repetition the nodes are
back in active mode and will respond with an ACK.
STBY is not affected by bit RESET.
3.6.10.6. Error Counter Reset
According to the CAN / CAN FD standard RECNT counts receive errors and TECNT counts transmit
errors. After too many transmit errors a CAN node has to go to busoff state (chap. 3.6.7 ). This will
activate the bit RESET. Deactivating the bit RESET does not modify the errors counters or busoff state.
The CAN / CAN FD specification defines rules how to disable busoff state and to decrease the error
counters. A good node will recover from all of this automatically if only a temporary error has caused the
problems. The classic CAN 2.0B specification requires this automatic behavior without host controller
interaction to avoid the babbling idiot problem.
The CAN FD specification relaxes this and allows the host controller to override the automatic error
counter handling. But this should be used with extra care and is suggested to use only for debugging
purposes.
Writing a 1 to the bit BUSOFF resets the error counters and therefore forces the node to leave the busoff
state. This is done without setting EIF.
3.6.11 Software Reset

If bit RESET in CFG_STAT is set to 1 then the software reset is active. Several components are forced to
a reset state if RESET=1 but no all components are touched by RESET. Some components are only
sensitive to a hardware reset. The reset values of all bits are always the same for software and hardware
reset.
Table 3-46 Software Reset
Register RESET Comment
ACFADR No -
ACODE_x No Register is writeable if RESET=1 and write-locked if 0.
AE_x No -
AFWL No -
AIF Yes -
ALC Yes -


ALIE No -
ALIF Yes -
AMASK_x No Register is writeable if RESET=1 and write-locked if 0.
BEIE No -
BEIF Yes -
BUSOFF (No) An error counter reset by setting BUSOFF=1 also resets BUSOFF.
EIE No -
EIF No -
EPASS No -
EPIE No -
EPIF Yes -
EWARN No -
EWL Yes -
FD_ISO No Register is writeable if RESET=1 and write-locked if 0.
F_PRESC No Register is writeable if RESET=1 and write-locked if 0.
F_Seg_1 No Register is writeable if RESET=1 and write-locked if 0.
F_Seg_2 No Register is writeable if RESET=1 and write-locked if 0.
F_SJW No Register is writeable if RESET=1 and write-locked if 0.
KOER Yes -
LBME Yes -
LBMI Yes -
LOM Yes -
Reception is immediately cancelled even if a reception is active. No ACK will be
RACTIVE Yes
generated.
RAFIE No -
RAFIF Yes -
RBALL Yes -
RBUF (Yes) All RB slots are marked as empty. RBUF contains unknown data.
RECNT No An error counter reset is possible by setting BUSOFF=1.
REF_ID No -
REF_IDE No -
RFIE No -
RFIF Yes -
RIE No -
RIF Yes -
ROIE No -
ROIF Yes -
ROM No -
ROV Yes All RB slots are marked as empty.
RREL Yes -
RSTAT Yes All RB slots are marked as empty.
SACK Yes -
SELMASK No -
STBY No -
S_PRESC No Register is writeable if RESET=1 and write-locked if 0.
S_Seg_1 No Register is writeable if RESET=1 and write-locked if 0.
S_Seg_2 No Register is writeable if RESET=1 and write-locked if 0.
S_SJW No Register is writeable if RESET=1 and write-locked if 0.
All transmissions are immediately terminated with RESET. If a transmission is active
TACTIVE Yes
this will result in an erogenous frame. Other nodes will generate error frames.
TBE Yes -


TBF Yes -
TBPTR No -
TBSEL Yes TBUF fixed to point to PTB.
TBUF (Yes) All STB slots are marked as empty. Because of TBSEL TBUF points to the PTB.
TECNT No An error counter reset is possible by setting BUSOFF=1.
TEIF Yes -
TIMEEN No -
TIMEPOS No -
TPA Yes -
TPE Yes -
TSA Yes -
TSALL Yes -
TSMODE No -
TSNEXT Yes -
TSONE Yes -
TPIE No -
TPIF Yes -
TPSS Yes -
TSFF Yes All STB slots are marked as empty.
TSIE No -
TSIF Yes -
TSSS Yes -
TSSTAT Yes All STB slots are marked as empty.
TTEN Yes -
TTIF Yes -
TTIE No -
TTPTR No -
TTS No -
TTTBM No -
TTYPE No -
TT_TRIG No -
TT_WTRIG No -
T_PRESC No -
WTIE No -
WTIF Yes -

6. CAN Bit Time
6.1 Data Bit Rates

CAN 2.0B defines data bit rates up to 1Mbit/s. For CAN FD there is no fixed limitation. For real life
systems the data rates are limited by the used transceiver and the achievable clock frequency for the
CAN-CTRL core which depends on the used target cell library.
The CAN-CTRL core can be programmed to arbitrarily chosen data rates only limited by the range of the
bit settings in the appropriate bit timing and prescaler registers.
6.2 Definitions
Figure 6-1 CAN Bit Timing Specifications
The CAN bit time BT consists of several segments as shown in Figure 6-1. Each segment consists of a
number of time quanta units nTQ . The duration of a time quanta TQ is:
n prescaler
TQ
f CLOCK
The values of nTQ and n prescaler have to be chosen depending on the system clock frequency f CLOCK to
match BTreal as close as possible to BTideal  1 BR where BR is the CAN bus baud rate:
n prescaler  nTQ
BTideal  BTreal   t Seg_1  t Segt_2
f CLOCK
The CAN specification requires several relationships between the segment lengths (Table 6-1) which
results in relationships between t Seg _ 1 , t Seg _ 2 and the maximum synchronization jump width t SJW . Please
note that Table 6-1 lists the minimum configuration ranges defined by the CAN / CAN FD specification.

Table 6-1 CAN Timing Segments (Minimum Configuration Ranges)

Segment Description
SYNC_SEG Synchronization Segment = 1 TQ
Propagation Segment
[1...8] TQ CAN 2.0 bit rate CAN FD not enabled
PROP_SEG [1...48] TQ CAN 2.0 bit rate CAN FD enabled
[1…48] TQ CAN FD nominal bit rate
[0...8] TQ CAN FD data bit rate
Phase Buffer Segment 1
PHASE_SEG1 [1...16] TQ CAN 2.0 bit rate CAN FD enabled
[1...16] TQ CAN FD nominal bit rate
Phase Buffer Segment 2
PHASE_SEG2 [2...16] TQ CAN 2.0 bit rate CAN FD not enabled
Synchronization Jump Width
SJW [1...16] TQ CAN 2.0 bit rate CAN FD not enabled
Information Processing Time = [0...2] TQ
IPT
PHASE_SEG2 ≥ IPT
As can be seen in Figure 6-1 the CAN-CTRL core collects SYNC_SEG, PROP_SEG and PHASE_SEG1
into one group and the length of the group is configurable with t Seg _ 1 . Table 6-2 lists the available
configuration ranges. Please note that the CAN-CTRL core does not check if all rules are met and offers
a wider configuration range than defined by the CAN / CAN FD specification.
Table 6-2 CAN-CTRL Timing Settings (Available Configuration ranges)
Setting Requirements
[2…65] TQ CAN 2.0 bit rate (slow)
t Seg _ 1 [2…65] TQ CAN FD nominal bit rate (slow)
[2…17] TQ CAN FD data bit rate (fast)
[1…8] TQ t Seg _ 1  t Seg _ 2  2 CAN 2.0 bit rate (slow)
tSeg _ 2 [1…32] TQ t Seg _ 1  t Seg _ 2  2 CAN FD nominal bit rate (slow)
[1…8] TQ t Seg _ 1  t Seg _ 2  1 CAN FD data bit rate (fast)
[1…16] TQ t Seg _ 2  t SJW CAN 2.0 bit rate (slow)
t SJW [1…16] TQ t Seg _ 2  t SJW CAN FD nominal bit rate (slow)
[1…8] TQ t Seg _ 2  t SJW CAN FD data bit rate (fast)
For CAN 2.0 bit rate and CAN FD (slow) nominal bit rate the register settings S_Seg_1, S_Seg_2,
S_SJW and S_PRESC define the appropriate segment lengths. For CAN FD (fast) data bit rate the
register F_Seg_1, F_Seg_2, F_SJW and F_PRESC are valid.
t Seg _ 1  S _ Seg _ 1  2 TQ t Seg _ 1  F _ Seg _ 1  2 TQ
t Seg _ 2  S _ Seg _ 2  1 TQ t Seg _ 2  F _ Seg _ 2  1 TQ
t SJW  S _ SJW  1 TQ t SJW  F _ SJW  1 TQ
n prescaler  S _ PRESC  1 n prescaler  F _ PRESC  1
A CAN FD core switches from slow nominal bit rate to fast data bit rate at the sample point in the BRS bit
and switches back at the sample point in the CRC delimiter bit.

f CLOCK
An illustration a suitable bit rate configuration is given in Figure 6-2 where f tq_clk  . The bit time
n prescaler
BTreal , the sample point and the synchronization jump width SJW will be derived from tq_clk.
Figure 6-2 Clock Division for Bit Sampling
Having the requirements from Table 6-2 in mind the host controller has to define the length of segment 1,
segment 2 and the synchronization jump width for the slow bit rate and if required for CAN FD for the fast
bit rate.
Some suggestions, given as rules of the thumb:
 Segment 1 must be slightly larger than segment 2. Then the sample point is in the a little bit later
than in the middle of the bit time.
 The synchronization jump width must not be bigger than segment 2. If SJW is too small the CAN
node may be too slow to resynchronize, if SJW is too big then the CAN node may resynchronize
too often. SJW being half as long as segment 2 seems to be a suitable value.
 All CAN nodes connected to a CAN bus should choose similar settings if possible.
The fastest CAN bus speed can be configured using the minimum timing values. But there are some
things that need to be considered:
 If the prescalers are bigger than one then all other timing parameters could be set to zero, but
this violates the rule t Seg _ 1  t Seg _ 2  2 (slow speed) resp. t Seg _ 1  t Seg _ 2  1 (fast speed) and
therefore S_Seg_1 and F_Seg_1 should be at least set to 1. But such a selecting of timing
parameters works in theory, but may not be robust enough for real nets.
 If the prescalers are set to one then synchronization becomes difficult. In general the CAN
specification requires one bit time to be at least 8 TQ long for CAN 2.0 and CAN FD slow
nominal bit rate. For CAN-CTRL one bit time of fast data bit rate needs to be also at least 8 TQ
long if the fast prescaler is set to 1.
 In summary the fastest CAN bus frequency is the can_clk frequency divided by 8: prescalers set
to 1 and 8 TQ bit time.
6.3 Example Configuration

This example refers to Figure 6-2. It is an example for CAN 2.0 / slow bit rate configuration but all
statements can be easily translated to CAN FD (fast) data bit rate. The following steps need to be carried
for the configuration of the CAN-CTRL core:
1. Set bit RESET=1.
2. Set registers S_Seg_1 and S_Seg_2:
In the example the data rate on the bus f BUS  1 Mbaud and the system clock is 16 MHz .
The values of nTQ and n prescaler have to be selected to fit BTreal as close as possible to BTideal .
In this example n prescaler  2 and nTQ  8 are chosen which results in a perfect match:
BTideal  BTreal  8 TQ .
With BTreal  t Seg_1  t Segt_2 and the time segment definitions given in chapter 6.1 t Seg_1  5 TQ

and t Seg_2  3 TQ can be chosen as suitable values which finally results in the register settings
S_Seg_1=3 and S_Seg_2=2.
3. Load the acceptance code and mask registers (optional).
4. Set register S_SJW:
With t Seg_2  t SJW one is free to chose t SJW  3 which finally results in 2.
5. Load the clock prescaler register S_PRESC: n prescaler  PRESC  1 results in S_PRESC=1.
6. Set bit RESET=0.
The given order is not mandatory. It is merely necessary to set bit RESET=1 at the beginning, as
it is otherwise not possible to load the bit timing, ACODE and AMASK registers. RESET=0 is
required upon completion of the configuration. The controller then waits for 8 recessive bits
(frame end) and resumes its normal operation.
7. Continue with configuration of interrupts other configuration bits and execute commands.
6.4 CAN Bit Timing Calculator (CBC)

The release package includes a software tool for MS Windows for the calculation of the CAN bit timings.
This tool can be used to calculate the CAN 2.0 as well as the CAN FD nominal and data bit rates.
Starting with the setting of the clock frequency of the CAN-CTRL core and the desired Baud rate this tool
outputs all possible settings for the prescaler, segment 1 and segment 2. For SJW the tool gives the
maximum value. Furthermore the tool outputs the position of the sample point as a factor of a bit time.
The tool gives on one hand the time in multiples of TQ as well as the register value. For example
“t_seg1=7” means that segment 1 is 7 TQ long and the register value needs to be set to S_Seg_1=5.
By default the tool tries to calculate the settings with a tolerance of 0%. In other words: With the given
clock speed and these settings the desired baud rate will be synthesized exactly. It is possible to modify
the tolerance setting to get also settings that will not match exactly. Please note that the tool does not
check if the selected tolerance is inside of the CAN specification.
This tool performs and exhaustive search for possible settings. The calculation time will increase for fast
baud rates and a big tolerance value. The tools searches for settings in steps of 1 Baud.
Additionally to the software tool a MS Excel sheet is included in the release package. This sheet can be
useful if CAN-CTRL needs to be adapted to an existing CAN network where the bit timing configuration is
already fixed. This Excel sheet includes the configuration parameters recommended by CAN in
Automation (CiA).
6.5 Bit Rate Switching and the Sample Point

In a CAN network when CAN FD frames with bit rate switching are used the exact position of the sample
point is important and needs to be for all nodes as similar as possible.
The bit rate is switched after the sample point of the BRS bit and the sample point of the CRC delimiter.
Therefore the lengths of these bits are intermediate. As can be seen in Figure 6-3 the position of the
sample point makes a big difference for the absolute length of the BRS bit. (1 TQ of the slow nominal bit
rate may be much bigger than several TQs of the fast data rate.) If the data rate is much higher than the
nominal bit rate then an earlier or later sample point may lead to false samples at fast data bit rate.

Figure 6-3 Bit Rate Switching at bit BRS S _ PRESC  F _ PRESC

6.6 Bit Timing Configuration for CAN FD Nodes
As stated in chap. 6.5 the position of the sample point is very important for bit rate switching. Therefore
there is the general recommendation for all CAN FD nodes to use exactly the same timing parameters in
a CAN network. In contrast to classic CAN where only the data rate needs to be the same for all nodes,
CAN FD requires the sample point at the same position. In others words segment 1 and segment 2 need
to be configured to the same length for all nodes. Furthermore it is recommended to use also the same
length of one TQ to make synchronization for all nodes equal.
This requirement can only be achieved if all nodes run with the same base clock frequency (called
can_clk for CAN-CTRL) or at least with compatible clock frequencies. The recommended settings are
20MHz, 40MHz or 80MHz.
6.7 TDC and RDC

For CAN FD nodes transmitter delay compensation (TDC) can be optionally enabled while receiver delay
compensation (RDC) is automatically active. These features have the following background: For
communication with CAN FD data bit rate it may be that the delay of the transmitting transceiver or the
delay of the bus is bigger than a bit time. This needs to be compensated. Without TDC, the bit rate in the
data-phase of FD frames is limited by the fact that the transmitter detects a bit error if it cannot receive its
own transmitted bit latest at the sample point of that bit.
Figure 6-4 Transmitter Delay
Figure 6-4 gives an example of the effect of a big transmitter delay. In this figure a txd data stream is
shown starting with bits A and B. One bit time consists of t Seg_1  5 TQ before the Sample Point (SP)
and t Seg_2  3 TQ behind. In this example the transmitter delay is longer than 2 bit times. Therefore the
original SP cannot be used to sample the correct bit value and the CAN FD specification defines an
additional Secondary Sample Point (SSP). If TDC is enabled with bit TDCEN=1 then CAN-CTRL
automatically determines the transmitter delay. The position of the SSP is the transmitter delay plus the
SSP Offset which is defined by the configuration bits SSPOFF. SSPOFF must be given as a number of
TQ and it is suggested to set t Seg_1 equal to SSPOFF. (Please remember that F_SEG_1 defines t Seg_1
during data bit rate. Therefore in the example given in Figure 6-4 SSPOFF=5 is chosen.)
CAN-CTRL is capable of automatically determining a transmitter delay of at least 4 bit times of the fast
data bit rate. The exact amount depends on the system clock and the chosen CAN bit timing
configuration.

A delay bigger than a bit time needs to be taken into account also for receiving nodes. CAN FD defines
an additional hard synchronization at the falling edge between bit EDL=1 and the following r0 bit. (At this
time the slow nominal bit rate is active.) Synchronization for CAN and CAN FD is in general defined to
operate in time steps of one TQ. But steps of one TQ at nominal bit rate may be to coarse for a
synchronization for the fast data bit rate. Therefore the additional hard synchronization at the EDL bit
needs to violate this rule and needs to synchronize as exact as possible and only limited by the clock
frequency of the system. CAN-CTRL uses this special synchronization and this is called RDC. RDC is
automatically done during reception if EDL=1, no matter if TDC is enabled or not.
6.8 Bit Timing Recommendations

CAN FD timing configuration requires to use the same data rate and the same sample point for all nodes
in a CAN network. Therefore it is recommended to use 20MHz, 40MHz or 80MHz as source for the CAN
protocol machine (can_clk). In Table 6-4, Table 6-5 and Table 6-6 there are some recommendations for
the bit timing settings that should apply to all nodes in a CAN FD network. These settings are
recommendations from CAN in Automation (CiA).
Please note that the bit time should be at least 8 TQ if the prescaler is set to 1 for a stable
communication. Lower settings are possible, but may cause problems.
The decision if TDC is used or not depends on the CAN network. The tables only give a suggestion and
TDC can be enabled or disabled as needed.
Table 6-3 Abbreviations for Table 6-4, Table 6-5 and Table 6-6
Abbreviation Description
PSP Primary Sample Point
SSP Secondary Sample Point
Seg 1 Segment 1
Seg 2 Segment 2
TDC Transmitter Delay Compensation (see SSPOFF)
Table 6-4 Recommendations for 20MHz can_clk

Bit Rate PSP SSP Bit Time Seg 1 Seg 2 SJW TDC
Prescaler
[Mbit/s] [%] [%] [TQ] [TQ] [TQ] [TQ] [clk]
0.25
80 - 1 80 64 16 16 -
(arbitration)
0.5
80 - 1 40 32 8 8 -
(arbitration)
0.5 80 (disable) 1 40 32 8 8 -
0.833 79 (disable) 1 24 19 5 5 -
1 80 80 1 20 16 4 4 16
1.538 77 77 1 13 10 3 3 10
2 80 80 1 10 8 2 2 8
4 80 80 1 5 4 1 1 4
5 75 75 1 4 3 1 1 3


Prescaler
0.25
80 - 1 160 128 32 32 -
(arbitration)
0.5
80 - 1 80 64 16 16 -
(arbitration)
0.5 80 (disable) 2 40 32 8 8 -
0.833 79 (disable) 2 24 19 5 5 -
1 80 80 1 40 32 8 8 32
1.538 77 77 1 26 20 6 6 20
2 80 80 1 20 16 4 4 16
3.077 77 77 1 13 10 3 3 10
4 80 80 1 10 8 2 2 8
5 75 75 1 8 6 2 2 6
6.667 83 83 1 6 5 1 1 5
8 80 80 1 5 4 1 1 4
10 75 75 1 4 3 1 1 3

Prescaler
0.25
80 - 2 160 128 32 32 -
(arbitration)
0.5
80 - 2 80 64 16 16 -
(arbitration)
0.5 80 (disable) 4 40 32 8 8 -
0.833 79 (disable) 4 24 19 5 5 -
1 80 80 2 40 32 8 8 64
1.538 77 77 2 26 20 6 6 40
2 80 80 2 20 16 4 4 32
3.077 77 77 2 13 10 3 3 20
4 80 80 2 10 8 2 2 16
5 75 75 2 8 6 2 2 12
6.667 83 83 1 12 10 2 2 10
8 80 80 1 10 8 2 2 8
10 75 75 1 8 6 2 2 6

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CAN-CTRL Core Users Guide

2.3.2 Receive Buffer

2.3.3 Transmit Buffer

2.3.4 Transmit Buffer Application Example in FIFO Mode

CAST, Inc. CAN-CTRL–USG–6H(V)14N00S00–145 CONFIDENTIAL Page 14

Figure 2-2 Transmit Buffer Application Example (TSALL=1)

2.3.5 Transmit Buffer Application Example in Priority Mode

2.3.6 Aborting a Transmission

CAST, Inc. CAN-CTRL–USG–6H(V)14N00S00–145 CONFIDENTIAL Page 15

CAST, Inc. CAN-CTRL–USG–6H(V)14N00S00–145 CONFIDENTIAL Page 16

Table 2-1 CAN Bit Abbreviations

Abbreviation Description Comment

CAST, Inc. CAN-CTRL–USG–6H(V)14N00S00–145 CONFIDENTIAL Page 17

Table 3-4 Register Map

Bit position Register name

CAST, Inc. CAN-CTRL–USG–6H(V)14N00S00–145 CONFIDENTIAL Page 22

Bit position Register name

CAST, Inc. CAN-CTRL–USG–6H(V)14N00S00–145 CONFIDENTIAL Page 23

Figure 3-3 Memory Map for 8 / 16 / 32 Bit Interface

CAST, Inc. CAN-CTRL–USG–6H(V)14N00S00–145 CONFIDENTIAL Page 24

Table 3-5 Transmission Time Stamp TTS (0x98 to 0x9f)

Bits Name Access Function

Table 3-6 Configuration and Status Register CFG_STAT (0xa0)

Bits Name Access Function

Table 3-7 Command Register TCMD (0xa1)

Bits Name Access Function

CAST, Inc. CAN-CTRL–USG–6H(V)14N00S00–145 CONFIDENTIAL Page 25

Bits Name Access Function

CAST, Inc. CAN-CTRL–USG–6H(V)14N00S00–145 CONFIDENTIAL Page 26

Bits Name Access Function

Table 3-8 Transmit Control Register TCTRL (0xa2)

Bits Name Access Function

CAST, Inc. CAN-CTRL–USG–6H(V)14N00S00–145 CONFIDENTIAL Page 27

Bits Name Access Function

Table 3-9 Receive Control Register RCTRL (0xa3)

Bits Name Access Function

Bits Name Access Function

CAST, Inc. CAN-CTRL–USG–6H(V)14N00S00–145 CONFIDENTIAL Page 28

Bits Name Access Function

Bits Name Access Function

CAST, Inc. CAN-CTRL–USG–6H(V)14N00S00–145 CONFIDENTIAL Page 29

Bits Name Access Function

Table 3-13 Warning Limits Register LIMIT (0xa7)

Bits Name Access Function

Table 3-14 Bit Timing Register S_Seg_1 (0xa8)

Bits Name Access Function

CAST, Inc. CAN-CTRL–USG–6H(V)14N00S00–145 CONFIDENTIAL Page 30

Table 3-15 Bit Timing Register S_Seg_2 (0xa9)

Bits Name Access Function

Table 3-16 Bit Timing Register S_SJW (0xaa)

Bits Name Access Function

Table 3-17 Bit Timing Register F_Seg_1 (0xac)

Bits Name Access Function

Table 3-18 Bit Timing Register F_Seg_2 (0xad)

Bits Name Access Function

Table 3-19 Bit Timing Register F_SJW (0xae)

Bits Name Access Function

3:0 F_SJW(3:0) rw-02

Table 3-20 Prescaler Registers S_PRESC (0xab) and F_PRESC (0xaf)