PIC18F2455/2550/4455/4550 Data Sheet
PIC18F2455/2550/4455/4550 Data Sheet
Data Sheet
28/40/44-Pin, High-Performance,
Enhanced Flash, USB Microcontrollers
with nanoWatt Technology
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
MCLR/VPP/RE3 1 28 RB7/KBI3/PGD
RA0/AN0 2 27 RB6/KBI2/PGC
RA1/AN1 3 26 RB5/KBI1/PGM
RA2/AN2/VREF-/CVREF 4 25 RB4/AN11/KBI0
RA3/AN3/VREF+ 5 24 RB3/AN9/CCP2(1)/VPO
PIC18F2455
PIC18F2550
RA4/T0CKI/C1OUT/RCV 6 23 RB2/AN8/INT2/VMO
RA5/AN4/SS/HLVDIN/C2OUT 7 22 RB1/AN10/INT1/SCK/SCL
VSS 8 21 RB0/AN12/INT0/FLT0/SDI/SDA
OSC1/CLKI 9 20 VDD
OSC2/CLKO/RA6 10 19 VSS
RC0/T1OSO/T13CKI 11 18 RC7/RX/DT/SDO
RC1/T1OSI/CCP2(1)/UOE 12 17 RC6/TX/CK
RC2/CCP1 13 16 RC5/D+/VP
VUSB 14 15 RC4/D-/VM
40-Pin PDIP
MCLR/VPP/RE3 1 40 RB7/KBI3/PGD
RA0/AN0 2 39 RB6/KBI2/PGC
RA1/AN1 3 38 RB5/KBI1/PGM
RA2/AN2/VREF-/CVREF 4 37 RB4/AN11/KBI0/CSSPP
RA3/AN3/VREF+ 5 36 RB3/AN9/CCP2(1)/VPO
RA4/T0CKI/C1OUT/RCV 6 35 RB2/AN8/INT2/VMO
RA5/AN4/SS/HLVDIN/C2OUT 7 34 RB1/AN10/INT1/SCK/SCL
RE0/AN5/CK1SPP 8 33 RB0/AN12/INT0/FLT0/SDI/SDA
PIC18F4455
PIC18F4550
RE1/AN6/CK2SPP 9 32 VDD
RE2/AN7/OESPP 10 31 VSS
VDD 11 30 RD7/SPP7/P1D
VSS 12 29 RD6/SPP6/P1C
OSC1/CLKI 13 28 RD5/SPP5/P1B
OSC2/CLKO/RA6 14 27 RD4/SPP4
RC0/T1OSO/T13CKI 15 26 RC7/RX/DT/SDO
RC1/T1OSI/CCP2(1)/UOE 16 25 RC6/TX/CK
RC2/CCP1/P1A 17 24 RC5/D+/VP
VUSB 18 23 RC4/D-/VM
RD0/SPP0 19 22 RD3/SPP3
RD1/SPP1 20 21 RD2/SPP2
RC1/T1OSI/CCP2(1)/UOE
44-Pin TQFP
NC/ICPORTS(2)
RC2/CCP1/P1A
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RD3/SPP3
RD2/SPP2
RD1/SPP1
RD0/SPP0
VUSB
44
43
42
41
40
39
37
36
35
34
38
RC7/RX/DT/SDO 1 33 NC/ICRST(2)/ICVPP(2)
RD4/SPP4 2 32 RC0/T1OSO/T13CKI
RD5/SPP5/P1B 3 31 OSC2/CLKO/RA6
RD6/SPP6/P1C 4 30 OSC1/CLKI
RD7/SPP7/P1D 5 PIC18F4455 29 VSS
VSS 6 28 VDD
VDD 7
PIC18F4550 27 RE2/AN7/OESPP
RB0/AN12/INT0/FLT0/SDI/SDA 8 26 RE1/AN6/CK2SPP
RB1/AN10/INT1/SCK/SCL 9 25 RE0/AN5/CK1SPP
RB2/AN8/INT2/VMO 10 24 RA5/AN4/SS/HLVDIN/C2OUT
RB3/AN9/CCP2(1)/VPO 11 23 RA4/T0CKI/C1OUT/RCV
12
13
14
15
16
17
18
19
20
21
22
RB4/AN11/KBI0/CSSPP
RA2/AN2/VREF-/CVREF
NC/ICCK(2)/ICPGC(2)
NC/ICDT(2)/ICPGD(2)
RB5/KBI1/PGM
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RB6/KBI2/PGC
RB7/KBI3/PGD
RA3/AN3/VREF+
RC1/T1OSI/CCP2(1)/UOE
RC0/T1OSO/T13CKI
RC2/CCP1/P1A
44-Pin QFN
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RD3/SPP3
RD2/SPP2
RD1/SPP1
RD0/SPP0
VUSB
44
43
42
41
40
39
37
36
35
34
38
RC7/RX/DT/SDO 1 33 OSC2/CLKO/RA6
RD4/SPP4 2 32 OSC1/CLKI
RD5/SPP5/P1B 3 31 VSS
RD6/SPP6/P1C 4 30 VSS
RD7/SPP7/P1D 5 PIC18F4455 29 VDD
VSS 28 VDD
6 PIC18F4550 27 RE2/AN7/OESPP
VDD 7
VDD 8 26 RE1/AN6/CK2SPP
RB0/AN12/INT0/FLT0/SDI/SDA 9 25 RE0/AN5/CK1SPP
RB1/AN10/INT1/SCK/SCL 10 24 RA5/AN4/SS/HLVDIN/C2OUT
RB2/AN8/INT2/VMO 11 23 RA4/T0CKI/C1OUT/RCV
12
13
14
15
16
17
18
19
20
21
22
RB4/AN11/KBI0/CSSPP
RB3/AN9/CCP2(1)/VPO
RA2/AN2/VREF-/CVREF
RB5/KBI1/PGM
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
NC
RB6/KBI2/PGC
RB7/KBI3/PGD
RA3/AN3/VREF+
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
8
Instruction State Machine
Decode & Control Signals
Control
PRODH PRODL
PORTC
8 x 8 Multiply RC0/T1OSO/T13CKI
3 8 RC1/T1OSI/CCP2(3)/UOE
(2) Internal RC2/CCP1
OSC1 Power-up
Oscillator BITOP W
Timer 8 RC4/D-/VM
Block 8 8
OSC2(2) Oscillator RC5/D+/VP
INTRC Start-up Timer RC6/TX/CK
Oscillator Power-on 8 8 RC7/RX/DT/SDO
T1OSI
Reset
8 MHz ALU<8>
T1OSO Oscillator Watchdog
Timer
8
Single-Supply Brown-out
MCLR(1) Reset
Programming
In-Circuit Fail-Safe
VDD, VSS Debugger Clock Monitor
PORTE
USB Voltage Band Gap
VUSB
Regulator Reference
MCLR/VPP/RE3(1)
BOR Data
EEPROM Timer0 Timer1 Timer2 Timer3
HLVD
ADC
Comparator CCP1 CCP2 MSSP EUSART USB
10-Bit
Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer
to Section 2.0 “Oscillator Configurations” for additional information.
3: RB3 is the alternate pin for CCP2 multiplexing.
Address PORTC
ROM Latch
Instruction Bus <16> Decode RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(4)/UOE
IR RC2/CCP1/P1A
RC4/D-/VM
RC5/D+/VP
8 RC6/TX/CK
Instruction State Machine RC7/RX/DT/SDO
Decode & Control Signals
Control
PRODH PRODL
PORTD
8 x 8 Multiply
VDD, VSS 3 8
Internal
Oscillator Power-up RD0/SPP0:RD4/SPP4
OSC1(2) Timer BITOP W
Block 8 8 8 RD5/SPP5/P1B
OSC2(2) Oscillator RD6/SPP6/P1C
INTRC RD7/SPP7/P1D
Start-up Timer
T1OSI Oscillator 8 8
Power-on
T1OSO 8 MHz
Oscillator Reset ALU<8>
Watchdog 8
ICPGC(3) Single-Supply Timer
Programming Brown-out
ICPGD(3) Reset PORTE
In-Circuit RE0/AN5/CK1SPP
ICPORTS(3) Debugger Fail-Safe RE1/AN6/CK2SPP
Clock Monitor Band Gap RE2/AN7/OESPP
ICRST(3)
Reference MCLR/VPP/RE3(1)
MCLR(1) USB Voltage
Regulator
VUSB
BOR Data
EEPROM Timer0 Timer1 Timer2 Timer3
HLVD
Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer
to Section 2.0 “Oscillator Configurations” for additional information.
3: These pins are only available on 44-pin TQFP packages under certain conditions. Refer to Section 25.9 “Special ICPORT Features
(Designated Packages Only)” for additional information.
4: RB3 is the alternate pin for CCP2 multiplexing.
PIC18F2455/2550/4455/4550
MUX
OSC2 ÷2 1
÷4 011 PLL
Sleep ÷3
010
OSC1 ÷2 001 FSEN
÷1 000
HSPLL, ECPLL, 1
USB
XTPLL, ECPIO Peripheral
CPUDIV
÷6 ÷4 0
PLL Postscaler
11
÷4
CPUDIV 10
÷3
01
Oscillator Postscaler
÷4 ÷2
11 00
÷3
10 CPU
XT, HS, EC, ECIO
÷2 01
1
÷1
0 Primary
00 Clock IDLEN
FOSC3:FOSC0
Secondary Oscillator Peripherals
MUX
T1OSO
T1OSC
T1OSCEN
Enable
T1OSI Oscillator
OSCCON<6:4> 8 MHz
111
4 MHz
Internal 110 Clock
INTOSC Postscaler
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2.2.5.4 Compensating for INTOSC Drift an interrupt occurs, the internally clocked timer is read
and both timers are cleared. If the internally clocked
It is possible to adjust the INTOSC frequency by
timer value is greater than expected, then the internal
modifying the value in the OSCTUNE register. This has
oscillator block is running too fast. To adjust for this,
no effect on the INTRC clock source frequency.
decrement the OSCTUNE register.
Tuning the INTOSC source requires knowing when to
Finally, a CCP module can use free-running Timer1 (or
make the adjustment, in which direction it should be
Timer3), clocked by the internal oscillator block and an
made and in some cases, how large a change is
external event with a known period (i.e., AC power
needed. When using the EUSART, for example, an
frequency). The time of the first event is captured in the
adjustment may be required when it begins to generate
CCPRxH:CCPRxL registers and is recorded for use
framing errors or receives data with errors while in
later. When the second event causes a capture, the
Asynchronous mode. Framing errors indicate that the
time of the first event is subtracted from the time of the
device clock frequency is too high; to adjust for this,
second event. Since the period of the external event is
decrement the value in OSCTUNE to reduce the clock
known, the time difference between events can be
frequency. On the other hand, errors in data may sug-
calculated.
gest that the clock speed is too low; to compensate,
increment OSCTUNE to increase the clock frequency. If the measured time is much greater than the calcu-
lated time, the internal oscillator block is running too
It is also possible to verify device clock speed against
fast; to compensate, decrement the OSCTUNE register.
a reference clock. Two timers may be used: one timer
If the measured time is much less than the calculated
is clocked by the peripheral clock, while the other is
time, the internal oscillator block is running too slow; to
clocked by a fixed reference source, such as the
compensate, increment the OSCTUNE register.
Timer1 oscillator. Both timers are cleared but the timer
clocked by the reference generates interrupts. When
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
T1OSI 1 2 3 n-1 n
CPU
Clock
Peripheral
Clock
Program
Counter PC PC + 2 PC + 4
FIGURE 3-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
T1OSI
OSC1
TOST(1) TPLL(1)
1 2 n-1 n
PLL Clock
Output
Clock(2)
Transition
CPU Clock
Peripheral
Clock
Program PC PC + 2 PC + 4
Counter
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 TOSC.
3.2.3 RC_RUN MODE This mode is entered by setting SCS1 to ‘1’. Although
it is ignored, it is recommended that SCS0 also be
In RC_RUN mode, the CPU and peripherals are
cleared; this is to maintain software compatibility with
clocked from the internal oscillator block using the
future devices. When the clock source is switched to
INTOSC multiplexer; the primary clock is shut down.
the INTOSC multiplexer (see Figure 3-3), the primary
When using the INTRC source, this mode provides the
oscillator is shut down and the OSTS bit is cleared. The
best power conservation of all the Run modes while still
IRCF bits may be modified at any time to immediately
executing code. It works well for user applications
change the clock speed.
which are not highly timing sensitive or do not require
high-speed clocks at all times. Note: Caution should be used when modifying a
If the primary clock source is the internal oscillator single IRCF bit. If VDD is less than 3V, it is
block (either INTRC or INTOSC), there are no distin- possible to select a higher clock speed
guishable differences between the PRI_RUN and than is supported by the low VDD.
RC_RUN modes during execution. However, a clock Improper device operation may result if
switch delay will occur during entry to and exit from the VDD/FOSC specifications are violated.
RC_RUN mode. Therefore, if the primary clock source
is the internal oscillator block, the use of RC_RUN
mode is not recommended.
INTRC 1 2 3 n-1 n
CPU
Clock
Peripheral
Clock
Program
Counter PC PC + 2 PC + 4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
INTOSC
Multiplexer
OSC1
TOST(1) TPLL(1)
1 2 n-1 n
PLL Clock
Output
Clock(2)
Transition
CPU Clock
Peripheral
Clock
Program PC PC + 2 PC + 4
Counter
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 TOSC.
CPU
Clock
Peripheral
Clock
Sleep
Program
Counter PC PC + 2
OSC1
TOST(1) TPLL(1)
PLL Clock
Output
CPU Clock
Peripheral
Clock
Program PC PC + 2 PC + 4 PC + 6
Counter
Q1 Q2 Q3 Q4 Q1
OSC1
CPU Clock
Peripheral
Clock
Program PC PC + 2
Counter
FIGURE 3-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Q1 Q2 Q3 Q4
OSC1
TCSD
CPU Clock
Peripheral
Clock
Program PC
Counter
Wake Event
TABLE 3-2: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Microcontroller Clock Source Clock Ready Status
Exit Delay
Before Wake-up After Wake-up Bit (OSCCON)
XT, HS
Primary Device Clock XTPLL, HSPLL OSTS
None
(PRI_IDLE mode) EC
INTOSC(3) IOFS
XT, HS TOST(4)
XTPLL, HSPLL TOST + trc(4) OSTS
T1OSC or INTRC(1)
EC TCSD(2)
INTOSC(3) TIOBST(5) IOFS
XT, HS TOST(4)
XTPLL, HSPLL TOST + trc(4) OSTS
INTOSC(3)
EC TCSD(2)
INTOSC(3) None IOFS
XT, HS TOST(4)
None XTPLL, HSPLL TOST + trc(4) OSTS
(Sleep mode) EC TCSD(2)
INTOSC(3) TIOBST(5) IOFS
Note 1: In this instance, refers specifically to the 31 kHz INTRC clock source.
2: TCSD (parameter 38, Table 28-12) is a required delay when waking from Sleep and all Idle modes and runs
concurrently with any other required delays (see Section 3.4 “Idle Modes”).
3: Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
4: TOST is the Oscillator Start-up Timer period (parameter 32, Table 28-12). trc is the PLL lock time-out
(parameter F12, Table 28-9); it is also designated as TPLL.
5: Execution continues during TIOBST (parameter 39, Table 28-12), the INTOSC stabilization period.
External Reset
MCLRE
MCLR
( )_IDLE
Sleep
WDT
Time-out
OST/PWRT
OST 1024 Cycles
Chip_Reset
10-Bit Ripple Counter R Q
OSC1
32 µs 65.5 ms
PWRT
INTRC(1) 11-Bit Ripple Counter
Enable PWRT
Enable OST(2)
Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin.
2: See Table 4-2 for time-out situations.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent
Power-on Resets may be detected.
2: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to
‘1’ by software immediately after POR).
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET
FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET
FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET