6502

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Rodnay Zaks
SYBEX
PROGRAMMING
THE 6502
PROGRAMMING
THE 6502

RODNAY ZAKS

FOURTH EDITION
Incorporating Answers to the Exercises

SYBEX
BERKELEY • PARIS • DUSSELDORF
 Every effort has been made to supply complete and accurate information. However,
Sybex assumes no responsibility for its use, nor for any infringements of patents or other
rights of third parties which would result. No license is granted by the equipment manufac­
turers under any patent or patent right. Manufacturers reserve the right to change circuitry
at any time without notice.

Copyright © 1983 SYBEX Inc. 2344 Sixth Street, Berkeley, CA 94710. World rights
reserved. No part of this publication may be stored in a retrieval system, copied, transmit­
ted, or reproduced in any way, including, but not limited to photocopy, photography, mag­
netic or other recording, without the prior agreement and written permission of the
publisher.

ISBN 0-89588-135-7
Library of Congress Card Number: 83-61686
First Edition published 1978. Fourth Edition 1983
Printed in the United States of America
10 9 8 7 6 5 4 3 2
 CONTENTS

PREFACE

I. BASIC C O N C EPTS.............................................................. 7

Introduction. What is Programming? Flowcharting. Information

Representation.

II. 6502 HARDWARE ORGANIZATION.............................38

Introduction. System Architecture. Internal Organization o f the 6502. The

Instruction Execution Cycle. The Stack. The Paging Concept. The 6502
Chip. Hardware Summary.

III. BASIC PROGRAMMING TECHNIQUES....................... 53

Introduction. Arithmetic Programs. BCD Arithmetic. Important Self-Test.
Logical Operations. Subroutines. Summary.

IV. THE 6502 INSTRUCTION S E T .........................................99

PAR T 1-0 VERALL DESCRIPTION
Introduction. Classes o f Instructions. Instructions Available on the 6502.
PART 2- THE INSTR UCTIONS
Abbreviations. Description o f Each Instruction.

V. ADDRESSING TEC H N IQ U ES......................................188

Introduction. Addressing Modes. 6502 Addressing Modes. Using the 6502
Addressing Modes. Summary.

VI. INPUT/OUTPUT TECHNIQUES.................................. 211

Introduction. Input/Output. Parallel Word Transfer. Bit Serial Transfer.
Basic I/O Summary. Communicating with Input/Output Devices.
Peripheral Summary. Input/Output Scheduling. Summary. Exercises.
VII. INPU T/O UTPUT D E V IC E S......................................... 254
Introduction. The Standard PIO (6520). The Internal Control Register.
The 6530. Programming a PIO. The 6522. The 6532. Summary.

VIII. APPLICATION E X A M PL E S....................................... 262

Introduction. Clear a Section o f Memory. Polling I /O Devices. Getting
Characters In. Testing a Character. Bracket Testing. Parity Generation.
Code Conversion: ASCII to BCD. Find the Largest Element o f a Table.
Sum o f N Elements. A Checksum Computation. Count the Zeroes. A
String Search. Summary.

IX. DATA STRUCTURES...................................................... 275

P A R T 1-DESIGN CONCEPTS
Introduction. Pointers. Lists. Searching and Sorting. Summary. Data Structures.
P A R T 2-DESIGN EXAMPLES
Introduction. Data Representation fo r the List. A Simple List. Alphabetic
List. Binary Tree. A Hashing Algorithm. Bubble-Sort. A Merge Algorithm.
Summary.

X. PROGRAM D EV ELO PM EN T...................................... 343

Introduction. Basic Programming Choices. Software Support. The Pro­
gram Development Sequence. The Hardware Alternatives. Summary o f
Hardware Alternatives. Summary o f Hardware Resources. The Assembler.
Macros. Conditional Assembly. Summary.

XI. CO N C LU SIO N .......... ...................................................... 368

Technological Development. The Next Step.

APPEN D ICES....................................................................................371
A. Hexadecimal Conversion Table
B. 6502 Instruction-Set: Alphabetic
C. 6502 Instruction-Set: Binary
D. 6502 Instruction-Set: Hexadecimal and Timing
E. ASCII Table
F. Relative Branch Table
G. Hex Opcode Listing
H. Decimal to BCD Conversion
I. Answers to the Exercises
 PREFACE
This book has been designed as a complete self-contained tex t
to learn programming, using the 6502. It can be used by a person
who has never program m ed before, and should also be of value to
anyone using the 6502.
For the person who has already program m ed, th is book will
teach specific program m ing techniques using (or working around)
the specific characteristics of the 6502. This tex t covers the
elem entary to interm ediate techniques required to s ta rt pro­
gram m ing effectively.
This text aim s a t providing a tru e level of competence to the
person who wishes to program using this microprocessor. Nat­
urally, no book will teach effectively how to program, unless one
actually practices. However, it is hoped th a t th is book will tak e
the reader to the point w here he feels th a t he can s ta rt program ­
m ing by him self and solve simple or even m oderately complex
problems using a microcomputer.
This book is based on the author’s experience in teaching more
th a n 1000 persons how to program microcomputers. As a result,
it is strongly structured. C hapters norm ally go from the simple to
the complex. For readers who have already learned elem entary
program m ing, the introductory chapter m ay be skipped. For
others who have never program m ed, the final sections of some
chapters may require a second reading. The book has been de­
signed to take the reader systematically through all the basic
concepts and techniques required to build increasingly complex
program s. It is, therefore, strongly suggested th a t the ordering of
the chapters be followed. In addition, for effective results, it is
im portant th a t the reader attem pt to solve as m any exercises as
possible. The difficulty w ithin the exercises h as been carefully
graduated. They are designed to verify th a t the m aterial which
has been presented is really understood. W ithout doing the pro­
gram m ing exercises, it will not be possible to realize the full
value of this book as an educational medium. Several of the exer­
cises m ay require tim e, such as the m ultiplication exercise for
example. However, by doing these, you will actually program and
learn by doing. This is indispensable.
For those who will have acquired a taste for program m ing w hen
reaching the end of this volume, companion volumes are available:
 —“ 6502 Applications” covers input/output.
—“ Advanced 6502 Programming” covers complex algorithms.

Other books in this series cover programming for other popular

microprocessors.
For those who wish to develop their hardware knowledge, it is
suggested that the reference books “ From Chips to Systems” (ref.
C201A) and “ Microprocessor Interfacing Techniques” (ref. C207) be
consulted.
The author would like to thank Rockwell International, who pro­
vided access to one of the first ASM65 development systems.
The contents of this book have been checked carefully and are
believed to be reliable. However, inevitably, some typographical
or other errors will be found. The au th o r will be grateful for any
comments by alert readers so that future editions may benefit from
their experience. Any other suggestions for improvements, such as
other programs desired, developed, or found of value by readers,
will be appreciated.

PREFACE TO THE FOURTH EDITION

In the five years since this book was originally published, the audience
of 6502 microprocessor users has grown exponentially, and it continues
to grow. This book has expanded with its audience.
The Second Edition increased in size by almost 100 pages, with most
of the new m aterial being added to Chapters 1 and 9. A dditional
improvements have been made continually throughout the book. In this
Fourth Edition, answers to the exercises have been included as an appen­
dix (Appendix I). These answers appear in response to the request of
many readers, who wanted to make sure that their knowledge of 6502
programming was thorough.
I would like to thank the many readers of the previous editions who
have contributed valuable suggestions for improvement. Special
acknowledgements are due to Eric Novikoff and Chris Williams for their
contributions to the answers to the exercises, as well as to the complex
programming examples in Chapter 9. Special thanks also go to Daniel J.
David, for his many suggested improvements. A number of changes and
enhancements are also due to the valuable analysis and comments pro­
posed by Philip K. Hooper, John Smith, Ronald Long, Charles Curlay,
N. Harris, John McClenon, Douglas Trusty, Fletcher Carson, and Pro­
fessor Myron Calhoun.
 Acknowledgements

The author would like to express his appreciation to Rockwell Interna­

tional and, in particular, to Scotty Maxwell, who made available to him
one of the very first system 65 development systems. The availability of
this powerful development tool, at the time the first version of this book
was being written, was a major help for the accurate and efficient check­
out of all the programs. I would also like to thank Professor Myron
Calhoun for his contributions.
BASIC CONCEPTS
IN TR O D U CTIO N

This chapter will introduce the basic concepts and definitions re­
latin g to com puter program m ing. The reader already fam iliar w ith
these concepts m ay w ant to glance quickly a t the contents of this
chapter and th en move on to C hapter 2. I t is suggested, however,
th a t even the experienced reader look a t the contents of this intro­
ductory chapter. M any significant concepts are presented here in­
cluding, for example, tw o’s complement, BCD, and other represen­
tations. Some of these concepts m ay be new to the reader; others
m ay improve the knowledge and skills of experienced program m ers.

W H A T IS PRO G R A M M IN G ?
Given a problem , one m u st first devise a solution. This solution,
expressed a s a step-by-step procedure, is called an algorithm. A n
algorithm is a step-by-step specification of the solution to a given
problem. I t m u st term inate in a finite num ber of steps. This
algorithm m ay be expressed in any language or symbolism . A sim­
ple example of an algorithm is:
1— insert key in the keyhole
2— tu rn key one full tu rn to the left
3— seize doorknob
4— tu rn doorknob left and push th e door
 A t this point, if the algorithm is correct for the type of lock in­
volved, the door will open. This four-step procedure qualifies as an
algorithm for door opening.
Once a solution to a problem has been expressed in the form of
an algorithm , th e algorithm m u st be executed by the com puter.
U nfortunately, it is now a well-established fact th a t com puters
cannot understand or execute ordinary spoken English (or any
other hum an language). The reason lies in the syntactic am biguity
of all common hum an languages. Only a well-defined su b set of
n atu ral language can be “ understood” by the com puter. This is
called a programming language.
C onverting an algorithm in to a sequence of instructions in a pro­
gram m ing language is called programming. To be more specific,
the actual tran slatio n phase of the algorithm into th e program ­
m ing language is called coding. Program m ing really refers n o t ju s t
to th e coding b u t also to the overall design of the program s and
“d a ta s tru c tu re s” which will im plem ent the algorithm .
E ffective program m ing requires no t only u nderstanding the
possible im plem entation techniques for stan d ard algorithm s, b u t
also th e skillful use of all th e com puter hardw are resources, such as
internal registers, memory, and peripheral devices, plus a creative
use of appropriate d a ta structures. These techniques will be
covered in the n ext chapters.
Program m ing also requires a stric t docum entation discipline, so
th a t the program s are understandable to others, as well as to the
author. D ocum entation m u st be both internal and external to the
program .
In tern al program docum entation refers to the com m ents placed
in the body of a program , which explain its operation.
E xtern al docum entation refers to the design docum ents which
are separate from the program : w ritten explanations, m anuals,
and flowcharts.

FLO W C H A R TIN G

One interm ediate step is alm ost alw ays used betw een the
algorithm and the program. I t is called a flowchart. A flow chart is
sim ply a symbolic representation of the algorithm expressed as a
sequence of rectangles and diam onds containing the steps of the
algorithm . R ectangles are used for commands, or “ executable
sta te m e n ts.” Diam onds are used for tests such as: If inform ation
X is true, then take action A, else B. In stead of presenting a formal
definition of flow charts a t this point, we will introduce and discuss
flow charts later on in the book when we present program s.
Flow charting is a highly recommended interm ediate step be­
tween the algorithm specification and the actual coding of the solu­
tion. Rem arkably, it has been observed th a t perhaps 10% of the
programming population can write a program successfully with­
out having to flowchart. U nfortunately, it has also been observed
that 90% of the population believes it belongs to this 10%! The
result: 80% of these program s, on the average, will fail the first
tim e they are run on a com puter. (These percentages are naturally
not m eant to be accurate.) In short, m ost novice program m ers sel­
dom see the necessity of draw ing a.-flowchart. This usually results
in “ unclean” or erroneous program s. They m u st then spend a long
time testing and correcting their program (this is called the

START

Fig. 1-1: A Flowchart for Keeping Room Temperature Constant

debugging phase). The discipline of flowcharting is therefore
highly recom mended in all cases. I t will require a sm all am ount of
additional tim e prior to the coding, b u t will usually result in a clear
program which executes correctly and quickly. Once flow charting
is well understood, a sm all percentage of program m ers will be able
to perform this step m entally w ithout having to do it on paper. U n­
fortunately, in such cases the program s th a t they w rite will usual­
ly be hard to understand for anybody else w ithout the docum enta­
tion provided by flow charts. A s a result, it is universally recom­
mended th a t flow charting be used as a stric t discipline for any
significant program . M any exam ples will be provided throughout
the book.

IN FO R M A T IO N R E PR E S E N T A T IO N

All com puters m anipulate inform ation in the form of num bers or
in the form of characters. L et us exam ine here the external and
internal representations of inform ation in a com puter.

IN T E R N A L R E P R E S E N T A T IO N OF IN F O R M A T IO N
All inform ation in a com puter is stored as groups of bits. A bit
stands for a binary digit (“ 0” or “ l ” )- Because of the limitations
of conventional electronics, the only practical representation of infor­
mation uses two-state logic (the representation of the state “ 0” and
“ 1” )- The two states of the circuits used in digital electronics
are generally “ on” or “ off” , and these are represented logi­
cally by the symbols “ 0” or “ 1” . Because these circuits are
used to im plem ent “ logical” functions, they are called “ binary
logic.” A s a result, virtually all inform ation-processing today is
perform ed in binary form at. In the case of m icroprocessors in
general, and of the 6502 in particular, these b its are stru ctu red in
groups of eight. A group of eight b its is called a byte. A group of
four b its is called a nibble.
L et us now exam ine how inform ation is represented internally in
this binary form at. Two entities m u st be represented inside the
com puter. The first one is th e program , which is a sequence of
instructions. The second one is the d a ta on which the program will
operate, which m ay include num bers or alphanum eric text. W e will
discuss below three representations: program , num bers, and alpha-
num erics.
P rogram R epresentation
All instructions are represented internally as single or m ultiple
bytes. A so-called “ sh o rt in stru ctio n ” is represented by a single
byte. A longer instruction will be represented by tw o or m ore
bytes. Because th e 6502 is an eight-bit m icroprocessor, it fetches
bytes successively from its memory. Therefore, a single-byte
instruction alw ays has a potential for executing faster th an a two-
or three-byte instruction. I t will be seen later th a t th is is an im por­
ta n t feature of the instruction set of any m icroprocessor and in
particular the 6502, where a special effort has been m ade to pro­
vide as m any single-byte instructions as possible in order to im ­
prove the efficiency of the program execution. However, the lim ita­
tion to 8 b its in length has resulted in im p o rtan t restrictions which
will be outlined. This is a classic exam ple of "the comprom ise be­
tween speed and flexibility in program m ing. The binary code used
to represent instructions is dictated by the m anufacturer. The
6502, like any other m icroprocessor, comes equipped w ith a fixed
instruction set. These instructions are defined by the m anufac­
tu re r and are listed a t the end of th is book, w ith their code. A ny
program will be expressed as a sequence of these binary instruc­
tions. The 6502 instructions are presented in C hapter 4.

R epresenting Num eric D a ta

R epresenting num bers is not quite straightforw ard, and several
cases m ust be distinguished. W e m ust first represent integers, then
signed num bers, i.e., positive and negative num bers, and finally we
m ust be able to represent decimal num bers. L et us now address
these requirem ents and possible solutions.
R epresenting integers m ay be perform ed by using a direct
binary representation. The direct binary representation is sim ply
the representation of the decimal value of a num ber in the binary
system . In the binary system , the right-m ost b it represents 2 to
the power 0. The next one to the left represents 2 to the power 1,
the nex t represents 2 to the power 2, and the left-m ost b it
represents 2 to the power 7 = 128.

b7b6b6b4b3b2b1bo
represents
b,27 + b626 + b625 + b„24 + b323 + b222 + b,2' + b02°
The powers of 2 are:
27 = 128, 2s = 64, 26 = 32, 24 = 16, 2s = 8, 22 = 4, 21 = 2, 2° = 1

The binary representation is analogous to the decim al representa­

tion of num bers, where “ 123” represents:

1 X 100 = 100
+ 2 X 10 = 20
+ 3 X 1 = 3
= 123
N ote th a t 100 = 102, 10 = 10*, 1 = 10°.
In th is “p o sitio n aln o ta tio n ,” each dig it represents a power of 10.
In the binary system , each binary dig it or “ b it” represents a power
of 2, instead of a power of 10 in the decimal system .
Example: “ 00001001” in binary represents:
IX 1= 1 (2°)
OX 2= 0 (2>)
OX 4= 0 (22)
IX 8= 8 (2s)
OX 16= 0 (24)
OX 32 = 0 (26)
OX 64 = 0 (28)
0 X 128 = 0 (27)
in decimal: = 9
L et us exam ine some m ore examples:
“ 10000001” represents:
1 X 1 = 1
0 X 2 = 0
0 X 4 = 0
0 X 8 = 0
0 X 16 = 0
0 X 32 = 0
0 X 64 = 0
1 X 128 = 128
in decimal: =129
“ 10000001” represents, therefore, the decimal number 129.
By exam ining the binary representation of num bers, you will
understand why b its are num bered from 0 to 7, going from rig h t to
left. B it 0 is “ b0” and corresponds to 2°. B it 1 is “ b ,” and cor­
responds to 21, and so on.

Decimal B inary Decimal Binary

0 00000000 32 00100000
1 00000001 33 00100001
2 00000010 e

3 00000011 e

4 00000100 e

5 00000101 63 00111111
6 00000110 64 01000000
7 00000111 65 01000001
e
8 00001000
e
9 00001001
10 00001010 127 01111111
11 00001011 128 10000000
12 00001100 129 10000001
13 00001101
14 00001110 e

15 00001111
16 00010000
17 00010001 e

e 254 11111110
31 00011111 255 11111111

Fig. 1-2: Decimal-Binary Table

The binary equivalents of the num bers from 0 to 255 are shown
in Fig. 1-2.

Exercise 1.1: W hat is the decimal value o f "11111100"?

 Decimal to Binary
Conversely, let us compute the binary equivalent of “ 11” decimal:
11 -5-2=5 remains 1 — M (LSB)
5-5-2=2 remains 1— »1
2-5-2=1 remains 0 — »0
1 -5- 2 = 0 remains 1 — * 1 (MSB)
The binary equivalent is 1011 (read right-most column from bottom
to top).
The binary equivalent of a decimal number may be obtained by dividing
successively by 2 until a quotient of 0 is obtained.
Exercise 1.2: What is the binary fo r 257?
Exercise 1.3: Convert 19 to binary, then back to decimal.
Operating on Binary Data
The arithmetic rules for binary numbers are straightforward. The rules
for addition are:
0+ 0= 0
0+1= 1
1+0= 1
1 + 1= ( 1) 0
where (1) denotes a “ carry” of 1 (note that “ 10” is the binary equivalent
of “ 2” decimal). Binary subtraction will be performed by “ adding the
complement” and will be explained once we learn how to represent
negative numbers.
Example:

(2) 10
+d) +01

=0) 11
Addition is performed just like in decimal, by adding columns, from
right to left:
Adding the right-most column:

10
+01
(0 + 1 = 1. No carry.)
A dding the next column:
10
+@1
11 ( 1 + 0 = 1 . No carry.)

Exercise 1.4: Compute 5 + 10 in binary. Verify that the result is 15.

Some additional exam ples of binary addition:

0010 (2) 0011 (3)

+0001 (1) +0001 1
( )

=0011 (3) = 0100 (4)

This la st example illu strates the role of the carry.

Looking a t the right-m ost bits: 1 + 1 = ( 1 ) 0
A carry of 1 is generated, which m ust be added to the next bits:
001 —column 0 has ju s t been added
+000 -

+ 1 (carry)
= (1)0 — where (1) indicates a new
carry into column 2.
The final result is: 0100
A nother example:
0111 (7)
+0011 + (3)
1010 =(10)
In this example, a carry is again generated, up to the left-m ost co­
lumn.
Exercise 1.5: Compute the result of:
1111
+0001
=?
Does the result hold in four bits?
W ith eight bits, it is therefore possible to represent directly the
num bers “ 00000000” to “ 11111111,” i.e., “ 0 ” to “ 255” . Two
obstacles should be visible imm ediately. First, we are only
representing positive num bers. Second, the m agnitude of these
num bers is lim ited to 255 if we use only eight bits. L et us address
each of these problem s in turn.

Signed Binary
In a signed binary representation, the left-m ost b it is used to in­
dicate the sign of the num ber. Traditionally, “ 0 ” is used to denote
a positive num ber while “ 1” is used to denote a negative num ber.
Now “ 11111111” will represent —127, while “ 01111111” will
represent +127. We can now represent positive and negative
num bers, b u t we have reduced the m axim um m agnitude of these
num bers to 127.
Exam ple: "0000 0001” represents + 1 (the leading “0 ” is “ + ” ,
followed by “ 000 0001” = 1).
“ 1000 0001” is - 1 (the leading “ 1” is “ - ” ).
Exercise 1.6: What is the representation o f “ —5 ” in signed binary?

L et us now address the magnitude problem: in order to represent

larger num bers, it will be necessary to use a larger num ber of bits.
For example, if we use sixteen b its (two bytes) to represent
num bers, we will be able to represent num bers from —32K to
+ 32K in signed binary (IK in com puter jarg o n represents 1,024).
B it 15 is used for the sign, and the rem aining 15 b its (bit 14 to bit
0) are used for the m agnitude: 216 = 32K. If this m agnitude is still
too small, we will use 3 bytes or more. If we wish to represent large
integers, it will be necessary to use a larger num ber of bytes inter­
nally to represent them. This is why m ost simple BA SICs, and
other languages, provide only a lim ited precision for integers. This
way, they can use a shorter internal form at for the num bers which
they m anipulate. B e tte r versions of BASIC, or of these other
languages, provide a larger num ber of significant decimal digits a t
the expense of a large num ber of bytes for each num ber.
Now let us solve another problem, the one of speed efficiency.
We are going to a tte m p t perform ing an addition in the signed
binary representation which we have introduced. L et us add “ —5 ”
and “ + 7 ”.
+ 7 is represented by 00000111
—5 is represented by 10000101
The binary sum is: 10001100, or —12
This is not the correct result. The correct result should be + 2 . In
order to use this representation, special actions m u st be taken, de­
pending on the sign. This results in increased com plexity and re­
duced performance. In other words, the binary addition of signed
num bers does not “ work correctly.” This is annoying. Clearly, the
com puter m ust not only represent inform ation, b u t also perform
arithm etic on it.
The solution to this problem is called the two's complement
representation, which will be used instead of the signed binary
representation. In order to introduce tw o’s com plem ent let us first
introduce an interm ediate step: one's complement

One's Complement
In the one’s com plem ent representation, all positive integers are
represented in their correct binary form at. For example “ + 3 ” is
represented as usual by 00000011. However, its com plem ent “ —3 ”
is obtained by com plem enting every b it in the original representa­
tion. E ach 0 is transform ed into a 1 and each 1 is transform ed into
a 0. In our example, the one’s com plem ent representation of “ —3 ’’
will be 11111100.

A nother example:
+ 2 is 00000010
. - 2 is 11111101
N ote th at, in this representation, positive num bers s ta rt w ith a
“ 0 ” on the left, and negative ones w ith a “ 1” on the left.

Exercise 1.7: The representation o f “ + d ” is “00000110". What is

the representation o f 6" in one's complement?

A s a test, let us add m inus 4 and plus 6:

 - 4 is 11111011
+ 6 is 00000110
the sum is: (1) 00000001 where (1) indicates a
carry
The “ correct re su lt” should be “ 2 ” , or “ 00000010” .
L et us try again:
—3 is 11111100
—2 is 11111101
(1) 00000001
The sum is:
or “ 1,” plus a carry. The correct result should be “ - 5 . ” The repre­
sentation of “ —5” is 11111010. It did not work.
This representation does represent positive and negative
num bers. However the resu lt of an ordinary addition does not
alw ays come ou t “ correctly.” We will use still another representa­
tion. I t is evolved from the one’s com plem ent and is called the
tw o’s com plem ent representation.

Two's Complement Representation

In the tw o’s com plem ent representation, positive num bers are
still represented, as usual, in signed binary, ju s t like in one’s com­
plem ent. The difference lies in th e representation of negative
numbers. A negative num ber represented in tw o’s com plem ent is
obtained by first com puting the one’s complement, and th en ad­
ding one. L et us exam ine this in an example:
+ 3 is represented in signed binary by 00000011. I ts one’s com­
plem ent representation is 11111100. The tw o’s com plem ent is ob­
tained by adding one. I t is 11111101.

Let us try an addition:

(3) 00000011
+(5) +00000101
= ( 8) =00001000
The result is correct.
Let us try a subtraction:
(3) 00000011
( - 5) +11111011
=11111110
L et us identify the result by com puting the tw o's complement:

the one's complement of 11111110 is 00000001

Adding 1 + 1
therefore the two’s complement is 00000010 or + 2
Our result above, “ 11111110" represents “ —2". I t is correct.
We have now tried addition and subtraction, and the results were correct
(ignoring the carry). It seems that two’s complement works!

Exercise 1.8: What is the two's complement representation o f (t+ 127”?

Exercise 1.9: What is the two's complement representation o f “-1 2 8 ”?

L et us now add + 4 and —3 (the subtraction is perform ed by add­

ing the tw o's complement):
+ 4 is 00000100
- 3 is 11111101
The result is: (1) 00000001
If we ignore the carry, the result is 00000001, i.e., “ 1” in decimal. This
is the correct result. Without giving the complete mathematical proof,
let us simply state that this representation does work. In two’s comple­
ment, it is possible to add or subtract signed numbers regardless of the
sign. Using the usual rules of binary addition, the result comes out
correctly, including the sign. The carry is ignored. This is a very signifi­
cant advantage. If it were not the case, one would have to correct the
result for sign every time, causing a much slower addition or subtraction
time.
For the sake of completeness, let us state that two’s complement is
simply the most convenient representation to use for simpler processors
such as microprocessors. On complex processors, other representations
may be used. For example, one’s complement may be used, but it requires
special circuitry to “ correct the result.’’
 From this point on, all signed integers will implicitly be represented
internally in two’s complement notation. See Fig. 1-3 for a table of
two’s complement numbers.

Exercise 1.10: What are the smallest and the largest numbers which one
may represent in two’s complement notation, using only one byte?

Exercise 1.11: Compute the two’s complement o f 20. Then compute the
two’s complement o f your result. Do you fin d 20 again ?
The following examples will serve to demonstrate the rules of two’s
complement. In particular, C denotes a possible carry (or borrow)
condition. (It is b it 8 of the result.)
V denotes a tw o’s com plem ent overflow, i.e., when the sign of the
resu lt is changed “ accidentally” because the num bers are too
large. I t is an essentially internal carry from b it 6 into b it 7 (the
sign bit). This will be clarified below.
L et u s now dem onstrate the role of the carry “C ” and the overflow
“V ”.

The Carry C
H ere is an exam ple of a carry:
(128) 10000000
+(129) +10000001
(257) = (1) 00000001
where (1) indicates a carry.
The result requires a ninth b it (bit “8 ”, since the right-m ost bit is
“ 0 ” ). I t is the carry bit.
If we assum e th a t the carry is th e nin th b it of the result, we
recognize the result as being 100000001 = 257.
However, the carry m u st be recognized and handled w ith care.
Inside the m icroprocessor, the registers used to hold inform ation
are generally only eight-bit wide;When storing the result, only bits 0 to
7 will be preserved.
A carry, therefore, alw ays requires special action: it m u st be
detected by special instructions, then processed. Processing the
carry m eans either storing it somewhere (with a special instruc­
tion), or ignoring it, or deciding th a t it is an error (if the largest
authorized result is “ 11111111” ).
 2’s complement 2’s complement
+ code - code

+ 127 01111111 -1 2 8 10000000

+ 126 01111110 -1 2 7 10000001
+ 125 01111101 -1 2 6 10000010
. . . -1 2 5 10000011

+ 65 01000001 -6 5 10111111
+ 64 01000000 -6 4 11000000
+ 63 00111111 -6 3 11000001

+ 33 00100001 -3 3 11011111
+ 32 00100000 -3 2 11100000
+ 31 00011111 -3 1 11100001

+ 17 00010001 -1 7 11101111
+ 16 00010000 -1 6 11110000
+ 15 00001111 -1 5 11110001
+ 14 00001110 -1 4 11110010
+ 13 00001101 -1 3 11110011
+ 12 00001100 -1 2 11110100
+ 11 00001011 -1 1 11110101
+ 10 00001010 -1 0 11110110
+9 00001001 -9 11110111
+8 00001000 -8 11111000
+7 00000111 -7 11111001
+6 00000110 -6 11111010
+5 00000101 -5 11111011
+4 00000100 -4 11111100
+3 00000011 -3 11111101
+ 2 00000010 —2 11111110
+ 1 00000001 -1 11111111
+ 0 00000000

Fig. 1-3:2’$ Complement Table

Overflow V
Here is an example of overflow:
b it 6
b it 7
01000000 (64)
+01000001 +(65)
= 10000001 = (-1 2 7 )
A n internal carry has been generated from bit 6 into bit 7. This is
called an overflow.
The result is now negative, “ by accident.” This situation m ust
be detected, so th a t it can be corrected.
L et us examine another situation:
11111111 (-1 )
+ 11111111 + (-l)
= ( 1) 11111110 = ( —2)
Y
carry
In th is case, an internal carry has been generated from b it 6 into
b it 7, and also from b it 7 into bit 8 (the formal “ C arry” C we have
exam ined in the preceding section). The rules of tw o’s complement
arithm etic specify th a t this carry should be ignored. The result is
then correct.
This is because the carry from b it 6 into bit 7 did not change the
sign bit.
This is not an overflow condition. W hen operating on negative
num bers, the overflow is not sim ply a carry from b it 6 into b it 7.
L et us examine one more example.
11000000 (-6 4 )
+ 10111111 (-6 5 )
01111111 (+127)
carry
This time, there has been no internal carry from b it 6 into b it 7, b u t
there has been an external carry. The result is incorrect, as b it 7
has been changed. A n overflow condition should be indicated.
Overflow will occur in four situations:
1—adding large positive num bers
2— adding large negative num bers
3 — su b tractin g a large positive num ber from a large negative
num ber
4— su b tractin g a large negative num ber from a large positive
num ber.

Let us now im prove our definition of the overflow:

Technically, the overflow indicator, a special b it reserved for this
purpose, and called a “ flag,” will be set when there is a carry from
bit 6 into bit 7 and no external carry, or else when there is no carry
from b it 6 into b it 7 b u t there is an external carry. This indicates
th a t b it 7, i.e., the sign of the result, has been accidentally
changed. For the technically-m inded reader, the overflow flag is
set by Exclusive ORing the carry-in and carry-out of bit 7 (the sign
bit). Practically every m icroprocessor is supplied w ith a special
overflow flag to autom atically detect this condition, which re­
quires corrective action.
Overflow indicates th a t the result of an addition or a subtraction
requires more b its th an are available in the stan d ard eight-bit
register used to contain the result.

The Carry and the Overflow

The carry and the overflow b its are called “ flags.” They are pro­
vided in every m icroprocessor, and in the next chapter we will
learn to use them for effective program m ing. These tw o indicators
are located in a special register called the flags or “ s ta tu s ”
register. This register also contains additional indicators whose
function will be clarified in C hapter 4.
Examples
L et us now illu strate the operation of the carry and the overflow
in actual examples. In each example, the symbol V denotes the
overflow, and C the carry.
If there has been no overflow, V = 0. If there has been an
overflow, V = 1 (same for the carry C). Remember th a t the rules of
tw o’s com plem ent specify th a t the carry be ignored. (The
m athem atical proof is not supplied here.)
Positive-Positive
00000110 ( + 6)
+ 00001000 ( + 8)
= 00001110 (+14) V:0 C:0
(CORRECT)
Positive-Positive w ith Overflow
01111111 ( + 127)
+ 00000001 (+1)
= 10000000 (-1 2 8 ) V:1 C:0
The above is invalid because an overflow has occurred.
(ERROR)
Positive-N egative (result positive)
00000100 (+4)
+ 11111110 ( -2 )
=(1)00000010 (+2) V:0 C:1 (disregard)
(CORRECT)
Positive-N egative (result negative)
00000010 (+2)
+ 11111100 ( -4 )
= 11111110 (-2 ) V:0 C:0
(CORRECT)
N egative-N egative
11111110 ( -2 )
+ 11111010 ( -4 )
=(1)11111010 (-6 ) V:0 C:1 (disregard)
(CORRECT)
Negative-N egative w ith Overflow
10000001 (-1 2 7 )
+ 11000010 (-6 2 )
=(1)01000011 (67) V:1 C:1
(ERROR)
This tim e an “ underflow ” has occurred, by adding two large
negative num bers. The result would be —189, which is too large to
reside in eight bits.
Exercise 1.12: Complete the following additions . Indicate the
result, the carry C, the overflow V, and whether the result is correct
or not:
10111111 ( > 11111010 ( )
+11000001 ( ) +11111001 ( )
V: C: = V: n*
□ CORRECT □ ER RO R □ CORRECT □ ER R O R

00010000 ( ) 01111110 ( )
+01000000 ( ) +00101010 ( )
= V: C:__ = V: C-
□ CORRECT 1 1 ER RO R □ CORRECT □ ER RO R

Exercise 1.13: Can you show an example o f overflow when adding a

positive and a negative number? Why?

Fixed Format Representation

Now we know how to represent signed integers. However, we
have not y et resolved the problem of m agnitude. If we w ant to
represent larger integers, we will need several bytes. In order to
perform arithm etic operations efficiently, it is necessary to use a
fixed num ber of bytes rath er than a variable one. Therefore, once
the num ber of bytes is chosen, the m axim um m agnitude of the
num ber which can be represented is fixed.

Exercise 1.14: What are the largest and the smallest numbers
which may be represented in two bytes using two’s complement?

The M agnitude Problem

When adding numbers we have restricted ourselves to eight bits

because the processor we will use operates internally on eight b its
a t a time. However, this restricts us to the num bers in the range
—128 to +127. Clearly, this is not sufficient for m any applications.
M ultiple precision will be used to increase the num ber of digits
which can be represented. A two-, three-, or N-byte form at m ay
then be used. F or example, let us examine a 16-bit, “ double-pre­
cision” form at:
00000000 00000000 is “ 0 ”
00000000 00000001 is “ 1”

01111111 11111111 is “ 32767

11111111 11111111 is “ - 1 ”
11111111 11111110 is “ - 2 ”
Exercise 1.15: What is the largest negative integer which can be
represented in a two's complement triple-precision format?
However, th is m ethod will result in disadvantages. W hen adding
tw o num bers, for example, we will generally have to add them
eight b its a t a time. This will be explained in C hapter 4 (Basic Pro­
gram m ing Techniques). I t results in slower processing. Also, this
representation uses 16 b its for any num ber, even if it could be
represented w ith only eight bits. I t is, therefore, common to use 16
or perhaps 32 bits, b u t seldom more.
L et us consider the following im portant point: w hatever the
num ber of b its N chosen for the tw o’s com plem ent representation,
it is fixed. If any resu lt or interm ediate com putation should
generate a num ber requiring more th a n N bits, some b its will be
lost. The program norm ally retains the N left-m ost b its (the m ost
significant) and drops the low-order ones. This is called truncating
the result.
H ere is an example in the decimal system , using a six digit
representation:
123456
X 1.2
246912
123456
= 148147.2
The result requires 7 digits! The “ 2 ” after the decimal point will be
dropped and the final result will be 148147. I t has been truncated.
Usually, as long as the position of the decimal point is not lost, this
m ethod is used to extend the range of the operations which m ay be
performed, a t the expense of precision.
The problem is the sam e in binary. The details of a binary multi-
plication will be shown in C hapter 4.
This fixed-format representation m ay cause a loss of precision,
b u t it m ay be sufficient for usual com putations or m athem atical
operations.
U nfortunately, in the case of accounting, no loss of precision is
tolerable. For example, if a custom er rings up a large to ta l on a
cash register, it would not be acceptable to have a five figure
am ount to pay, which would be approxim ated to the dollar.
A nother representation m ust be used wherever precision in the
result is essential. The solution norm ally used is BCD , or
binary-coded decimal.

BCD Representation
The principle used in representing num bers in BCD is to encode
each decimal digit separately, and to use as m any b its as necessary
to represent the complete num ber exactly. In order to encode each
of the digits from 0 through 9, four b its are necessary. Three b its
would only supply eight combinations, and can therefore not en­
code the ten digits. Four b its allow sixteen com binations and are
therefore sufficient to encode the digits “ 0 ” through “9 ” . I t can
also be noted th a t six of the possible codes will not be used in the
BCD representation (see Fig. 1-3). This will result later on in a po­
tential problem during additions and subtractions, which we will
have to solve. Since only four b its are needed to encode a BCD

BCD BCD
CODE SYMBOL CODE SYMBOL

0000 0 1000 8
0001 1 1001 9
0010 2 1010 unused
0011 3 1011 unused
0100 4 1100 unused
0101 5 1101 unused
0110 6 1110 unused
0111 7 ini unused

Fig. 1-4: BCD Table

digit, tw o BCD digits m ay be encoded in every byte. This is called
“packed BCD. ”
A s an example, “ 00000000” will be " 0 0 ” in BCD. “ 10011001”
wiU be “ 99” .
A BCD code is read as follows:
0010 0001
BCD digit “ 2”
BCD digit “ 1”
BCD number “ 21”
Exercise 1.16: What is the BCD representation fo r ”29"? ”91"?

Exercise 1.17: Is ”10100000" a valid BCD representation? Why?

A s m any bytes as necessary will be used to represent all BCD
digits. Typically, one or m ore nibbles will be used a t the beginning
of the representation to indicate the to ta l num ber of nibbles, i.e.,
the to ta l num ber of BCD digits used. A nother nibble or by te will
be used to denote the position of the decim al point. However, con­
ventions m ay vary.
H ere is an exam ple of a representation for m ultibyte BCD in­
tegers:
3 | + 2 2 1 (3 bytes)

I num ber “ 221”

num ber
of digits *
(up to 255) sign
This represents +221
(The sign m ay be represented by 0000 for + , and 0001 for —, for
example.)
Exercise 1.18: Using the same convention, represent ” -23123”. Show
it in BCD format, as above, then in binary.
Exercise 1.19: Show the BCD fo r ”222” and ”111", then fo r the result
o f 222 x 111. (Compute the result by hand, then show it in the above
representation.)

The BCD representation can easily accom m odate decimal

num bers.
For example, +2.21 m ay be represented by:

2 Hb 2 2 1 —

13 digits
^ 1
(<
is on the - -
r 221

left of digit 2

The advantage of BCD is th a t it yields absolutely correct

results. I ts disadvantage is th a t it uses a large am ount of m em ory
and results in slow arithm etic operations. This is acceptable only
in an accounting environm ent and is norm ally n o t used in other
cases.
Exercise 1.20: How many bits are required to encode ’9999” in BCD?
A nd in Two’s complement?
We have now solved the problem s associated w ith the represen­
tatio n of integers, signed integers and even large integers. W e
have even already presented one possible m ethod of representing
decimal num bers, w ith BCD representation. L et us now exam ine
the problem of representing decimal num bers in a fixed length for­
m at.

Floating-Point Representation
The basic principle is th a t decimal num bers m u st be represented
w ith a fixed form at. In order no t to w aste bits, the representation
will normalize all the num bers.
For example, “ 0.000123” w astes three zeros on the left of the
num ber, which have no m eaning except to indicate the position of
the decim al point. Norm alizing this num ber results in .123 X 10'3.
“ .123” is called a normalized mantissa, “ —3 ” is called the expo­
nent. We have normalized this number by eliminating all the meaning­
less zeros on the left of it and adjusting the exponent.
L et us consider another example:
22.1 is normalized as .221 x 102
or M X 10E where M is the m antissa, and E is the exponent.
 I t can be readily seen th a t a normalized num ber is characterized
by a m antissa less th an 1 and g reater or equal to .1 in all cases
where the num ber is not zero. In other words, this can be repre­
sented m athem atically by:
.1 < M < 1 or 1 0 1< M < 10°
Similarly, in the binary representation:
' 2 1<M <2° (or .5<M<1)
W here M is the absolute value of the m antissa (disregarding the
sign).
F or example:
111.01 is normalized as: .11101 X 23.
The m antissa is 11101.
The exponent is 3.

Now th a t we have defined the principle of the representation,

let us examine the actual format. A typical floating-point represen­
tation appears below.

31 24 23 16 15
---- 1--- I
EXP M A N S S A
____ I _____I_____

Fig. 1-5: Typical Floating-Point Representation

In the representation used in this example, four bytes are used

for a to ta l of 32 bits. The first byte on the left of the illustration is
used to represent the exponent. B oth the exponent and the m an­
tissa will be represented in tw o’s complement. A s a result, the
maximum exponent will be -1 2 8 . “ S” in Fig. 1-5 denotes the sign
bit.
Three bytes are used to represent the m antissa. Since the first
b it in the tw o’s com plem ent representation indicates the sign, this
leaves 23 b its for the representation of the m agnitude of the m an­
tissa.
Exercise 1.21: How many decimal digits can the mantissa repre­
sent with the 23 bits?
This is only one example of a floating point representation. I t is
possible to use only three bytes, or it is possible to use more. The
four-byte representation proposed above is ju s t a common one
which represents a reasonable compromise in term s of accuracy,
m agnitude of num bers, storage utilization, and efficiency in
arithm etic operation.
W e have now explored the problem s associated w ith the rep­
resentation of num bers and we know how to represent them in in­
teger form, w ith a sign, or in decimal form. L et us now examine
how to represent alphanum eric d a ta internally.

R epresenting Alphanum eric D ata

The representation of alphanum eric data, i.e. characters, is com­
pletely straightforw ard: all characters are encoded in an eight-bit
code. Only two codes are in general use in the com puter world, the
A SC II Code, and the EB CD IC Code. A SC II stands for “ Am erican
S tan d ard Code for Inform ation Interchange,” and is universally
used in the world of m icroprocessors. EBCDIC is a variation of
A SC II used by IBM , and therefore not used in the m icrocom puter
world unless one interfaces to an IBM terminal.
L et us briefly examine the A SC II encoding. W e m u st encode 26
letters of the alphabet for both upper and lower case, plus 10
num eric symbols, plus perhaps 20 additional special symbols. This
can be easily accom plished w ith 7 bits, which allow 128 possible
codes. (See Fig. 1-6.) All characters are therefore encoded in 7 bits.
The eighth bit, when it is used, is the parity b it P arity is a tech­
nique for verifying th a t the contents of a byte have not been ac­
cidentally changed. The num ber of l ’s in the byte is counted and
the eighth b it is set to one if the count was odd, th u s m aking the
to ta l even. This is called even parity. One can also use odd parity,
i.e. writing the eighth bit (the left-most) so th a t the total num ber of
l ’s in the byte is odd.
Exam ple: let u s com pute the p arity b it for “ 0010011 ” using even
parity. The num ber of l ’s is 3. The p arity bit m u st therefore be a 1
so th a t the to ta l num ber of b its is 4, i.e. even. The result is
10010011, where the leading 1 is the p arity b it and 0010011 iden­
tifies the character.
 The table of 7-bit ASCII codes is shown in Fig. 1-6. In practice, it
is used “ as is,” i.e. without parity, by adding a 0 in the left-most
position, or else w ith parity, by adding the appropriate ex tra bit on
th e left.
Exercise 1.22: Compute the 8-bit representation o f the digits “0 ”
through using even parity. (This code will be used in applica­
tion examples o f Chapter 8.)
Exercise 1.23: Same for the letters “A ” through "F".
Exercise 1.24: Using a non-parity A S C II code (where the left-most
bit is “0 indicate the binary contents o f the 4 bytes below:
ttr p a tSX*9
f f J J i

Fig. 1-6: ASCII Conversion Table

In specialized situations such as telecom m unications, other

codings m ay be used such as error-correcting codes. However they
are beyond the scope of this book.
 We have exam ined the usual representations for both program
and d a ta inside the com puter. L et us now examine the possible ex­
ternal representations.

E X T E R N A L R E P R E S E N T A T IO N OF IN F O R M A TIO N
The external representation refers to the way inform ation is pre­
sented to the user, i.e. generally to the program m er. Inform ation
m ay be presented externally in essentially three form ats: binary,
octal or hexdecim al, and symbolic.
1. Binary
I t has been seen th a t inform ation is stored internally in bytes,
which are sequences of eight bits (0’s or l ’s). I t is som etim es
desirable to display this internal information directly in its binary
form at and this is called binary representation. One simple exam ­
ple is provided by L ight E m ittin g Diodes (LEDs) which are essen­
tially m iniature lights, on the front panel of the m icrocom puter. In
the case of an eight-bit m icroprocessor, a front panel will typically
be equipped w ith eight L E D s to display the contents of any inter­
nal register. (A register is used to hold eight b its of inform ation
and will be described in C hapter 2). A lighted LED indicates a one.
A zero is indicated by an LED which is not lighted. Such a binary
representation m ay be used for the fine debugging of a complex
program , especially if it involves input/output, b u t is naturally
im practical a t the hum an level. This is because in m ost cases, one
likes to look a t inform ation in symbolic form. Thus “9 ” is m uch
easier to understand or rem em ber th an “ 1001” . More convenient
representations have been devised, which im prove the person-
m achine interface.

2. Octal and Hexadecimal

“ O ctal” and “ hexadecim al” encode respectively three and four
binary b its into a unique symbol. In the octal system , any
com bination of three binary b its is represented by a num ber be­
tween 0 and 7.
“ O ctal” is a form at using three bits, where each com bination of
three bits is represented by a symbol between 0 and 7:
 binary octal
000 0
001 1
010 2
O il 3
100 4
101 5
110 6
111 7

Fig. 1-7: Octal Symbols

F or example, “ 00 100 100” binary is represented by:

T T T
0 4 4
or “ 044” in octal.
A nother example: 11 111 111 is:
T T y
3 7 7
or “ 377” in octal.
Conversely, the octal “ 211” represents:
010 001 001
or “ 10001001” binary.
O ctal has traditionally been used on older com puters which were
employing various num bers of b its ranging from 8 to perhaps 64.
M ore recently, w ith the dom inance of eight-bit m icroprocessors,
the eight-bit form at has become the standard, and another more
practical representation is used. This is hexadecimal.
In the hex decimal representation, a group of four bits is en­
coded as one hexadecim al digit. Hexadecim al digits are
represented by the sym bols from 0 to 9, and by the letters A, B, C,
D, E, F. For example, “ 0000” is represented by “ 0 ”, “0001” is
represented by “ 1” and “ 1111” is represented by the letter “ F ”
(see Fig. 1-8).
DECIMAL BINARY HEX OCTAL

0 0000 0 0

1 0001 1 1

2 0010 2 2

3 0011 3 3

4 0100 4 4

5 0101 5 5
6 0110 6 6

7 0111 7 7

8 1000 8 10

9 1001 9 11

10 1010 A 12

11 1011 B 13

12 1100 C 14

13 1101 D 15

14 1110 E 16

15 1111 F 17

Fig. 1-8: Hexadecim al Codes

Exam ple: 1010 0001 in binary is represented by
A 1 in hexadecimal.

Exercise 1.25: W hat is the hexadecimal representation o f

“ 10101010 ? "

Exercise 1.26: Conversely, what is the binary equivalent o f “FA ”

hexadecimal?
Exercise 1.27: What is the octal o f “01000001 ”?

Hexadecim al offers the advantage of encoding eight b its into on­

ly tw o digits. This is easier to visualize or memorize and faster to
type into a com puter th an its binary equivalent. Therefore, on
m ost new m icrocom puters, hexadecim al is the preferred m ethod of
representation for groups of bits.
N aturally, whenever the inform ation present in the memory has
a meaning, such as representing te x t or num bers, hexadecimal is
not convenient for representing th e m eaning of this inform ation
when it is brought out for use by hum ans.

Symbolic Representation
Symbolic representation refers to the external representation of
inform ation in actual symbolic form. F or example, decimal num ­
bers are represented as decimal num bers, and not as sequences of
hexadecim al sym bols or bits. Similarly, te x t is represented as
such. N aturally, symbolic representation is m ost practical to the
user. I t is used whenever an appropriate display device is
available, such as a CRT display or a printer. (A CRT display is a
television-type screen used to display te x t or graphics.) Unfortu­
nately, in smaller systems such as one-board microcomputers, it is
uneconomical to provide such displays, and the user is restricted
to hexadecimal com m unication w ith the com puter.

Sum m ary of E xternal R epresentations

Symbolic representation of information is the most desirable

since it is th e m ost n atu ral for a hum an user. However, it requires
an expensive interface in the form of an alphanum eric keyboard,
plus a prin ter or a CRT display. For this reason, it may not be
available on the less expensive systems. An alternative type of rep­
resentation is th en used, and in this case hexadecimal is the domi­
n a n t representation. Only in rare cases relating to fine de-bugging
a t the hardw are or the softw are level is the binary representation
used. Binary directly displays the contents of registers of m emory
in binary form at.
(The u tility of a direct binary display on a front panel has alw ays
been the subject of a heated em otional controversy, which will n ot
be debated here.)
W e have seen how to represent inform ation internally and exter­
nally. We will now examine the actual microprocessor which will
m anipulate this inform ation.

Additional Exercises

Exercise 1.28: What is the advantage o f two’s complement over other

representations used to represent signed numbers?

Exercise 1.29: How would you represent “1024” in direct binary? Signed
binary? Two’s complement?

Exercise 1.30: What is the V-bit? Should the programmer test it after an
addition or subtraction?

Exercise 1.31: Compute the two’s complement o f ” +16”, “ +17”,

” +18”, ” - 1 6 ”, ” - 1 7 ”, ” - 1 8 ”.

Exercise 1.32: Show the hexadecimal representation o f the following

text, which has been stored internally in ASCII format, with no parity:
= “MESSAGE”.
6502 HARDWARE ORGANIZATION
INTRO DUCTIO N
In order to program a t an elem entary level, it is not necessary
to understand in detail the in tern al structure of the processor
th a t one is using. However, in order to do efficient program m ing,
such an understanding is required. The purpose of this chapter is
to present the basic hardware concepts necessary for understan­
ding the operation of the 6502 system. The complete microcompu­
te r system includes not only the microprocessor u n it (here the
6502), b u t also other components. This chapter presents th e 6502
proper, while the other devices (mainly input/output) will be pre­
sented in a separate chapter (Chapter 7).
We will review here the basic architecture of the microcomputer
system, then study more closely the internal organization of the
6502. We will examine, in particular, the various registers. We will
then study the program execution and sequencing mechansim.
From a hardware standpoint, this chapter is only a simplified
presentation. The reader interested in gaining detailed understanding
is referred to our book ref. C201 (“ Microprocessors,” by the same
author).

SYSTEM ARCH ITECTURE

The architecture of the microcomputer system appears in Figure

2-1. The microprocessor unit (MPU), which will be a 6502 here,
appears on the left of the illustration. It implements the functions
of a central processing unit (CPU) within one chip: it in­
cludes an arithmetic-logical-unit (ALU), plus its internal registers,
and a control-unit (CU) in charge of sequencing the system.
Its operation will be explained in this chapter.

POWER

CONTROL LINES

Fig. 2-1: Architecture of a Standard Microprocessor System

The M PU creates three buses: a n 8-bit bi-directional data-bus,

which appears a t the top of the illustration, a 16-bit mono­
directional address-bus and a control-bus which appears a t th e
bottom of the illustration. L et us describe the function of each of
the buses.
The data-bus carries data being exchanged by the various
elements of the system. Typically, it will carry data from the
memory to the MPU, from the MPU to the memory, or from
the MPU to an input/ouput chip. (An input/output chip is a com­
ponent in charge of communicating with an external device.)
The address-bus carries a n address generated by the MPU,
which will select one in te rn al register w ithin one of th e chips
attached to th e system. This address specifies th e source, or the
destination, of th e d a ta which will tra n s it along the data-bus.
The control-bus carries th e various synchronization signals re ­
quired by the system.
 Having described the purpose of the busses, let us now connect the ad­
ditional components required by a complete system.
Every MPU requires a precise timing reference, which is supplied by a
clock and a crystal. In most “ older” microprocessors, the clock-oscilla­
tor is external to the MPU and requires an extra chip. In most recent mi­
croprocessors, the clock oscillator is usually incorporated within the
MPU. The quartz crystal, however, because of its bulk is always external
to the system. The crystal and the clock appear on the left of the MPU
box in the illustration.
Let us now turn our attention to the other elements of the system. Go­
ing from left to right on the illustration, we distinguish:
The ROM is the read-only-memory and contains the program for the
system. The advantage of the ROM is that its contents are permanent
and do not disappear whenever the system is turned off. The ROM,
therefore, always contains a bootstrap or a monitor program (their func­
tion will be explained later) to permit initial system operation. In a pro­
cess-control environment, nearly all the programs will reside in ROM as
they will probably never be changed. In such case, the industrial user has
to protect the system against power failures: programs may not be vola­
tile. They must be in ROM.
However, in a hobbyist environment, or in a program-development
environment (when the programmer tests the program), most of the pro­
grams will reside in RAM so that they can easily be changed. Later, they
may remain in RAM, or be transferred into ROM, if desired. RAM,
however, is volatile. Its contents are lost when power is turned off.
The R A M (random-access-memory) is the read/write memory for the
system. In the case of a control system, the amount of RAM will typi­
cally be small (for data only). On the other hand, in a program-develop­
ment environment, the amount of RAM will be large, as it will contain
programs plus development software. All RAM contents must be loaded
prior to use from an external device.
Finally, the system will contain one or more interface chips so that it
may communicate with the external world. The most frequently used in­
terface chip is the “PIO” or parallel-input-output chip. It is the one
shown in the illustration. This PIO, like all other chips in the system,
connects to all three busses and provides at least two 16-bit ports for
communication with the outside world. For more details on how an ac­
tual PIO works, refer to book C201 or else, for specifics of the 6502 sys­
tem, refer to Chapter 7 (Input/Output devices).
 All these chips are connected to all three busses, including the
control bus. However, to clarify the illustration, the connections be­
tween the control bus and these various chips are not shown on the
diagram.
The functional modules which have been described need not
necessarily reside on a single LSI chip. In fact, we will use combina­
tion chips which include both a PIO and a lim ited am ount of ROM
or RAM. For more details refer to C hapter 7.
Still more components will be required to build a real system . In
particular, the busses usually need to be buffered. Also decoding
logic m ay be used for the memory RAM chips, and finally some
signals may need to be amplified by drivers. These auxiliary circuits
will not be described here as they are not relevant to programming.
The reader interested in specific assem bly and interfacing tech­
niques is referred to book C207 “M icroprocessor Interfacing Tech­
niques.”

IN TER N A L ORGANIZATION O F T H E 6502

A simplified diagram of the internal organization of the 6502 ap­
pears in Figure 2-2.
The arithm etic logical un it (ALU) appears on the right of the il­
lustration. I t can easily be recognized by its characteristic V
shape. The function of the ALU is to perform arithm etic and logical
operations on the d a ta which is fed to it via its two input ports. The
two input ports of the ALU are respectively the “ left input” and the
“right input.” They correspond to the top extrem ities of the “V ”
shape. A fter performing an arithm etic operation such as an addition
or subtraction, the ALU outputs its contents a t the bottom of the il­
lustration.
The ALU is equipped w ith a special register, the accumulator (A).
The accum ulator is on the left input. The ALU will autom atically
reference this accum ulator as one of the inputs. (However, a bypass
also exists.) This is a classic accum ulator-based design. In
arithm etic and logical operations, one of the operands will be the ac­
cumulator, and the other will typically be a memory location.
The result will be deposited in the accumulator. Referencing the ac­
cum ulator as both the source and the destination for d ata is the
reason for its name: it accum ulates results. The advantage of this
accum ulator-based approach is the possibility of using very short
instructions-just a single byte (8 bits) to specify the opcode i.e.
 Fig. 2-2: Internal Organization of the 6502

the nature of the operation performed. If the operand had to be

fetched from one of the other registers (other th an an accumulator),
it would be necessary to use a num ber of extra b its to designate t-.hig
register within the instruction. The accum ulator architecture there­
fore, results in improved execution speed. The disadvantage is th a t
the accum ulator m ust always be loaded w ith the desired d a ta prior
to its use. This m ay result in some inefficiency.
L et us go back to the illustration. B y the side of th e ALU, to its
left, appears a special 8-bit register, the processor status-flags (P).
This register contains 8 sta tu s bits. E ach of these bits, physically
implemented by a flip-flop inside the register is used to denote a
special condition. The function of the various sta tu s b its will be ex­
plained progressively during the programming examples presented
in the next chapter, and will be described completely in Chapter
4, which presents the complete instruction set. As an example,
three such status flags are the N, Z, and C bits.
 N stands for "negative.” It is b it 7 (i.e., the left-most) of regis­
te r P. W henever th is b it is one it indicates th a t the resu lt of th e
operation through the ALU is negative.
B it Z stands for zero. W henever th is b it (bit position 1) is a one,
it denotes th a t a zero resu lt was obtained.
B it C, in the right-m ost position (position 0), is a carry bit.
W henever two 8-bit num bers are added and the resu lt cannot be
contained in 8 bits, bit C is th e n in th b it of the result. The carry is
used extensively during arithm etic operations.
These sta tu s bits are autom atically set by the various instruc­
tions. A complete list of the instructions and the way in which
they affect the sta tu s bits of the system appears in Appendix A, as
well as in C hapter 4. These bits will be used by th e program m er to
test various special or exceptional conditions, or else to te st
quickly for some erroneous result. As a n example, testing b it Z
m ay be accomplished w ith special instructions and will im ­
mediately tell whether the result of a previous operation was 0
or not. All decisions in an assem bly language program , i.e. in all
the program s th a t will be developed in this book, will be based on
the testin g of bits. These bits will be eith er bits th a t will be read
from the outside world, or else the sta tu s bits of th e ALU. It is
therefore very important to understand the function and use of all
statu s bits in the system. The ALU here is equipped w ith a sta tu s
register containing these bits. All other input/output chips in the
system will also be equipped w ith sta tu s bits. These will be
studied in Chapter 7.

Let us now move leftw ards of the ALU on illu stratio n 2-2. The
horizontal rectangles represent the in tern al registers of the 6502.
PC is the program counter. It is a 16-bit register and is physi­
cally im plem ented as two 8-bit registers: PCL and PCH. PCL
stands for the low h a lf of the program counter, i.e., bits 0 through
7. PCH stands for the high p a rt of th e program counter, i.e., bits 8
through 15. The program counter is a 16-bit register which con­
tain s the address of the next instruction to be executed. Every
com puter is equipped w ith a program counter so th a t it knows
which instruction to execute next. Let us review briefly the m em ­
ory access m echanism in order to illu strate the role of th e pro­
gram counter. ,
 Fig. 2-3: Fetching an Instruction from the Memory

THE INSTRUCTION EXECUTION CYCLE

Let us refer now to Figure 2-3. The microprocessor u n it appears

on the left, and the mem ory appears on the right. The memory
chip m ay be a ROM or a RAM, or any other chip which happens to
contain memory. The m em ory is used to store instructions and
data. Here, we will fetch one instruction from the mem ory to
illu strate the role of the program counter. We assum e th a t the
program counter has valid contents. It now holds a 16-bit address
which is the address of the next instruction to fetch in the mem­
ory. Every processor proceeds in three cycles:
1 — Fetch the next instruction
2 — Decode the instruction
3 — Execute the instruction

Fetch

L et us now follow the sequence. In the first cycle, the contents of

the program counter are deposited on the address bus and gated
to the mem ory (on the address bus). Simultaneously, a read signal
m ay be issued on the control bus of the system , if required. The
mem ory will receive the address. This address is used to specify
one location w ithin the memory. Upon receiving th e read signal,
the memory will decode the address it has received, through
in tern al decoders, and will select the location specified by the
address. A few hundred nanoseconds later, the memory will de­
posit th e 8-bit d a ta corresponding to the specified address on its
data-bus. This 8-bit word is the instruction th a t we w ant to fetch.
In our illustration, this instruction will be deposited on top of the
data bus.
Let us briefly summarize the sequencing. The contents of the
program counter are output on the address bus. A read signal is
generated. The memory cycles. Perhaps 300 nanoseconds later,
th e instruction a t the specified address is deposited on the data-
bus. The microprocessor th en reads the data-bus and deposits its
contents into a specialized in ternal register, the IR register. The
IR register is the instruction-register. It is 8 bits wide and is used
to contain the instruction just fetched from the memory. The fetch
cycle is now completed. The 8 bits of the instruction are now physi­
cally in the special in tern al register of th e 6502, the IR register.
This IR register appears on the left of Figure 2-4.

Decoding and Execution

Once the instruction is contained in IR, the control-unit of the
microprocessor will decode the contents and will be able to gen­
erate the correct sequence of in tern al and external signals for the
execution of the specified instruction. There is, therefore, a short
decoding delay followed by an execution phase, the length of
which depends on the n a tu re of the instruction specified. Some
instructions will execute entirely within the MPU. Other instruc­
tions will fetch or deposit d a ta from or into the memory. This is
why the various instructions of th e 6502 require various lengths
of tim e to execute. This duration is expressed as a num ber of
(clock) cycles. Refer to the Appendix for the number of cycles re­
quired by each instruction. A typical 6502 uses one-megahertz
clock. The length of each cycle is therefore 1 microsecond. Since
various clock rate s m ay be used w ith different components, speed
of execution is norm ally expressed in num ber of cycles ra th e r
than in number of nanoseconds.

In the case of the 6502, its clock is internal, represented by the in ­

ternal oscillator (see Fig. 2-1).
F e tch in g th e N ex t In s tr u c tio n

We have now described how, using the program counter, an

instruction can be fetched from the memory. D uring the execution
of a program , instructions are fetched in sequence from the m em ­
ory. An autom atic m echanism m ust therefore be provided to fetch
instructions in sequence. This task is performed by a simple in-
crementor attached to the program counter. This is illustrated in
Figure 2-4. Every tim e th a t the contents of the program counter
(at the bottom of the illustration) are placed on the address-bus,
its contents will be increm ented and w ritten back into the pro­
gram counter. As an example, if the program counter did contain
the value 0, the value 0 would be output in the address bus. Then
the contents of the program counter would be increm ented and
the value 1 would be w ritten back into the program counter. In
this way, the next time that the program counter is used, it is the
instruction at address 1 that will be fetched. We have just imple­
mented an automatic mechanism for sequencing instructions.

Fig. 2-4: Automatic Sequencing

 It m ust be stressed th a t th e above descriptions are simplified.
In reality, some instructions may be 2- or even 3-bytes long so that
successive bytes will be fetched in th is m anner from the memory.
However, the m echanism is identical. The program counter is
used to fetch successive bytes of an instruction, as well as to fetch
successive instructions themselves. The program counter, to­
gether w ith its increm enter, provides an autom atic m echanism
for pointing to successive memory locations.

O th e r 6502 R e g is te rs
One last area on Figure 2-2 has not yet been explained. It is the
set of three registers labeled X, Y and S. Registers X and Y are
called index registers. They are 8 bits wide. They may be used to
contain d ata on which the program will operate. However, they
norm ally are used as index registers.
The role of index registers will be described in C hapter 5 on
addressing techniques. Briefly, the contents of these two index
registers m ay be added in several ways to any specified address
w ithin the system to provide an autom atic offset. This is an im ­
p ortant facility for retrieving data efficiently w hen it is stored in
tables. These two registers are not completely sym m etrical, and
th eir roles will be differentiated in the chapter on addressing
techniques.
The stack register S is used to contain a pointer to the top of the
stack area w ithin the memory.
Let us now introduce th e formal concept of a stack.

THE STACK
A stack is formally called an LIFO structure Oast-in, first-out). A
stack is a set of registers, or memory locations, allocated to this
data structure. The essential characteristic of this structure is
that it is a chronological structure. The first element introduced
into the stack is always at the bottom of the stack. The element
most recently deposited in the stack is on the top of the stack. The
analogy can be drawn to a stack of plates on a restaurant
counter. There is a hole in the counter with a spring in the bottom.
Plates are piled up in the hole. With this organization, it is
guaranteed that the plate which has been put first in the stack
(the oldest) is always at the bottom. The one that has been placed
 m ost recently on the stack is the one which is on top of it. This
exam ple also illu strates another characteristic of the stack. In
norm al use, a stack is only accessible via two instructions: "push”
and “ pop” (or “ pull” ). The push operation results in depositing one
element on top of the stack. The pull operation consists of remov­
ing one elem ent from th e stack. In practice, in the case of a mic­
roprocessor, it is the accumulator th a t will be deposited on top of
the stack. The pop will resu lt in a transfer of the top elem ent of
the stack into the accumulator. O ther specialized instructions
m ay exist to tran sfer the top of the stack betw een other spe­
cialized registers, such as the sta tu s register.
The availability of a stack is required to im plem ent th ree pro­
gram m ing facilities w ithin the com puter system: subroutines, in­
terrupts, and tem porary d a ta storage. The role of the stack during
subroutines will be explained in C hapter 3 (Basic Program m ing
Techniques). The role of the stack during in terru p ts will be ex­
plained in Chapter 6 (Input/O utput Techniques). Finally, the role
of the stack to save d a ta a t high speed will be explained during
specific application program s.
We will simply assum e a t th is point th a t the stack is a required
facility in every com puter system. A stack m ay be im plem ented
in two ways:
1. A fixed num ber of registers m ay be provided w ithin the m i­
croprocessor itself. This is a "hardw are stack.” It has the advan­
tage of high speed. However, it has th e disadvantage of a lim ited
num ber of registers.
2. Most general-purpose microprocessors choose another ap­
proach, the software stack, in order not to restrict the stack to
a very sm all num ber of registers. This is the approach chosen in
the 6502. In the software approach, a dedicated register within
the microprocessor, here register S, stores the stack pointer, i.e.,
the address of the top element of the stack (or more precisely, the
address of the top element of the stack plus one). The stack is then
implemented as an area of memory. The stack pointer will therefore
require 16 bits to point anywhere in the memory.
However, in the case of th e 6502, the stack pointer is restricted
to 8 bits. It includes a 9th bit, in the left-m ost position, alw ays set
to 1. In other words, the a rea allocated to the stack in the case of
th e 6502 ranges from address 256 to address 511. In binary, th is is
"100000000” to "111111111.” The stack alw ays sta rts a t address
111111111 and may have up to 255 words. This may be viewed
as a lim itation of th e 6502 and will be discussed la te r in this book.
In th e 6502, the stack is a t the high address, and grows
“ backwards” ; the stack pointer is decremented by a PUSH.
In order to use the stack, th e program m er will simply initialize
th e S register. The rest is autom atic.
The stack is said to reside in page 1 of the memory. Let us now
introduce the paging concept.

MICROPROCESSOR 7 MEMORY 0
r” REGISTER “J

7 | DATA 1 ° I
PUSH

8 f ADDRESS 1° | POP,
SP 1 ■ ---- i
BASE

Fig. 2-5: The 2 Stack Manipulation Instructions

THE PAGING CONCEPT

The 6502 microprocessor is equipped w ith a 16-bit address-bus.
16 binary bits m ay be used to create up to 216 = 64K combinations
(IK equals 1,024). Because of addressing features of th e 6502
which will be presented in C hapter 5, it is convenient to partition
the memory into logical pages.. A page is simply a block of 256
words. Thus, memory locations 0 to 255 are page 0 of the memory.
It will be used for “ page zero” addressing.Page 1 of the memory
includes memory locations 256 through 511. We have ju st estab­
lished th a t page 1 is norm ally reserved for the stack area. All
other pages in the system are unconstrained by th e design and
m ay be used in any way. In th e case of the 6502, it is im portant to
keep in m ind th e page organization of the memory. W henever a
page boundary h as to be crossed, it will often introduce an extra
cycle delay in the execution of an instruction.
 MEMORY

Fig. 2-6: The Paging Concept

T H E 6502 C H IP

To complete our description of the diagram, the data bus at the up­
per part of Figure 2-2 represents the external data bus. It will be used to
communicate with the external devices, and the memory in particular.
AO-7 and A8-15 represent respectively the low-order and the high-order
part of the address-bus created by the 6502.
For completeness, we present here th e actual pin-out of the
6502 microprocessor. You need not read it to understand the rest
of th is book. However, if you intend to connect devices to a system ,
th is description will be valuable.
The actual pin-out of the 6502 appears in Figure 2-7. The data
bus is labeled DBO-7 and is easily recognizable on the right of the
illustration. The address bus is labeled A0-11 and A12-15. It comes
 Fig. 2-7; 6502 Pinout

from pins 9 to 20 on the left of the chip, and pins 22 to 25 on its

right.
The rest of the signals are power and control signals.

The control signals

—R/W : the READ/W RITE line controls the direction of data
transfers on the data-bus.
—IRQ and NMI are “ Interrupt Request” and “ Non-Maskable
Interrupt” . They are two interrupt lines and will be used in
Chapter 7.
—SYNC is a signal which indicates an opcode fetch to the exter­
n al world.
—RDY is norm ally used to synchronize w ith a slow memory: it
will stop th e processor.
—SO sets the overflow flag. It is norm ally not used.
—0o, 0! and 02 are clock signals.
—RES is RESET, used to initialize.
—Yss and Vcc are for power (5V).
HARDW ARE SUM M ARY

This completes our hardw are description of the internal organi­

zation of the 6502. The exact in tern al bussing structure of the
6502 is not im portant a t this point. However, th e exact role of
each of the registers is im portant and should be fully understood
before the reader proceeds. If you are fam iliar w ith the concepts
th a t have been presented, read on. If you do not feel sure about
some of them , it is suggested th a t you read again the relevant
sections of th is chapter, as they will be needed in the next chap­
ters. It is suggested th a t you look again a t Figure 2-2 and m ake
sure th a t you understand the function of every register in the
illustration.
BASIC PROGRAMMING
TECHNIQUES
IN T R O D U C T IO N
The purpose of this chapter is to present all the basic tech­
niques necessary to w rite a program using the 6502. This chapter
will introduce additional concepts such as register m anagem ent,
loops, and subroutines. It will focus on program m ing techniques
using only the internal 6502 resources, i.e., the registers. Actual
program s will be developed such as arithm etic program s. These
program s will serve to illu strate the various concepts presented
so far and will use actual instructions. Thus, it will be seen how
instructions m ay be used to m anipulate the inform ation betw een
the memory and the MPU, as well as m anipulate inform ation
w ithin the MPU itself. The next chapter will th en discuss in com­
plete detail the instructions available on the 6502. Chapter 6 will
present the techniques available to m anipulate information out­
side the 6502: the input/output techniques.
In this chapter, we will essentially learn by “doing.” By examining
program s of increasing complexity, we will learn the role of the
various instructions and of the registers and will apply the concepts
developed so far. However, one im portant concept will not be
presented here; it is the concept of addressing techniques. Because of
its apparent complexity, it will be presented separately in chapter 5.

Let us im m ediately s ta rt w riting some program s for the 6502.

We will s ta rt w ith arithm etic programs.
A R IT H M E T IC PR O G R A M S

Arithm etic program s cover addition, subtraction, multiplication,

and division. The programs th at will be presented here will operate on
integers. These integers may be positive binary integers or may be ex­
pressed in two's complement notation, in which case the left-most bit
is the sign bit (See Chapter 1 for a reminder of the tw o's complement
notation.)

8-B it A d d itio n
We will add two 8-bit operands called OP1 and OP2, re­
spectively stored at memory address ADR1 and ADR2. The sum
will be called RES and will be stored a t memory address ADR3.
This is illu strated in F igure 3-1. The program which will perform
this addition is the following:

LDA ADR1 LOAD OP1 IN A

ADC ADR2 ADD OP2 TO OP1
STA ADR3 SAVE RES AT ADR3
MEMORY

ADR1 OP1 (FIRST OPERAND)

ADR2 OP2 (SECOND OPERAND)

ADR3 RES (RESULT)

ADDRESSES

Fig. 3-1:8-Bit Addition Res=O Pl + OP2

 This is a three-instruction program . Each line is one instruc­
tion, in symbolic form. Each such instruction will be tran slated by
the assem bler program into 1, 2, or 3 binary bytes. We will not
concern ourselves w ith the tran slatio n here and only look a t the
symbolic representation. The first line specifies an LDA instruc­
tion. LDA means “ load the accumulator A from the address which
follows.”
The address specified on the first line is ADR1. ADR1 is a sym ­
bolic representation for an actual 16-bit address. Somewhere else
in the program, the ADR1 symbol will be defined. It could be, for
example, address 100.
The instruction LDA specifies "load accum ulator A” (inside the
6502) from memory location 100. This will resu lt in a read opera­
tion from address 100, the contents of which will be tran sm itted
along the data-bus and deposited inside the accumulator. You
will recall that arithmetic and logical operations operate on the ac­
cum ulator as one of the source operands. (Refer to the previous
chapter for more details.) Since we wish to add the two values
OP1 and OP2 together, we first load OP1 into the accumulator.
Then we will be able to add the contents of the accum ulator (OP1)
to OP2.
The right-m ost field of th is instruction is called a comment field .
It is ignored by the processor, but it is provided for program
readability. In order to understand w hat the program does, it is of
param ount im portance to use good comments.
This is called documenting a program . H ere the comment is self
explanatory: the value of OP1, which is located a t address ADR1,
is being loaded in accum ulator A.
The result of this first instruction is illustrated by Figure 3-2.
6502 M EM ORY

Fig. 3-2: LDA ADR1: OP1 is Loaded from Memory

 The second instruction of our program is:
ADC ADR2
It specifies “ add the contents of memory location ADR2 to the
accumulator.” Referring to Figure 3-1, the contents of memory
location ADR2 are OP2, our second operand. The actual contents of
the accumulator now OP1, our first operand. As a resu lt of th e
execution of the second instruction, OP2 will be fetched from the
memory and added to OP1. The sum will be deposited in th e
accumulator. The reader will rem em ber th a t the resu lts of an
arithm etical operation, in the case of the 6502, are deposited back
into the accumulator. In other microprocessors, it m ay be possible
to deposit these results in other registers or back into the memory.
The sum of OP1 and OP2 is now in the accumulator. We have
ju s t to tran sfer the contents of the accum ulator into mem ory loca­
tion ADR3 in order to store the results a t the specified location.
Again, the right-m ost field of th e second instruction is simply a
comment field which explains th e role of the instruction (add OP2
to A ).'

Fig. 3-3:ADCADR2

The effect of the second instruction is illustrated by Figure 3-3.

It can be verified in F igure 3-3 that, initially the accum ulator
contained O P l. A fter the addition, a new resu lt has been w ritten
into the accumulator. It is O P l + OP2. The contents of any regis­
te r w ithin the system, as well as any memory location, rem ain the
sam e when a read operation is performed. In other words, reading
the contents of a register or a memory location does not change its
contents. It is only, and exclusively, a w rite operation th a t will
change the contents of a register. In th is example, the contents of
memory locations ADR1 and ADR2 are unchanged. However,
after th e second instruction of this program , the contents of the
accum ulator have been modified because the output of the ALU
has been w ritten into the accumulator. Its previous contents are
then lost.
Let us now save this resu lt a t address ADR3 and we will have
completed our simple addition.
The th ird instruction specifies: STA ADR3. This m eans “ Store
the contents of accum ulator A a t the address ADR3.” This is self­
explanatory and is illustrated in Figure 3-4.
6502 M EM ORY

Fig. 3-4: STA ADR3 (Save Accumulator in Memory)

6502 Peculiarities
The above three-instruction program would indeed by the com­
p le te p ro g ra m for m ost m icro p ro cesso rs. H ow ever, tw o
peculiarities of the 6502 exist, which will norm ally require two
additional instructions.
F irst, the ADC instruction really m eans "add with carry?
ra th e r th a n "add.” The difference is th a t a reg u lar add instruction
adds two num bers together. An add-with-carry adds two num bers
together plus the value of the carry bit. Since we are adding here
8-bit numbers, no carry should be used, and at the time we start
the addition we do not necessarily know the condition of the carry
bit (it may have been set by a previous instruction), so we must clear
it, i.e., set it to zero. This will be accomplished by the CLC instruc­
tion: “ clear carry.”
 U nfortunately, the 6502 does not have both types of addition
operations. I t has only an ADC operation. As a result, for single
8-bit additions, a necessary precaution is to alw ays clear the carry
bit. This is no significant disadvantage b u t should not be forgot­
ten.
The second peculiarity of th e 6502 lies w ith th e fact th a t it is
equipped w ith powerful decim al instructions, which will be used
in th e next section on BCD arithm etic. The 6502 alw ays operates
in one of two modes: binary or decimal. The sta te it is in is con­
ditioned by a statu s bit, th e "D” b it (of register P). Since we are
operating in binary mode in th is example, it is necessary to m ake
sure th a t the D b it is correctly set. This will be done by a CLD
instruction, which will clear th e D bit. N aturally, if all arithm etic
w ithin th e system is done in binary, the D b it will be cleared once
and for all a t the beginning of the program , and it will not be
necessary to set it every tim e. Therefore, this instruction may, in
fact, be om itted in m ost program s. However, th e reader, who will
practice these exercises on a computer, m ay go back and forth
betw een BCD and binary exercises, and this ex tra instruction has
been included here as it m ust appear a t least once before any
binary addition is performed.
lb summ arize: our complete, and safe, 8-bit program is now:
CLC CLEAR CARRY BIT
CLD CLEAR DECIMAL BIT
LDA ADR1 LOAD OP1 IN A
ADC ADR2 ADD OP2 TO OP1
STA ADR3 SAVE RES AT ADR3
Actual physical addresses m ay be used instead of ADR1, ADR2,
and ADR3. If one wishes to keep symbolic addresses, it will be
necessary to use so-called "pseudo-instructions” which specify the
value of these symbolic addresses so th a t the assem bly program
may, during translation, su b stitute the actual physical addresses.
Such pseudo-instructions would be, for example:
ADR1 = $100
ADR2 = $120
ADR3 = $200

Exercise 3.1: Now close this book. Refer only to the list o f instruc­
tions at the end o f the book. Write a program which will add two
numbers stored at memory locations LOCI and LOC2. Deposit the
results at memory location LOC3. Then, compare your program to
the one above.

16-Bit A ddition

A n 8-bit addition will only allow the addition of 8-bit numbers, i.e.,
numbers between 0 and 255, if absolute binary is used. For m ost prac­
tical applications it is necessary to use multiplepredsion and to add
num bers having 16 b its or more. We will present here exam ples of
arithm etic on 16-bit num bers. They can be readily extended to 24,
32 bits,or more. (One always uses multiples of 8 bits.) We will assume
th a t the first operand is stored a t m emory locations ADR1 and
ADR1 —1. Since OP1 is a 16-bit number this time, it will require two
8-bit memory locations. Similarly, OP2 will be stored at ADR2 and
A D R 2 - 1. The result is to be deposited at memory addresses ADR3
and ADR3 - 1 . This is illustrated in Figure 3-5.
 The logic of th is program is exactly analogous to the previous
one. F irst, the lower h a lf of the two operands will be added, since
the microprocessor can only add on 8 bits a t a tim e. Any carry
generated by the addition of these low order bytes will be au ­
tom atically stored in the in tern al carry bit ("C”). Then, the high
order h a lf of the two operands will be added together along w ith
any carry, and the resu lt will be saved in the memory. The pro­
gram appears below:
CLC
CLD
LDA ADR1 LOW HALF OF OP1
ADC ADR2 (OP1 + OP2) LOW
STA ADR3 SAVE LOW HALF OF RES
LDA ADR1-1 HIGH HALF OF OP1
ADC ADR2-1 (OP1 + OP2) HIGH + CARRY
STA ADR3-1 SAVE HIGH HALF OF RES

The first two instructions of this program are used to be safe: CLC,
CLD. Their roles have been explained in the previous section. Let us
examine the program. The next three instructions are essentially iden­
tical to the ones for the 8-bit addition. They result in adding the least
significant half (bits 0 through 7) of OP1 and OP2. The sum, called
RES, is stored a t mem ory location ADR3.
Automatically, whenever an addition is performed, any resu lt­
ing carry is saved in the carry b it of the flags register (register P).
If the two 8-bit num bers do not generate any carry, the value of
th e carry bit will be zero. If the two num bers do generate a carry,
th en th e C bit will be equal to 1.
The next th ree instructions of the program are also essentially
identical to the previous 8-bit addition program . They add to­
gether the m ost significant h a lf (bits 8 through 15) of OP1 and
OP2, plus any carry, and store the results a t address ADR3-1.
A fter this program has been executed, th e 16-bit result is stored
a t memory locations ADR3 and ADR3-1.
It is assum ed here th a t no carry will resu lt from th is 16-bit
addition. It is assum ed th a t th e resu lt is, indeed, a 16-bit number.
If the program m er suspects for any reason th a t the result m ight
have 17 bits, th en additional instructions should be inserted th a t
would te st the carry b it after this addition.
The location of the operands in the memory is illustrated in Fig­
ure 3-5.
Note that we have assumed here that the high part of the operand
is stored “ on top of” the lower part, i.e., at the lower memory ad­
dress. This need not necessarily be the case. In fact, addresses
are stored by th e 6502 in the reverse m anner: th e low p a rt is first
saved in the memory, and the high p a rt is saved in the next
memory location. In order to use a common convention for both
addresses and data, it is recommended th a t d ata also be kept w ith
the low part on top of the high part. This is illustrated in Figure
3-6A.

Fig. 3-6A: Storing Operands in Reverse Order

Exercise 3.2: Rewrite the 16-bit addition program above with the mem­
ory layout indicated in Figure 3-6A.
Exercise 3.3: Assume now that ADR1 does not point to thelowerhalf o f
OPR1 (see Figure 3-6A), but points to the higher part ofO PR l. This is
illustrated in Figure 3-6B. Again, write the corresponding program.
 Fig. 3-6B: Pointing to the High Byte

It is the programmer, i.e., you, who m ust decide how to store 16-bit
num bers (low p a rt or high p a rt first) and also whether your address
references point to the lower or to the higher half of such num bers.
This is the first of m any choices which you will learn to m ake when
designing algorithm s or d a ta structures.
We have now learned to perform a binary addition. Let us tu rn
to the subtraction.

S ubtracting 16-Bit N um bers

Doing an 8-bit subtract would be too simple. Let us keep it as an ex­
ercise and directly perform a 16-bit subtract. A s usual, our two
numbers, OPR1 and OPR2, are stored a t addresses ADR1 and ADR2.
The memory layout will be assumed to be that of Figure 3-6A. In order
to subtract, we will use a subtact operation (SBC) instead of an add
operation (ADC). The only other change, when com paring it to the
addition, is th at we will use an SEC instruction a t the beginning of the
program instead of a CLC. SEC m eans “ set carry to 1.” This in­
dicates a “no-borrow” condition. The rest of the p r o g r a m is identical
to the one for addition. The program appears below:

CLD
SEC SET CARRY TO 1
LDA ADR1 (OPR1) L INTO A
SBC ADR2 (OPR1) L -(OPR2)L
STA ADR3 STORE (RESULT)L
LDA ADR1 + 1 (OPR1) H INTO A
SBC ADR2 + 1 (OPR1) H -(OPR2)H
STA ADR3 + 1 STORE (RESULT)H

Exercise 3.4: Write the subtraction program fo r 8-bit operands.

It must be remembered that in the case of two’s complement

arithm etic, the final value of the carry flag has no m eaning. If an
overflow condition has occurred as a resu lt of the subtraction,
th en th e overflow b it (bit V) of the flags register will have been
set. It can th en be tested.
The exam ples ju s t presented are simple binary additions. How­
ever, another type of addition may be necessary; it is the BCD
addition.

BCD Arithmetic
8-B it BC D A d d itio n
The concept of BCD arithmetic has been presented in Chapter 1.
It is used essentially for business applications w here it is im pera­
tive to re ta in every significant digit in a result. In the BCD nota­
tion, a 4-bit nibble is used to store one decimal digit (0 through 9).
As a result, every 8-bit byte m ay store two BCD digits. (This is
called packed BCD.) L et us now add two bytes containing two
BCD digits each.
In order to identify the problems, let us try some num eric
examples first.
Let us add "01” and "02”:
"01” is represented by 0000 0001.
 "02” is represented by 0000 0010.
The resu lt is 0000 0011.
This is the BCD representation for "03”. (If you feel unsure of the
BCD equivalent, refer to th e conversion table a t the end of the
book.) Everything worked very simply in this case. Let us now try
another example.
“ 08” is represented by 0000 1000.
“ 03” is represented by 0000 0011.

E x e rc is e 3.5: Compute the sum o f the two numbers above in the

BCD representation. What do you obtain? (answer follows)

If you obtain 0000 1011, you have computed the binary sum of
"8” and "3”. You have indeed obtained "11” in binary. U nfortu­
nately, "1011” is an illegal code in BCD. You should obtain the
BCD representation of "11”, i.e., "0001 0001”!
The problem stem s from the fact th a t the BCD representation
uses only the first ten com binations of 4 digits in order to encode
th e decim al symbols "0” through "9”. The rem aining six possible
com binations of 4 digits are unused, and illegal "1011” is one such
combination. In other words, w henever th e sum of two binary
digits is g reater th a n "9”, th e n one m ust add "6” to the resu lt in
order to skip over th e unused 6 codes. Add the binary representa­
tion for "6” to "1011”:
1011 (illegal binary result)
+ 0110 (+ 6 )

The resu lt is: 0001 0001.

This is, indeed, “ 11” in the BCD notation! We now have the
correct result.
This example illustrates one of the basic difficulties of the BCD
mode. One must compensate for the six missing codes. On most
microprocessors, a special instruction, called “ decimal adjust,”
m u st be used to a d ju st the result of the binary addition (add 6 if
result g reater th an 9). In the case of the 6502, th e ADC instruc­
tion does it autom atically. This is a clear advantage of the 6502
w hen doing BCD arithm etic.
The next problem is illu strated by the same example. In our
example, the carry will be generated from the lower BCD digit
(the right-m ost one) into the left-m ost one. This in tern al carry
m ust be tak en into account and added to the second BCD digit.
The addition instruction for the 6502 tak es care of th is autom ati­
cally. However, it is often convenient to detect th is in te rn al carry
from b it 3 to bit 4 (the "half-carry”). No flag is provided in the
6502.
Finally, just as in the case of the binary addition, the usual
SED and CLC instructions m ust be used prior to executing th e
BCD addition proper. As a n example, a program to add the BCD
num bers "11” and "22” appears below:
CLC CLEAR CARRY
SED SET DECIMAL MODE
LDA #$11 LITERAL BCD "11”
ADC #$22 LITERAL BCD “ 22”
STA ADR
In th is program , we are using two new symbols: " # ” and "$”.
The " # ” symbol denotes th a t a "literal” (or constant) follows. The
"$” sign w ithin the operand field of the instruction specifies th a t

MEMORY

LDA

1
1 1

ADC

2 1 2
1

1 ADR _
(RESULT)

Fig. 3-7: Storing BCD Digits

the d a ta which follows is expressed in hexadecim al notation. The
hexadecim al and the BCD representations for digits "0” through
”9” are identical. H ere we wish to add the literals (or constants)
"11” and "22”. The resu lt is stored a t the address ADR. W hen the
operand is specified as p a rt of the instruction, as it is in the above
example, th is is called immediate addressing. (The various ad­
dressing modes will be discussed in detail in C hapter 5.) Storing
the resu lt a t a specified address, such as STA ADR, is called abso­
lute addressing when ADR represents a regular 16-bit address.
E xercise 3.6: Could we move the CLC instruction in the program
below the instruction L D A ?

BC D Subtraction

BCD subtraction appears to be complex. In order to perform a

BCD subtraction, one m u st add th e 10's complement of th e num ­
ber, ju s t like one adds the 2’s com plem ent of a num ber to perform
a binary subtract. The 10’s com plem ent is obtained by com put­
ing th e com plem ent to 9, then adding 1. This typically requires
th ree to four operations on a sta n d a rd microprocessor. However,
the 6502 is equipped w ith a special BCD subtraction instruction
which perform s th is in a single instruction! N aturally, and ju s t as
in th e binary example, the program will be preceded by the in­
structions SED , which sets the decim al mode, unless it has been
previously set, and SEC, which sets the carry to 1. Thus, th e pro­
gram to su b tra c t BCD “ 25” from BCD “ 26” is the following:

SED SET DECIMAL MODE

SEC SET CARRY
LDA #$26 LOAD BCD 26
SBC #$25 MINUS BCD 25
STA ADR STORE RESULT

16-Bit BCD A ddition

16-bit addition is perform ed ju s t as sim ply as in the binary

case. The program for such an addition appears below:
CLC
SED
LDA ADR1
ADC ADR2
STA ADR3
LDA ADR1-1
ADC ADR2-1
STA ADR3-1

E x e rc is e 3.7: Compare the program above to the one for the 16-bit
binary addition. What is the difference?

E x e rc is e 3.8: Write the subtraction program for a 16-bit BCD. (Do

not use CLC and ADC!)

BCD F la g s
In BCD mode, the carry flag during an addition indicates the
fact that the result is larger than 99. This is not like the two’s
complement situation, since BCD digits are represented in true
binary. Conversely, th e absence of the carry flag during a subtrac­
tion indicates a borrow.

Programming Hints fo r Add and Subtract

—Always clear the carry flag before perform ing an addition.
—Always set th e carry flag to 1 before perform ing a subtrac­
tion.
—Set th e appropriate mode: binary or decimal.

Instruction Types
We have now used three types of microprocessor instructions.
We have used LDA and STA, which respectively load th e ac­
cumulator from the memory address and store its contents at the
specified address. These two instructions are data transfer in­
structions.
Next, we have used arithmetic instructions, such as ADC and
SBC. They perform respectively an addition and a subtraction
operation. More ALU instructions will be introduced in th is chap­
te r soon.
Finally, we have used instructions such as CLC, SEC and others,
which manipulate the flag bits (respectively the carry and the de­
cimal bits in our examples). They are status manipulation or con­
trol instructions. A comprehensive description of the 6502 instruc­
tions will be presented in Chapter 4.
Still other types of instructions are available within the micro­
processor which we have not yet used. They are in particular
th e "branch” and "jump” instructions, which will modify the order
in which the program is being executed. This new type of instruc­
tion will be introduced in our next example.

M ultiplication
Let us now exam ine a more complex arithm etic problem: the
multiplication of binary numbers. In order to introduce the al­
gorithm for a binary m ultiplication, let us s ta rt by exam ining a
usual decim al m ultiplication: We will m ultiply 12 by 23.
12 (M ultiplicand) (MPD)
x23 (M ultiplier) (MPR)

36 (P artial Product) (PP)

+ 24

=276 (Final Result) (RES)

The multiplication is performed by multiplying the right-most digit
of the multiplier by the multiplicand, i.e., “ 3” x “ 12” . The partial
product is “ 36.” Then one multiplies the next digit of the multi­
plier, i.e., “ 2,” by “ 12.” “ 24” is then added to the partial pro­
duct.
B ut th ere is one m ore operation: 24 is offset to the left by one
position. We will say th a t 24 is being shifted left by one position.
Equivalently, we could have said th a t the p artial product (36) had
been shifted one position to the right before adding.
The two num bers, correctly shifted, are then added and the sum
is 276. This is simple. Let us now look at the binary multiplica­
tion. The binary m ultiplication is performed in exactly the same
way.
Let us look a t an example. We will m ultiply 5 x 3 :
(5) 101 (MPD)
(3) x O ll (MPR)
101 (PP)
101
000
(15) 01111 (RES)
 In order to perform the multiplication, we operate exactly as
we did above. The formal representation of this algorithm ap­
pears in Figure 3-8. It is a flowchart for the algorithm, our first
flowchart. Let us examine it more closely.

DONE

Fig. 3-8: The Basic Multiplication Algorithm: Flowchart

This flow-chart is a symbolic representation of the algorithm we

have ju s t presented. Every rectangle represents an order to be
carried out. It will be tra n sla ted into one or m ore program in ­
structions. Every diam ond-shaped symbol represents a test being
performed. This will be a branching point in the program . If the
te st succeeds, we will branch to a specified location. If th e test
does not succeed, we will branch to another location. The concept
of branching will be explained late r in the program itself. The
reader should now examine th is flow-chart and ascertain th a t it
does indeed represent the algorithm exactly. N ote th a t there is an
arrow coming out of the la st diam ond a t the bottom of the flow­
chart, back to the first diam ond on top. This is because th e same
portion of the flow-chart will be executed eight tim es, once for
 every b it of th e m ultiplier. Such a situation where execution will
re s ta rt a t the same point is called a program loop, for obvious
reasons.

E x e rc is e 3.9: Multiply "4” by "7” in binary using the flow chart,

and verify that you obtain "28.”I f you do not, try again. It is only If
you obtain the correct result that you are ready to translate this flow
chart into a program.
L et us now tra n sla te th is flow-chart into a program for the
6502. The complete program appears in Figure 3.9. We are now go­
ing to study it in detail. As you will recall from Chapter 1, pro­
gramming consists here of translating the flowchart of Figure
3-8 into the program of Figure 3-9. Each of the boxes in th e flow­
c h art will be tra n sla ted by one or more instructions.
I t is assum ed th a t M PR and M PD already have a value.

LDA ZERO ACCUMULATOR

STA TMP CLEAR TH IS A DDRESS
STA RESAD CLEAR
STA RESAD+1 CLEAR
LDX m X IS COUNTER
MULT LSR MPRAD SH IFT MPR RIGHT
BCC NO A D D TEST CARRY BIT
LDA RESAD LOAD A WITH LOW RES
CLC PREPARE TO ADD
ADC M PDAD A D D MPD TO RES
STA RESAD SAVE RESULT
LDA R E S A D +1 A D D REST OF SH IFTED MPD
ADC TMP
STA RESAD+1
NOADD ASL M PDAD SH IFT MPD LEFT
ROL TMP SAVE B IT FROM MPD
DEX DECREM ENT COUNTER
BNE MULT DO IT AG A IN IF COUNTER #0

Fig. 3-9:8x8 Multiply

The first box of the flow-chart is an initialization box. It is neces­

sary to set a num ber of registers or memory locations to "0,” as
this program will require th e ir use. The registers which will be
used by the multiplication program appear in Figure 3-10. On the
left of the illustration appears th e relevant portion of th e 6502
microprocessor. On the rig h t of the illustration appears the rele-
v an t section of th e memory. We will assum e here th a t m em ory
addresses increase from th e top to th e bottom of th e illustration.
N aturally, the reverse convention could be used. The X reg ister on
the far left (one of the two index registers of th e 6502) will be used
as a counter. Since we are doing an 8-bit m ultiplication, we will
have to te s t 8 b its of the m ultiplier. U nfortunately, there is no in­
struction in th e 6502 which allows u s to te s t those b its in se­
quence. The only b its th a t can conveniently be tested are the
flags in the s ta tu s register. A s a resu lt of this lim itation of m ost
m icroprocessors, in order to te s t successively all the b its of the
m ultiplier, it will be necessary to transfer the m ultiplier value
into th e accum ulator. Then, the co n ten ts of the accum ulator will
be shifted right. A shift in struction m oves every b it in th e regis­
te r by one position to the rig h t or to th e left. The b it which falls
off the register drops into th e carry b it of the s ta tu s register. The
effect of a shift operation is illu strated in Figure 3-11. There are
m any variations possible depending upon the b it th a t comes into
th e register, b u t these differences will be discussed in C hapter 4
(6502 instruction set).

(MEMOSVI

Fig. 3-10: Multiplication: The Registers

Let us go back to the successive testing of each of the 8 bits of

the multiplier. Since one can easily test the carry bit, the multi­
plier will be shifted by one position 8 times. Every time its right­
most bit will fall into the carry bit, where it will be tested.
The next problem to be solved is that the partial product which
is accumulated during the successive additions will require
16 bits. Multiplying two 8-bit numbers may yield a 16-bit re­
 suit. This is because 28x 2 8= 2 16. We need to reserve 16 bits for th is
result. Unfortunately, the 6502 has very few internal registers, so
th a t th is p artial product cannot be stored w ithin th e 6502 itself.
In fact, because of the lim ited num ber of registers, we are unable
to store the m ultiplier, the m ultiplicand, or the p a rtial product
w ithin the 6502. They will all be stored in the memory. This will
resu lt in a slower execution th a n if it were possible to store them
all in internal registers. This is a limitation inherent in the 6502.
The mem ory a re a used for the m ultiplication appears on th e rig h t
of F igure 3-10. On top one can see the memory word allocated for
th e m ultiplier. We will assum e, for example, th a t it contains "3” in
binary. The address of th is mem ory location is MPRAD. Below it,
we find a "tem porary” whose address is TMP. The role of th is
location will be clarified below. We will shift the m ultiplicand left
into th is location prior to adding it to the p a rtia l product. The
m ultiplicand is next and will be assum ed to contain the value "5”
in binary. Its address is MPDAD.
Finally, a t th e bottom of th e memory, we find the two words
allocated for th e p artial product or the result. T heir address is
RESAD.

SHIFT LEFT
- r\ r \ r\ r r\ r \

CA R RY

ROTATE LEFT
r \r \
CA R RY 1

---------------------------------------------------- □ — :-------------------------------------------

Fig. 3-11: Shift and Rotate

 These memory locations will be our "working registers ” and
the word "register” m ay be used interchangeably w ith "location”
in th is context.
The arrow which appears on the top rig h t of th e illu stratio n
coming out of M PR into b it C is a symbolic way of showing how
the m ultiplier will be shifted in the carry bit. N aturally, th is carry
b it is physically contained w ithin the 6502 and not w ithin th e
memory.
L et us now go back to the program of Figure 3-9. The first five
instructions are initialization instructions:
The first four instructions will clear the contents of "registers”
TMP, RESAD, and RESAD+1. Let us verify this.
LDA # 0
This instruction loads the accumulator with the literal value “ 0.”
As a result of this instruction, the accumulator will contain
“ 00000000 . ”
The contents of the accumulator will now be used to clear the
th ree "registers” in the memory. It m ust be rem em bered th a t
reading a value out of a reg ister does not em pty it. I t is possible to
read as m any tim es as necessary out of a register. Its contents are
not changed by the read operation. Let us proceed:
STA TMP
This instruction stores th e contents of the accum ulator in m em ­
ory location TMP. Refer to Figure 3-10 to understand the flow of
d a ta in the system . The accum ulator contains "00000000.” The
resu lt of th is instruction will be to w rite all zeroes in m em ory
location TMP. Rem em ber th a t the contents of th e accum ulator
remain 0 after a read operation on the accumulator. It is unchanged.
We are going to use it again.
STA RESAD
This instruction operates ju s t like th e one before and clears the
contents of address RESAD. Let us do it one m ore time:
STA RESAD+1
We finally clear memory location RESAD+1 w hich has been re ­
served to store the high p a rt of the result. (The high h a lf is bits
8-15; th e low p a rt is b its 0-7.)
Finally, in order to able to stop shifting the multiplier bits
a t th e rig h t tim e, it is necessary to count the num ber of shifts th a t
have to be performed. E ig h t shifts are necessary. R egister X will
be used as a counter and initialized to th e value "8.” Every tim e
th a t the shift will have been performed, th e contents of th is
counter will be decrem ented by 1. W henever the value of th is
counter reaches "0,” th e m ultiplication is finished. Let us ini­
tialize th is reg ister to "8”:
LDX # 8
This instruction loads the literal "8” into register X.
R eferring back to the flow c h art of F igure 3-8, we m ust te s t the
least significant b it of th e m ultiplier. I t has been indicated above
that this test cannot be performed in a single instruction. Two instruc­
tions must be used. First the multiplier will be shifted right, then the
bit which fell out of it will be tested. It is the carry bit. Let us perform
these operations:
LSR MPRAD
This instruction is a "Logical Shift Right” of the contents of
memory location MPRAD.

Exercise 3.10: A ssum ing that the multiplier in our example is

“5, ” which bit falls o ff the right end o f memory location M PRAD ?
(In other words, which will be the value o f the carry after this
shift?)
The next instruction tests th e value of the carry bit:
BCC NOADD
This instruction m eans "B ranch if C arry C lear” (i.e. equals zero)
to th e address NOADD.
This is th e first tim e we encounter a branch instruction. All th e
program s we have considered so far have been strictly sequential.
Each instruction w as executed after th e previous one. In order to
be able to use logical tests such as testin g the carry bit, one m ust
be able to execute instructions anyw here in the program after th e
test. The branch instruction perform s ju s t such a function. I t will
te st th e value of th e carry bit. If the carry was "0,” i.e., if it was
cleared, th en th e program will branch to address NOADD. This
m eans th a t the n ext instruction executed after the BCC will be
th e instruction a t address NOADD if th e test succeeds.
 Otherw ise, if the te st fails, no branch will occur and th e in­
struction following BCC NOADD will be norm ally executed.
One more explanation is in order about NOADD: th is is a sym­
bolic label. I t represents an actual physical address w ithin th e
memory. For the convenience of the program mer, the assem bler
program allows using symbolic nam es instead of actual addres­
ses. D uring the assem bly process, the assem bler will substitute
the real physical address instead of the symbol "NOADD.” This
improves th e readability of the program substantially and also
allows the program m er to in se rt additional instructions betw een
the branch point and NOADD, w ithout having to rew rite every­
thing. These merits will be studied in more detail in Chaper 10 on
th e assembler.
If the test fails, th e next sequential instruction in th e program
is executed. We will now study both alternatives:
Alternative 1: the carry was "1”
If the carry was 1, the test specified by BCC has failed and the next
instruction after BCC is executed.
LDA RESAD
Alternative 2: the carry was "0”
The te st succeeds, and the next instruction is th e one a t label
"NOADD.”
R eferring to F igure 3-8, th e flow-chart specifies th a t if th e carry
bit was 1, the m ultiplicand m ust be added to the p artial product
(here, the RES registers). Also, a shift m ust be performed. The
p artial product m ust be moved by one position to th e rig h t or else
the m ultiplicand m ust be moved by one position to the left. We
will adopt here the usual convention in perform ing m ultiplica­
tions by hand, and we will move the m ultiplicand by one position
to the left.
The m ultiplicand is contained in registers TM P and MPDAD.
(To simplify, we call mem ory locations "registers,” a usual term .)
The 16 bits of the p a rtia lrproduct are contained in mem ory ad­
dresses RESAD and RESAD +1.
In order to illu strate this, let us assum e th a t th e m ultiplicand
was “ 5.” The various registers appear in Figure 3-10.
We simply have to add two 16-bit numbers. This is a problem
that we have learned to solve. (If you have any doubts, refer to
the section on 16-bit addition above.) We are going to add the low-
 order bytes first, and th en the high-order bytes. Let us proceed:
LDA RESAD
The accum ulator is loaded w ith the low p a rt of RES.
CLC
P rior to any addition, the 6502 requires th a t th e carry b it be
cleared. It is im portant to do so here as we know th a t the carry bit
had been set to 1. It m ust be cleared.
ADC MPDAD
The m ultiplicand is added to th e accumulator, which contains
(RES)LOW
STA RESAD

The resu lt of th e addition is saved a t the appropriate m emory

location, (RES)LOW The second h a lf of the addition is th en per­
formed. W hen checking execution of th is program la te r by b a n d ,
do not forget th a t the addition will set the carry bit. The carry will
be set to either "0” or "1” depending on th e results of the addition.
Any carry that might have been generated will automatically be
carried forward into the high-order part of the result.
Let us now finish the addition:
LDA RESAD+1
ADC TMP
STA RESAD+1
These th ree instructions complete our 16-bit add. We have now
added the m ultiplicand to RES. We still have to shift it by one
position to the left in anticipation of the next addition. We could
also have considered shifting the multiplicand by one position
to the left before adding, except for the first time. This is one of many
programming options which are always open to the programmer.
Let us shift the m ultiplicand to the left:
NOADD ASL MPDAD
This instruction is an "Arithmetic Shift Left.” It will shift by one
position to the left th e contents of memory location MPDAD
which happens to contain the low part of the multiplicand. This is
not enough. We cannot afford to lose th e b it which falls off the left
end of the m ultiplicand. This b it will fall into the carry bit. It
should not be stored there perm anently since it can be destroyed
by any arithm etic operation. This bit should be saved in a
"perm anent” register. It should be shifted into mem ory location
TMP. This is precisely accomplished by the next instruction:
ROL TMP
This specifies: "Rotate Left” the contents of TMP.
One interesting observation can be m ade here. We ju s t used two
different kinds of shift instructions to shift a register by one posi­
tion to the left. The first one is ASL. The second one is ROL.
What is the difference?
The ASL instruction shifts the contents of th e register. The
ROL instruction is a rotate instruction. It does shift the contents
of the register by one position to the left, and the b it falling off the
left end goes into the carry bit, as usual. The difference is th a t the
previous contents o f the carry bit are forced into the right-most posi­
tion. This is called a circular rotation in m athem atics (a 9-bit
rotation). This is exactly w hat we w ant. As a resu lt of th e ROL,
the bit which had been shifted out of MPDAD on the left and pre­
served in the carry bit C will land in the right-most position of
register TMP. It works.
We are now finished with the arithmetic portion of this pro­
gram. We still have to test whether we have performed the opera­
tion eight times, i.e., whether we are finished. As usual in most
microprocessors, this test will require two instructions:
DEX
This instruction decrem ents the contents of register X. If it con­
tained 8, its contents w ill be 7 after execution of th is instruction.
BNE MULT
This is another test-and-branch instruction. It specifies "branch if
resu lt is not equal to 0 to location MULT.” As long as our counter­
register decrem ents to a non-zero integer, th ere will be a n au ­
tom atic branch back to label MULT. This is called the m ultiplica­
tion loop. Referring back to the multiplication flow-chart, this corre-
ponds to the arrow coming out of th e la st box. This loop will be
executed 8 tim es.

Fvprrigp 3.J.1; What happens when X decrements to 0? What is

the next instruction to be executed?

In m ost cases, the program th a t we ju st developed will be a

subroutine and the final instruction in the subroutine will be
RTS. The subroutine m echanism will be explained late r in th is
chapter.

IM PO R T A N T SELF-TEST

If you wish to learn how to program, it is extremely important

that you understand such a typical program in complete detail.
We have introduced many new instructions. The algorithm is rea­
sonably simple, but the program is much longer than the previous
programs that we have developed so far. It is very strongly sug­
gested that you do the following exercise completely and correctly
before you proceed in this chapter. If you do it correctly, you will
have really understood the mechanism by which instructions
manipulate the contents of memory and of the microprocessor
registers and how the carry flag is being used. If you do not, it is
likely that you will experience difficulties in writing programs
yourself. Learning to program does involve actually programming.
Please pause to take a piece of paper and do the following exer­
cise.

E x e rc is e 3.12: Every time that a program is written, one should

verify it by hand, in order to ascertain that its results will be correct.
We are going to do ju st that: the purpose of this exercise is to fill in
the table of Figure 3-12.
You can w rite directly on it or else m ake a copy of it. The
purpose is to determ ine th e contents of every relevant register
and memory location in the system after each instruction is exe­
cuted by this program , from beginning to end. You will find hori­
zontally on F igure 3-12 all the register locations used by the
program: X, A, MPR, C (the carry bit flag), TMP, MPD, RESADL,
RESADH. On the left part of the illustration you must fill in the
label, if applicable, and the instruction being executed. At the
rig h t of th e illustration you m u st w rite the contents of every reg­
iste r after execution of th a t instruction. W henever the contents
of a register are indefinite, we will use dashes. L et us s ta rt filling
Fig. 3-12: Form To Be Filled Out For Exercise 3-12
 in this table together. You will have to fill in the remainder alone.
The first line appears below:

LABEl INSTRUCTION
IDA «0

fig. 3-13: first Instruction of Multiplication

The first instruction to be executed is LDA # 0 .

A fter execution of th is instruction, th e contents of reg ister X
are unknown. This is indicated by dashes. The contents of th e
accum ulator are all zeroes. We also assum e th a t the m ultiplier
and th e m ultiplicand had been loaded by the program m er prior to
execution of th is program . (Otherwise, additional instructions
would be needed to set th e contents of MPR and MPD.) We find in
M PR the binary value for "3.” We find in MPD the binary value
for "5.” The carry bit is undefined. R egister TM P is undefined.
And both registers used for RESAD are undefined. Let us now fill
the next line. It appears below; the only difference is that the con­
tents of register TMP have been set to “ 0.” The next instruction
will set the contents of RESAD to “ 0” and the one after will set
the contents of RESAD +1 to "0.”

IABK INSTRUCTION MPR MPD

IDA f0 00000011 00000101
STA TEMP

Fig. 3-14: First Two Lines of Multiplication

The fifth instruction, #8, will set the contents of X to “ 8.” Let
us do one more instruction set (see Figure 3-15).
The LSR MPRAD instruction will shift the contents of MPRAD
rig h t by one position. You can see th a t after the shift the contents
of MPR are “ 0000 0001.” The right-most “ 1” of MPR has fallen
 Fig. 3-15: Partially Com pleted Form For Exercise 3-12

into th e carry bit. B it C is now set to 1. O ther registers are u n ­

changed.
It is now your tu rn . Please fill in th e rest of th is table com­
pletely. I t is not difficult, b u t it does require attention. If you have
doubts about the role of some instructions, you m ay w ant to refer
to C hapter 4 w here you will find each of them listed and de­
scribed, or else to the Appendix section of th is book where they
are listed in table form.
The final result of your multiplication should be “ 15” in binary
form, contained in registers RESAD low and high. RESAD high should
be set to “0000 0000.” RESAD low should be “0000 1111.” If you
obtained this result, you won. If you did not, try one more time.
The most frequent source of errors is a mishandling of the carry
bit. Make sure that the carry bit is changed every time you per­
form an arithm etic instruction. Do not forget th a t th e ALU will
set the carry b it after each addition operation.

Program m ing A ltern atives

The program that we have just developed is one of many
ways in which it could have been written. Every programmer can
find ways to modify and sometimes improve a program. For
example, we have shifted the multiplicand left before adding. It
would have been mathematically equivalent to shift the result by
one position to the right before adding it to the multiplicand. The
advantage is that we would not have required register TMP, thus
saving one memory location. This would be a preferred method in
a microprocessor equipped with enough internal registers so that
MPR, MPD, and RESAD could be contained within the microproces­
sor. Since we were obliged to use the memory to perform these
operations, saving one memory location is not relevant. The ques­
tion is, therefore, whether the second method might result in a
somewhat faster multiplication. This is an interesting exercise:

Exercise 3.13: Now write an 8 x 8 multiply, using the same al­

gorithm, but shifting the result by one position to the right instead o f
shifting the multiplicand by one position to the left. Compare it to
the previous program and determine whether this different ap­
proach would be faster or slower than the preceding one.
One m ore problem m ay come up: In order to determ ine the
speed of the program , you m ay w an t to refer to the tables in the
A ppendix section which list the num ber of cycles required by
each instruction. However, the num ber o f cydles required by
some instructions depends on where they are located. A special
addressing mode exists for the 6502 called the Direct Addressing
Zero Page Mode, where the first page (memory location 0 to 255)
is reserved for fa st execution. This will be explained in C hapter 5
on addressing techniques. Briefly, all program s th a t require a
fa st execution tim e will use variables located in page 0 so th a t in­
structions require only tw o bytes to address m em ory locations
(addressing 256 locations requires only one byte), whereas instruc­
tions located anywhere else in the m em ory will typically require
3-byte instructions. L et us defer th is analysis until after Chap­
te r 5.
A n Im proved M ultiplication Program

The program we have ju s t developed is a straightforw ard

tran slatio n of th e algorithm into code. However, effective pro­
gram m ing requires close atten tio n to detail so th a t the length of
the program can be reduced and so th a t its execution speed can be
improved. We are now going to present an improved im plem enta­
tion of the sam e algorithm .
One of the tasks which consume instructions and time is the
shifting of the resu lt and th e m ultiplier. A standard "trick” used
in th e m ultiply algorithm is based on the following observation:
every tim e th a t the m ultiplier is shifted by one b it position to the
right, a b it position becomes available on the left. S im ultane­
ously, we can observe th a t th e first resu lt (or p artial product) will
use, a t most, 9 bits. A fter the next m ultiply shift, the size of the
p artial product will be increased by one b it again. In other words,
we can ju s t reserve, initially, one mem ory location for the partial
product and th en use the b it positions which are being freed by
the m ultiplier as it is being shifted.
We are now going to shift the multiplier right. It will free one bit posi­
tion to the left. We are going to enter the right-most bit of the partial
product into this bit position that has been freed. Let us now consider the
program.
L et us now also consider the optim al use of registers. The inter­
nal registers of the 6502 appear in Fig. 3-16. X is best used as a
counter. We will use it to count the num ber of b its shifted. The
accum ulator is (unfortunately) the only internal register which
can be shifted. In order to im prove efficiency, we should store in
it either the m ultiplier or the result. •

0
ACCUMULATOR

INDEX REGISTERS

STACK POINTER

PROGRAM COUNTER

FLAGS

Which one should we put in the accumulator? The result must be

added to the multiplicand every time a 1 is shifted out. Since the
6502 also always adds something to the accumulator only, it is the
result which will reside in the accumulator.
The other num bers will have to reside in the memory (see Fig-
gure 3-17).
A and B will hold the result. A will hold the high part o f the
result, and B will hold the low part o f the result. A is the ac­
cum ulator, and B is a memory location, preferably in page 0. C
will hold the multiplier (a memory location). D holds the multipli-
 (4009) (MEMORY)

Fig. 3-17: Register Allocation (Improved Multiply)

cand (a memory location). The program appears below:

MULT LDA #0 INITIALIZE RESULT TO ZERO (HIGH)
STA B INITIALIZE RESULT (LOW)
LDX #8 X IS SHIFT COUNTER
LOOP LSR C SHIFT MPR
BCC NOADD
CLC CARRY WAS ONE. CLEAR IT
ADC D A = A + MPD
NOADD ROR A SHIFT RESULT
ROR B CATCH BIT INTO B
DEX DECREMENT COUNTER
BNE LOOP LAST SHIFT?
Rg. 3-18: Improved Multiply

L et us exam ine the program . Since A and B will hold the result,
they m ust be initialized to th e value 0. Let us do it:
MULT LDA # 0
STA B
We will th en use register X as a shift counter and initialize it to
th e value 8:
LDX # 8
We are now ready to e n te r th e m ain m ultiplication loop as
before. We will first shift th e m ultiplier, th en te st the carry b it
w hich holds the right-m ost b it of th e m ultiplier, which h as fallen
off. L et us do it:
LOOP LSR C
BCC NOADD
 Here we shift the multiplier right as before. This is equivalent
to the previous algorithm because the addition operation is said
to be communicative.
Two possibilities exist: if the carry was 0, we will branch to
NOADD. Let us assume that the carry was 1. We will proceed:

CLC
ADC D

Since the carry was 1, it m ust be cleared, and we then add the
m ultiplicand to the accum ulator. (The accum ulator holds ithe re­
sults, 0 so far.)
Let us now shift the p artial product:
NO ADD RORA
RORB

The p artial product in A is shifted rig h t by one bit. The rig h t­

most bit falls into the carry bit. The carry bit is captured and
rotated into register B, which holds the low p a rt of the result.
We simply have to test w hether we are finished:
DEX
BNE LOOP

If we now examine this new program , we see that it has been

written in about half the number o f instructions o f the previous
program . It will also execute much faster. This shows the value of
selecting the correct registers to contain the inform ation.
A straightforw ard design will result in a program th a t works. It
will not result in a program th a t is optimized. It is, therefore, of
significant im portance to use the available registers and m emory
locations in the best possible way. This example illu strates a r a ­
tional approach to register selection for m axim um efficiency.

Exercise 3.14: Compute the speed of a multiplication operation

using this last program. Assume that a branch will occur in fifty
percent o f the cases. Look up the number o f cycles required by every
instruction in the table at the end o f the book. Assume a clock rate
of one cycle = 1 microsecond.
B inary D ivision
The algorithm for binary division is analogous to the one which
has been used for multiplication. The divisor is successively
subtracted from the high order bits of the dividend. A fter each
subtraction, the resu lt is used instead of the in itial dividend. The
value of the quotient is sim ultaneously increased by 1 every tim e.
Eventually, the result of the subtraction is negative. This is called
an overdraw. One must then restore the partial result by adding
the divisor back to it. Naturally, the quotient must be simultane­
ously decremented by 1. Quotient and dividend are then shifted
by one bit position to the left and the algorithm is repeated.
The method just described is called the restoring method. A
variation of this method which yields an improved speed of execu­
tion is called non-restoring method.

END (REMAINDER IS IN LEFT (DIVIDEND))

Fig. 3-19:8 Bit Binary Division Flowchart

The 16-bit D ivision

The non-restoring division for a 16-bit dividend, and an 8-bit divisor

will now be described. The result will have 8 bits. The register and memory
location for this program are shown in Fig. 3-22. The dividend is con­
tained in the accumulator (high part) and in memory location 0, called B
here. The result is contained in Q (memory location 1). The divisor is
contained in D (memory location 2). The result will be contained in Q and
A (A will contain the remainder).
The program appears on Fig. 3-21, the corresponding flow chart is
shown in Fig. 3-20.

Exercise 3.15: Verify the correct operation o f this program by

performing the division by hand and exercising the program, as
you did in Exercise 3.12. Divide 33 by 3. The result naturally
should be 11, with a remainder ofO.

LO G IC A L O P E R A T IO N S

The other class of instructions th a t the ALU inside the micro­

processor can execute is the set of logical instructions. They in ­
clude: AND, OR and exclusive OR (EOR). In addition, one can also
include there the shift operations which have already been
utilized, and the comparison instruction, called CMP for the 6502.
The individual use of AND, ORA, EOR, will be described in Chap­
ter 4 on the 6502 instruction set. Let us now develop a brief
program which will check whether a given memory location
called LOC contains the value “ 0,” the value “ 1,” or something
else. The program appears below:

LDA LOC READ CHARACTER IN LOC

CMP #$0 0 COMPARE TO ZERO
BEQ ZERO IS IT A 0?
CMP #$01 1?
BEQ ONE
NONE FOUND

ZERO

ONE

The first instruction: LDA LOC reads the contents of memory

location LOC. This is the character we w ant to test.
CMP #$00
 OUT

Fig. 3-20: 16 by 8 Division Flowchart

 LINE * LOC CODE LINE

0002 0000 * = $0
0003 0000 B *= *+ 1
0004 0001 Q *= *+ 1
0005 0002 D *= *+ 1
0006 0003 * = $200
0007 0200 A0 08 DIV LDY # 8
0008 0202 38 SEC
0009 0203 E5 02 SBC D
0010 0205 08 LOOP PHP
0011 0206 26 01 ROLQ
0012 0208 06 00 ASLB
0013 020A 2A ROLA
0014 020B 28 PLP
0015 020C 9005 BCC ADD
0016 020E E5 02 SBC D
0017 0210 4C 1502 JMP NEXT
0018 0213 65 02 ADD ADC D
0019 0215 88 NEXT DEY
0020 0216 DO ED BNE LOOP
0021 0218 BO 03 BCS LAST
0022 021A 65 02 ADC D
0023 021C 18 CLC
0024 021D 26 01 LAST ROLQ
0025 021F 00 BRK
0026 0220 END

Fig. 3-21: Program

(A|
(B)

(A LSO REAAAINDER) --
IQ)

(D)

Fig. 3-22:16 by 8 Division Registers and Memory Map (non-restoring 8-bit result)
 This instruction compares the contents of the accumulator with
th e lite r a l hex ad ecim al v a lu e "00 ” (i.e., th e b it p a tte rn
“ 00000000” ). T his comparison instruction will set the Z b it in the
flags register, which will th en be tested by th e next instruction:
BEQ ZERO
The BEQ instruction specifies "branch if equal.” The branch
instruction will determ ine w hether the test succeeds by exam in­
ing th e Z bit. If set, the program will branch to ZERO. If the test
fails, th en the next sequential instruction will be executed:
CMP #$01
The process will be repeated ag ain st the new pattern. If the test
succeeds, th e next instruction will result in a branch to location
one. If it fails, the next sequential instruction will be executed.

Exercise 3.16: Write a program which will read the contents o f

memory location “24” and branch to the address called “STAR” if
there were a in memory location 24. The bit pattern fo r a in
assembly language notation is represented by “00101010”.

SUMMARY
We have now studied m ost of the im portant instructions of the
6502 by using them . We have transferred values betw een the
mem ory and the registers. We have performed arithm etic and
logical operations on such data. We have tested it, and depending
on the resu lts of these tests, we have executed various portions of
th e program . We have also introduced a stru ctu re called th e loop,
in the m ultiplication program . An im portant program m ing struc­
tu re will be introduced now: the subroutine.

SUBROUTINES
In concept, a subroutine is simply a block of instructions which
has been given a nam e by th e programmer. From a practical
standpoint, a subroutine m ust s ta rt w ith a special instruction
called the subroutine declaration, which identifies it as such for
the assembler. It is also term inated by another special instruction
called a return. Let us first illu strate the use of subroutines in the
program in order to dem onstrate its value. Then, we will exam ine
how it is actually im plem ented.
 MAIN PROGRAM

Fig. 3-23: Subroutine Calls

The use of a subroutine is illustrated in Figure 3-23. The main

program appears on the left of the illustration. The subroutine is
represented symbolically on the right. Let us exam ine the sub­
routine m echanism. The lines of the m ain program are executed
succesively until a new instruction, CALL SUB, is met. This
special instruction is the subroutine call and results in a transfer
to the subroutine. This m eans th a t the next instruction to be
executed after the CALL SUB is the first instruction w ithin the
subroutine. This is illu strated by arrow 1 in the illustration.
Then, the subprogram w ithin the subroutine executes ju st like
any other program . We will assum e th a t the subroutine does not
contain any other calls. The last instruction of th is subroutine is a
RETURN. This is a special instruction which will cause a return
to the m ain program . The next instruction to be executed after
the RETURN is the one following the CALL SUB. This is illus­
trated by arrow 3 in the illustration. Program execution con­
tinues th en as illu strated by arrow 4.
In the body of the m ain program a second CALL SUB appears.
A new tran sfer occurs, shown by arrow 5. This m eans th a t the
body of the subroutine is again executed following the CALL SUB
instruction.
Whenever the RETURN within the subroutine is encountered,
a return occurs to the instruction following the CALL SUB in
question. This is illustrated by arrow 7. Following the return to
the main program, program execution proceeds normally, as illus­
trated by arrow 8.
The role of the two special instructions CALL SUB and RE-
TURN should now be clear. What is the value of the subroutine?
The essential value of the subroutine is that it can be called
from any number of points in the main program and used re­
peatedly without rewriting it. A first advantage is that this ap­
proach saves memory space and there is no need to rewrite the
subroutine every time. A second advantage is that the pro­
grammer can design a specific subroutine only once and then use
it repeatedly. This is a significant simplification in program de­
sign.

Exercise 3.17: What is the main disadvantage o f a subroutine?

The disadvantage of the subroutine should be clear just from

examining the flow of execution between the main program and
the subroutine. A subroutine results in a slower execution, since
extra instructions must be executed: the CALL SUB and the RE­
TURN.

Im plem entation o f the Subroutine M echanism

We will examine here how the two special instructions, CALL
SUB and RETURN, are implemented internally within the processor.
The effect of the CALL SUB instruction is to cause the next instruct­
ion to be fetched at a new address. You will remember (or else read
Chapter 1 again) that the address of the next instruction to be ex­
ecuted in a computer is contained in the program counter (PC). This
means that the effect of the CALL SUB is to substitute new contents
in register PC. Its effect is to load the start address of the subrou­
tine in the program counter. Is that really enough?
l b answ er this question, let us consider the other instruction
which has to be im plem ented: the RETURN. The RETURN m ust
cause, as its nam e indicates, a re tu rn to the instruction th a t fol­
lows the CALL SUB. This is possible only if the address of this
instruction has been preserved somewhere. This address happens
to be the value of the program counter a t the tim e th a t the CALL
SUB was encountered. This is because the program counter is
automatically incremented every time it is used (read Chapter 1
again?). This is precisely the address that we want to preserve so
th a t we can later perform RETURN.
This address must be saved in a reasonable location where it is
guaranteed that it will not be erased. However, let us now consi­
der the following situation, illustrated by Figure 3-24: in this
example, subroutine 1 contains a call to SUB2. Our mechanism
should work in this case as well. Naturally, there might even be
more than two subroutines, say N “ nested” calls. Whenever a
new CALL is encountered, the mechanism must therefore store
the program counter again. This implies that we need at least 2N
memory locations for this mechanism. Additionally, we will need
to return from SUB2 first and SUB1 next. In other words, we need
a structure which can preserve the chronological order in which
data will have been saved.
The structure has a name. We have already introduced it. It is
the stack. Figure 3-26 shows the actual contents of the stack
during successive subroutine calls. Let us look at the main pro­
gram first. At address 100, the first call is encountered: CALL
SUB1. We will assume that, in this microprocessor, the subroutine
call uses 3 bytes. The next sequential address is therefore not

Fig. 3-24: Nested Calls

"101”, b u t “ 103.’’The CALL instruction uses addresses "100”,

“ 101” , and “ 102” . Because the control unit of the 6502 “ knows’ that it
is a 3-byte instruction, the value of th e program counter w hen the
call h as been completely decoded will be "103”. The effect of the
call will be to load the value "280” in th e program counter. "280”
is the sta rtin g address of SUB1.
The second effect of the CALL will be to push into the stack (to
preserve) the value "103” of the program counter. This is illus­
tra ted a t the bottom left of th e illu stratio n which shows th a t a t
time l, the value “ 103” is preserved in the stack. Let us move to
the right of the illustration. At location 300, a new call is encoun­
tered. Just as in the preceding case, the value “ 900” will be
loaded in the program counter. This is the starting address of
SUB2. Simultaneously, the value "303” will be pushed into the
stack. This is illu strated a t the bottom left of th e illustration
w here the en try a t tim e 2 is "303”. Execution will th en proceed
to the right of the illustration within SUB2.
We are now ready to demonstrate the effect of the RETURN
instruction and the correct operation of our stack m echanism .
Execution proceeds w ithin SUB2 u n til the RETU RN instruction
is encountered a t tim e 3. The effect of the RETURN instruction is
simply to pop the top of the stack into the program counter. In
other words, th e program counter is restored to its value prior to
th e en try into the subroutine. The top of the stack in our example
is “ 303.” Figure 3-26 shows that, at time 3, value “ 303” has been
removed from the stack and has been put back into the program
counter. As a result, instruction execution proceeds from address
“303.” At time 4, the RETURN of SUB1 is encountered. The value
on top of the stack is “ 103.” It is popped and is installed in the
program counter. As a result, the program execution will proceed
from location “ 103” on within the main program. This is, indeed,

A DD RESS (M A IN )

100:

103:

Fig. 3-25: The Subroutine Calls

the effect that we wanted. Figure 3-26 shows that at time 4 the
stack is again empty. The mechanism works.
 The subroutine call mechanism works up to the maximum di­
mension of the stack. This is why early microprocessors, which
had a 4 or 8-register stack, were essentially limited to 4 or 8 levels
of subroutine calls. In theory, the 6502, which is restricted to 256
memory locations for the stack (Page 1), can therefore accommo­
date up to 128 successive subroutine calls. This is true only if
there are no interrupts, if the stack is used for no other purpose,
and if no register needs be stored within the stack. In practice,
fewer subroutine levels will be used.
Note that, on illustrations 3-24 and 3-25, the subroutines
have been shown to the right of the main program. This is only for
the clarity of the diagram. In reality, the subroutines are typed by
the user as regular instructions of the program. On a sheet of

TIME (T ) TIME (? ) TIME (3 ) TIME @

103 103 103

303

Fig. 3-26: Stack vs. Time

paper, in a listing of the complete program, the subroutines may

be at the beginning of the text, in its middle, or at the end. This is
why they are preceded by a subroutine declaration: they must be
identified. The special instructions tell the assembler that what
follows should be tre a te d as a subroutine. Such assem bler di­
rectives will be presented in Chapter 10.

6502 Subroutines
We have now described th e subroutine m echanism , and how th e
stack is used to im plem ent it. The subroutine call instruction for
th e 6502 is called JS R (jump to subroutine). I t is, indeed, a 3-byte
instruction. U nfortunately, it is an unconditional jum p: it does not
te st bits. E xplicit branches m ust be inserted prior to a JS R if a
te s t need be performed.
The re tu rn from subroutine is th e RTS instruction (R eturn
from subroutine). I t is a 1-byte instruction.
 Exercise 3.18 ‘.Why is the return from a subroutine as long as the
CALL? (Hint: i f the answer is not obvious, look again at the stack
implementation o f the subroutine mechanism and analyze the
internal operations that must be performed.)

Subroutine E xam ples

Most of the programs that we have developed and are going to
develop would usually be written as subroutines. For example,
the multiplication program is likely to be used by many areas of
the program. In order to facilitate program development and
clarify it, it is therefore convenient to define a subroutine whose
name would be, for example, MULT. At the end of this subroutine
we would simply add the instruction, RTS.

Exercise 3.19: I f MULT is used as a subroutine, would it " damage”

any internal flags or registers?

R ecursion
Recursion is a word used to indicate th a t a subroutine is r a ilin g
itself. If you have understood the im plem entation m echanism ,
you should now be able to answ er the following question:

Exercise 3.20: Is it legal to let a subroutine call itself? (In other

words, will everything work even if a subroutine calls itself?) I f
you are not sure, draw the stack and fill it with the successive ad­
dresses. You will physically verify whether it works or not. This
will answer the question. Then, look a t the registers and memory
(see Exercise 3.19) and determine i f a problem exists.
Subroutine Param eters

W hen calling a subroutine, one norm ally expects th e sub­

routine to work on some data. For example, in the case of the
m ultiplication, one w ants to tra n sm it two num bers to th e sub­
routine which w ill perform th e m ultiplication. We saw in th e case
of th e m ultiplication routine th a t th is subroutine expected to find
the m ultiplier and the multiplicand in given memory locations.This
illu strates the first m ethod of passing param eters: through m em ­
ory. IWo other techniques are used, and p aram eters can be passed
in th ree ways:
1. Through registers
2. Through m emory
3. Through the stack
—Registers can be used to pass parameters. This is an advan­
tageous solution, provided that registers are available, since
one does not need to use a fixed memory location. The sub­
routine remains memory-independent. If a fixed memory loca­
tion is used, any other user of the subroutine must be very
careful that he uses the same convention and that the memory
location is indeed available (look at Exercise 3-20 above). This is
why, in many cases, a block of memory locations is reserved,
simply to pass parameters between various subroutines.
—Using memory has the advantage of greater flexibility (more data),
but results in poorer performance and also in tying up the sub­
routine to a given memory area.
—Depositing parameters in the stack has the same advantage as using
registers: it is memory-independent. The subroutine simply knows that
it is supposed to receive, say, two parameters which are stored on top
of the stack. Naturally, it has a disadvantage: it clutters the stack with
data and, therefore, reduces the number of possible levels of sub­
routine calls.
The choice is up to the programmer. In general, one wishes to
remain independent from actual memory locations as long as pos­
sible.
If registers are not available, the next best solution is usually
the stack. However, if a large quantity of information should be
passed to a subroutine, then this information will have to reside
in the memory. An elegant way around the problem of passing a
block of data is to simply transmit a pointer to the information. A
pointer is the address at the beginning of the block. A pointer can
be transmitted in a register (in the case of the 6502, this limits
the pointer to 8 bits), or else in the stack (two-stack locations can
be used to store a 16-bit address).
Finally, if neither of the two solutions is applicable, then an
agreement may be made with the subroutine that the data will be
at some fixed memory location (the “ mailbox” ).

Exercise 3.21: Which o f the three methods above is best fo r recur­

sion?
PROGRAMMING THE 6502

Subroutine Library
There is a strong advantage to structuring portions of a pro­
gram into identifiable subroutines: they can be debugged inde­
pendently and can have a mnemonic name. Provided that they
will be used in other areas of the program, they become shareable,
and one can thus build a library of useful subroutines. However,
there is no general panacea in computer programming. Using
subroutines systematically for any set of instructions that can be
grouped by function may also result in poor efficiency. The alert
programmer will have to weigh the advantages vs. the disadvan­
tages.

SUMMARY
This chapter h as presented th e w ay inform ation is m anipulated
inside the 6502 by instructions. Increasingly complex algorithm s
have been introduced, and tra n sla ted into program s. The m ain
types of instructions have been used.
Im portant stru ctu res such as loops, stacks and subroutines
have been defined.
You should now have acquired a basic understanding of pro­
gram m ing, and of the m ajor techniques used in standard applica­
tions. Let us study the instructions available.
THE 6502 INSTRUCTION SET
P A R T 1 - O V ER A LL D E SC R IPT IO N

IN TR O D U C TIO N
This chapter will first analyze the various classes of in stru c­
tions which should be available in a general purpose computer. It
will th e n analyze one by one all of the instructions available for
the 6502, and explain in detail th e ir purpose and the m anner in
which th ey affect flags, or can be used in conjunction w ith th e
various addressing modes. A detailed discussion of addressing
techniques will be presented in C hapter 5.

C L A SSE S O F IN ST R U C T IO N S
Instructions m ay be classified in m any ways, and th ere is no
standard. We will distinguish here five m ain categories of instruc­
tions:
1. d a ta transfers
2. d a ta processing
3. te st and branch
4. input/output
5. control
Let us now exam ine in tu rn each of these classes of in stru c­
tions.

D ata transfers
D ata tran sfer instructions will tran sfer 8-bit d a ta betw een two
registers, or between a register and memory, or between a register
and an input/output device. Specialized transfer instructions may
exist for registers which play a special role, for example, a push
and pull operation, for efficient stack implementation. They will
move a word of data between the top of the stack and the ac­
cumulator in a single instruction, while automatically updating the
stack-pointer register.

D ata P rocessin g
Data processing instructions fall into four general categories:
- arithm etic operations (such as plus/m inus)
- logical operations (such as AND, OR, exclusive OR)
- skew and shift operations (such as shift, rotate, swap)
- increment and decrement
It should be noted that for efficient data processing, it is desir­
able to have powerful arithmetic instructions, such as multiply and
divide. Unfortunately, this is not available on most microprocessors.
It is also desirable to have powerful shift and skew instructions, such
as shift n bits, or a nibble exchange, where the right half and the
left half of the byte are exchanged. These are also unavailable on
most microprocessors.

Before exam ining th e actual 6502 instructions, let us recall the

difference betw een a shift and a rotation. The shift will move the
contents of a register or a mem ory location by one bit-location to
the left or to the right. The bit falling out of the register will go
into th e carry bit. The b it coming in on the other side will be a "0.”
In the case of a rotation, the b it coming out still goes in the
carry. However, the bit coming in is th e previous value which was
in the carry bit. This corresponds to a 9-bit rotation. It would often
be desirable to have a true 8-bit rotation where the bit coming in
on one side is the one falling off on the other side. This is not us­
ually provided on microprocessors. Finally, when shifting a word
to the right, it is convenient to have one more type of shift called
a sign-extension or an “ arithmetic shift right” . When doing opera­
tions on two’s complement numbers, particularly when implement­
ing floating-point routines, it is often necessary to shift a negative
number to the right. When shifting a two’s complement number to
the right, the bit which must come in on the left side should be a 1
(the sign bit should get repeated as many times as needed by the suc-
 SHIFT LEFT
- r r r \ r\ r r\ r
CAR!RY

ROTA!fE LEFT
. r\ r \ r vr \ r r -
CARRY

Fig. 4-1: Shift and Rotate

cessive shifts). Unfortunately, this type of shift does not exist in the
6502. It exists in other microprocessors.

T est a n d B ra n c h

The test instructions will test all bits of the flags register of “ 0”
or “ 1,” or combinations. It is, therefore, desirable to have as many
flags as possible in this register. In addition, it is convenient to be
able to test for combinations of such bits with a single instruction.
Finally, it is desirable to be able to test any bit position in any
register, and to test the value of a register compared to the value of
any other register (greater than, less than, equal). Microprocessor
test instructions are usually limited to testing single bits of the
flags register.
The jump instructions that may be available generally fall into
three categories:
- the jump proper, which specifies a full 16-bit address,
- the branch, which often is restricted to an 8-bit displacem ent
field,
- the call, which is used with subroutines.
 It is convenient to have two- or even three-way branches, de­
pending, for example, on w hether the resu lt of a comparison is
"greater than,” "less than,” or "equal.” It is also convenient to
have skip operations, which will jum p forward or backw ards by a
few instructions. Finally, in m ost loops, there is usually a decre­
m ent or increm ent operation a t the end, followed by a te st and
branch. The a v ailab ility of a single-instruction increm ent/
decrem ent plus te st and branch is, therefore, a significant advan­
tage for efficient loop im plem entation. This is not available in
most microprocessors. Only simple branches, combined with sim­
ple tests, are available. This naturally complicates programming,
and reduces efficiency.

Input/O utput

Input/output instructions are specialized instructions for the

handling of input/output devices. In practice, nearly all micro­
processors use memory-mapped I/O . This means that input/output
devices are connected to the address-bus, just like memory chips,
and addressed as such. They appear to the program m er as m em ­
ory locations. All memory-type operations can th e n be applied to
desired devices. This has th e advantage of providing a wide v ari­
ety of instructions which can be applied. The disadvantage is th a t
memory-type operations norm ally require 3 bytes and are, th ere ­
fore, slow. For efficient input/output handling in such an envi­
ronm ent, it is desirable to have a short addressing m echanism
available so that I/O devices whose handling speed is crucial may
reside in page 0. However, if page 0 addressing is available, it is
usually used for RAM memory, and therefore prevents its effec­
tive use for input/output devices.

C ontrol Instructions
Control instructions supply synchronization signals and m ay
suspend or in te rru p t a program . They can also function as a break
or a sim ulated interrupt. (Interrupts will be described in C hapter
6 on Input/O utput Techniques.)

INSTRUCTIONS AVAILABLE ON THE 6502

D ata Transfer Instructions

The 6502 has a complete set of d a ta transfer instructions, ex­

cept for the loading of the stack pointer, which is restricted in
flexiblility. The contents of the accumulator may be exchanged
with a memory location with the instructions LDA (load) and
STA (store). The same applies to registers X and Y. These are,
respectively, instructions LDX LDY, and STX STY. There is no
direct loading for S. Inter-register transfers are naturally pro­
vided: the instructions are TAX (transfer A to X), TAY, TSX,
TXA, TXS, TYA. There is a slight asymmetry, since the stack
contents may be exchanged with X, but not with Y.
There is no 2-address memory to memory operation, such as “add
contents of LOCI and LOC2.”

Stack O perations
Two “ push” and “ pop” operations are available. They transfer
register A or the status register (P) to the top of the stack in the
memory while updating the stack pointer S. They are PHA and
PH P. The reverse instructions are PLA and PLP (pull A and pull
P), which transfer the top of the stack respectively into A or P.

D ata P rocessin g
Arithmetic
The usual (restricted) com plem ent of arithm etic, logical and
shift functions is available. A rithm etic operations are: ADC,
SBC. ADC is an addition w ith carry, and th ere is no addition
w ithout carry. This is a m inor nuisance as it requires a CLC
instruction prior to any addition. The subtraction is performed by
SBC.
A special decim al mode is available which allows the direct
addition and subtraction of num bers expressed in BCD. In m any
other microprocessors only one of these BCD instructions is av­
ailable as a separate instruction code. The presence of the decim al
flag m ultiplies by two th e effective num ber of arithm etic opera­
tions available.
Increment!Decrement
Increm ent and decrement operations are available on th e
memory, and on index registers X and Y, b u t not on the ac­
cumulator. They are respectively: INC and DEC, w hich operate on
the memory; INX, INY and DEX, DEY, which operate on index
registers X and Y.
Logical Operations
The logical operations are the classic ones: AND, ORA, EOR.
The role of each of these instructions will be clarified.

AND
E ach logical operation is characterized by a tru th table, which
expresses th e logical value of the resu lt in function of the inputs.
The tru th table for AND appears below:
0 AND 0 = 0
0 AND 1 = 0
1 AND 0 = 0
1 AND 1 = 1
The AND operation is characterized by the fact th a t the output
is "1” only if both inputs are "1.” In other words, if one of the
inputs is "0,” it is g uaranteed th a t th e resu lt is "0.” This feature is
used to zero a b it position in a word. T his is called "m asking.”
One of the important uses of the AND instruction is to clear or
mask out one or more specified bit positions in a word. Assume, for
example, that we want to zero the right-most four-bit positions in a
word. This will be performed by the following program:

LDA WORD WORD CONTAINS 10101010’

AND # % 1 1110000 11110000’ IS MASK

Let us assum e th a t WORD is equal to 10101010.’ The resu lt of

th is program is to leave in th e accum ulator the value 101 0 0000.’
"%” is used to represent a binary number.

Exercise 4.1: Write a three-line program which will zero bits 1 and
6 o f WORD.

Exerdse4.2: What happens with a mask: M A SK = '1111111V?

ORA

This instruction is th e inclusive OR operation. I t is charac­

terized by the following truth table:
0 OR 0 = 0
0 OR 1 = 1
1 OR 0 = 1
1 OR 1 = 1

The logical OR is characterized by the fact that if any one o f the

operands is “ 1” , the result is to set any bit in a word t o = “ l ” .

LDA #WORD
ORA #% 00001111

Let us assum e th a t WORD did contain '10101010.’ The final

value of the accum ulator will be '10101111.’

Exercise 4.3: What would happen if we were to use the instruction

ORA #%10101111?
Exercise 4.4: What is the effect o f ORing with “FF” hexadecimal?

EOR
EOR stands for “exclusive O R .” The exclusive OR differs from the
inclusive OR, that we have just described, in one respect: the result is “ 1”
only if one, and only one, of the operands is equal to “ 1.” If both operands
are equal to “ 1,” the normal OR would give a “ 1” result. The exclusive
OR gives a “0” result. The truth table is:
0 EOR 0 = 0
0 EOR 1 = 1
1 EOR 0 = 1
1 EOR 1 = 0
The exclusive OR is used for comparisons. If any bit is different,
th e exclusive OR of two words will be non-zero. In addition, in the
case of the 6502, the exclusive OR is used to complement a word,
since th ere is no specific complement instruction. This is done by
perform ing the EOR of a word w ith all l ’s. The program appears
below:
LDA #WORD
EOR #% 11111111
 Let us assum e th a t WORD did contain "10101010.” The final
value of the accum ulator will be "01010101.” We can verify th a t
th is is the com plem ent of th e original value.

Exercise 4.5: What is the effect o f EOR #$00?

Shift O perations
The stan d ard 6502 is equipped w ith a left shift, called ASL
(arithm etic shift left), and a rig h t shift, called LSR (logical shift
right). They will be described below.
However, the 6502 h as only one ro tate instruction, to th e left
(ROL).
Warning: newer versions of the 6502 have an extra rotate instruction.
Check the manufacturer’s data to verify this fact. (R O R =rotate right)

Comparisons
Registers X, Y, A can be compared to the mem ory w ith instru c­
tions CPX, CPY, CMP.

Test and Branch

Since testin g is alm ost exclusively performed on the flags regis­
ter, le t us exam ine now th e flags available in the 6502. The con­
tents of the flags register appear in Figure 4-2 below.

7 6 5 4 3 2 1 0
N V -
B D 1 Z c
SIGN BREAK INTERRUPT CARRY
(NEGATIVE)

OVERFLOW DECIMAL ZERO

Fig. 4-2: The Flags Register

 Let us exam ine the function of the flags from left to right.

Sign

The N flag is identical to bit 7 of the accumulator, in most cases.

As a result, bit 7 of the accumulator is the only bit that one can
test conveniently with a single instruction. To test any other bit of
the accumulator, it is necessary to shift its contents. In all cases
where one wants to test the contents of the word quickly, the
preferred bit position will, therefore, be bit 7. This is why input/
output status bits are normally connected to position 7 of the
data-bus. When reading the status of an I/O device, one will simply
read the contents of the external status register into the ac­
cumulator and then test bit N.

The left-most bit is the sign bit, or negative bit. Whenever N is

1, it indicates that the value of a result is negative in two’s com­
plement representation. In practice, flag N is identical to bit 7 of a
result. It is set, or reset, by all data transfers and data processing
instructions.

The bit within the accumulator which is the next easiest to test
is bit Z (zero). However, it requires a right shift by 1 into the carry
bit so that it can be tested.

Instructions that set N are: ADC, AND, ASL, BIT, CMP, CPY,
CPX, DEC, DEX, DEY, EOR, INC, INX, INY, LDA, LDX, LDY,
LSR, ORA, PLA, PLP, ROL, ROR, TAX, TAY, TXS, TXA, TYA.

Overflow
The role of the overflow has already been discussed in Chapter
3 in the section on arithmetic operations. It is used to indicate
that the result of the addition or subtraction of two’s complement
numbers might be incorrect because of an overflow from bit 6 to
bit 7, i.e., into the sign bit. A special correction routine must be
used whenever this bit is set. If one does not use two’s complement
representation, but direct binary, the overflow bit is equivalent to
a carry from bit 6 into bit 7.
 A special use of this b it is m ade by the BIT instruction. A resu lt
of this instruction is to set the "V” bit identical to b it 6 of the d a ta
being tested.
The V flag is conditioned by ADC, BIT, CLV PLP, RTI, SBC.

Break

This break flag is automatically set by the processor if an inter­

rupt is caused by the BRK command. It differentiates between a
programmed break and a hardware interrupt. No other user in­
struction will modify it.

Decimal

The use of this flag has already been discussed in C hapter 3 in

the section on arithm etic program s. W henever D is set to "1”, the
processor operates in BCD mode, and w henever it is set to "0”, it
operates in binary mode. This flag is conditioned by four instruc­
tions: CLD, PLP, RTI, SED.

Interrupt

This interrupt-mask bit may be set explicitly by the programmer with

the SEI or PLP instructions, or by the microprocessor during the reset or
during an interrupt.
Its effect is to inhibit any fu rth er interrupt.
Instructions which condition this bit are: BRK, CLI, PLP, RTI,

Zero
The Z flag indicates, when set (equal to “ 1” ), that the result of
a transfer or an operation is a zero. It is also set by the comparison
instruction. There is no specific instruction which will set or clear
the Z bit. However, the same result can easily be accomplished. In
order to set the zero bit, one can, for example, execute the follow­
ing instruction:
LDA # 0

The Z b it is conditioned by m any instructions: ADC, AND,

ASL, BIT, CMP, CPY, CPX, DEC, DEX, DEY, EOR, INC, INX,
INY, LDA, LDX, LDY, LSR, ORA, PLA, PLP, ROL, ROR, RTI,
SBC, TAX, TAY, TXA, TYA.

Carry
It h as been seen th a t th e carry b it is used for a dual purpose. Its
first purpose is to indicate a n arithm etic carry or borrow during
arithmetic operations. Its second purpose is to store the bit falling
out” of a register during the shift or rotate operations. The
two roles do not necessarily need be confused, and they are not on
larg er computers. However, th is approach saves tim e in the m i­
croprocessor, in particu lar for the im plem entation of a m ultiplica­
tion or a division. The carry b it can be set or cleared explicitly.
Instructions which will condition the carry b it are: ADC, ASL,
CLC, CMP, CPX, CPY, LSR, PLP, ROL, ROR, RTI, SBC, SEC.

Tkst and Branch Instructions

In the 6502, it is not possible to te s t every b it of the flags regis­
ter for one or zero. There are 4 bits which can be tested, and there are,
therefore, 8 different branch instructions. They are:

— BMI (branch on m inus), BPL (branch on plus). These two

instructions, naturally, test the N bit.
— BCC (branch on carry clear) and BCS (branch on carry set):
they test C.
__ BEQ (branch w hen resu lt is null) and BNE (branch on
resu lt not zero). They test Z.
— BVS (branch w hen overflow is set) and BVC (branch on
overflow clear). They test V.
 These instructions te s t and branch w ithin th e sam e instruction.
All branches specify a displacem ent relative to the cu rren t in­
struction. Since the displacem ent field is 8 bits, th is allows a
displacement of —128 to +127 (in two’s complement). The dis­
placem ent is added to the address of the first instruction following
th e branch.

Since all branches are 2 bytes long, this results in an effective

displacement of -1 2 8 + 2 = -1 2 6 to +127 + 2 = +129.

Two more unconditional instructions are available: JM P and

JSR. JMP is a jump to a 16-bit address. JSR is a subroutine call. It
jumps to a new address and automatically preserves the program
counter into the stack. Being unconditional, these two instructions
are usually preceded by a “ test and branch” instruction.

Two returns are available: RTI, a return from interrupt, which

will be discussed in the in te rru p t section, and RTS, a retu rn from
subroutine, which pulls a re tu rn address from the stack (and in ­
crem ents it).

Two special instructions are provided especially for bit-testing

and for comparisons.

The BIT instruction performs an AND between the memory

location and the accumulator. One im portant aspect is th a t it does
not change the contents o f the accumulator. The flag N is set to th e
value of bit 7 of the location tested, while the V flag is set to
bit 6 of the m em ory location being tested. Finally, b it Z indicates
the resu lt of th e AND operation. Z is set to "1” if th e resu lt is "0”.
Typically a mask will be loaded in the accumulator, and successive
memory values will then be tested using the BIT instruction.
If the m ask contains a single "1” for example, th is will te st
w hether any given mem ory word does contain a ”1” in th a t posi­
tion. In practice, th is m eans th a t a m ask should be used only
when one is testin g mem ory b it locations "0” to "5”. The reader
will rem em ber th a t b it locations "6” and ”7” are autom atically
stored respectively, in the "V” flag and in the "N” flag. They do not
need to be m asked.
The CMP instruction will compare the contents of the memory
location to those of the accumulator by subtracting it from the ac­
cumulator. The resu lt of th e comparison will be indicated, th ere­
fore, by bits Z and N. One can detect equality, greater than, or less
than. The value of the accumulator is not changed by the compar­
ison. CPX and CPY will compare to X and Y respectively.

I n p u t/O u tp u t I n s tr u c tio n s
There are no specialized input/output instructions in the 6502.

C o n tro l I n s tr u c tio n s
Control instructions include specialized instructions to set or
clear th e flags. They are: CLC, CLD, CLI, CLV, which clear re­
spectively bits C, D, I and V; and SEC, SED, SEI, which set re ­
spectively in bits C, D, and I.
The BRK instruction is th e equivalent of a software in te rru p t
and will be described in C hapter 7 in th e in te rru p t section. ^
The NOP instruction is an instruction which has no effect and is
commonly used to extend the timing of a loop. Finally, two special
pins on the 6502 will trigger an interrupt mechanism, and this will
be explained in Chapter 6 on input/output techniques. It is a hard­
ware control facility (IRQ and NMI pins).
Let us now examine each instruction in detail.
In order to truly understand the various addressing modes, the reader
is encouraged to read the following section quickly the first time, and
then in more detail the second time after studying Chapter 5 on
Addressing Techniques.

ill
 PART 2 - TH E IN ST R U C T IO N S

A B B R E V IA T IO N S

A Accum ulator
M Specified address (memory)
P S tatu s register
S Stack pointer
X Index register
Y Index register
DATA Specified d ata
HEX Hexadecim al
PC Program counter
PCH Program counter high
PCL Program counter low
STACK C ontents of top of stack
V Logical or
A Logical and
V Exclusive or
• Change
Receives the value of (assignm ent)
( ) C ontents of
(M6) B it position 6 a t address M
ADC A d d w ith c a r r y

F u n c tio n : A-*- (A) + DATA + C

OllbbbOl ADDR/DATA ADDR 1

F o rm a t:
D e sc rip tio n :
Add th e contents of mem ory address or literal to the ac­
cum ulator, plus the carry bit. The resu lt is left in the ac­
cum ulator.
R e m a rk s :
— ADC m ay operate e ith er in decim al or binary mode: flags
m ust be set to the correct value
—To ADD w ithout carry, flag C m ust be cleared (CLC).

D ata Paths:

A ddressing Modes:
Instruction Codes:

ABSOLUTE 01101101 16-BIT ADDRESS

1
b b b = Oil HEX = 6D CYCLES = 4

ZERO-PAGE 01100101 ADDR

b b b = 001 HEX - 65 CYCLES - 3

IMMEDIATE 01101001 DATA

bbb = 010 HEX ■= 69 CYCLES = 2

1
ABSOLUTE, X 01111101 16 BIT ADDRESS

bbb - 111 HEX = 7D CYCLES = 4*

l1------------------------------------- --
ABSOLUTE, Y 01111001 16-BIT ADDRESS
1l
bbb - 110 HEX ■= 79 CYCLES = 4*

(IND. X) 01100001 ADDR

bbb = 000 HEX - 61 CYCLES = 6

(IND),Y 01110001 ADDR

bbb ^ 100 HEX = 71 CYCLES - 5*

7ERO-PAGE, X 01110101 ADDR

bbb-= 101 HEX ~ 75 CYCLES ^ 4

*: PIUS I CYCLE IF CROSSING PAGE BOUNDARY.

AND L ogical AND
F u n c tio n : A-*- (A) A DATA
F o rm a t: OOlbbbOl ADDR/DATA ADDR 1
.......................... J
D e sc rip tio n :
Perform th e logical AND of the accum ulator and specified data.
The re su lt is left in the accum ulator.
The tru th table is:
a\ m 0 1

0 0 0

. ,1 0 1

D a ta P a th s :

*: PLUS 1 CYCLE IF CROSSING PAGE BOUNDARY.

Instruction Codes:

1----------------------------------------
ABSOLUTE 00101101 16-BIT ADDRESS
1
bbb = 011 HEX = 2D CYCLES = 4

ZERO-PAGE 00100101 ADDR

bbb = 001 HEX = 25 CYCLES = 3

IMMEDIATE 00101001 DATA

b b b - 010 HEX ~ 29 CYCLES = 2

l ‘
ABSOLUTE, X 00111101 16-BIT ADDRESS
l
bbb - 111 HEX = 3D CYCLES = 4*

. i
ABSOLUTE, V 00111001 16-BIT ADDRESS

bbb - 110 HEX = 39 CYCLES - 4*

(IND, X) 00100001 ADDR

bbb = 000 HEX = 21 CYCLES-- 6

(IND),Y 0011001 ADDR

bbb ^ 100 HEX - 31 CYCLES - 5*

ZERO PAGE, X 00110101 ADDR

bbb - 101 HEX - 35 CYCLES = 4

•: PLUS 1 CYCLE IF CROSSING PAGE BOUNDARY.

ASL A rithm etic sh ift left

Function:

Format:

D e sc rip tio n :
Move the contents of the accumulator or of the memory location
left by one bit position. 0 comes in on the right. Bit 7 falls into the
carry. The result is deposited in the source, i.e. either accumulator
or memory.

D a ta p a th s :

A ddressing Modes:
Instruction Codes:

ACCUMULATOR 00001010

bbb=010 H EX= 0A CYCLES = 2

i
ABSOLUTE 000011 10 ADDRESS

bbb=011 H EX= 0E CYCLES = 6

ZERO-PAGE 000 001 10 ADDR

bbb=001 HEX = 06 CYCLES = 5

--------------------------------------------1----------------------------------------
ABSOLUTE, X 000111 10 ADDRESS
________________________ 1____________________:____
b b b = 111 HEX = IE CYCLES = 7

ZERO-PAGE, X 000 101 10 ADDR

bbb = 101 H EX= 16 CYCLES = 6

F u n c tio n :
Go to specified address if C = 0
F o rm a t: 1001000 DISPLACEMENT

Description:
Test th e carry flag. If C = 0, branch to th e cu rren t address plus
the signed displacem ent (up to +127 or —128). If C = 1, tak e no
action. The displacem ent is added to the address of the first in­
struction following the BCC. This resu lts in an effective dis­
placem ent of +129 to -1 2 6 .
Data Paths:

Addressing Mode:
Relative only:
HEX = 90, bytes = 2, cycles = 2 + 1 if branch succeeds
+ 2 if into another page

Flags:
N V B D I Z C

(N O A C T IO N )
BCS
Function:
Go to specified address if C = 1

Format: 10110000 DISPLACEMENT

Description:
Test the carry flag. If C = 1, branch to the current address plus
the signed displacement (up to +127 or -128). If C = 0, take no
action. The displacement is added to the address of the first instruc­
tion following the BCS. This results in an effective displacement of
+129 to -126.

Addressing Mode:
Relative only:
HEX = B0, bytes = 2, cycles = 2 +1 if branch succeeds
+2 if into another page

F lags:
N V B D I Z C
Function:
Go to specified address if Z = 1 (result = 0).
F o rm a t: DISPLACEMENT

Description:
Test the Z flag. If Z = 1, branch to the current address plus the
signed displacem ent (up to +127 or -1 2 8 ). If Z = 0, tak e no
action.
The displacem ent is added to the address of th e first instruction
following the BEQ. This resu lts in an effective displacem ent of
+ 129 t o -1 2 6 .

Data Paths:

Addressing Mode:
Relative only:
HEX = F0, bytes = 2, cycles = 2 +1 if branch succeeds
+ 2 if into another page

Flags:
N V B D I Z C
BIX Compare memory bits w ith accumulator
Function:
Z-*-(A) A (M) , N-<-(M7), V-e-lM")
t
Format: 0010b100 ADDR ADDR 1

D escription:
The logical AND of A and M is performed, but not stored. The result
of the comparison is indicated by Z. Z = 1 if the comparison fails; 0
otherwise. In addition, bits 6 and 7 of the memory data are transferred
into V and N of the status register. It does not modify the contents of A.

Addressing Modes:

Flags:

Instruction Codes:
16-BIT ADDRESS

H E X = 2C CYCLES = 4

HEX = 24 CYCLES = 3
Function:
Go to specified address if N = 1 (result < 0).
Format: DISPLACEMENT

D escription:
Test the N flag (sign). If N = 1, branch to the cu rren t address
plus the signed displacem ent (up to +127 or -1 2 8 ). If N = 0, tak e
no action.
The displacement is added to the address of the first instruction
following the BMI. This results in an effective displacement of
+129 to -1 2 6 .

A ddressing Mode:
R elative only:
HEX = 30, bytes = 2, cycles = 2 +1 if branch succeeds
+ 2 if into another page

F lags:
N V B 0 I Z C
Function:
Go to specified address if Z = 0 (result ^ 0).
Format: DISPLACEMENT

D escription:
T est the resu lt (Z flag). If the resu lt is not equal to 0 (Z = 0),
branch to the current address plus the signed displacem ent (up to
+127 to -128). If Z = 1, take no action.
The displacem ent is added to th e address of the first instruction
following the BNE. This resu lts in an effective displacem ent of
+ 129 to -1 2 6 .

D ata Paths:

A ddressing Mode:
Relative only:
HEX = DO, bytes = 2, cycles = 2'. +1 if branch succeeds
+ 2 if into another page

F lags:
N V B D | Z C
Function:
Go to specified address if N = 0 (result 0 ).

Format: 0001 oooo d is p la c e m e n t

D escription:
T est th e N flag (sign). If N = 0 (result positive), branch to th e
cu rren t address plus the signed displacem ent (up to +127 or
-128). If N = 1, take no action.
The displacement is added to the address of the first instruction
following the BPL. This results in an effective displacement of
+129 to -1 2 6 .

ADDRl

A ddressing Mode:
Relative only:
HEX = 10, bytes = 2, cycles = 2 +1 if branch succeeds
+ 2 if into another page

F lags:
N V B D I Z C
BRK B reak
Function:
STACK (PC) + 2, STACK (P), PC ■(FFFE,FFFF)
Format: 00000000

D escription:
O perates like a n in terrupt: the program counter is pushed on
th e stack, th en the sta tu s register P. The contents of m emory
locations FFF E and F F F F are th en deposited respectively in PCL
and PCH. The value of P stored in th e stack has th e B flag set to 1,
to differentiate a BRK from a n IRQ.
Im portant: unlike an in terru p t, PC + 2 is saved. This m ay not
be the next instruction, and a correction m ay be necessary. This is
due to the assumed use of BRK to patch existing programs where BRK
replaces a 2-byte instruction. When debugging a program, BRK is gen­
erally used to cause exit to monitor. Then, BRK often replaces the first
byte of an instruction.

A ddressing Mode:
Implied only:
HEX = 00 , byte = 1, cycles = 7

Hags: n y ,
★

Note: B is set in before P is pushed in the stack.

Function:
Go to specified address if V = 0.
Form at: 0101000 DISPLACEMENT

D escription:
Test the overflow flag (V). If th ere is no overflow (V = 0), branch
to the cu rren t address plus the signed displacem ent (up to +127
or -128). If V = 1, take no action.
The displacement is added to the address of the first instruction
following the BVC. This results in an effective displacement of
+129 to -1 2 6 .
D ata Paths:

A ddressing Mode:
Relative only:
Hex = 50, bytes = 2, cycles = 2 +1 if branch succeeds
+2 if into another page

Flags:
N V B D I Z C
BVS
Function:
Go to specified address if V = 1.
Format: omoooo DISPLACEMENT

D escription:
Test the overflow flag (V). If an overflow has occurred (V = 1),
branch to the current address plus the signed displacement (up to
+127 or -128). If V = 0, take no action.
The displacement is added to the address of the first instruction
following the BVS. This results in an effective displacement of
+129 to -1 2 6 .
D ata Paths:

A ddressing Mode:
R elative only:
HEX = 70, bytes= 2, cycles = 2 +1 if branch succeeds
+ 2 if into another page

Flags:
N V B D | z C
Function:
C+ 1
Form at: 00011000

D escription:
The carry b it is cleared. This is often necessary before an ADC.
A ddressing Mode:
Im plied only
HEX = 18, byte = 1, cycles= 2

Flags:
CLD
Function:
D -< -0
Form at: lionooo

D escription:
The D flag is cleared, setting th e binary mode for ADC and
SBC.
A ddressing Mode:
Implied only:
HEX = D8, byte = 1, cycles= 2

F lags:
CLI Clear interrupt m ask
Function:
I-«-0
Format: 01011000

D escription:
The in te rru p t m ask b it is set to 0. This enables interrupts. An
in te rru p t handling routine m ust alw ays clear the I bit, or else
other in terru p ts m ay be lost.
A ddressing Mode:
Implied only:
HEX = 58, byte= 1, cycles= 2

F lags:
N V B D 1 Z C

0
CLV
F u n c tio n :
V m-6
10111000
F o rm a t:

D e sc rip tio n :
The overflow flag ii cleared.
A d d re s s in g M ode:
Im plied only:
HEX = B8, byte = 1, cycles = 2

F lags: N V B O I Z C

0
Function: + (A > DATA) - (A <0 A TA )
o
(A) - DATA
-0 1 O il -0 0

i
Format: 1lObbbOl ADDR/DATA ADDR |
......................... J
D escription:
The specified contents are su b tracted from A. The result is not
stored, b u t flags NZC are conditioned, depending on w hether the
resu lt is positive, null or negative. The value of th e accum ulator
is n o t changed. Z is set by an equality, reset otherwise; N is set;
rese t by the sign (bit 7), C is set when (A) > DATA. CM P is usual­
ly followed by a branch: BCC detects A < DATA, BEQ d etects A
= DATA, BCS detects A > DATA, and BEQ followed by BCS
detects A > DATA.
D ata Paths:

HEX CD C5 C9 DD D9 Cl Dl D5

BYTES 3 2 2 3 3 2 2 2

CYCLES 4 3 2 4* 4* 6 5* 4

O il 001 010 111 110 000 100 101

: PLUS 1 CYCLE IF CROSSING PAGE BOUNDARY.

I n s t r u c t i o n C odes:

1----------------------------------------
ABSOLUTE 11001101 16-BIT ADDRESS
1
b b b = Oil HEX = CD CYCLES = 4

ZERO-PAGE 11000101 ADDR

b b b = 001 HEX = C5 CYCLES = 3

IMMEDIATE 11001001 DATA

b b b = 010 H EX= C9 CYCLES = 2

ABSOLUTE, X 11011101 16-BIT ADDRESS

b b b = 111 HEX = DD CYCLES = 4*

i
ABSOLUTE, Y 11011001 16-BIT ADDRESS

b b b = 110 HEX = D9 CYCLES = 4*

(IND, X) 11000001 ADDR

b b b = 000 HEX = C l CYCLES = 6

. (IND), Y 11010001 ADDR

bbb = 100 HEX = D1 CYCLES = 5*

ZERO-PAGE, X 11010101 ADDR

b b b = 101 HEX = D5 CYCLES = 4

*: PLUS 1 CYCLE IF CROSSING PAGE BOUNDARY.

Function: + ( X > DATA) = —(X<D A TA )

X - DATA -►NZC: -0 1 on -0 0

Form at: 1110bb00 ADDR/DATA ADDR 1I

J

D escription:
The specified contents are subtracted from X. The resu lt is not
stored, b u t flags NZC are conditioned, depending on w hether the
resu lt is positive, null or negative. The value of the accum ulator
is not changed. CPX is usually followed by a branch: BCC detects X <
DATA, BEQ detects X =D A TA , and BEQ followed by BCS detects
X>DATA. BCS detects X > DATA.
D ata Paths:
In stru ction Codes:

1------------------------------ ----------
ABSOLUTE 11101100 16-BIT ADDRESS

bb= 11 HEX = EC CYCLES = 4

ZERO-PAGE 11100100 ADDR

bb= 01 HEX = E4 CYCLES = 3

IMMEDIATE 11100000 DATA

bb= 00 H E X = EO CYCLES = 2
Function: + (Y > DATA) = —(Y < DATA)

(Y) - DATA -*-NZC: -0 1 Oil -0 0

Format: HOObbOO ADDR 'DATA

D escription: ,
The specified contents are subtracted from Y. The resu lt is not
stored, b u t flags NZC are conditioned, depending on w hether th e
resu lt is positive, null or negative. The value of the accum ulator
is not changed. CPY is usually followed by a branch: BCC detects
Y < data, BEQ detects Y = data, and BEQ followed by BCS
detects Y > data. BCS detects Y s= data.
D ata Paths:
In stru ction Codes:

□
1---------------------------
ABSOLUTE 11001100 16-BIT ADDRESS
I
b b = 11 H E X = CC CYCLES = 4

ZERO-PAGE 11000100 ADDR

b b = 01 H E X = C4 CYCLES = 3

IMMEDIATE 11000000 DATA

b b = 00 H E X = CO CYCLES = 2
Function:

Format: liobblio ADDR ADDR

J

D escription:
The contents of the specified memory address are decrem ented
by 1. The resu lt is stored back a t th e specified mem ory address.
D ata Paths:

DATA-^-DATA —1

A dd ressin g M odes:
In stru ction Codes:

i
ABSOLUTE 11001110 ADDRESS

bb = 01 H EX= CE CYCLES = 6

ZERO-PAGE 11000110 ADDR

cr
tr
II

H EX= C6 CYCLES = 5
8

i
ABSOLUTE, X 11011110 ADDRESS
cr
cr

H EX= DE
II

CYCLES = 7

ZERO-PAGE, X 11010110 ADDR

cr
cr

HEX = D6 CYCLES = 6
II
o
Function:
X ^-(X )-l
Format: 11001010
D escription: .
The contents of X are decrem ented by 1. Allows th e use of X as
a counter.

D ata Paths:

A ddressing Mode:
Implied only:
HEX = CA, byte= 1, cycles = 2
DEY
Function:
Y ^ _ (Y ) -1
Format: 10001000
Description:
The contents of Y are decrem ented by 1. Allows the use of Y as
a counter.

Data Paths:

Addressing Mode:
Implied only:
HEX = 88, byte = 1, cycles — 2

F lags:
EOR Exclusive—ORwith accumulator

Function:
A **- (A) V DATA
Format: OlObbbOl ADDR/DATA ADDR

Description:
The contents of the accumulator are exclusive -O R e d with the
specific data. The truth table is:

Note: EOR w ith "-1” m ay be used to complement.

Instruction Codes:

i
ABSOLUTE 01001101 16-BIT ADDRESS
1
bbb = Oil HEX = 4D CYCLES = 4

ZERO-PAGE 01000101 ADDR

bbb = 001 HEX = 45 CYCLES = 3

IMMEDIATE 01001001 DATA

bbb - 010 HEX ~ 49 CYCLES = 2

1
ABSOLUTE, X 01011101 16-BIT ADDRESS
i
bbb = 111 HEX ■= 5D C YCLES- 4*

11----------------------------------------
ABSOLUTE, Y 01011001 16 BIT ADDRESS
1l
bb b= 110 HEX - 59 CYCLES-= 4*

(IND, X) 01000001 ADDR

bbb = 000 HEX = 41 CYCLES ~ 6

(IN D ), Y 01010001 ADDR

bbb--- 100 HEX -- 51 CYCLES - 5*

ZERO-PAGE, X 010101-01 ADDR

bbb •= 101 HEX - 55 CYCLES = 4

*: PLUS 1 CYCLE IF CROSSING PAGE BOUNDARY.

Function:
M (M) +1
i
Format: 11lb b l10 ADDR ADDR 1
_____________ J
Description:
The contents of th e specified mem ory location are increm ented
by one, th en redeposited into it.
Data Paths:

DATA-*-DATA + l

A dd ressin g M odes:
I n s tr u c tio n C odes:

ABSOLUTE 11101110

HEX = EE
cr
cr
II CYCLES = 6
o

ZERO-PAGE 11100110 ADDR

bb = 00 HEX = E6 CYCLES = 5

----------------------------------------- 1-------------------------------------;—
ABSOLUTE, X 11111110 ADDRESS
_________________________ 1_________________________
HEX = FE
cr
cr

CYCLES = 7
II

ZERO-PAGE, X 11110110 ADDR

b b = 10 HEX = F6 CYCLES = 6
F u n c tio n :
X -*- (X) +1
F o rm a t: m o io o o

D e sc rip tio n :
The contents of X are increm ented by one. This allows the use
of X as counter.

D a ta P a th s :

A d d re s s in g M ode:
Im plied only:
HEX = E8, byte = 1, cycles = 2

Flags:
INY Increm ent Y
Function:
¥ ◄ -(¥ ) + 1
Format:
11001000

D escription:
The contents of Y are increm ented by one. This allows the use
of Y as counter.

D ata Paths:

A ddressing Mode:
Implied only:
HEX = C8, byte = 1, cycles = 2

F lags:
JMP Jum p to address
Function:
PC -*- ADDRESS
Format: OlbOllOO ADDRESS

D escription:
A new address is loaded in the program counter, causing a jum p
to occur in the program sequence. The address specification m ay
be absolute or indirect.

Data Paths:
P C

JM P

7 v A D D R E SS

(ABSOLUTE)

A ddressing Modes:

N V B 0 I Z C

(N O EFFECT)
In stru ction Codes:

-------------------------------------------------- 1--------------------------------------------------

ABSOLUTE 01001100 ADDRESS

i
JO

HEX = 4C CYCLES = 3
o
II

i
INDIRECT 01101100 ADDRESS

b=1 HEX=6C CYCLES= 5

 eJS R Jum p to subroutine
Function:
STACK-*- (PC) +2
PC -*- ADDRESS
l
Format: 00100000 ADDRESS
i

D escription:
The contents of the program counter +2 are saved into the
stack. (This is the address of the instruction following the JSR).
The subroutine address is th en loaded into PC. This is also called
a "subroutine CALL.”
Data Paths:

A ddressing Mode:
Absolute only:
HEX = 20, bytes = 3, cycles = 6

Flags:
N V B D I Z C

(N O EFFEC T)
LDA Load accum ulator
F u n c tio n :
A -«- DATA
i
F o rm a t: lOIbbbO! ADDR/DATA ADDR 1
_____________ J
D e sc rip tio n :
The accum ulator is loaded w ith new data.
D a ta P a th s :

A dd ressin g M odes:

F lags:
 1
ABSOLUTE 10101101 16-BIT ADDRESS
1
bbb = Oil HEX = AD CYCLES = 4

ZERO-PAGE 10100101 ADDR

bbb — 001 HEX ~ A5 CYCLES = 3

IMMEDIATE 10101001 DATA

bbb-- 010 HEX ~ A9 CYCLES = 2

1
ABSOLUTE, X 10111101 16-BIT ADDRESS
i
bbb - 111 HEX ~ BD CYCLES - 4*

1
ABSOLUTE, Y 10111001 16-BIT ADDRESS
1l
bbb " 110 HEX = B9 CYCLES = 4*

(IND, X) 10100001 ADDR

bbb - 000 HEX ~ A1 CYCLES- 6

(IND).Y 10110001 ADDR

bbb * 100 HEX-- B1 CYCLES - 5*

ZERO-PAGE, X 10110101 ADDR

bbb - 101 HEX = B5 CYCLES = 4

LDX L o a d r e g is te r X
F u n c tio n :
X-*- DATA

lOlbbblO ADDR/DATA ADDR

F o rm a t:

D e sc rip tio n :
Index register X is loaded w ith d a ta from the specified address.
D a ta P a th s :

A dd ressin g M odes:

*: PLUS 1 CYCLE IF CROSSING PAGE BOUNDARY.

Flags:
 i
ABSOLUTE 10101110 16-BIT ADDRESS
1
bbb -- 011 HEX - AE CYCLES - 4

ZERO-PAGE 10100110 ADDR

bbb - 001 HEX -= A6 CYCLES = 3

IMMEDIATE 10100010 DATA

bbb 000 HEX * A2 CYCLES -- 2

l
ABSOLUTE, Y 10111110 16 BIT ADDRESS
1
bbb ^ 111 HEX BE CYCLES = 4*

ZERO PAGE, Y 10111010 ADDR

bbb 110 HEX • B6 CYCIES : 4

•: PLUS 1 CYCLE IF CROSSING PAGE BOUNDARY.

LDY Load register Y
Function:
Y -«- DATA
lOlbbbOO ADDR/DATA ADDR
Format: J

D escription:
Index register Y is loaded w ith d a ta from the specified address.
D ata Paths:

A dd ressin g M odes:

F lags:
 ------------------------------------------- !
I
ABSOLUTE 10101100 16-BIT ADDRESS
1____________________ _______
b b b = 011 HEX = AC CYCLES- 4

ZERO-PAGE 10100100 ADOR

bbb=001 H E X - A4 CYCLES - 3

IMMEDIATE 10100000 DATA

bbb — 000 H E X -A 0 CYCLES- 2

11
ABSOLUTE, X 10111100 16-BIT ADDRESS
i -
bbb — 111 H EX=BC CYCLES - 4*

ZERO -PAGE, X 10110100 ADDR

bbb - 101 H E X - B4 CYCLES- 4

LSR L ogical sh ift right

Function:

Form at:
D escription:
Shift the specified contents (accumulator or memory) right by
one bit position. A “ 0” is forced into bit 7. Bit 0 is transferred to
the carry. The shifted data is deposited in the source, i.e., either
accumulator or memory.
D ata Paths:

A dd ressin g M odes:

Flags:
N V B D I 2 C

0 ••
ACCUM ULATOR 01010110

bbb=010 H EX=4A C YCLES = 2

------ ----------- i
ABSOLUTE 01011110 ADDRESS
l
bbb=011 HEX = 4E CYCLES = 6

ZERO-PAGE 01001110 ADDR

bb b= 0 0 1 HEX = 4 6 CYCLES = 5

— ------------------------------------- 1
ABSOLUTE, X 01111110 ADDRESS
i
bbb = 111 H EX=5E C YCLES = 7

ZERO-PAGE, X 01101110 ADDR

bbb = 10l HEX = 56 C YCLES = 6

NOP No operation

Function:
None
Form at: 11101010

D escription:
Does nothing for 2 cycles. M ay be used to tim e a delay loop or to
fill patches in a program .

A ddressing Mode:
Im plied only:
HEX = EA, byte = 1, cycles = 2

Flags:
N V B D I Z C

(NO ACTION)
ORA In clu siv e OR w ith accum ulator
Function:
A -*- (A) V DATA
Format: OOObbbOl ADDR/DATA

Description:
Perform s th e logical (inclusive) OR of A and the specified data.
The resu lt is stored in A. M ay be used to force a "1” a t selected b it
locations.
T ru th table:

Data Paths:

A dd ressin g M odes:

HEX OD 05 09 ID 19 01 II 15

BYTES 3 2 2 3 3 2 2 2

CYCLES 4 3 2 4* 4* 6 5* 4

Oil 001 0 10 111 no 0 00 100 101

: PLUS 1 CYCLE IF CROSSING PAGE BOUNDARY.

Instruction Codes:

1
ABSOLUTE 00001101 16-BIT ADDRESS

b b b = 011 HEX = 0D CYCLES = 4

ZERO-PAGE 00000101 ADDR

b b b = 001 HEX = 05 CYCLES = 3

IMMEDIATE 00001001 DATA

b b b = 010 HEX = 09 CYCLES = 2

i
ABSOLUTE, X 00011101 16-BIT ADDRESS
i
b b b = 111 H EX = ID CYCLES = 4*

l1----------------------------------------
ABSOLUTE, Y 00011001 16-BIT ADDRESS
il
b b b = 110 HEX = 1 9 CYCLES = 4*

(IND, X) 00000001 ADDR

b b b = 000 HEX - 01 CYCLES = 6

(IND),Y 00010001 ADDR

b b b = 100 HEX •= 11 CYCLES = 5*

ZERO-PAGE, X 00010101 ADDR

bbb =101 HEX = 15 CYCLES - 4

*: PLUS I CYCLE IF CROSSING PAGE BOUNDARY.

PHA Push A
Function:
STACK-*- (A)
S-*-(S)-l
Format: 01001000
Description:
The contents of th e accum ulator are pushed on th e stack. The
stack pointer is updated. A is unchanged.

Data Path:

Addressing Mode:
Im plied only:
HEX = 48, byte = 1, cycles = 3

Flags:
N V B D 1 Z C

(NO EFFECT)
PHP P u s h p ro c e s s o r s t a t u s
F u n c tio n :
STACK-*- (P)
S -* -(S ) - 1
F o rm a t: 00001000

D e sc rip tio n :
The contents of the sta tu s register P are pushed on the stack.
The stack pointer is updated. A is unchanged.

D a ta P a th :

A d d re s s in g M ode:
Implied only
Hex = 08, byte = 1, cycles= 3

F la g s :
N V B D I Z C

(NO EFFECT)
PLA Pull accumulator
Function:
A m - (STACK)
S-*- (S) +1
Format: 01101000
Description:
Pop th e top word of th e stack into the accum ulator. Increm ent
th e stack pointer.

Data Paths:

Addressing Mode:
Implied only:
HEX = 68, byte = 1, cycles = 4
PLP Pull processor status from stack
Function:
P-*- (STACK)
S«*-(S) +1
Format: 00101000

Description:
The top word of the stack is popped (transferred) into the sta tu s
register P. The stack pointer is increm ented.

Data Paths:

Addressing Mode:
Implied only:
HEX = 28, byte = 1, cycles = 4

Flags:
N V B D I Z C
ROL R otate le ft one b it
Function:

Format:
D escription:
The contents of the specified address (accum ulator or memory)
are rotated left by one position. The carry goes into b it 0. Bit 7
sets th e new value of the carry. T his is a 9-bit rotation.
D ata Paths:

A dd ressin g M odes:

N V B D 1 Z C

• ••
In stru ction Codes:

ACCUMULATOR 00101010

bbb=010 HEX=2A CYCLES= 2

i
ABSOLUTE 00101110 16 BIT-ADDRESS
1
bbb=011 HEX = 2E CYCLES = 6

ZERO-PAGE 00100110 ADDR

bbb=001 HEX = 2 6 CYCLES = 5

i
ABSOLUTE, X 00111110 16 BIT-ADDRESS
1
bbb = 111 HEX = 3E CYCLES = 7

ZERO-PAGE, X 00110110 ADDR

bbb = 101 HEX = 3 6 CYCLES = 6

ROR R otate righ t one b it
W a rn in g : This instruction m ay not be available on older 6502’s;
also., it m ay exist b u t not be listed.
F u n c tio n :

F o rm a t:
D e sc rip tio n :
The contents of the specified address (accumulator or memory)
are rotated right by one bit position. The carry goes into bit 7. Bit 0
sets the new value of the carry. This is a 9-bit rotation.
D a ta P a th s :

A dd ressin g M odes:
In stru ction Codes:

ACCUMULATOR 01101010

bbb=010 HEX=6A CYCLES= 2

i
ABSOLUTE 01101110 16 BIT-ADDRESS
______________________ 1______________________
bbb=011 HEX = 6E CYCLES = 6

ZERO-PAGE 01100110 ADDR

bbb=001 HEX = 66 CYCLES = 5

i
ABSOLUTE, X 01111110 16 BIT-ADDRESS

bbb = 111 HEX = 7E CYCLES = 7

ZERO-PAGE, X 01110110 ADDR

bbb= 101 HEX = 76 CYCLES = 6

RTI R eturn from interrupt
Function:
P (STACK)
S ■<- (S) +1
PCL (STACK)
S < « -( S ) + l
PCH (STACK)
S -* -(S )+ l
Form at: 01000000

D escription:
Restore the status register P and the program counter (PC)
which had been saved in the stack. Adjust the stack pointer.

D ata Paths:

A ddressing Mode:
Im plied only:
HEX = 40, byte = 1, cycles = 6

N V B D 1 Z C
RTS R eturn from subroutine
Function:
PCL (STACK)
S * * -(S )+ l
PC H -«- (STACK)
S -* -(S )+ l
PC -* -(P C + 1)

Format: 01100000

D escription:
Restore the program counter from the stack and increment it
by one. Adjust the stack pointer.
D ata Paths:
s

A ddressing Mode:
Implied only:
HEX = 60, byte = 1, cycles = 6

F lags:
N V B D I Z C

(NO EFFECT)
SBC S u btract w ith carry
Function: _ _
A - * - (A) -D A T A - C (C is borrow)
?I
Form at: 11lbbbOl ADDR/DATA ] ADDR I
i

D escription:
S ubtract from the accum ulator the d ata a t the specified ad­
dress, w ith borrow. The resu lt is left in A. Note: SEC is used for a
subtract w ithout borrow.
SBC may be used in decimal or binary mode, depending on bit
D o f the status register.

D ata Paths:
A

A dd ressin g M odes:

N V B 0 1 Z c

• • • •
In stru ction Codes:

1----------------------------------------
ABSOLUTE 11101101 16-BIT ADDRESS
1
b b b = 011 HEX = ED CYCLES = 4

ZERO-PAGE 11100101 ADDR

bbb =001 HEX = E5 CYCLES = 3

IMMEDIATE 11101001 DATA

bbb =010 HEX = E9 CYCLES = 2

l
ABSOLUTE, X 11111101 16-BIT ADDRESS
i
bbb = 111 HEX = FD CYCLES = 4*

1
ABSOLUTE, Y 11111001 16-BIT ADDRESS

b b b=1 10 HEX = F9 CYCLES = 4*

(IND, X) 11100001 ADDR

bbb = 000 HEX = El CYCLES = 6

(IND), Y 11110001 ADDR

bbb = 100 HEX = FI CYCLES = 5*

ZERO-PAGE, X 11110101 ADDR

b b b = 101 HEX = F5 CYCLES = 4

•: PIUS I CYCLE IF CROSSING PAGE BOUNDARY.

SEC S et carry
Function:
C -« -l

Format: 00111000

D escription:
The carry bit is set to 1. This is used prior to an SBC to perform
a subtract w ithout carry.

A ddressing M odes:
Implied only:
HEX = 38, byte = 1, cycles= 2

N V B D I Z C
Flags:
1
SED S et decim al m ode
Function:
D -* - 1

Format:

11111000

D escription:
The decim al b it of th e sta tu s register is set to 1. W hen it is 0,
the mode is binary. W hen it is 1, the mode is decim al for ADC and
SBC.

A dd ressin g M odes:
Implied only:
HEX = F8, b y te = l, cycles = 2

Flags: N V B P I Z C
1
SEI Set interrupt disable

Function:
1^-1
Form at: o n nooo

D escription:
The interrupt mask is set to 1. Used during an interrupt or a system
reset.

A dd ressin g M odes:
Implied only:

HEX = 78, byte = 1, cycles = 2

F lags: N V B D I Z C
1
SX A S tore accum ulator in m em ory
Function:
M ^ - (A)
Format: lOObbbOl ADDRESS I
I
D escription:
The contents of A are copied a t the specified memory location.
The contents of A are not changed.
D ata Paths:

A dd ressin g M odes:

Flags:
N V B D | z C

(NO EFFECT)
In stru ction Codes:

1
ABSOLUTE 10001101 16-BIT ADDRESS
1
b b b = 011 HEX = 8D CYCLES = 4

ZERO-PAGE 10000101 ADDR

b b b = 001 H EX = 85 CYCLES = 3

1
ABSOLUTE, X 10011101 16-BIT ADDRESS

b b b = 111 HEX = 9D CYCLES = 5

1 "
ABSOLUTE, Y 10011001 16-BIT ADDRESS

b b b = 110 HEX = 99 CYCLES = 5

(IND, X) 10000001 ADDR

bbb = 000 HEX = 81 CYCLES = 6

(IND),Y 10010001 ADDR

b b b = 100 HEX = 91 CYCLES = 6

ZERO-PAGE, X 10010101 ADDR

bbb = 101 HEX = 9 5 CYCLES = 4

STX Store X in m em ory
Function:
M -«- (X)
Format: ADDRESS

D escription:
Copy the contents of index register X a t the specified memory
location. The contents of X are left unchanged.

F lags:
N V B D | 2 C

(N O EFFECT)

In stru ction Codes:

ABSOLUTE

ZEROPAGE

ZERO PAGE. V

b b =IO HEX- 9 6 CYCLES 4

STY Store Y in m em ory
Function:
M ^ - (Y)
Format: lOObblOO ADDRESS

D escription:
Copy th e contents of index register Y a t the specified m em ory
location. The contents of Y are left unchanged.
D ata Paths:

(NO EFFECT)

In stru ction Codes:

ABSOLUTE

ZERO-PAGE

ZERO-PAGE. X

bb = 10 HEX = 94 CYCLES = 4
TAX T ransfer accum ulator in to X
Function:
X -*-(A )
Format: 10101010

D escription:
Copy the contents of the accumulator into index register X. The
contents of A are left unchanged.

D ata Paths:

A ddressing Mode:
Im plied only:
HEX = AA, byte = 1, cycles = 2

F lags:
Function:
(A)
Format: { 10101000 |
D escription:
T ransfer the contents of th e accum ulator into index register Y.
The contents of A are left unchanged.
Data Paths:

A ddressing Mode
Implied only:
HEX = A8, byte = 1, cycles = 2

Flags:
TSX Transfer S into X
Function:
X ^ -(S )
Format:
10111010

Description:
The contents of the stack pointer S are transferred into index
register X. The contents of S are unchanged.

Data Paths:

Addressing Mode:
Implied only:
HEX = BA, byte = 1, cycles = 2

F lags:
 Function:
A -* -(X )
Format: j 10001010 |
D escription:
The contents of index register X are transferred into the ac­
cumulator. The contents of X are unchanged.
D ata Paths:

A ddressing Mode:
Implied only:
HEX = 8A, byte = 1, cycles = 2

F lags:
TXS Transfer X into S
Function:
S-«-(X)
Format: 10011010

Description:
The contents of index register S are transferred into the stack
pointer. The contents of X are unchanged.
Data Paths:

Addressing Mode:
Implied only:
HEX = 9A, byte = 1, cycles = 2

F lags:
N V B D I Z C

(N O A C T IO N )
Function:
A ^ - (Y)
Form at: 10011000 I
D escription:
The contents of index register Y are transferred into the ac­
cum ulator. The contents of Y are unchanged.
D ata Paths:

A ddressing Mode:
Implied only:
HEX = 98, byte = 1, cycles = 2

F lags:
ADDRESSING TECHNIQUES
INTRODUCTION
This chapter will present th e general theory of addressing, w ith
th e various techniques w hich have been developed to facilitate
th e retriev al of data. In a second section, the specific addressing
modes which are available in the 6502 will be reviewed, along
with their advantages and limitations, where they exist. Finally,
in order to fam iliarize th e reader w ith the various trade-offs pos­
sible, a n applications section will show possible trade-offs be­
tw een the various addressing techniques by studying specific ap­
plication program s.
Because th e 6502 has no 16-bit register, other th a n the program
counter, which can be used to specify a n address, it is necessary
th a t th e 6502 user understand the various addressing modes, and
in particular, th e use of the index registers. Complex retriev al
modes, such as a com bination of indirect and indexed, m ay be
om itted a t the beginning stage. However, all th e addressing
modes are useful in developing program s for this micro­
processor. L et us now stu d y the various alternatives available.

ADDRESSING MODES
Addressing refers to the specification, w ithin an instruction, of
th e location of th e operand on which th e instruction will operate.
The m ain m ethods will now be examined.
 IAAPLICIT/IAAPLIED OPCODE A I R
_____ ;_______i__

IMMEDIATE OPCODE

LITERAL

I LITERAL
l_____________ - J

DIRECT/SHORT OPCODE

SHORT ADDRESS

EXTENDED/ABSOLUTE OPCODE

FULL 16-BIT

ADDRESS

INDEXED OPCODE X REG

DISPLACEMENT

i OR ADDRESS
L ..
Fig. 5-1: Addressing
Im plicit A ddressing

In stru ctio n s which operate exclusively on registers norm ally

use im plicit addressing. This is illu strate d in Figure 5-1. A n im ­
plicit instruction derives its nam e from the fact th a t it does not
specifically contain the address of th e operand on which it oper­
ates. Instead, its opcode specifies one or m ore registers, usually
th e accum ulator, or else any other register(s). Since internal reg­
iste rs are usually few in num ber (say a m axim um of 8), th is will
require a sm all num ber of bits. A s an example, three b its w ithin
the instruction will point to 1 out of 8 internal registers. Such in­
stru ctio n s can, therefore, norm ally be encoded w ithin 8 bits. This
is an im p o rtan t advantage, since an 8-bit instruction norm ally
executes faster th a n any two- or three-byte instruction.
A n exam ple of an im plicit in struction for the 6502 is TAX which
specifies “ tran sfer the contents of A to X .”

Im m ediate A ddressing

Im m ediate addressing is illu strated in Figure 5-1. The 8-bit

opcode is followed by an 8- or a 16-bit literal (a constant). This
ty p e of instruction is needed, for example, to load an 8-bit value
to an 8-bit register. I f th e m icroprocessor is equipped w ith 16-bit
registers, it m ay be necessary to load 16-bit literals. This depends
upon th e internal architecture of th e processor. A n exam ple of an
im m ediate instruction is ADC #0.
The second word of th is in struction contains the literal “ 0 ” ,
which is added to the accum ulator.

A bsolute A ddressing

A bsolute addressing refers to th e w ay in which d a ta is usually

retrieved from memory, where an opcode is followed by a 16-bit
address. A bsolute addressing, therefore, requires 3-byte instruc­
tions. A n exam ple of absolute addressing is STA $1234.
I t specifies th a t th e contents of th e accum ulator are to be stored
a t th e m em ory location “ 1234” hexadecimal.
The disadvantage of absolute addressing is to require a 3-byte
instruction. In order to im prove th e efficiency of the microproces­
sor, another addressing m ode m ay be m ade available, where only
one word is used for the address: direct addressing.
D irect A ddressing
In th is addressing mode, the opcode is followed by an 8-bit
address. This is illustrated in Figure 5-1. The advantage of this
approach is to require only 2 bytes instead of 3 for absolute ad­
dressing. The disadvantage is to lim it all addressing w ithin th is
mode to addresses 0 to 255. This is page 0. This is also called
short addressing, or 0-page addressing. Whenever short addressing
is available, absolute addressing is often called extended addressing
by contrast.

R elative A ddressing
Norm al jum p or branch instructions require 8 bits for th e op­
code, plus th e 16-bit address which is the address to w hich th e
program has to jump. J u s t as in the preceding example, this has
the inconvenience of requiring 3 words, i.e., 3 memory cycles. To
provide more efficient branching, relative addressing uses only a
two-word form at. The first word is th e branch specification,
usually along w ith the te st it is im plem enting. The second word is
a displacem ent. Since the displacem ent m ust be positive or nega­
tive, a relative branching instruction allows a branch forw ard to
128 locations (7-bits) or a branch backwards to 128 locations (plus
or m inus 1, depending on th e conventions). Because m ost loops
tend to be short, relative branching can be used m ost of the tim e
and results in significantly improved performance for such short
routines. As an example, we have already used th e instruction
BCC, which specifies a "branch on carry clear” to a location
w ithin 127 words of th e branch instruction.

Indexed A ddressing
Indexed addressing is a technique specifically useful to access
successively the elem ents of a block or of a table. This w ill be
illu strated by exam ples la te r in th is chapter. The principle of
indexed addressing is th a t th e instruction specifies both an index
register and an address. In the m ost general scheme, the contents
of the register are added to the address to provide the final ad­
dress. In th is way, the address could be th e beginning of a table in
the memory. The index register would then be used to access
successively all th e elem ents of th e table in an efficient way. In
practice, restrictions often exist and m ay lim it th e size of the
index register, or th e size of th e address or displacem ent field.

P re-indexing and Post-indexing

Two modes of indexing m ay be distinguished. Pre-indexing is
th e usu al indexing mode w here th e final address is the sum of a
displacem ent or address and the contents of th e index register.
Post-indexing tre a ts th e contents of th e displacem ent field like
th e address of th e actual displacem ent, ra th e r th a n th e displace­
m ent itself. This is illustrated in Figure 5-2. In post-indexing, the
final address is the sum of the contents of the index register plus
th e contents of th e m em ory word designated by the displacement
field. This feature utilizes, in fact, a com bination of indirect ad­
dressing and pre-indexing. B ut we have not defined indirect ad­
dressing yet, so let us do that now.

Fig. 5-2: Indirect Post-Indexed Addressing

Indirect A ddressing
We have already seen th e case w here two subroutines m ay w ish
to exchange a large q u a n tity of d a ta stored in th e memory. More
generally, several programs, or several subroutines, may need ac­
cess to a common block of information. To preserve the generality
of th e program , it is desirable not to keep such a block a t a fixed
memory location. In particular, the size of this block m ight grow
or shrink dynam ically, and it m ay have to reside in various
areas of th e memory, depending on its size. I t would, therefore,
be im practical to try to have access to th is block using absolute
addresses.
The solution to th is problem lies in depositing th e s ta rtin g ad­
dress of the block a t a fixed m em ory location. This is analogous
to a situation in which several persons need to g e t into a house,

INSTRUCTION MEMORY

OPCODE

INDIRECT (A.) FINAL

ADDRESS A. ADDRESS (A2)

a3 DATA

Fig. 5-3: Indirect Addressing

and only one key exists. B y convention, the key to the house
will be hidden under the m at. Every user will then know where to
look (under th e m at) to find th e key to the house (or, perhaps, to
find th e address of a scheduled m eeting, to have a m ore correct
analogy). Indirect addressing, therefore, uses a n 8-bit opcode fol­
lowed by a 16-bit address. Simply, th is address is used to retrieve
a word from the memory. Normally, it will be a 16-bit word (in our
case, two bytes) w ithin th e memory. This is illu strated by Figure
5-3. The two bytes a t the specified address, A l, contain A2. A2 is
th e n interpreted as the actual address of the d a ta th a t one wishes
to access.
Indirect addressing is particularly useful any time that pointers
are used. Various areas of the program can then refer to these
pointers to access conveniently and elegantly a word or a block of
data.

C om binations o f M odes
The above addressing modes m ay be combined. In particular, it
should be possible in a completely general addressing scheme to
use m any levels of indirection. The address A2 could be inter­
preted as an indirect address again, and so on.
Indexed addressing can also be combined w ith indirect access.
T h a t allows th e efficient access to word n of a block of data, pro­
vided one knows w here th e pointer to the s ta rtin g address is.
We have now become fam iliar w ith all usual addressing modes
th a t can be provided in a system . M ost microprocessor system s,
because of the lim itation on the complexity of an MPU, which
must be realized within a single chip, do not provide all possible
modes b u t only a sm all subset of these. The 6502 provides a n
unusually large subset of possibilities. Let us exam ine them now.

6502 ADDRESSING MODES

Im plied A ddressing (6502)

Implied addressing is used by a single byte instruction which
operates on in tern al registers. W henever im plicit instructions
operate exclusively in in te rn al registers, they require only two
clock cycles to execute. W henever they access memory, they re ­
quire th ree cycles.
Instructions w hich o p e ra te e x c lu siv ely in sid e th e 6502
are: CLC, CLD, CLI, CLV, DEX, DEY, INX, INY, NOP, SEC, SED,
SEI, TAX, TAY, TSX, TXA, TXS, TYA.
Instructions which require mem ory access are: BRK, PHA,
PHP, PLA, PLP, RTI, RTS.
These instructions have been described in th e preceding chap­
ter, and th e ir mode of operation should be clear.

Im m ediate A ddressing (6502)

Since the 6502 has only 8-bit w orking registers (the PC is not a
w orking register), im m ediate addressing in th e case of the 6502 is
limited to 8-bit constants. All instructions in immediate addressing
mode are, therefore, two bytes in length. The first byte contains
the opcode, and the second byte contains the constant or literal
which is to be loaded in a register or used in conjunction with one
of the registers for an arithmetic or logical operation.
Instructions using th is addressing mode are: ADC, AND, CMP,
CPX, CPY, EOR, LDA, LDX, LDY, ORA, SBC.

A bsolute A ddressing (6502)

By definition, absolute addressing requires th re e bytes. The
first byte is the opcode and the n ext two bytes are the 16-bit
address specifying the location of the operand. Except in th e case
of a jum p absolute, this address mode requires four cycles.
Instructions which m ay use absolute addressing are: ADC,
AND, ASL, BIT, CMP, CPX, CPY, DEC, EO R, INC, JMP, JSR ,
LDA, LDX, LDY, LSR, ORA, ROL, ROR, SBC, STA, STX, STY.

Zero-Page A ddressing (6502)

By definition zero-page addressing requires two bytes: th e first
one is for the opcode; the second one is for th e 8-bit, or short
address.
Zero-page addressing requires th ree cycles. Because zero-page
addressing offers significant speed advantages as well as shorter
code, it should be used w henever possible. This requires careful
mem ory m anagem ent by th e programmer. G enerally speaking,
the first 256 locations of mem ory m ay be viewed as the set of
w orking registers for the 6502. Any instruction will essentially
execute on these 256 “ reg isters” in ju s t three cycles. This space
should, therefore, be carefully reserved for essential d a ta th a t
needs to be retrieved a t high speed.
Instructions which can use zero-page addressing are those
which can use absolute addressing, except for JM P and JS R
(which require a 16-bit address).
The list of legal instructions is: ADC, AND, ASL, BIT, CMP,
CPX, CPY, DEC, EOR, INC, LDA, LDX, LDY, LSR, ORA,
ROL, ROR, SBC, STA, STX, STY.

R elative A ddressing (6502)

By definition, relative addressing uses two bytes. The first one
is a jum p instruction, w hereas the second one specifies the dis­
placem ent and its sign. In order to differentiate th is mode from
the jum p instruction, they are here labeled branches. Branches,
in the case of the 6502, alw ays use the relative mode. Ju m p s
alw ays use the absolute mode (plus, naturally, the other sub­
modes which m ay be combined w ith those, such as indexed and
indirect). From a tim ing standpoint, this instruction should be
examined with caution. Whenever a te st fails, i.e., whenever there
is no branch, this instruction requires only two cycles. This is be­
cause the next instruction to be executed is pointed to by the pro­
gram counter. However, whenever the te st succeeds, i.e., whenever
the branch m ust take place this instruction requires three cycles: a
new effective address m ust be computed. The updating of the
program counter requires an ex tra cycle. However, if a branch
occurs through a page boundary, one more updating is necessary
for the program counter, and the effective length of the instruc­
tion becomes four cycles.
From a logical standpoint, the user does not need to worry about
crossing a page boundary. The hardware takes care of it. However,
because an extra carry or borrow is generated whenever one crosses
a page boundary, the execution time of the branch will be changed.
If this branch was part of an exact timing loop, caution must be
exercised.
A good assem bler will norm ally tell the program m er a t the
tim e th e program is assem bled th a t a branch is crossing a page
boundary, in case tim ing m ight be critical.
W henever one is not sure w hether the branch will succeed, one
m u st take into consideration the fact th a t som etim es the branch
will require tw o cycles, and som etim es three. O ften an average
tim e is computed.
The only instructions which implement relative addressing are the
branch instructions. There are 8 branch instructions which test flags
within the status register for value “ 0” or “ 1” . The list is: BCC,
BCS, BEQ, BMI, BNE, BPL, BVC, BVS.

Indexed A ddressing (6502)

The 6502 does not provide a completely general capability, b u t
only a lim ited one. It is equipped w ith two index registers. How­
ever, these registers are lim ited to 8 bits. The contents of a n index
register are added to th e address field of the instruction. Usually,
the index reg ister is used as a counter in order to access ele­
m ents of a block or a table successively. This is why specialized
instructions are available to increm ent or decrem ent each one of
the index registers separately. In addition, two specialized in­
structions exist to compare the contents of the index registers
ag ain st a mem ory location, a n im portant facility for the effective
use of the index registers to te st ag ain st lim its.
In practice, because m ost user tables are norm ally shorter th a n
256 words, th e lim itation of th e index registers to 8 bits is usually
not a significant lim itation.
The indexed addressing mode can be used not only w ith reg u lar
absolute addressing, i.e., w ith 16-bit address fields, bu t also w ith
th e zero-page addressing mode, i.e., w ith 8-bit address fields.
There is only one restriction. R egister X can be used With both
types of addressing. However, register Y allows only absolute in­
dexed addressing and not zero-page indexed addressing (except for
LDX and STX instructions, which can be modified by register Y).
Absolute indexed addressing will require four cycles, unless th e
page boundary is being crossed, in which case five cycles w ill be
required.
Absolute indexed instructions can use eith er registers X or Y to
provide the displacem ent field. The list of instructions which m ay
use th is mode are:
- with X: ADC, AND, ASL, CMP, DEC, EOR, INC, LDA, LDY,
LSR, ORA, ROL, ROR, SBC, STA, (not STY).
 - w i t h Y: ADC, AND, CMP, EOR, LDA, LDX, ORA, SBC, STA
(not ASL, DEC, LSR, ROL, ROR).

In th e case of zero-page indexed addressing, register X is the

legal displacem ent register, except for LDX and STX. Legal in­
stru ctio n s are: ADC, AND, ASL, CMP, DEC, EOR, INC, LDA,
LDY, LSR, ORA, ROL, ROR, SBC, STA, STY.
Indirect A ddressing (6502)
The 6502 does not have a fully general indirect addressing
capability. I t restricts th e address field to 8 bits. In other words,
all indirect addressing uses th e sub-mode of zero page addressing.
The effective address on w hich the opcode is to operate is th en th e
16 bits specified by the zero-page address of the instruction. Also,
no fu rth e r indirection m ay occur. This m eans th a t an address
retrieved from page zero m ust be used as is, and cannot be used as
a fu rth er indirection.
Finally, all indirect accesses m ust be indexed, except for JMP.
For fairness, it should be noted th a t very few microprocessors
provide any indirect addressing a t all. Further, it is possible to
im plem ent a m ore general indirect addressing using a m acro
definition.
Two modes of indirect addressing are possible: (pre) indexed indirect
addressing, and indirect indexed addressing (post-indexed), except
with JM P, which uses pure indirect.

Indexed Indirect Addressing

This mode adds the contents of index register X to th e zero-page
address to retrieve the final 16-bit address. This is an efficient way to
retrieve one of several possible data pointed to by pointers whose
number is contained in index register X. This is illustrated in Figure
5-4.
In this illustration, page zero contains a table of pointers. The
first pointer is a t the address A, which is p a rt of the instruction. If
the contents of X are 2N, then this instruction will access pointer
number N of this table and retrieve the d ata it is pointing to.
Indexed indirect addressing requires 6 cycles. It is n a tu ra lly
less efficient time-wise th a n any direct addressing mode. Its ad­
vantage is the flexibility which may result in coding, or the overall
speed improvement.
 Fig. 5-4: Pro-Indexed Indirect Addressing

Perm issible instructions are: ADC, AND, CMP, EOR, LDA,

ORA, SBC, STA.

Indirect Indexed Addressing

This corresponds to the post-indexing m echanism which has
been described in the preceding section. There, the indexing is
performed after the indirection, ra th e r th a n before. In other
words, the sh o rt address w hich is p a rt of the instructions is used
to access a 16-bit pointer in page zero. The contents of index
reg ister Y are th en added as a displacem ent to th is pointer. The
final data are then retrieved, (see Fig. 5-2.)
In th is case, th e pointer contained in page zero indicates the
base of a table in the memory. Index register Y provides a dis­
placem ent. I t is a tru e index w ithin a table. This instruction is
particularly powerful for referring to the n th elem ent of a table,
provided th a t the s ta rt address of the table is saved in page zero.
I t can do so in ju s t tw o bytes.
Legal instructions are: ADC, AND, CMP, EOR, LDA, ORA, SBC,
STA.

Exception: Jum p Instruction.

The jum p instruction m ay use indirect absolute. I t is th e only
instruction th a t m ay use th is mode.

USING THE 6502 ADDRESSING MODES

Long and Short A ddressing

We have already used b ranch instructions in various program s
th a t we have developed. They are self explanatory. One in te rest­
ing question is: w hat can we do if th e perm issible range for
branching is not sufficient for our needs? One sim ple solution is to
use a so-called long branch. T his is sim ply a branch to a location
w hich contains a jum p specification:
BCC + 3 BRANCH TO CURRENT ADDRESS
+ 3 IF C CLEAR
JM P FAR OTHERWISE JU M P TO FAR
(NEXT INSTRUCTION)
The two-line program above will re su lt in branching to location
F A R whenever th e carry is set. This solves our long branch
problem. Let us therefore now consider the more complex addres­
sing modes, i.e. indexing and indirection.

U se o f in d exin g for seq u en tial b lock a ccesses

Indexing is prim arily used to address successive locations
w ithin a table. The restriction is th a t th e m axim um displacem ent
m u st be less th a n 256 so th a t it can reside in a n 8-bit index
register.
We have learned to check for the character Now we will
search a table of 100 elem ents for th e presence of a The s ta r t­
ing address for th is table is called BASE. The table has only 100
elem ents. I t is less th a n 256 and we can use a n index register. The
program appears below:
 SEARCH LDX #0
NEXT LDA BASE, X
CMP r*
BEQ STARFOUND
INX
CPX #100
BNE NEXT
NOTFOUND . . .

STARFOUND ...

The flowchart for this program appears in Figure 5-5. The equiva­
lence between the flowchart and the program should be verified.
The logic of th e program is quite simple. R egister X is used to
point to the elem ent w ithin th e table. The second instruction of
th e program :

NEXT LDA BASE, X

uses absolute indexed addressing. It specifies th a t the accum u­

lato r is to be loaded from th e address BASE (16-bit absolute ad­
dress) plus contents of X. A t the beginning, th e contents of X are
”0.” The first elem ent to be accessed will be th e one a t address
BASE. It can be seen th a t after the next iteration, X will have the
value "1,” and th e next sequential elem ent of th e table will be
accessed, a t address BASE + 1.

The third instruction of the program, CMP compares the value

of the character which has been read in the accumulator with the code
for The next instruction tests the results of the comparison. If a
match has been found, the branch occurs to the label STARFOUND:

BEQ STARFOUND

Otherw ise, the n ext sequential instruction is executed:

INX
The index counter is increm ented b y 1. We find by inspecting the
bo tto m of the flow-chart of Figure 5.5 th a t the value of our index
reg ister a t th is point m u st be checked to m ake sure th a t we are
n o t going beyond the bounds of th e table (here 100 elements).
T his is im plem ented by th e following instruction:
CPX # 1 0 0

STARFOUND

NOT FOUND

Fig. 5-5: Character Searching Table

This instruction compares register X to the value $100. If the te st

fails we m ust again fetch the next character. This is w hat occurs
with:
BNE NEXT
This instruction specifies a branch to th e label NEXT if the te st
h as failed (the second instruction in our program ). This loop will
be executed as long as a is not found, or as long as the value
"100” is not reached in th e index. Then the nex t sequential in­
struction to be executed will be "NOT FOUND”. It corresponds to
the case where a has not been found.
The actions tak e n for found and not found are irrelevant
here and would be specified by the programmer.
W e have learned to use th e indexed addressing mode to
access successive elem ents in a table. L et us now use th is new
skill and slightly increase the difficulty. W e will develop an im­
p o rtan t u tility program , capable of copying a block from one area
of the memory into another. We will initially assume that the
num ber of th e elem ents w ith in the block is less th a n 256 so th a t
we can use index register X. Then we will consider the general
case w here the num ber of elem ents in th e block is greater th a n
256.

A Block Transfer Routine fo r less than 256 elements

We will call "NUMBER” th e num ber of elem ents in the block to
be moved. . The number is assumed to be less than 256. BASE is
the base address of the block. DESTINATION is the base of the
memory area where it should be moved. The algorithm is quite simple:
we will move a word at a time, keeping track of which word we are
moving by storing its position in index register X. The program
appears below:
LDX #N U M BER
NEXT LDA BASE, X
STA DEST, X
DEX
BNE NEXT
L et us exam ine it:
LDX # NUMBER

This line of the program loads the number N of words to be trans­

ferred in the index register. The next instruction loads word # N of
th e block w ithin th e accum ulator and the th ird instruction depo­
sits it into the destination area. See Figure 5-6.

CAUTION: th is program will work correctly only if th e base

pointer is assum ed to point ju s t below the block, ju st like the
destination register. O therw ise a sm all ad ju stm en t to th is
program is needed.
 A fter a word has been transferred from the origin to th e desti­
nation area, th e index register m ust be updated. This is per­
form ed by the instruction D EX , which decrem ents it. Then the
program simply tests whether X has decremented to O. If so, the
program terminates. Otherwise, it loops again by going bade to
location NEXT.
You will notice th a t w hen X = 0, th e program does not loop.
Therefore, it w ill not tra n sfe r the word a t location BASE. The la st
word to be transferred will be a t BA SE+1. This is why we have
assum ed th a t th e base was ju s t below th e block.

Exercise 5.1: M odify the program above, assum ing th a t

B A S E and D E S T p o in t to the firs t entry in the block.

This program also illu strates th e use of loop counters. You will
notice th a t X has been loaded w ith the final value, th en decre­
m ented and tested. A t first sight, it m ight seem sim pler to s ta rt
w ith “ 0 ” in X, and then increm ent it until it reaches the m axi­
m um value. However, in order to te s t w hether X has attain ed its
m axim um value, one e x tra in stru ctio n would be needed (the com­
parison instruction). This loop would then require 5 instructions
in stead of 4. Since this tran sfer program will norm ally be used for
large num bers of words, it is im p o rtan t to reduce the num ber of
instructions for th e loop. This is why, a t least for short loops, the
index register is norm ally decrem ented rather than increm ented

A Block Transfer Routine (more than 256 elements)

L et us now consider th e general case of moving a block which

m ay contain m ore th a n 256 elem ents. We can no longer use a
single index register as 8 b its do not suffice to store a num ber
g rea ter th a n 256. The m em ory organization for th is program is
illu strated in Figure 5-7. The length of the memory-block to be
transferred requires 16 bits, and therefore is stored in memory.
The high-order p a rt represents th e num ber of 256-word blocks:
"BLOCKS”. The rest is called "REMAIN” and is the num ber of
words to be transferred after all the blocks have been transferred.
The address for the source and th e destination will be m em ory
locations FROM and TO. L et us first assum e th a t REMAIN is
Fig. 5-7: Memory Map for General Block Transfer
 zero, i.e., th a t we are tran sferrin g 256 word blocks. The program
appears below:
LDA #SOURCELO
STA FROM
LDA #SOURCEHI
STA FROM +1 STORE SOURCE ADDRESS
LDA #DESTLO
STA TO
LDA #DESTHI
STA TO+1 STORE DEST ADDRESS
LDX #BLOCKS HOW MANY BLOCKS
LDY #0 BLOCK SIZE
NEXT LDA (FROM), Y READ ELEMENT
STA (TO), Y TRANSFER IT
DEY UPDATE WORD POINTER
BNE NEXT FINISHED?
NEXBLK INC FROM+1 INCREMENT BLOCK POINTER
INC TO+1 SAME
DEX BLOCK COUNTER
BMI DONE
BNE NEXT
LDY # REMAIN
BNE NEXT

The 16-bit source address is stored by the first four instructions at

m em ory address “ FR O M .” The n ext four instructions do the
same thing for the destination, which is stored a t address “TO”.
Since we have to tran sfer a num ber of words g rea ter th a n 256, we
will sim ply use two 8-bit index registers. The next instruction
loads register X w ith the num ber of blocks to be transferred. This
is instruction 9 in the program . The next instruction loads th e
value zero in index register Y in order to initialize it for the
tra n sfe r of 256 words. We will now use indexed indirect address­
ing. I t should be rem em bered th a t indexed indirect will resu lt
first in a n indirection w ithin page zero, th en an indexed access to
th e 16-bit address specified by the index register. Look a t th e
program :
NEXT LDA (FROM), Y
The instruction loads th e accum ulator w ith th e contents of th e
memory location whose address is the source plus the index regis­
te r Y’s contents. Look a t F igure 5-7 for th e mem ory map. H ere,
th e content of register Y is in itially 0. "A” will therefore be loaded
from memory address “SOURCE.” Note th a t here, unlike in our
previous example, we assum e th a t "SOURCE” is th e address of
th e first word w ith in the block.
U sing the sam e technique, th e next instruction will deposit th e
contents of th e accum ulator (the first word of the block we w an t to
transfer) a t the appropriate destination location:
STA (TO), Y
J u s t as in the preceding case, we simply decrement the index
register, th en we loop 256 tim es. This is im plem ented by th e
n ext tw o instructions:
DEY
BNE NEXT
Caution: a program m ing trick is used here for compact pro­
gram m ing. The a le rt reader w ill notice th a t th e index register Y
is decremented. The first word to be transferred will, therefore, be
th e word in position 0. The n ext one will be word 255. This is
because decrem enting 0 yields all l ’s in the reg ister (or 255). The
read er should also ascertain th a t th ere is no error. W henever
reg ister Y decrem ents to 0, a tran sfer w ill not occur. The next
instruction to be executed will be: NEXBLK. Therefore, exactly
256 words w ill have been transferred. C learly th is trick could
have been used in the previous program to w rite a shorter pro­
gram .
Once a complete block h as been transferred, it is sim ply a m a t­
te r of pointing to the next page w ithin our original block and our
destination block. This is accomplished by adding "1” to th e
higher order p a rt of the address for source and destination. This is
perform ed by th e next two instructions in th e program :

NEXBLK INC FROM +1

INC TO +1
After having incremented the page pointer, we simply check
w hether or not we should tra n sfe r one m ore block by decrem ent­
ing th e block counter contained in X. This is performed by:
DEX
If all blocks have been transferred, we exit from th e program by
branching to location DONE:
 BMI DONE
Otherw ise, we have two possibilities: E ith e r we have not de­
crem ented to 0 or else we have exactly decrem ented to zero. If we
have not yet decrem ented to 0, we branch to location NEXT:
BNE NEXT

If we have decrem ented exactly to 0, we still have to tran sfer

the words specified by REMAIN. This is the last part of our
transfer. This is accomplished by:
LDY #REM A IN
which loads index Y w ith th e tran sfer count.
We th en branch back to location NEXT:
BNE NEXT

The reader should ascertain that, during this last loop where
th e branch instruction to NEXT will be executed, th e n ext tim e
we re-enter NEXBLK, we will, indeed, exit for good from th is
program . This is because th e index X had th e value 0 prior to
en terin g NEXBLK. The th ird instruction of NEXBLK will
change it to —1, and we will exit to DONE.

Adding Two Blocks

This example will provide a simple illustration of the use of an

index register for the addition of tw o blocks of less th an 256
elem ents. Then, th e next program will m ake use of the indirect
indexed feature to address blocks whose address is known to re ­
side a t the given location, b u t whose actual absolute address is
not known. The program appears below:

BLKADD LDY #NBR -1 ------LOAD COUNTER

NEXT CLC
LDA PTRl, Y ------READ NEXT ELEMENT
ADC PTR2, Y ADD THEM
STA PTR3, Y STORE RESULT
DEY DECREMENT COUNTER
BPL NEXT FINISHED?
Index Y is used as a n index counter and is loaded w ith th e
num ber of elem ents m inus one. We assum e th a t pointer PTR1
points to th e first elem ent of Block 1, PTR2 to th e first elem ent of
Block 2, and PTR3 points to the destination a rea where th e re ­
sults should be stored.
The program is self-explanatory. The last element of Block 1 is
read in the accum ulator, th en added to the la st elem ent of Block
2. I t is th en stored a t the appropriate location of Block 3. The next
sequential elem ent is added, and so on.

Same Exercise Using Indexed Indirect A ddressing

We assum e here th a t th e addresses PTR1, PTR2, PTR3 are not
known initially. However, we know th a t they are stored in Page 0
a t addresses LO CI, LOC2, LOC3. This is a common m echanism
for passing inform ation betw een subroutines. The corresponding
program ap p ears below :
BLKADD LDY #N BR -1
NEXT CLC
LDA (LOCI), Y
ADC (LOC2), Y
STA (LOC3), Y
DEY
BPL NEXT
The correspondence between this new program and the previous
one should now be obvious. It illu strates clearly the use of the
indexed indirect m echanism w henever th e absolute address is not
known at the time that the program is written,but the location of the
information is known. It can be noted that the two programs
have exactly the sam e num ber of instructions. A n interesting
exercise is now to determ ine which one will execute faster.

Exercise 5.2: Com pute the num ber o f bytes a n d the num ber o f
cycles fo r each o f these two program s, using the tables in the A p ­
pen dix section.

SUMMARY
A complete description of addressing modes h as been presented.
It has been shown that the 6S02 offers most of the possible mecha­
nisms, and its features have been analyzed. Finally, several ap­
plication program s have been presented to dem onstrate the value
of each of th e addressing m echanism s. Program m ing the 6502
requires an understanding of these m echanism s.
EXERCISES

5.3: W rite a program to add the firs t 10 bytes o f a table stored a t

location “B A SE . ” The result will have 16 bits. (This is a
checksum computation).
5.4: Can you solve the same problem w ithout using the indexing
mode?
5.5: Reverse the order o f the 10 bytes o f this table. Store the re­
su lt a t address “R E V E R . ”
5.6: Search the same table for its largest element. Store it a t
memory address “LA R G E . ”
5.7: A d d together the corresponding elem ents o f three tables,
whose bases are B A SE 1, B A SE 2, BA SE3. The length o f
these tables is stored in page zero a t address “LEN G TH . ”
INPUT/OUTPUT TECHNIQUES

INTRODUCTION
We have learned so far how to exchange information between the
m emory and th e various registers of the processor. We have
learned to m anage the registers and to use a variety of instruc­
tions to m anipulate the data. We m ust now learn to comm unicate
w ith the external world. This is called the input/output.
Input refers to the capture of d a ta from outside peripherals
(keyboard, disk, or physical sensor). Output refers to the tran sfer
of d a ta from th e microprocessor or the memory to external devices
such as a printer, a CRT, a disk, or actual sensors and relays.
We w ill proceed in two steps. First, we will learn to perform the
input/output operations required by common devices. Second, we
will learn to m anage several input/output devices simultaneously,
i.e., to schedule them . This second p a rt will cover, in particular,
polling vs. interrupts.

INPUT/OUTPUT
In th is section we will learn to sense or to generate simple
signals, such as pulses. Then we will study techniques for enforc­
ing or m easuring correct tim ing. We will th en be ready for more
complex types of input/output, such as high-speed serial and par­
allel transfers.
Generate a Signal
In the sim plest case, an output device will be tu rn ed off (or on)
from the computer. In order to change the sta te of the output
device, the program m er will m erely change a level from a logical
"0” to a logical "1”, or from "1” to "0”. Let us assum e th a t an
external relay is connected to bit "0” of a register called "OUT1.”
In order to tu rn it on, we will sim ply w rite a "1” into the appropri­
a te b it position of the register. We assum e here th a t OUT1 repre­
sents th e address of this output register w ithin our system. The
program which will tu rn the relay on is:
TURNON LDA #% 00000001
STA OUT1

We have assum ed th a t th e state of the other 7 bits of the regis­

te r OUT1 is irrelevant. However, th is is often not the case.
These b its m ight be connected to other relays. L et us, therefore,
improve th is sim ple program . We w ant to tu rn the relay on, w ith­
out changing th e sta te of any other b it w ithin th is register. We
will assum e th a t it is possible to read and w rite the contents of
th is register. O ur improved program now becomes:

TURNON LDA OUT1 READ CONTENTS OF OUT1

ORA #% 00000001 FORCE BIT 0 TO "1”
STA OUT1
The program first reads the contents of location OUT1, then
perform s an inclusive OR on its contents. This changes only b it
position 0 to “ 1” , and leaves the re s t of the register intact. (For
m ore details on the ORA operation, refer to C hapter 4). This is
illustrated by Figure 6-1.

Pulses
G enerating a pulse is accom plished exactly as in the case of
the level above. A n output bit is first turned on, then later turned
off. This results in a pulse. This is illustrated in Figure 6*2. This
tim e, however, a n additional problem m ust be solved: one m ust
generate the pulse for the correct length of tim e. Let us, therefore,
study the generation of a computed delay.
 BEFORE AFTER

OU T 1

Fig. 6-1: Turning on a Relay

OUTPUT PORT
REGISTER

SIGNAL

CPU

, HE PROGRAM: S E U C . & U T P U . W „ H PATTERN

WAIT (LOOP FOR N U S EC )
LOAD OUTPUT PORT WITH ZERO
RETURN

Fig. 6-2: A Programmed Pulse

Delay Generation and Measurement

A delay m ay be generated by software or by hardw are methods.
We w ill study here the way to perform it by program , and la te r
show how it can also be accomplished w ith a hardw are counter,
called a program m able in terv al tim er (PIT).
Program m ed delays are achieved by counting. A counter regis­
te r is loaded w ith a value, th en is decremented. The program
loops on itself and keeps decrem enting u n til th e counter reaches
th e value "0”. The total length of tim e used by th is process will
im plem ent the required delay. As a n example, let us generate a
delay of 37 microseconds.
DELAY LDY # 0 7 Y IS COUNTER
NEXT DEY DECREMENT
BNE NEXT TEST
This program loads index register Y w ith th e value 7. The next
instruction decrem ents Y, and th e next instruction will cause a
branch to NEXT to occur as long as Y does not decrem ent to "0.”
W hen Y finally decrem ents to zero, the program will exit from
th is loop and execute w hatever instruction follows. The logic of
the program is simple and appears in the flow c h art of Figure 6-3.

OUT
Fig. 6-3: A Delay Flowchart

L et us now com pute the effective delay which will be im ­

plemented by the program. Looking a t the Appendix section of the
book, we will look up the num ber of cycles required by each of
these instructions:
LDY, in th e im m ediate mode, requires 2 cycles. DEY will use 2
cycles. Finally, BNE will use 3 cycles. W hen looking up th e
num ber of cycles for BNE in the table, verify th a t 3 possibilities
exist; if the branch does not occur, BNE will only require 2 cycles.
If th e branch does succeed, which will be the norm al case during
th e loop, th en one more cycle is required. Finally, if the page
boundary is being crossed, th en one ex tra cycle will be required.
We assum e here th a t no page boundary will be crossed.
The tim ing.is, therefore, 2 cycles for the first instruction, plus 5
cycles for the next 2, m ultiplied by the num ber of tim es the loop
will be executed, minus one cycle for the last BNE:
Delay = 2 + 5 x 7 - 1 = 36.
A ssum ing a 1-microsecond cycle tim e, th is program m ed delay
will be 36 microseconds.
W e can see th a t the m axim um definition w ith which we can
a d ju st th e length of the delay is 2 m icroseconds. The m inim um
delay is 2 microseconds.
E xercise 6.1: W hat is the m axim um delay which can be im ple­
m en ted w ith these three in stru ction s? Can you m odify the p ro ­
gram to obtain a one m icrosecond delay?
E xercise 6.2: M o d ify the program to obtain a delay o f abou t 100
m icroseconds .
If one wishes to im plem ent a longer delay, a sim ple solution is
to add ex tra instructions in th e program , betw een DEY and BNE.
The sim plest w ay to do so is to add NO P instructions. (The
NO P does nothing for 2 cycles).

L onger D elays
G enerating longer delays by software can be achieved by using
a w ider counter. Two in tern al registers, or, better, two words in th e
memory, can be used to hold a 16-bit count. To simplify, le t us
assum e th a t th e lower count is ”0.” The lower byte will be loaded
w ith ”255,” the m axim um count, th en go through a decrem enta­
tion loop. W henever it is decrem ented to ”0,” the upper byte of th e
counter will be decrem ented by 1. W henever the upper byte is
decrem ented to the value ”0,” the program term inates. If more
precision is required in the delay generation, th e lower count can
have a non-null value. In th is case, we would w rite the program
ju st as explained and add a t the end the three-line delay genera­
tion program , which has been described above.
N aturally, still longer delays could be generated by using more
th a n two words. This is analogous to the way an odometer works
on a car. W hen th e right-m ost wheel goes from ”9” to ”0,” th e next
wheel to the left is increm ented by 1. This is the general principle
when counting with multiple discrete units.
However, the m ain objection is th a t when one is counting long
delays, th e microprocessor will be doing nothing else for hundreds
of milliseconds or even seconds. If the com puter has nothing else
to do, th is is perfectly acceptable. However, in th e general case,
the m icrocom puter should be available for other task s so th a t
longer delays are norm ally not im plem ented by software. In fact,
even short delays m ay be objectionable in a system if i t is to
provide some guaranteed response tim e in given situations.
H ardw are delays m ust th e n be used. In addition, if in terru p ts are
used, tim ing accuracy m ay be lost if the counting loop can be
interrupted.

E xercise 6.3: W rite a program to im plem en t a 100 m s dela y (for a

Teletype).

H ardw are D ela y s

H ardw are delays are im plem ented by using a program m able
interval timer, or “ timer” for short. A register of the timer is loaded
with a value. The difference is that, this time, the timer will
autom atically decrem ent th is counter periodically. The period is
usually adjustable or selectable by the programmer. W henever
the tim er will have decrem ented to "0,” it will norm ally send an
in te rru p t to the microprocessor. I t m ay also set a sta tu s b it which
can be sensed periodically by the computer. The use of in te rru p ts
will be explained la te r in th is chapter.
O ther tim er operating modes m ay include sta rtin g from "0” and
counting the duration of th e signal, or else counting the num ber
of pulses received. W hen functioning as an interval tim er, the
tim er is said to operate in a one-shot mode. W hen counting pulses,
it is said to operate in a pulse-counting mode. Some tim er devices
m ay even include m ultiple registers and a num ber of optional
facilities which are program -selectable. This is the case, for
example, with the tim ers contained in the 6522 component, an I/O
chip described in the n ex t chapter.

Sensing P u lses
The problem of sensing pulses is th e reverse problem of gener­
a tin g pulses, plus one m ore difficulty: w hereas an o u tp u t pulse is
generated under program control, in p u t pulses occur asynchron­
o u sly w ith th e program . In order to detect a pulse, tw o m ethods
m ay be used: pollin g and in terru pts. In te rru p ts will be discussed
late r in th is chapter.
Let us consider now th e polling technique. Using this technique,
the program reads the value of a given inp u t register continu­
ously, testing a b it position, perhaps b it 0. I t will be assumed th a t
bit 0 is originally “ 0 .” Whenever a pulse is received, this bit will
take the value “ 1.” The program m onitors b it 0 continuously until
it tak es th e value ”1.” W hen a "1” is found, the pulse has been
detected. The program appears below:

POLL LDA #$01

AGAIN BIT IN PU T
BEQ AGAIN
ON
Conversely, le t us assum e th a t the inp u t line is norm ally "1”
and th a t we w ish to detect a ”0.” This is the norm al case for
detecting a START bit when monitoring a line connected to a
Teletype. The program appears below:
POLL LDA #$01
NEXT BIT IN PU T
BNE NEXT
START ...

M onitoring th e D uration

M onitoring th e duration of the pulse m ay be accomplished in

the sam e way as com puting th e duration of an output pulse.
E ith e r a hardw are or a software technique m ay be used. W hen
m onitoring a pulse by software, a counter is regularly in­
crem ented by 1, th e n the presence of the pulse is verified. If the
pulse is still present, the program loops upon itself. W henever th e
pulse disappears, the count contained in the counter reg ister is
used to compute th e effective duration of th e pulse. The program
appears below
DURTN LDX #0 CLEAR COUNTER
LDA #$01 MONITOR BIT 0
AGAIN BIT IN PU T
BEQ AGAIN
LONGER INX
BIT IN PU T
BNE LONGER
Naturally, we assum e th a t the maximum duration of the pulse
will n o t cause register X to overflow. If th is were th e case, th e
program would have to be longer to ta k e this into account (or else
it would be a program m ing error!)
Since we now know how to sense and generate pulses, le t us
capture or tran sfer larg er am ounts of data. Two cases w ill be
distinguished: serial d a ta and parallel data. Then we will apply
th is knowledge to actual in p u t/o u tp u t devices.

Fig. 6-4: Parallel Word Transfer: The Memory

PARALLEL WORD TRANSFER

I t is assum ed here th a t 8 b its of tran sfer d a ta are available in
parallel a t address "INPUT.” The microprocessor m ust read the
d a ta word a t th is location w henever a sta tu s word indicates th a t
it is valid. The status information will be assumed to be contained
in b it 7 of address “ STA TU S.” W e will here w rite a program
which will read and autom atically save each word of d a ta a s it
comes in. To simplify, we will assum e th a t the num ber of words
to be read is know n in advance and is contained in location
“COUNT.” If this information were not available, we would te st
for a so-called break character, such a s a rubout, or perhaps th e
character W e have learned to do th is already.

PO LLING OR SERVICE REQUEST

OUT

Fig. 6-5: Parallel Word Transfer: Flowchart

The flowchart appears in Figure 6-5. I t is quite straightfor­

ward. We test the status information until it becomes “1,” indi­
cating th a t a word is ready. W hen the word is ready, we read
it and save it a t an appropriate memory location. We decre­
m ent the counter and then te st whether it has decremented to
“0.” If so, we are finished; if not, we read the next word. The
program which im plem ents th is algorithm appears below:
PARAL LDX COUNT COUNTER
WATCH LDA STATUS BIT 7 IS "1” IF DATA VALID
BPL WATCH DATA VALID?
LDA INPU T READ IT
PH A SAVE IT IN THE STACK
DEX
BNE WATCH
The first two instructions of th e program read the statu s infor­
m ation and cause a loop to occur as long as bit 7 of the status
register is “ 0 .” (It is th e sign bit, i.e. b it N ).
WATCH LDA STATUS
BPL WATCH
W hen BPL fails, d ata is valid and we can read it:
LDA INPU T
The word h as now been read from address IN PU T where it was,
and must be saved. Assuming that the number of words to be trans­
ferred is small enough, we use:
PHA
If the stack is full, or the number of words to be transferred is large,
we could not push them on the stack and we would have to transfer
them to a designated memory area, using, for example, an indexed
instruction. However, this would require an extra instruction to in­
crement or decrement the index register. PHA is faster.
The word of data has now been read and saved. We will simply
decrement the word counter and test whether we are finished:

DEX
BNE WATCH
We keep looping until the counter eventually decrements to “ 0 . ”
This 6-instruction program can be called a benchmark. A benchmark
program is a carefully optimized program designed to test the cap­
abilities of a given processor in a specific situation. Parallel trans­
fers are one such typical situation. This program has been designed
for maximum speed and efficiency. Let us now compute the maximum
transfer speed of this program. We will assume that COUNT is con­
tained in page 0. The duration of every instruction is determined by
inspecting the table at the end of the book and is found to be the
follow ing:
CYCLES
LDX COUNT 3
WATCH LDA STATUS 4
BPL WATCH 2 /3 (FAIL/SUPCEED)
LDA INPUT 4
PHA 3
DEX 2
BNE WATCH 2 /3 (FAIL/SUCCEED)
The m inim um execution tim e is obtained by assum ing th a t
d ata is available every tim e th a t we sam ple STATUS. In other
words, the first BPL will be assum ed to fail every tim e. Tim ing is
then: 3 + (4 + 2 + 4 + 3 + 2 + 3 ) x COUNT.
N eglecting the first 3 microseconds necessary to initialize the
counter register, the tim e used to tran sfer one word is 18 m i­
croseconds.
The m axim um d a ta tra n sfe r ra te is, therefore,
— -— = 55 K b y tes per second.
18(10-6)

E x e rc is e 6.4: A ssum e that the number o f words to be transferred

is greater than 256. M odify the program accordingly and deter­
mine the impact on the m axim um data transfer rate.
We have now learned to perform high-speed parallel transfers.
Let us consider a more complex case.

B I T S E R IA L T R A N S F E R
A serial input is one in which the b its of inform ation (0's or
l ’s) come in successively on a line. These b its m ay come in a t
regular intervals. This is normally called synchronous transm is­
sion. Or else, they m ay come as bursts of d ata a t random inter­
vals. This is called asynchronous transmission. We will develop a
program which can work in both cases. The principle of th e cap­
tu re of sequential d a ta is simple: we will w atch an inp u t line,
which will be assumed to be line 0. When a bit of data is detected
on this line, we will read the bit in, and shift it into a holding reg­
ister. Whenever 8 b its have been assembled, we will preserve the
 PA G E 4

PA G E 1

STA TU S O R C LO C K
© SER IA L D ATA
INPUT

Fig. 6 6: Serial to Parallel Conversion

byte of data into the m em ory and assem ble the next one. In order
to simplify, we will assum e th a t th e num ber of bytes to be received
is known in advance. Otherw ise, we m ight, for example, have to
w atch for a special break character, and stop the bit-serial
tran sfer a t th is point. We have learned to do th a t. The flow-chart
for this program appears in Figure 6-7. The program appears
below:
SERIAL LDA #$00
STA WORD
LOOP LDA INPUT BIT 7 IS STATUS, ”0” IS DATA
BPL LOOP BIT RECEIVED?
LSR A SHIFT IT INTO C
ROL WORD SAVE BIT IN MEMORY
BCC LOOP CONTINUE IF CARRY = "0”
LDA WORD
PHA SAVE ASSEMBLED BYTE
LDA #$01 RESET BIT COUNTER
STA WORD
DEC COUNT DECREMENT WORD COUNT
BNE LOOP ASSEMBLE NEXT WORD
 This program has been designed for efficiency and will use new
techniques which we will explain. (See Fig. 6-6.)
The conventions are the following: memory location COUNT is
assum ed to contain a count of the num ber of words to be tra n s ­
ferred. Memory location WORD will be used to assemble 8 con­
secutive bits coming in. Address IN PU T refers to an input regis­
ter. I t is assum ed th a t b it position 7 of th is register is a sta tu s flag,
or a clock bit. W hen it is "0,” d a ta is not valid. W hen it is ”1,” the
d a ta is valid. The d a ta itself will be assum ed to appear in b it
position 0 of th is sam e address. In m any instances, the sta tu s
inform ation will appear on a different register th a n th e d ata reg-
POLLING OR SERVICE REQUEST

DONE

Rg. 6-7: Bit Serial Transfer: Rowchart

 ister. I t should be a sim ple task, then, to modify th is program
accordingly. In addition, we will assum e th a t the first bit of data
to be received by this program is guaranteed to be a "1.” It indi­
cates th a t th e real d ata follows. If th is were not the case, we will
see la te r an obvious modification to tak e care of it. The program
corresponds exactly to the flowchart of Figure 6-7. The first few
lines of th e program im plem ent a w aiting loop which tests
w hether a b it is ready. Ib determ ine w hether a b it is ready, we
read the in put register th e n te st the sign b it (N). As long as th is
b it is ”0,” the instruction BPL will succeed, and we will branch
back to the loop. W henever the sta tu s (or clock) b it will become
tru e ("1”), th en BPL will fail and th e next instruction will be
executed.
Remember th a t BPL means “Branch on Plus,” i.e. when b it 7
(the sign bit) is “ 0.” This initial sequence of instructions corre­
sponds to arrow 1 on Figure 6-6.
A t this point, the accum ulator contains a "1” in bit position 7
and th e actual d a ta bit in b it position 0. The first d a ta bit to arrive
is going to be a "1.” However, th e following ones m ay be eith er "0”
or "1.” We now wish to preserve th e d a ta b it which has been
collected in position 0. The instruction:
LSR A
shifts th e contents of the accum ulator rig h t by one position. This
causes th e right-m ost b it of A, which is our d a ta bit, to fall into
the carry bit. We will now preserve this data bit into the memory
location WORD (this is illustrated by arrows 2 and 3 in Fig. 6-6):
ROL WORD.
The effect of th is instruction is to read the carry bit into the
right-m ost bit position of address WORD. At the sam e tim e, the
left-most b it of WORD falls into the carry bit. (If you have any
doubts about the rotation operation, refer to C hapter 4!)
It is im portant to rem em ber th a t a rotation operation will both
save the carry bit, here into the right-m ost b it position, and also
recondition the carry b it w ith the value of b it 7.
Here, a “ 0 ” will fall into the carry. The n ext instruction:
BCC LOOP
tests the can y and branches back to address LOOP as long as the
carry is “0.” This is our autom atic bit counter. I t can readily be
seen th a t as a resu lt of the first ROL, WORD will contain
”00000001” E ight shifts later, the ”1” will finally fall into th e
carry b it and stop the branching. This is an ingenious w ay to
im plem ent an autom atic loop counter w ithout having to w aste an
instruction to decrem ent the contents of an index register. This
technique is used in order to shorten the program and improve its
performance.
Whenever BCC finally fails, 8 bits have been assembled into lo­
cation WORD. This value should be preserved in the memory. This
is accom plished by the nex t instructions (arrow 4 in Fig. 6-6):
LDA WORD
PHA
We are here saving the WORD of data (8 bits) into the stack.
Saving it into th e stack is possible only if there is enough room in
the stack. Provided th a t th is condition is met, it is the fastest way
to preserve a word in th e memory. The stack pointer is updated
autom atically. If we were not pushing a word in th e stack, we
would have to use one m ore instruction to update a m emory
pointer. We could equivalently perform an indexed addressing
operation, b u t th a t would also involve decrem enting or incre­
m enting the index, using ex tra tim e.
A fter the first WORD of d a ta has been saved, th ere is no longer
any guarantee that the first data bit to come in will be a “ 1.” It can
be anything. We m ust, therefore, reset the contents of WORD to
”00000001” so th a t we can keep using it as a b it counter. This is
performed by the next two instructions:
LDA #$01
STA WORD
Finally, we will decrem ent the word counter, since a word has
been assembled, and te st w hether we have reached the end of th e
transfer. This is accomplished by th e next two instructions:
DEC COUNT
BNE LOOP
The above program has been designed for speed, so th a t one
m ay capture a fast input stream of d a ta bits. Once the program
term inates, it is n a tu ra lly advisable to im m ediately read away
from th e stack th e words' th a t have been saved th ere and tran sfer
them elsewhere into the memory. We have already learned to
perform such a block tra n sfe r in C hapter 2.

Exercise 6.5: ;Compute the m axim um speed at which this pro­

gram will be able to read serial bits. To compute this speed, as­
sume that addresses WORD and COUNT are kep t in Page 0. Also,
assume that the complete program resides within the same page.
Look up the number o f cycles required by every instruction, in the
table a t the end o f this book, then compute the time which will
elapse during execution o f this program. To compute the length
o f time which will be used by a loop, sim ply m ultiply the total
duration o f this loop, expressed in microseconds, by the number
o f times it will be executed Also, when computing the m aximum
speed assume that a data bit will be ready every time that the in­
p u t location is sensed
This program is more difficult to understand than the previous
ones. Let us look at it again (refer to Figure 6-6) in more detail,
examining some trade-offs.
A b it of d a ta comes into b it position 0 of “ IN P U T ” from
time to time. There might be, for example, three “ l ’s” in succession.
We m ust, therefore, differentiate between the successive bits com­
ing in. This is th e function of the “ clock” signal.
The clock (or STATUS) signal tells us that the input bit is
now valid.
Before reading a bit, we will therefore first test the status bit.
If the s ta tu s is “ 0 ” , we m u st wait. If i t i s “ l ” , then the d a ta
b it is good.
We assume here that the status signal is connected to bit 7
of register INPUT.

Exercise 6.6: Can you explain why bit 7 is used for status, and
bit 0 for data?

Once we have captured a d a ta bit, we w ant to preserve it in

a safe location, th en shift it left, so th a t we can g e t the n ext bit.
Unfortunately, the accumulator is used to read and test both data
and status in this program. If we were to accumulate data in the
accumulator, bit position 7 would be erased by the status bit.

Exercise 6.7: Can you suggest a way to test status w ithout eras­
ing the contents o f the accumulator (a special instruction)? I f this
can be done, could we use the accumulator to accumulate the suc­
cessive bits coming in?

Exercise 6.8: Re-write the program, using the accumulator to

store the bits coming in. Compare it to the previous one in terms
o f speed and number o f instructions.

Let us address two more possible variations:

We have assumed that, in our particular example, the very first bit to
come in would be a special signal, guaranteed to be “ 1 However, in
the general case, it may be anything.

Exercise 6.9: M odify the program above, assuming that the very
first bit to come in is valid data (not to be discarded), and can be
“0 ” or “I ."H int: our “bit counter" should still work correctly,
if you initialize it with the correct value.

Finally, we have been saving the assembled WORD in the stack, to

gain time. We could naturally save it in a specified memory area:

Fvgrrigp 6.10: M odify the program above, and save the assem­
bled WORD in the memory area starting a t BA SE.

Exercise 6.11: M odify the program above so that the transfer

will stop when the character “S " is detected in the input stream.

The Hardware Alternative

As usual for m ost stan d ard in p u t/output algorithm s, it is possi­
ble to implement this procedure by hardware. The chip is called a
UART. I t will autom atically accum ulate th e bits. However, w hen
one wishes to reduce the component count, th is program , or a
variation of it, will be used instead.

6.12: M odify the program assuming that data is avail­

able in bit position 0 o f location INPUT, while the status informa­
tion is available in bit position 0 o f address IN P U T + 1.
BA SIC I/O SUMMARY
W e have now learned to perform elem entary in p u t/output op­
erations as well as to m anage a stream of parallel d a ta or serial
bits. We are ready to communicate with real input/output devices.

COMMUNICATING WITH INPUT/OUTPUT DEVICES

In order to exchange d a ta w ith inp u t/o u tp u t devices, we will
first have to ascertain w hether d a ta is available, if we w ant to
read it, or w hether the device is ready to accept data, if we w ant to
send it. Two procedures m ay be used: handshaking and inter­
ru p ts. L et us stu d y handshaking first.

Handshaking
H andshaking is generally used to com m unicate betw een any
two asynchronous devices, i.e., betw een any two devices which
are not synchronized. For example, if we w ant to send a word to a
parallel prin ter, we m ust first m ake sure th a t the input buffer of
th is p rin te r is available. We will, therefore, ask the printer: Are
you ready? The printer will say “yes” or “no.” If it is not ready we
will wait. If it is ready, we will send the data. (See Fig. 6-8.)

I/O CHIP

Fig. 6-8: Handshaking (Output)

Conversely, before reading d a ta from an inp u t device, we will

verify w hether the d a ta is valid. We will ask: "Is d a ta valid?” And
the device will tell us “yes” or “no.” The "yes” or "no” m ay be
indicated by sta tu s bits, or by other means. (See Fig. 6-9.)
 Fig. 6-9: Handshaking (Input)

In short, w henever you w ish to exchange inform ation w ith

someone who is independent and m ight be doing som ething else
a t th e tim e, you should ascertain th a t he is ready to comm unicate
w ith you. The usu al courtesy rule is to shake his hand. D ata
exchange m ay th en follow. This is the procedure norm ally used in
com m unicating w ith inp u t/o u tp u t devices.
L et us illu strate th is procedure now w ith a simple example:

Sending a Character To The Printer

The character will be assum ed to be contained in mem ory loca­
tion CHAR. The program to p rin t it appears below:
CHARPR LDX CHAR READ CHARACTER
WAIT LDA STATUS BIT 7 IS "READY”
BPL WAIT
TXA
STA PRINTD
R egister X is first loaded from the mem ory w ith a character to
be printed. Then we te st th e sta tu s b it of th e p rin te r to determ ine
th a t it is ready to accept th e character. As long as it is not ready to
print, however, we branch back to address WAIT, and we loop.
W henever the p rin te r indicates th a t it is ready to p rin t by settin g
its ready-bit (here b it 7 b y convention of address STATUS), we
can send the character. We transfer the character from register X
to register A:
TXA
and we send it to the p rin te r’s output register address, called here
PR IN TD .
STA PRINTD

Exercise 6.13: M odify the program above to p rin t a string o f n

characters, where n will be assum ed to be less than255.

Exercise 6.14: M odify the above program to prin t a string of

characters until a “carriage-return ” code is encountered
L et us now complicate the output procedure by requiring a code
conversion and by outputting to several devices at a time:

A / A /

Fig. 6-10: Seven Segment LEO

O utput to a 7-Segm ent LFX>

A traditional 7-segm ent light-em itting-diode (LED) m ay dis­
play th e digits "0” through "9,” or even ”0” through "F” hexadec­
im al by lighting com binations of its 7 segm ents. A 7-segm ent
LED is shown in illustration 6-10. The characters that may be gen­
erated with this LED appear in Figure 6-11. The segments of an LED
ARE LABELLED “ A” through “ G” in Figure 6-10.
F or example, "0” will be displayed by lighting the segm ents
“ABCD EF.” Let us assume, now, th a t b it “0" of an output port is
connected to segment “A ,” th a t “ 1” is connected to segment “B,”
and so on. B it 7 is not used. The binary code required to light up
“ FE D C B A ” (to display “ 0 ” ) is, therefore, “ 0111111.” In hexa­
decimal this is “ 3 F .” Do the following exercise.

/ / / / / /
•/ / / r j _/ /
r i n niun
•/ 7
o o
0 /_ i ir r
1 I /_/ /_ u i_ i
Fig. 6-11: Characters Generated with a 7-Segment LED

E x e rc is e 6.15: Compute the 7-segment equivalent for the hexa­

decimal digits “0 ” through “F. "F ill out the table below:

Hex LED code Hex LED code Hex LED code Hex LED code
0 ifr 4 8 C
1 5 9 D
2 6 A E
3 7 B F
Let us now display hexadecim al values on several LEDs.

D riv in g M u ltip le L E D s
An LED h as no memory. It will display th e d a ta only as long as
its segment lines are active. In order to keep the cost of an LED
display low, the microprocessor will display information in turn
on each of the LEDs. The rotation between the LED s m ust be fast
enough so th a t there is no apparent blinking. This implies th a t
the tim a spent from one LED to the next is less than 100 milli­
seconds. Let us design a program which will accomplish this.
R egister Y will be used to point to th e LED on which we w ant to
display a digit. The accum ulator is assum ed to contain th e
hexadecim al value to be displayed on the LED. O ur first concern
is to convert th e hexadecim al value into its 7-segm ent repre­
sentation. In th e preceding section, we have bu ilt the equivalence
table. Since we are accessing a table, we will use the indexed
addressing mode, w here the displacem ent index will be provided
by the hexadecim al value. This m eans th a t the 7-segm ent code for
hexadecim al digit # 3 is obtained by looking up th e th ird elem ent
of th e table after th e base. The address of the base will be called
SEGBAS. The program appears below:
LEDS TAX U SE H E X VALUE AS INDEX
LDA SEGBAS,X READ CODE IN A
LDX #$00
STX SEGDAT TURN OFF SEGMENT DRIVERS
STA SEGDAT DISPLAY DIGIT
LDX #$70 ANY LARGE NUMBER
STY SEGADR
DELAY DEX
BNE DELAY
DEY POINT TO NEXT LED
BNE OUT
LDY LEDNBR
OUT RTS

The program assumes th at register Y contains the number of the

LED to be illuminated next, and th a t register X contains the digit.
to be displayed.
The program first looks up the 7-segm ent code corresponding to
th e hexadecim al value contained in th e accum ulator w ith its first
two instructions. The next two instructions load "00” as the value
of th e segm ents to be displayed, i.e., tu rn them off. The next
instruction then selects the appropriate LED segments for dis­
play: STY SEGADR.
A three-instruction loop delay is th en im plem ented before
sw itching to the next LED. Finally, the LED pointer is de­
crem ented. (It could be increm ented).
If th e LED pointer decrem ents to "0,” it m ust be reloaded w ith
the highest LED num ber. T his is accomplished by th e next two
instructions. I t is assum ed here th a t th is is a subroutine and th e
last instruction is an RTS: “ return from subroutine.”
 STOP1ST0P2
H— h
MARK-------- --
SPACE----------- 1
nnBUHtroa
USB

9.09 ms

Fig. 6-12: Format of a Teletype Word

Exercise 6.16: Assum ing that the above program is a subroutine,

you will notice that it uses registers X and Y internally and mod -
ifies their contents. A ssum ing that the subroutine may freely use
the memory area designated by address T1, T2, T3, T4, T5, could
you add instructions at the beginning and at the end o f this pro­
gram which will guarantee that, when the subroutine returns, the
contents o f registers X and Y will be the same as when the sub­
routine was entered?
Exercise 6.17: Same exercise as above, but assume that the
memory area Tl, etc. is not available to the subroutine. (Hint: re­
member that there is a built-in mechanism in every computer for
preserving information in a chronological order).
We have now solved common in p ut/ou tput problems. Let us
consider the case of a real peripheral: th e Teletype.

Teletype Input/Output
The Teletype is a serial device. I t both sends and receives words
of inform ation in a serial form at. Each character is encoded in ah
8-bit ASCII format (the ASCII table appears at the end of this
book). In addition, every character is preceded by a "sta rt” bit,
and term inated by two "stop” bits. In th e so-called 20-milliam p
cu rren t loop interface, w hich is m ost frequently used, th e sta te of
the line is norm ally a "1.” This is used to indicate to the processor
th a t the line has not been cut. A s ta rt is a " l ”-to-"0” transition. It
indicates to the receiving device that data bits follow. The standard
Teletype is a 10-characters-per-second device. We have just es­
tablished that each character requires 11 bits. This means that
the Teletype will transm it 110 bits per second. I t is said to be a 110­
baud device. W e will design a program to serialize b its in from the
Teletype a t the correct speed.
One hundred and ten b its per second im plies th a t bits are sepa­
rated by 9.09 milliseconds. T his will have to be the duration of th e
delay loop to be im plem ented betw een successive bits. The form at
of a Teletype word appears in Figure 6-12. The flowchart for b it
input appears in Figure 6-13. The program follows:

TTYN LDA STATUS

BPL TTYIN USUAL STATUS POLL
JSR DELAY WAIT
LDA TTYBIT START BIT
STA TTYBIT ECHO BACK
JSR DELAY
LDX #$08 BIT COUNTER
NEXT LDA TTYBIT SAVE INPUT
STA TTYBIT ECHO BACK
LSR A SAVE BIT IN CARRY
ROL CHAR SAVE BIT IN CHAR
JSR DELAY
DEX NEXT BIT
BNE NEXT
LDA TTYBIT STOP BIT
STA TTYBIT
JSR DELAY
RTS

Fig. 6-14: Input from Teletype

Note that this program differs slightly from the flowchart of Fig. 6-13.
 The program should be examined with attention. The logic is quite
simple. The new fact is that, whenever a bit is read from the Tele­
type (at address TTYBIT), it is echoed back to the Teletype. This
is a standard feature of the Teletype. Whenever a user presses a key,
the information is transmitted to the processor and then back to the
printing mechanism of the Teletype. This verifies that the transmis­
sion lines are working and that the processor is operating when a
character is, indeed, printing correctly on the paper.

MEMORY + I/O

Fig. 6-15: Teletype Input

The first two instructions are the waiting loop. The program waits
for the status bit to become true before it starts reading bits in.
As usual, the status bit is assumed to come in bit position 7,
since this position can be tested in one instruction by BPL (Branch
on Plus-this is the sign bit).
JS R is the subroutine jum p. We use a DELAY subroutine to
implement the 9.09 ms delay. Note that DELAY can be a delay loop,
or can use the hardware timer, if our system has one.
The first bit to come in is the start bit. It should be echoed to the
Teletype, but otherwise ignored. This is done by instructions 4 and 5.
Again, we wait for the next bit. But, this time, it is a true
data bit, and we must save it. Since all shift instructions will
drop a bit in the carry flag, we need two instructions to preserve
our data bit (the X in Figure 6-15): one to drop it into C(LSR A),
and one to preserve it into m em ory location CH A R (ROL).
Beware of one problem: th e “ RO L” will destroy the contents of
C. If we w ant to echo th e d a ta b it back, a precaution m u st be ta k ­
en to preserve it before it disappears into CHAR. Finally, we echo
the d a ta b it (STA TTYBIT) and w ait for the n ext one (JSR
DELAY) until we accum ulate all eight d a ta b its (DEX).
W henever we decrem ent to zero, all 8 b its are in CHAR. We
ju s t have to echo the STO P bits, and we are finished.

Exercise 6.18: Write the delay routine which results in the 9.09
millisecond delay. (D ELAY subroutine)

Fig. 6-16: Teletype Output

E xercise 6.19: Using the example o f the program developed
above, write a P R IN TC program which will p rin t on the Teletype
the contents o f memory location CHAR.
E xercise 6.20: M odify the program so that it waits for a S T A R T
bit instead o f a STATU S bit.

P rinting a String o f C haracters

We will assume that the PRINTC routine (see Exercise 6-18)

takes care of printing a character on our printer, display, or any
output device. We will here p rin t th e contents of m em ory loca­
tions START + N to START.
We will naturally use the indexed addressing mode and the
program is straight-forward:
PSTRING LDX #N NUMBERS OF WORDS
NEXT LDA START+N
JS R PRINTC
DEX
BPL NEXT
MEMORY

Fig. 6-17: Print a Memory Block

P E R IPH E R A L SUM M ARY

We have now described th e basic program m ing techniques used
to com m unicate w ith typical input/o u tp u t devices. In addition to
th e d a ta transfer, it will be necessary to condition one or more
control registers w ithin each I/O device in order to condition cor­
rectly th e tran sfer speeds, th e in te rru p t m echanism , and th e v ar­
ious other options. The m anual for each device should be con­
sulted. (For m ore details on th e specific algorithm s to exchange
inform ation w ith all the usu al peripherals, the read er is referred
to our book,"C207, Microprocessor Interfacing Techniques.” )
We have now learned to m anage single devices. However, in a
real system , all peripherals are connected to the busses, and m ay
request service sim ultaneously. How are we going to schedule the
processor’s tim e?

INPUT/OUTPUT SCHEDULING
Since in p u t/output requests m ay occur sim ultaneously, a
scheduling m echanism m ust be im plem ented in every system to
determ ine in which order service will be granted. Three basic
in p u t/o u tp u t techniques are used, which can be combined.
They are: polling, in te rru p t, DM A. Polling and in te rru p ts
will be described here. DM A is purely a hardw are tech-
nique, and a s such will no t be described here. (It is covered in
th e reference books C201 and C207)-

P ollin g

Conceptually, polling is the simplest method for managing multiple

peripherals. With this strategy, the processor interrogates the devices
connected to the buses in turn. If a device requests service, the service
is granted. If it does not request service, the next peripheral is exam­
ined. Polling is not just used for the devices, but for any device service
routine.

Fig. 6-19: Polling Loop Flow-chart

As an example, if the system is equipped with a Teletype, a tape re­

corder, and a CRT display, the polling routine would interrogate the
Teletype: “ Do you have a character to transmit?” It would interrogate
the Teletype output routine, asking: “ Do you have a character to send?”
Then, assuming that the answers are negative so far, it would interro­
gate the tape recorder routines, and finally the CRT display. In the case
that only one device is connected to a system, polling will be used as
Fig. 6-20: Reading from a Paper-Tape Reader
well to determine whether it needs service. As an example, the flow­
charts for reading from a paper-tape reader and for printing on a print­
er appear in Figures 6-20 and 6-21.

Example: a polling loop for devices 1, 2, 3, 4, (see Fig. 6-18):

POLL4 LDA STATUS 1 SERVICE REQUEST IS BIT 7

BMI ONE
LDA STATUS2 DEVICE2?
BMI TWO
LDA STATUS3 DEVICE3?
BMI THREE
LDA STATUS4 DEVICE4
BMI FOUR
JM P POLL4 TEST AGAIN
B it 7 of the sta tu s reg ister for each device is "1” when it w ants
service. W hen a request is sensed, this program branches to the
device handler, a t address ONE for device 1, TWO for device 2, etc.
The advantages of polling are obvious: it is simple, does not
require any hardw are assistance, and keeps all input/output syn­
chronous w ith the program operation. Its disadvantage is ju s t as
obvious: m ost of th e processor’s tim e is w asted looking a t devices
th a t do not need service. In addition, the processor m ight give
service to a device too late, by w asting so m uch tim e.
A nother m echanism is, therefore, desirable which guarantees
th a t the processor’s tim e can be used to perform useful com puta­
tions, rath e r th a n polling devices needlessly all the time. How­
ever, let us stre ss th a t polling is used extensively whenever a
microprocessor h as nothing b etter to do, as it keeps the overall
organization simple. Let us now exam ine the essential a lte rn a ­
tive to polling: interrupts.

Interrupts
The concept of in terru p ts is illustrated in Figure 6-18. A spe­
cial hardw are line is available, the in te rru p t line, which is con­
nected to a specialized pin of the microprocessor. M ultiple input/
output devices m ay be connected to th is in te rru p t line. W hen any
one of them needs service, it sends a level or a pulse on th is line.
An in te rru p t signal is the service request from a n input/output
IRQ

IGNORE
INTERRUPT
device to th e processor. Let us exam ine the response of the proc­
essor to th is interrupt.
In any case, the processor completes the instruction that it was
currently executing, or else this would create chaos inside the
microprocessor. Next, the microprocessor should branch to an
interrupt handling routine which will process the interrupt. Branching
to such a subroutine implies that the contents of the program counter
must be saved on the stack. An interrupt must, therefore, cause
the automatic preservation o f the program counter on the stack.
In addition, the statu s register (P) should also be autom atically
preserved, as its contents will be altered by any subsequent in­
struction. Finally, if the interrupt handling routine should modify
any internal registers, these internal registers should also be pre­
served on the stack.
A fter all these registers have been preserved, one can branch to
the appropriate in te rru p t handling address. A t the end of this
routine, all the registers should be restored, and a special inter­
ru p t re tu rn should be executed so th a t the m ain program will
resum e execution. Let us exam ine in more detail the two inter­
ru p t lines of the 6502.

6502 Interrupts
The 6502 is equipped w ith two in te rru p t lines, IRQ and NMI.
IRQ is the reg u lar in te rru p t line, while NMI is a higher priority
non-m askable interrupt. Let us exam ine th e ir operation.
IRQ is the level-activated interru p t. The sta tu s of the IRQ line
will be sensed or ignored by the microprocessor depending upon
the value of its internal flag I (interrput-m ask flag). We will ini­
tially assum e th a t in terru p ts are enabled. W henever IRQ is
activated, the interrupt will be sensed by the microprocessor. A s
soon as the interrupt is accepted (upon completion of the instruc­
tion currently executing), the internal I flag is autom atically set.
This will prevent the m icroprocessor from being in terrupted
again a t a tim e when it is m anipulating internal registers. The
6502 then autom atically preserves the contents of PC (the pro­
gram counter) and P (the sta tu s register) into the stack. The
aspect of the stack after an in te rru p t has been processed is illus­
trated by Figure 6-23.
Next, the 6502 will automatically fetch the content of memory
locations “ FFFE” and “ FFFF.” This 16-bit memory location will
 Fig. 6-23:6502 Stack After Interrupt

contain the interrupt-vector. The 6502 will fetch the contents of

this address, th en branch to the specified 16-bit vector. The user is
responsible for depositing this vectoring address a t "FFFE ”-
"FFFF”. However, several devices m ay be connected to th e IRQ
line. In th is case, we are branching to a single in te rru p t handling
routine. How are we going to differentiate betw een the various
devices? This will be studied in the next section.
The NMI in te rru p t is essentially identical to IRQ except th a t it
cannot be m asked by th e I bit. It is a higher priority in terru p t,
typically used for power failures. Its operation is otherw ise iden­
tical except th a t th e processor branches autom atically to th e con­
tents of “ FFFA” -“ FFFB” . This is illustrated in Figure 6-24.
The re tu rn from an in te rru p t is accomplished by instruction
RTI. This instruction tran sfers back into the microprocessor th e
top three words of the stack which contains P and PC (the 16-bit
program counter). The program which had been interrupted can
th e n resum e. The in tern al sta te of the m achine is exactly identi­
cal to the one a t the tim e th a t the in te rru p t occurred. The effect
h as been to introduce a delay in the execution of the program .
P rio r to retu rn in g from a n in terrupt, the program m er is re­
sponsible for clearing the in te rru p t th a t it has now serviced, and
restoring th e in te rru p t disable flag. In addition, should the inter­
ru p t handling routine modify the contents of any register, such as
X or Y, the program m er is specifically responsible for preserving
these registers in th e stack prior to executing the in te rru p t h a n ­
dling routine. Otherw ise, the contents of these registers will be
modified, and when the interrupted program resumes execution,
it will not be correct.
Assum ing th a t the interrupt handling routine will use regis­
ters A, X, and Y, five instructions will be necessary within the
in te rru p t h andler to preserve these registers. They are:

SAVAXY PH A PU SH A IN THE STACK

TXA TRANSFER X TO A
PHA PU SH IT
TYA TRANSFER Y TO A
PHA PU SH IT

Unfortunately, the 6502 may only directly push the contents of A or

P on the stack. As a result, preserving X and Y is time-consuming; it
requires 4 instructions. This is illustrated in Figure 6-25.
Upon the completion of the in te rru p t handling routine, these
registers m ust be restored and the in te rru p t h an d ler m ust term i­
n ate w ith the sequence of six instructions:
 PLA P U L L Y FROM STACK
TAY RESTORE Y
PLA PU LL X
TAX RESTORE X
PLA RESTORE A
RTI E X IT

Fig. 6-25: Saving all the Registers

E x e rc is e 6.21: Using the table indicating the number o f cycles

per instruction, in the Appendix, compute how much time will be
lost by saving and then restoring registers A, X, and Y.

For a graphic comparison o f the polling process vs. the interrupt

process, refer to Figure 6-18, where the polling process is illustrated
on the top, and the interrupt process underneath. I t can be seen that
in the polling technique, the program wastes a lot o f time waiting.
Using interrupts, the program is interrupted, the interrupt is serviced,
then the program resumes. However, the obvious disadvantage o f an
interrupt is to introduce several additional instructions at the beginning
and at the end, resulting in a delay before the first instruction o f the
device handler can be executed. This is additional overhead.
 Having clarified the operation of the two interrupt lines, let us
now consider two im portant problems remaining:
1. How do we resolve the problem of m ultiple devices trigger­
ing an in te rru p t a t th e sam e time?
2. How do we resolve th e problem of a n in te rru p t occurring
while another in te rru p t is being serviced?

M u ltip le D e v ic e s C o n n e c te d to a S in g le I n t e r r u p t L in e
W henever an in terru p t occurs, the processor autom atically
branches to an address contained a t “ F F F E -F F F F ” (for an IRQ),
or a t “ F F F A -FFFB ” (for an NMI). Before it can do any effective
processing, the in terru p t handling routine m u st determ ine which
device triggered the interrupt. Two m ethods are available to iden­
tify the device, as usual: a softw are m ethod and a hardw are
m ethod.
INT 1 POLLING INTERRUPT VECTORED

Fig. 6-26: Polled vs. Vectored Interrupt

In the software method, polling is used: the microprocessor in­

terrogates each of the devices in tu rn and asks them, “Did you
trigger the interrupt?” If not, it interrogates the next one. This
process is illustrated in Figure 6-26. A sam ple program is:

LDA STATUS 1
BMI ONE
LDA STATUS 2
BMI TWO
 The hardw are m ethod uses additional components b u t provides
the address of th e in terru p tin g device sim ultaneously w ith the
in te rru p t request. The device now universally used to provide th is
facility is called a “ PIC ,” or priority-interrupt-controller. Such a
PIC will autom atically place on the d a ta bus the actual required
branching address for the in terru p tin g peripheral. W hen th e
6502 goes to “ FFFE” -“ FFFF,” it will fetch this vectoring address.
This concept is illustrated in Figure 6-26.
In m ost cases, th e speed of reaction to an in te rru p t is not cru­
cial, and a polling approach is used. If response tim e is a prim ary
consideration, a hardw are approach m ust be used.

I/O •• • I/O
HPU
INTERFACE 1 INTERFACE n
INT

1__ ______ _ IlNTl._____ J INT"

Fig. 6-27: Several Devices May Use the Same Interrupt Line

Multiple Interrupts

The next problem which m ay occur is th a t a new in te rru p t can

be triggered during the execution of an in te rru p t handling
routine. Let us exam ine w h at happens and how the stack is used
to solve the problem. We have indicated in C hapter 2 th a t th is
was another essential role of the stack, and th e tim e has come
now to demonstrate its use. We will refer to Figure 6-28 to illus­
tra te m ultiple interrupts. Time elapses from left to rig h t in the
illustration. The contents of the stack are shown a t the bottom of
the illustration. Looking a t the left, a t tim e TO, program P is in
execution. Moving to the right, a t tim e T l, in te rru p t I I occurs. We
will assum e th a t the in te rru p t m ask was enabled, authorizing II.
Program P will be suspended. This is shown a t the bottom of the
illustration. The stack will contain th e program counter and the
statu s register of Program P, a t least, plus any optional registers
th a t m ight be saved by the in te rru p t handler or I I itself.
A t tim e T l, in te rru p t II sta rts executing u n til tim e T2. A t tim e
T2, in te rru p t 12 occurs. We will assum e th a t in te rru p t 12 is con­
sidered to have a higher priority th a n in te rru p t II. If it had a
 tim e t0 t, t, t, t4 t, t4

PROGRAM P I---------- I --------------- ---------- ---------- — ------------------— — - - -H -

INTERRUPT 1( -------------K -
INTERRUPT 1,
INTERRUPT 1,

I
STACK
7] [7 | P

T, t4 T, t4
T,

Fig. 6-28: Stack During Interrupts

lower priority, it would be ignored until I I had been completed. A t

time T2, the registers for I I are stacked, and this appears a t the
bottom of the illustration. Again, the contents of the program
counter and P are pushed into th e stack. In addition, the routine
for 12 m ight decide to save an additional few registers. 12 w ill now
execute to completion a t tim e T3.
W hen 12 term inates, th e contents of the stack are autom ati­
cally popped back into the 6502, and this is illu strated a t the
bottom of Figure 6-28. Automatically, interrupt II thus resumes
execution. U nfortunately, a t tim e T4, an in te rru p t 13 of higher
priority occurs again. We can see a t the bottom of the illustration
th a t the registers for II are again pushed into the stack. Interrupt
13 executes from T4 to T5 and terminates atT5. At that time, the
contents of the stack are popped into 6502, and in te rru p t I I re ­
sumes execution. This tim e it runs to completion and term inates
a t T6. A t T6, the rem aining registers th a t have been saved in the
stack are popped into the 6502, and program P may resume execu­
tion. The reader will verify th a t the stack is em pty a t th is point.
In fact, the num ber of dashed lines indicating program suspen­
sion indicates at the same time the number of levels there are in the
stack.

E x e rc is e 6.22: I f we assume that every time an interrupt occurs

the program counter PC, the register P, and the accumulator will
be saved, this will be a minimum o f four locations. (In practice, X
and Y may be saved as well, resulting in six locations used). A s ­
suming, therefore, that three registers only are saved in the stack,
how many interrupt levels does the 6502 allow? tRemember that
the stack is limited to 256 locations with Page 1).
Exercise 6.23: A ssum ing this time that 5 registers may be pre­
served in the stack, what is the maximum number o f simultane­
ous interrupts that can be handled? Will any other factor reduce even
further the number o f simultaneous interrupts?

It m ust be stressed, however, th at, in practice, microprocessor

system s are norm ally connected to a sm all num ber of devices
using interrupts. It is, therefore, unlikely th a t a high num ber of
sim ultaneous in terru p ts will occur in such a system.
We have now solved all th e problems norm ally associated w ith
interrupts. T heir use is, in fact, simple and they should be used to
advantage even by the novice program m er. L et us complete our
analysis of the 6502 resources by introducing one m ore instruc­
tion whose effect is identical to th a t of a synchronous interrupt:

Break
The BRK command in the 6502 is the equivalent of a software
in terrupt. I t can be inserted in a program and results, ju s t a s in
the case of IRQ, in th e autom atic preservation of PC and P, and
an indirect branch to “ F F F E ”-“ F F F F .” This instruction can be
used to advantage to generate programmed interrupts during the de­
bugging of a program. This will result in creating a breakpoint, halt­
ing the program a t a predeterm ined location, and branching to a
routine which will typically allow the user to analyze th e pro­
gram . Since th e n et effect of the break and an in te rru p t are iden­
tical afte r they have occurred, a m eans m ust be provided for the
program m er to determ ine w hether it was an in te rru p t or a break.
The 6502 will set a B-flag in register P (saved in the stack) to “ 1” if
it was a break and to "0” if it was an in terrupt. Testing the sta tu s
of this b it m ay be accomplished by th e following sim ple program:

BTEST PLA READ TOP OF STACK INTO A

PHA WRITE IT BACK
AND #$10 MASK B-BIT
BNE BRKPRG GO TO BREAK PROGRAM
 This test program is norm ally inserted a t the end of the polling
sequence w hich determ ines th e n a tu re of th e device th a t
triggered the interrupt.
Caution: A feature of th e break is to preserve th e contents of
the program counter plus 2 automatically. Since the break is only
a 1-byte instruction, the programmer may sometimes have to adjust
th e contents of th e program counter in the stack by using an
increm enting or decrem enting instruction in order to resum e
execution of th e correct address. In particular, th e break is exten­
sively used during debugging by w riting it over another instruc­
tion in the program . If the program is reassem bled prior to execu­
tion, the contents of the program counter which have been saved
will norm ally have to be decrem ented by 1.

SU M M A RY

We have presented in th is chapter the range of techniques used

to com m unicate w ith the outside world. From elem entary input/
output routines to more complex program s to com m unicate w ith
actual peripherals, we have learned to develop all the usual pro­
gram s and have even exam ined the efficiency of benchm ark pro­
gram s in th e case of a parallel tran sfer and a parallel-to-serial
conversion. Finally, we have learned to schedule th e operation of
m ultiple peripherals by using polling and interrupts. N aturally,
m any other exotic input/output devices m ight be connected to a
system . W ith the a rray of techniques which have been presented
so far, and w ith a n understanding of the peripherals involved, it
should be possible to solve m ost usual problems.
In th e next chapter, we will exam ine th e actual characteristics
of th e input/output interface chips usually connected to a 6502.
Then, we will consider th e basic d a ta stru ctu res th a t th e pro­
grammer may consider using.

E X E R C ISE S

E xercise 6.24: A 7-segment LED display can also display digits

other than the hex alphabet. Compute the codes forH,I,J,L,0,P,S,
U, Y, g,h,i,j,l,n,o,p,r,t,u,y.
E xercise 6.25: The flow-chart for interrupt management appears
in Figure &29 below. Answ er the following questions:
a-What is done by hardware, what is done by software?
b-What is the use o f the mask?
c-How many registers should be preserved?
d-How is the interrupting device identified?
e-What does the R T I instruction do? How does it differ from
a subroutine return?
f-Suggest a way to handle a stack overflow situation.
g- What is the overhead ("lost time”) introduced by the interrupt
mechanism?

RETURN

Fig. 6-29: Interrupt Logic

INPUT/OUTPUT DEVICES
IN T R O D U C T IO N
We have learned how to program the 6502 m icroprocessor in
m ost usual situations. However, we should m ake a special m en­
tion of the input/output chips norm ally connected to the micro­
processor. Because of the progress in LSI integration, new chips
have been introduced which did n o t exist before. A s a result, pro­
gram m ing a system requires, naturally, first program m ing a mi­
croprocessor itself, b u t also programming the input/output chips.
In fact, it is often more difficult to rem em ber how to program the
various control options of an inp u t/o u tp u t chip th an to program
th e m icroprocessor itself! This is n o t because the program m ing in
itself is more difficult, b u t because each of these devices has its
own idiosyncrasies. We are going to exam ine here first the m ost
general input/output device, the program m able input/output chip
(in sh o rt a “ P IO ”), then “ im provem ents” over this stan d ard PIO ,
now frequently used w ith the 6502: the 6520, 6530, 6522 and
6532. The com plete details are presented in reference D302.

T h e S ta n d a r d P IO (6520)
There is no “ standard PIO .” However, the 6520 device is essen­
tially analogous in function to all similar PIO s produced by other
m anufacturers for the sam e purpose. The purpose of a PIO is to
provide a m ultiport connection for input/output devices. (A "port ”
is sim ply a set of 8 input/output lines). Each PIO provides a t least
two sets of 8-bit lines for I/O devices. Each I/O device needs a data
buffer in order to stabilize th e contents of the d a ta bus on output
a t least. O ur PIO will, therefore, be equipped a t a m inim um w ith
a buffer for each port.
In addition, we have established th a t the m icrocom puter will
use a handshaking procedure, or else interrupts to comm unicate
w ith th e I/O device. The PIO will also use a sim ilar procedure to
comm unicate w ith the peripheral. Each PIO m ust, therefore, be
equipped w ith a t least two control lines per port to im plem ent the
handshaking function.
The microprocessor will also need to be able to read the sta tu s
of each port. Each port m ust be equipped w ith one or more status
bits. Finally, a num ber of options will exist w ithin each PIO to
configure its resources. The program m er m ust be able to access a
special register w ithin th e PIO to specify the program m ing op­
tions. This is the control register. In the case of the 6520, the
sta tu s inform ation is p a rt of the control register.

Fig. 7-1: Typical PIO

One essential faculty of the PIO is the fact that each line may
be configured as either an input or an output line. The diagram of
a PIO appears in illustration 7-1. The programmer may specify
whether any line will be input or output. In order to program the
direction of the lines, a data direction register is provided for each
port. A “ 0” in a bit position of the data direction register specifies
an input. A “ 1” specifies an output.
 It m ay be surprising to see th a t a "0” is used for inp u t and a "1”
for output w hen really "0” should correspond to O utput and "1” to
Input. This is quite deliberate: w henever power is applied to the
system , it is of g rea t im portance th a t all the I/O lines be confi­
gured as input. Otherw ise, if the microcom puter is connected to
some dangerous peripheral, it m ight activate it by accident.
W hen a reset is applied, all registers are norm ally zeroed and th a t
will resu lt in configuring all input lines of the PIO as inputs. The
connection to the microprocessor appears on the left of the illus­
tration. The PIO naturally connects to the 8-bit data bus, the mi­
croprocessor address bus, and th e m icroprocessor control bus.
The program m er will sim ply specify the address of any register
th a t it wishes to access w ithin the PIO . The 6520, which is com­
patible w ith M otorola’s 6820, has inherited one of its peculiari­
ties: it is equipped w ith 6 internal registers. However, one can
specify only one out of four registers! The way this problem is
solved is by sw itching b it position 2 of th e control register. W hen
th is b it is a “ 0 ,” the corresponding d a ta direction register m ay be
selected. W hen it is a “ 1,” th e d a ta register m ay be selected.
Therefore, whenever the program m er w ants to w rite d a ta into the
d a ta direction register, he will first have to m ake sure th a t b it 2
of th e appropriate control register is zero, before he can select
th is register. This is som ew hat aw kw ard to program , b u t it is im ­
p o rta n t to rem em ber in order to avoid painful difficulties.

7 6 5 4 3 2 1 0
DDRA CA1
IRQA1 IRQA2 CA2 CONTROL
ACCESS CONTROL

READ-ONLY READ/WRITE BY MPU

Fig. 7-2: PIA Control Word Format

RSI RS0 CRA 2 CRB 2 REGISTER SELECTED

0 0 1 - PERIPHERAL REGISTER A

0 0 0 - DATA DIRECTION REGISTER A

0 1 - - CONTROL REGISTER A

1 0 - 1 PERIPHERAL REGISTER B

1 0 - 0 DATA DIRECTION REGISTER B

1 1 - - CONTROL REGISTER B

Fig. 7-3: Addressing PIA Registers

 Tb clarify the effect of th e address selection on the 6520, the
address selection table appears above. RSO and R S I are two
register-selection signals which are derived from the address bus.
In other words, they represent two bits of the address specified by
the programmer. CRA is the control register for port A. CRA (2)
is bit 2 of this register. CRB is the control register for port B.

The Internal Control Register

The Control R egister of the 6520 specifies, as we have seen, in
b it position 2, a selection mode for the in ternal registers of the
port. In addition, it provides a num ber of options for generating or
sensing interrupts, or for im plem enting autom atic handshake
functions. The complete description of the facilities provided is
not necessary here. Simply, the user of any practical system which
uses the 6520 will have to refer to the data sheet showing the
effect of setting the various bits of th e control register. W henever
the system is initialized, the program m er will have to load the
control register of the 6520 w ith th e correct contents for th e ex­
pected application.

PAO

PA7

PBO

PB5/CS2
PB6/CS1
PB7/IRQ

Fig. 7-4: 6530 Pinout

 The 6530
The 6530 im plem ents a com bination of four functions, RAM ,
ROM, PIO , and TIM ER . The RAM is a 64x8 memory. The ROM
is a 1K x 8 memory. The tim er provides the program m er w ith mul­
tiple interval tim ing facilities. The P IO section is essentially ana­
logous to the 6520, which we have described: There are tw o ports,
each w ith a d a ta register and a d a ta direction register. A “ 0 ” in a
given b it position of the direction register specifies an input,
while a “ 1” specifies an output.
The programmable interval tim er can be programmed to count
up to 256 intervals (it has 8 bits internally). The program mer m ay
specify the tire© period to be 1, 8, 64, or 1024 times the system dock.
Whenever the count is reached, the interrupt flag of the chip will be
set to a logic “ 1” . The contents of the timer are set by means of the
data bus. The four possible time intervals must be specified on lines
A0 and A1 of the address bus.
Three pins of port B have a dual role: PB5, PB6, and PB7 m ay
be used for control functions. Pin PB7, for example, m ay be pro­
gram m ed as an interrupt input.
This chip is used, in particular, on the K IM board. (Note:
on the KIM , PB 6 is not available.)

Program m ing a PIO

A s an example, here is a program to use a 6520 or a 6522.

(We assum e th a t the control register has already been set).

LDA #FF SET DATA DIRECTION

STA DDRB CONFIGURE B FOR OUTPUT
LDA #00
STA IORB GENERATE ZERO OUTPUT

DDRB is the address of the Data Direction Register of port B for this
PIO . IORB is the In p u t/O u tp u t or d a ta register for p o rt B;
“ F F ” hexadecim al is “ 11111111” binary = all outputs.

The 6522
The 6522, also called "versatile interface ad ap ter” (VIA), is an
improved version of the 6520. In addition to the capabilities of the
 Fig. 7-5: Using a PIA Load Control Register

CA 1
IRQA - CA 2

PERIPHERAL
INTERFACE B

DATA DIRECTION

(DDRB)

CONTROL

CB 1
IRQB - ► CB 2

Fig. 7-6: Using a PIA Load Data Direction

 Fig. 7-7: Using a PIA Read Status

Fig. 7-8: Using a PIA: Read Input

6520, it provides two programmable interval timers and a serial-
to-parallel, plus parallel-to-serial converter, plus input data latch­
ing. The detailed hardware description of this component is be­
yond the scope of this book. Simply, with the description which
has been provided for the previous components, it should be
simple for the program m er to fam iliarize him self w ith the ad­
dressing of the in tern al registers of th is component as well as its
programming. This information is supplied in the manufacturer’s
d a ta sheets.

The 6532
The 6532 is a combination chip which includes one 128 x 8 RAM,
a PIO with two bi-directional ports, and a programmable interval
timer. It is used on the SYM board, manufactured by Synertek
Systems, which is analogous to the KIM board, manufactured
by MOS Technology and by Rockwell. Again, the user should
carefully examine the data sheets for this component in order to
learn how to address and use the various internal registers.

SUMMARY
Unfortunately, in order to make effective use of such compo­
nents, it will be necessary to understand in detail the function of
every bit, or group of bits, w ithin th e various control registers.
These complex new chips autom ate a num ber of procedures th a t
had to be carried out by software or special logic before. In par­
ticular, many of the handshaking procedures are automated with­
in components such as a 6522. Also, some interrupt handling
and detection m ay be internal. W ith the inform ation th a t has
been presented in the preceding chapter, the reader should be able
to read the corresponding d a ta sheets and understand w h at the
functions of the various signals and registers are. Naturally, still
new components are going to be introduced which will offer a
hardw are im plem entation of still more complex algorithm s.
For a comprehensive description of I/O devices and techniques, the
reader is referred to the companion volume D302.
APPLICATION EXAMPLES
IN TR O D U C TIO N

This chapter is designed to te st your new program m ing alrillc b y

presenting a collection of utility programs. These programs, or
“ routines,” are frequently encountered in applications and are generally
called “ utility routines.” They will require a synthesis of the knowledge
and techniques presented so far.
We are going to fetch characters from an I/O device and process
them in various ways. But first, let us clear an area of the memory
(this may not be necessary; each of these programs is only presented as
a programming example).

C LEAR A SEC TIO N OF M EM ORY

W e Want to clear (zero) the contents of the memory from ad­

dress B A SE + 1 to address B A S E + L E N G T H , where
length is less than 256.
The program is:
ZEROM LDX#LENGTH
LDA#0
CLEAR STABASE, X
DEX
BNE CLEAR
RTS

Note that register X is used as an index to point to the current

location of the memory section to be zeroed.

The accumulator A is loaded only once with the value 0 (all 0’s),
then written at successive memory locations:
BASE + LENGTH, BASE + LENGTH - 1, etc., until X dec­
rements to zero. When X=0, the program returns.

In a memory test for example, this program could be used to zero

a block, then verify its contents.

Exercise 8.1: Write a memory test program which will zero a 256-word
block and verify that each location is 0. Then, it will write all 1’s and
verify the contents o f the block. Next, it will write 01010101 and verify
the contents. Finally, it will write 10101010 and verify the contents.

Let us now poll our I/O devices to find which one needs service.

POLLING I/O DEVICES

We will assu m e that 3 I/O devices are connected to our system.
Their status registers are located at addresses IOSTATUS1,
IOSTATUS2, and IOSTATUS3.

If their status bits are in bit position 7, we will just read the status
registers, and test their sign bits. If the status bits are anywhere else,
we will take advantage of the BIT instruction of the 6502:
TEST LDA MASK
BIT IOSTATUS1
BNE FOUND1
BIT IOSTATUS2
BNE FOUND 2
BIT IOSTATUS3
BNE FOUND3
(failure exit)

The M ASK will contain, for example, “ 00100000” if we te s t b it

position 5. A s a result of th e B IT instruction, the Z b it of th e
statu s flags will be set to 0 if “M ASK AND IOSTATUS” is non­
zero i.e. if th e corresponding bit of IOSTA TUS m atches th e one
in M ASK. The BN E instruction (branch if non-equal to zero)
will th en resu lt in a branch to the appropriate FOUND routine.

GETTING CHARACTERS IN

Assume we have ju s t found th a t a character is ready a t the key­

board. L et us accum ulate characters in a m em ory area called
buffer un til we encounter a special character called SPC, whose
code has been previously defined.

The subroutine G E TC H A R will fetch one character from th e

keyboard (see C hapter 6 for m ore details) and leave it in the ac­
cumulator. We assume that a maximum of 256 characters will be
fetched before an SPC character is found.

STRING LDX #0 INITIALIZE INDEX TO ZERO

NEXT JSR GETCHAR
CMP #SPC IS IT THE BRK CHAR?
BEQ OUT IF SO, FINISHED
STA B U FFE R , X NO: SAVE CHAR
INX INCREMENT POINTER
JM P NEXT GET NEXT CHAR
OUT RTS
Exercise 8.2: L et us improve this basic routine:
ct-Echo the character back to the device (for a Teletype, for example)
b-Check that the input string is no longer than 256 characters

We now have a string of characters in a memory buffer. Let us

process them in various ways.

TESTING A CHARACTER
Let us determine if the character at memory location LOC is
equal to 0 ,1 , or 2:
ZOT LDA LOC
CMP #$00
BEQ ZERO
CMP #$01
BEQ ONE
CMP #$02
BEQ TWO
JM P NOTFND

We simply read the character, then use the CMP instruction to check
its value.
Let us run a different test now.

BRACKET TESTING
Let us determine if the ASH character at memory location LOC
is a digit between 0 and 9:
BRACK LDA #$40
ADC #$40 FORCE OVERFLOW
LDA LOC
ORA #$80 SE T B IT 7 = 1
CM P #$B0 A SC II 0
BCC TOOLOW
CM P #$B9 A SC II 9
BEQ OUT 9 EXACTLY
BCS T O O H IG H
OUT CLC
CLV
RTS
TOOLOW SEC SET C TO ONE
CLV
RTS
TOOHIGH RTS (C IS ONE)

ASCII 0 is represented in hexadecimal by “ BO”

A S C II 9 is represented in hexadecim al by “B 9”

Remember that when using a CMP instruction, the carry bit will be
set if the value of the literal that follows is less than or equal to the
accumulator. It will be reset (0) if greater.

If BO is g reater th a n the character, our character is too low, and

a branch occurs.

We then com pare it ag ain st B9. If it is less th a n or equal to 9,

all is well, and we exit. Otherwise, we go to TO O H IG H .

When we exit from this program, we w ant to know if the number

is TOOLOW, TOOHIGH, or else between 0 and 9. This will be
indicated by the flags C and V. V is not altered by CMP, whereas Z, N
and C are.

When returning from the subroutine, a “0” in V indicates “too low,” a

“ 1” in V indicates “too high,” and a “0” in C indicates a correct digit
between 0 and 9.

Naturally, other conventions could be used, such as loading a digit

in the accumulator to indicate the result of the tests.

Exercise 8.3: Sim plify the above program by testing against the
A S C II character which follows “9 ” instead o f testing against 9
exactly.

Exercise 8.4: Determine if an A S C II character contained in the

accumulator is a letter o f the alphabet.
 W hen using an A SC II table, you will notice th a t parity is often
used. (The example above does not use parity.) For example, the
A SC II for “ 0 ” is “ 0110000,” a 7-bit code. However, if we use odd
parity,! for example we guarantee th a t the to ta l num ber of ones
in a word is odd), then the code becomes “ 10110000.” A n ex tra
“ 1 ” is added to th e left. This is “ B 0” in hexadecimal. L et us there­
fore develop a program to generate parity.

PARITY GENERATION

This program will generate an even parity in b it position 7:

PARITY LDX mi BIT COUNT
LDA #$oo
STA ONECNT COUNT OF l ’S
LDA CHAR READ CHARACTER
ROL A DISCARD BIT 7
NEXT ROL A NEXT BIT
BCC ZERO IS IT A 1?
ONE INC ONECNT
ZERO DEX DECREMENT BIT COUNT
BNE NEXT LAST BIT?
ROL A RESTORE BIT 0
ROL A DISCARD BIT
LSR ONECNT RIGHTMOST BIT IS PARITY
ROR A PUT IT IN A
RTS

Register X is used to count bits as they are shifted left from the
accumulator. Every time th a t a “ 1” is shifted off the left of A
(it is tested by BCC), the one-counter is incremented. W hen 8
b its have shifted (the program ignores b it 7 which will be
the parity bit), A is shifted left two more times so that bit 6 is on
the left of A.

The correct parity bit is the right-most bit of ONECNT; it is installed

into the carry bit by LSR and becomes bit 7 of A. Another ROR
A copies this b it back into position 7 of A, and we are finished.
Exercise 8.5: Using the above program as an example, verify the
parity o f a word. You m u st compute the correct parity, then com­
pare it to the one expected.

CODE CONVERSION: A SC II to BCD

C onverting A SC II to BCD is very simple. We will observe th a t

the hexadecimal representations of ASCII characters 0 to 9 are BO to B9
with parity, or 30 to 39 without parity. The BCD representation is
simply obtained by dropping the “ B” ; that is, by masking off the left
nibble (4 bits):
LDA CHAR
AND #$OF MASK OFF LEFT NIBBLE
STA BCDCHAR

Exercise 8.6: Write a program to convert BCD to ASC II.

Exercise 8.7: (more difficult) Write a program to convert BCD to

binary.

Hint: N 3 N2 Ni No in BCD is (((Ns x 10) + N2) x 10 + Ni) x 10

+ No in binary.
To multiply by 10, use a left shift (=x2), another left shift (=x4),
an ADC (=x5), and another left shift(=xl0).
In full BCD notation, the first word m ay contain the count of
BCD digits, the next nibble may contain the sign, and every successive
nibble may contain a BCD digit. (We assume no decimal point ).The last
nibble of the block may be unused.

FIN D THE LARGEST ELEM ENT OF A TABLE

The beginning address of the table is contained at memory ad­

dress BASE in page zero. The first entry of the table is the num­
ber of bytes it contains. This program will search for the largest
element of the table. Its value will be left in A, and its position
will be stored in memory location INDEX.
This program uses registers A and Y, and will use indirect addressing,
so that it can search any table anywhere in the memory.

LDY #0 T H IS IS OUR IN D E X TO T A B LE
MAX
LDA (BASE), Y ACCESS ENTRY 0 = L E N G T H
TAY SAVE IT IN Y
LDA #0 M AX VALUE IN IT IA L IZ E D TO ZERO
STA IN D E X IN IT IA L IZ E IN D E X TO ZERO
CMP (BASE), Y IS C U R R EN T MAX E LE M E N T?
LOOP
BCS NOSW ITCH Y ES?
LDA (BASE), Y LOAD NEW MAX
STY IN D E X LOCATION O F MAX
N OSW ITCH DEY P O IN T TO N EX T E L E M E N T
BNE LOOP K E E P T EST IN G ?
RTS F IN IS H IF Y = 0

This program te sts the N th entry first. If it is greater th an 0, it

goes in A, and its location is remembered into INDEX. The (N-l)st
en try is then tested, etc.

This program works for positive integers.

Exercise 8.8: M odify the program so that it works also for nega­
tive numbers in two's complement.

Exercise 8.9: Will this program also work for A S C II characters ?

Exercise 8.10: Write a program which will sort N numbers in as­

cending order.

Exercise 8.11: Write a program which will sort N names (3 char­

acters each) into alphabetical order.

SUM OF N ELEMENTS

This program will compute the 16-bit sum of N entries of a table.

The sta rtin g address of the table is contained a t memory address
BA SE in page zero. The first entry of the table contains the num ­
ber of elem ents N. The 16-bit sum will be left in memory locations
SUMLO and SU M H I. If the sum should require more th an 16
bits, only the lower 16 will be kept. (The high-order bits are said to be
truncated.)
 elements maximum.

LDA #0 INITIALIZE SUM

STA SUM LO INITIALIZE SUM
STA SUMHI INITIALIZE SUM
TAY INITIALIZE Y TO ZERO
LDA (BASE), Y GET N
TAY IN TO Y
CLC CLEAR CARRY FOR ADC
ADLOOP LDA (BASE), Y GET NEXT ELEMENT
ADC SUMLO ADD IT TO SUMLO
STA SUMLO SAVE RESULT
BCC NOCARRY CARRY?
INC SUMHI ADD IT TO SUMHI
CLC FOR NEXT SUM
NOCARRY DEY NEXT ELEMENT
BNE ADLOOP AGAIN IF Y NOT ZERO
RTS

This program is straightforward and should be self-explanatory.

Exercise 8.12: M odify this program to compute:

a) a 24-bit sum,
b) a 32-bit sum,
c) to detect any overflow.

A CHECKSUM COMPUTATION

A checksum is a digit, or set of digits, computed from a block of

successive characters. The checksum is computed a t the time the
data is stored and p u t a t the end. In order to verify the integrity
of the data, the data is read and the checksum is recomputed and
compared against the stored value. A discrepancy indicates an error
or a failure.
 Several algorithms are used. Here, we will ;xclusive-OR all bytes
in a tahlft of N elements, and leave the result in the accumulator.
A s usual, the base of the table is stored a t th e address B A SE in
page zero. The first entry of the table is its num ber of elements N.
The program modifies A and Y. N m u st be less th a n 256.
CHECKSUM LDY #0 POINT TO FIRST ENTRY
LDA (BASE), Y GET N
TAY STORE IT IN Y
LDA HO INITIALIZE CHECKSUM
CHLOOP EOR (ADDR), Y EO R N E X T EN TRY
DEY PO IN T TO N E X T
BNE CHLOOP KEEP GOING
RTS

COUNT THE ZEROES

This program will count the number of zeroes in our usual table,
and leave it in register X.
It modifies A ,X ,Y :
ZEROES LDY #0 POINT TO FIRST ENTRY
LDA (ADDR), Y GET N
TAY STORE IT IN Y
LDX »0 INITIALIZE NO. OF ZEROES
ZLOOP LDA (ADDR), Y GET NEXT ENTRY
BNE NOTZ IS IT ZERO?
INX YES. COUNT IT
NOTZ DEY POINT TO NEXT
BNE ZLOOP KEEP GOING
RTS

E x e rc is e 8.13: M odify this program to count:

a-the number o f stars (the character ”*”)
b-the number o f letters o f the alphabet
c-the number o f digits between 0 and 9

A STRING SEARCH

A string of characters is stored in the memory, as indicated in

F ig 8-1 We will search the strin g for the occurrence of a shorter
one, called a template (TEMPLT), of length TPTLEN. The length
of th e original strin g is STR LEN , and the program will retu rn
 w ith register X containing the location where the TEM PLT was
found, and F F hexadecimal otherwise. The flowchart for the pro­
gram is shown in Fig. 8-2. The strin g is first scanned for the oc­
currence of th e first character in TEMPLT. If this first character
is never found, the program will exit w ith a failure. If this first
character is found, the second character will be m atched against
the next one in the string. If th a t fails, the search is resta rted for
the first character since there m ight be another occurrence of this
first character within the original string. If the first and the sec­
ond one m atch, the search will proceed w ith the following charac­
ters of TEM PLT in the sam e m anner. The corresponding pro­
gram is shown in Fig. 8-3. N ote th a t R egister X is used as the
running pointer during the search pointing to the current elem ent
of string. Indexed addressing is naturally used to retrieve the
current elem ent of string.

Fig: 8-1: String Search: The Memory

Fig. 8-2: Program Flowchart: String Search
 LI NE « IOC C0IE LINE

00 02 00 0 0 • S TR IN G S E A R CH .
00 03 00 0 0 ;F IN0S L O C A T I O N IN S T R I N G OF L E N I T N 'STR IE M'
0004 00 00 ; S T6 RT IN 6 AT 'STRING'’ OF A TE NP L A T E OF
00 0 5 00 0 0 •LEN GT H 'TPTLEN' S T A R T I N G A T 'T ENPLT', A M )
0 0 00 00 0 0 •'RETURNS W I T H R E L O C A T I O N OF T E N P L 6 T E
00 0 7 0 0 00 ,'IN ST R I N G IF F 0 U N 8 f O R X« 0 F F IF NOT FOUND.
00 0 8 00 0 0 t
00 0 9 00 0 0 S T RI N6 « 120 J1 ST L O C A T I O N O F S T RI NG .
ooto 00 0 0 TE NP LT » 050 ;1ST L O C A T I O N O F T E MP LA TE .
0 0 tt 00 0 0 « * no
0012 00 1 0 CMKPTR M M |
0013 0011 T E NP TR 1
0 0 14 00 1 2 ST RL EN ;L E N G T H O F STRING.
0015 00 1 3 TP TL EN • L EN GT H OF TEMPLATE.
00 1 6 0014 4 « 02 00
00 1 7 0 2 00 62 00 L8X 80 ,'R E S E T S E A R C H ST A R T POIN TE R.
0018 02 02 65 50 N X TP 0S L 8 6 T E NP LT IIS F I R S T E L E M E N T OF T E MP LA TE .. .
0019 0204 05 20 C N P ST RI N G , ! •*> C U R R E N T ST RI N6 E L E M E N T ?
0020 02 06 F0 08 8 E 0 C H EC K •'IF YES, C H EC K F O R RE S T OF MA TC H.
0021 02 0 8 E8 N X T S T R INX •'INCREMENT SE A R C H S T A R T COUN TE R.
00 2 2 02 0 9 E4 12 CP X S T R L E N ;IS IT EO UA L TO S T R I N G LE N G T H ?
0023 02 08 80 F5 ONE N X T P O S ,*N0, CH E C K NEXT S T R I N G P O SI TI ON .
00 24 02 0 8 62 FF LBX 80 FF IVES, S E T 'NOT F O UN D' IN DI CA TO R.
0025 020F 60 RTS ;R E T U RN S ALL CH R S CH EC K E R .
00 2 6 02 10 86 11 C H EC K STX TE NP TR 2LE T TE MP O R A R Y P O I N T E R *
00 2 7 02 12 •'CURRENT ST R I N G POIN TE R.
00 2 8 02 12 69 00 L 8 6 80
00 2 9 0214 85 10 ST6 C H X P T R ;r e s e t template pointer .
00 3 0 02 16 E6 11 C H KL P INC TE N P T R ;IN C R E M E N T T E MP OR AR Y POIN TE R.
0031 0 2 18 E6 10 INC CH K P T R 2IN CR E M E N T TENP LA TE POIN TE R.
00 3 2 02 16 64 10 LO T CH K P T R
00 3 3 02 1C C4 13 CPY T P TL EN •'DOES T E NP LA TE P O I N T E R = T E H P L A T E L E N G T H ?
00 34 02 IE F0 OC 8E 0 F0 U N 8 ,'IF YES, TE NP LA TE M A T C HE D.
00 3 5 02 20 89 SO 00 L8A TENPLT,Y 2L 0A0 T E N P L A T E EL EM EN T.
00 36 0 2 23 64 11 LOT T E NP TR
00 3 7 02 25 89 20 00 C N P ST R I N G , ! •'COMPARE T O S T R I N G CHR.
00 38 02 28 80 8E ONE N X T S T R ,'IF NO NATCH, C H E C K NE X T S T R I N G CHR.
00 39 0226 F0 E6 8E 0 CH K L P ,'IF NATCH, CH ECK NE X T CHR.
00 40 022C 60 F0 UN 8 RTS ,'DONE.
0041 02 28 .END

Fig. 8-3: String Search Program

SUM M ARY
In this chapter, we have presented common utility routines which use
combinations of the techniques described in previous chapters. These
routines should now allow you to start designing your own programs.
Many of them have used a special data structure, the table. However,
other possibilities exist for structuring data, and these will now be
reviewed.
DATA STRUCTURES
PART I: DESIG N CONCEPTS
INTRODUCTION
The design of a good program involves tw o tasks: algorithm
design and data structures design. In m ost simple program s, no
significant d a ta stru ctu res are involved, so the m ain problem th a t
m u st be surm ounted to learn program m ing is learning how to
design algorithm s and code them efficiently in a given m achine lan­
guage. This is w hat we have accomplished here. However, design­
ing more complex program s also requires an understanding of d a ta
structures. Two d a ta stru ctu res have already been used through­
out the book: the table, and the stack. The purpose of th is chapter
is to present other, more general, d a ta stru ctu res th a t you m ay
w ant to use. This chapter is completely independent from the
m icroprocessor, or even the com puter, selected. I t is theoretical
and involves logical organization of d a ta in the system . Specialized
books exist on the topic of d a ta structures, ju s t like specialized
books exist on the subject of efficient m ultiplication, division or
other usual algorithms. This single chapter, therefore, should be con­
sidered as an overview, and it will be necessarily limited to the essentials
only. It does not claim to be exhaustive.
Let us now review the most common data structures:

POINTERS
A pointer is a num ber which is used to designate the location of
the actual data. E very pointer is an address. However, every ad-
dress is not necessarily called a pointer. A n address is a pointer on­
ly if it points a t some type of d a ta or a t stru ctu red inform ation. W e
have already encountered a typical pointer, the stack pointer,
which points to th e top of the stack (or usually ju s t over the top of
the stack). We will see th a t the stack is a common d a ta structure,
called a L IFO structure.
A s another example, when using indirect addressing, the in­
direct address is alw ays a pointer to the d ata th a t one wishes to
retrieve.
Exercise 9.1: Exam ine Figure 9-1. A t address 15 in the memory,
there is a pointer to Table T. Table T starts at address 500. What
are the actual contents o f the pointer to T?

Fig 9-1: An Indirection Pointer

L IST S
A lm ost all d a ta stru ctu res are organized as lists of various
kinds.

Sequential L ists
A sequential list, or table, or block, is probably the sim plest d a ta
structure, and one th a t we have already used. Tables are norm ally
ordered in function of a specific criterion, such as, for example,
alphabetical ordering, or num erical ordering. I t is then easy to
retrieve an elem ent in a table, using, for example, indexed address­
ing, as we have done. A block norm ally refers to a group of data
which has definite lim its b u t whose contents are not ordered. I t
may, for example, contain a strin g of characters. Or it m ay be a
sector on a disk. Or it m ay be some logical area (called segment) of
the memory. In such cases, it m ay not be easy to access a random
elem ent of the block.
In order to facilitate the retrieval of blocks of information, directories
are used.

Directories
A directory is a list of tables, or blocks. For example, the file
system will normally use a directory structure. As a simple exam ­
ple, the m aster directory of the system m ay include a list of the
u se rs’ names. This is illustrated in Figure 9-2. The entry for user
“Jo h n ” points to J o h n ’s file directory. The file directory is a table
which contains the names of all of J o h n ’s files and their location.
This is, again, a table of pointers. In this case, we have ju s t de­
signed a two-level directory. A flexible directory system will allow
the inclusion of additional interm ediate directories, as m ay be
found convenient by the user.

USER DIRECTORY

Fig. 9-2: A Directory Structure

Linked List

In a system there are often blocks of inform ation which repre­

sent data, or events, or other structures, which cannot be easily
moved. If they could be easily moved, we would probably assemble
them in a table in order to sort them or structure them. The
problem now is that we wish to leave them where they are and
still establish an ordering between them such as first, second,
third, and fourth. A linked list will be used to solve this pro­
blem. The concept of a linked list is illustrated by Figure 9-3. In
the illustration, we see th a t a list pointer, called FIRSTBLO CK,
points to the beginning of the first block. A dedicated location
within Block 1, such as, perhaps, the first or the last word of it,
contains a pointer to Block 2, called PTR1. The process is then re­
peated for Block 2 and Block 3. Since Block 3 is the last entry in
the list, PTR3, by convention, contains a special “ nil” value, or
else points to itself, so th a t the end of the list can be detected. This
structure is economical as it requires only a few pointers (one per
block) and prevents the user from having to physically move the
blocks in the memory.

Fig. 9-3: A Linked List

L et us examine, for example, how a new block will be inserted.

This is illustrated by Figure 9-4. Let us assum e th a t the new block
is a t address NEW BLOCK, and is to be inserted between Block 1
and Block 2. Pointer PTR1 is simply changed to the value N EW ­
BLOCK, so th a t it now points to Block X. PTR X will contain the
former value of PTR1 (i.e., it will point to Block 2). The other
pointers in the structure are left unchanged. We can see that the inser­
tion of a new block has sim ply required updating two pointers in
the structure. This is clearly efficient.
Exercise 9.2: Draw a diagram showing how Block 2 would be
removed from this structure.
Several types of lists have been developed to facilitate specific
 Fig. 9-4: Inserting a New Block

types of access or insertions or deletions to or from the list. L et us

exam ine some of the m ost frequently used types of linked lists:

Queue
A queue is formally called a FIFO , or first-in-first-out list. A
queue is illustrated in Figure 9*5. To clarify the diagram , we can
assum e, for example, th a t the block on th e left is a service routine
for an o u tp u t device, such a s a printer. The blocks appearing on th e
rig h t are the request blocks from various program s or routines, to
p rin t characters. The order in which they will be serviced is th e

Fig. 9-5: A Queue

order established by the waiting queue. It can be seen that the
next event which will obtain service is Block 1, then Block 2, and finally
Block 3. In a queue, the convention is that any new event arriving in the
queue will be inserted at the end of it. Here it will be inserted after
PTR3. This guarantees that the first block to have been inserted in the
queue will be the first one to be serviced. It is quite common in a com­
puter system to have waiting queues for a number of events whenever
they must wait for a scarce resource, such as the processor or some
input/output device.
Stack
The stack stru ctu re has already been studied in detail through­
o u t the book. I t is a last-in-first-out stru ctu re (LIFO). The la s t ele­
m ent deposited on top of it is the first one to be removed. A stack
m ay be im plem ented as a sorted block, or else it m ay be imple­
m ented as a list. Because m ost stacks in m icroprocessors are used
for high speed events, such as subroutines and interrupts, a contin­
uous block is usually allocated to the stack rath e r th an using a
linked list.

Linked L ist vs. Block

Similarly, the queue could be im plem ented as a block of reserved

locations. The advantage of using a continuous block is fast
retrieval and the elim ination of the pointers. The disadvantage is
th a t it is usually necessary to dedicate a fairly large block to ac­
com m odate th e worst-case size of the structure. Also, it m akes it
difficult or im practical to insert or remove elem ents from w ithin
the block. Since mem ory is traditionally a scarce resource, blocks
have been traditionally reserved for fixed-size stru ctu res or else
stru ctu res requiring the m axim um speed of retrieved, such a s the
stack.

Circular L ist

“ Round robin” is a common nam e for a circular list. A circular

list is a linked list where the la st en try points back to the first one.
This is illustrated in Figure 9-6. In the case of a circular list, a
current-block pointer is often kept. In the case of events or pro­
gram s w aiting for service, the current-event pointer will be moved
by one position to the left or to the rig h t every tim e. A round-robin
usually corresponds to a stru ctu re where all blocks are assum ed to
have the same priority. However, when performing a search a circular
list may also be used as a subcase of other structures simply to facilitate
the retrieval of the first block after the last one.
A s an example of a circular list, a polling program usually goes
around in a round-robin fashion, interrogating all peripherals and
th en coming back to the first one.

C U R R E N T EVENT

Fig. 9-6: Round-Robin is Circular List

Trees

W henever a logical relationship exists between all elem ents of a

stru ctu re (this is usually called a syntax), a tree stru ctu re m ay be
used. A simple example of a tree stru ctu re is a descendant tree or a
genealogical tree. This is illustrated in Figure 9-7. I t can be seen
th a t Sm ith has two children: a son, Robert, and a daughter, Jane.
Jane, in turn, has three children: Liz, Tom and Phil. Tom, in tu rn
has two more children: M ax and Chris. However, Robert, on the
left of the illustration, has no descendants.
This is a stru ctu red tree. We have, in fact, already encountered
an example of a simple tree in Figure 9-2. The directory stru ctu re
is a two-level tree. Trees are used to advantage whenever elem ents
m ay be classified according to a fixed structure. This facilitates in­
sertion and retrieval. In addition, trees may establish groups of infor­
mation in a structured way. Such information may be required for later
processing, such as in a compiler or interpreter design.

Doubly-Linked L ists
A dditional links m ay be established between elem ents of a list.
The sim plest example is the doubly-linked list. This is illustrated
in Figure 9-8. W e can see th a t we have the usual sequence of links
from left to right, plus another sequence of links from rig h t to left.
 Fig. 9-7: G enealogical Tree

The goal is to allow easy retrieval of th e elem ent ju s t before the

one which is being processed, as well as the one just after it. This costs
an extra pointer per block.

Fig. 9-8: Doubly-Linked List

SE A R C H IN G AN D SO RTIN G

Searching and sorting elem ents of a list depend directly on the

type of stru ctu re which has been used for the list. M any searching
algorithm s have been developed for the m ost frequently used d a ta
structures. W e have already used indexed addressing. This is pos­
sible whenever the elem ents of a table are ordered in function of a
known criterion. Such elem ents m ay then be retrieved by their
num bers.
Sequential searching refers to th e linear scanning of an entire
block. This is clearly inefficient but, for lack of a better technique, may
have to be used whenever the elements are not ordered.
 Binary , or logarithmic searching, a tte m p ts to find an elem ent in a
sorted list by dividing the search interval in half a t every step.
A ssum ing, for example, th a t we are searching an alphabetical list,
one might start in the middle of a table and determine if the name
for which we are looking is before or after this point. If it
is after this point, we will elim inate the first half of the table and
look a t the middle elem ent of the second half. We again compare
this entry to the one for which we are looking, and restrict our search
to one of the two halves, and so on. The m axim um length of a
search is then guaranteed to be log2n, where n is the num ber of
elem ents in the table.
M any other search techniques exist.

SUM M ARY

This section was intended as only a brief presentation of typical

d a ta stru ctu res which m ay be used by a program m er. A lthough
m ost common d a ta stru ctu res have been rationalized in types and
given a name, the overall organization of d a ta in a complex system
m ay use any com bination of them , or require the program m er to
invent more appropriate structures. The array of possibilities is
lim ited only by the im agination of the program m er. Similarly, a
num ber of well-known sorting and searching techniques have been
developed to cope w ith the usual d a ta structures. A comprehensive
description is beyond the scope of this book. The contents of this
section were intended to stress the im portance of designing appro­
priate d ata stru ctu res for the data to be m anipulated and to pro­
vide the basic tools to th a t effect.
DATA STRUCTURES
PART II: D ESIG N EXAM PLES
INTRO D U CTIO N

A ctual design exam ples will be presented here for typical d a ta

structures: table, linked list, sorted tree. Practical sorting, search­
ing and insertion algorithm s will be program m ed for these stru c ­
tures. A dditional advanced techniques such as hashing and m erg­
ing will also be described.
The reader interested in these advanced program m ing tech­
niques is encouraged to analyze in detail the program s presented
in this section. However, th e beginning program m er m ay skip this
section initially, and come back to it when he feels ready for it.
A good understanding of the concepts presented in the first p a rt
of this chapter is necessary to follow the design examples. Also,
the program s will use all the addressing modes of the 6502, and
integrate many of the concepts and techniques presented in the
previous chapters.
Four stru ctu res will now be introduced: a simple list, an alpha­
betical list, a linked list plus directory, and a tree. For each stru c­
ture, three program s will be developed: search, enter and delete.
In addition, three specialized algorithms will be described separately
at the end o f the section: hashing, bubble-sort, and merging.
 ENTLEN LENGTH OF ENTRY

TABLEN NUMBER OF ENTRIES

TAB BASE r
LABEL

ENTRY i DATA M BYTES

ENTER NEW ELEMENT

hA W l
Fig. 9-9: The Table Structure

ENTLEN

ENTLEN
D A TA R E P R E S E N T A T IO N FO R T H E L IST
B oth the sim ple list and the alphabetic list will use a common re­
presentation for each list element:

3-byte label d a ta

E ach elem ent or “ e n try ” includes a 3-byte label and an n-byte

block of data with n between 1 and 253. Thus, each entry uses, at
most, one page (256 bytes). Within each list, all elements have the
sam e length (see Fig. 9-10). The program s operating on these two
simple lists use some common variable conventions:
E N T L E N is the length of an element. For example, if each ele­
m ent has 10 bytes of data, E N T L E N = 3 + 10 = 13 bytes
TA BA SE is th e base of the list or table in the m emory
PO IN TR is a running pointer to the current elem ent
O B JE C T is the current en try to be inserted or deleted
TA BLE N is the num ber of entries
All labels are assum ed to be distinct. Changing this convention
would require a m inor change in the program s.

A S IM P L E L IS T

The simple list is organized as a table of n elem ents. The

elem ents are n o t sorted (see Fig. 9-11).
W hen searching, one m u st scan through the list until an e n try is
found or the end of the table is reached. W hen inserting, new en­
tries are appended to the existing ones. W hen an entry is deleted,
the entries in higher mem ory locations, if any, will be shifted down
to keep the table continuous.

Searching
A serial search technique is used. E ach e n try ’s label field is com­
pared in tu rn to th e O B JE C T ’S label, lette r by letter.
The running pointer PO IN TR is initialized to the value of
TA BA SE.
The index register X is initialized to the num ber of entries con­
tained in the list (stored a t TA BLE N).
 Fig. 9-11: The Simple List

The search proceeds in the obvious way, and the corresponding

flow chart is shown in Fig. 9-12. The program appears in Fig.
9-16 a t the end of this section (program “ SE A R C H ”).

Element Insertion
W hen inserting a new element, the first available mem ory block
of (ENTLEN) bytes a t the end of the list is used (see Fig. 9-11).
The program first checks th a t th e new en try is not already in the
list (all labels are assum ed to be distin ct in th is example). If not, it
increm ents the list length TA BLEN , and moves th e O B JE C T to
th e end of the list. The corresponding flow chart is shown on Fig.
9-13.
The program is shown on Fig. 9-16 a t th e end of this section. I t is
called “ N E W ” and resides a t m em ory locations 0636 to 0659.

Element Deletion
In order to delete an elem ent from the list, the elem ents follow­
ing it at higher addresses are merely moved up by one element position.
The length of the list is decremented. This is illustrated in Fig. 9-14.
SEARCH
 END

Fig. 9-13: Table Insertion Flowchart

The corresponding program is straightforw ard and appears in

Fig. 9-16. I t is called “ D E L E T E ” and resides a t m em ory ad­
dresses 0659 to 0686. The flow chart is shown in Fig. 9-15.
M emory location T E M PT R is used as a tem porary pointer point­
ing to the elem ent to be moved up.
Index register Y is set to the length of a list elem ent, and used to
autom ate block transfers. N ote th a t indirect indexed addressing is
used:
(0672) LOOPE DEY
LDA (TEMPTR), Y
STA (POINTR), Y
cpy to
BN E LOOPE
D uring the transfer, PO IN T R alw ays points to the “ hole” in the
list, i.e. the destination of the n ext block transfer.
The Z flag is used to indicate a successful deletion upon exit.
 BEFORE AFTER

o ©
© _ ©

© ©
DELETE •
© ) MOVE _ ©
TEMPTR • J
_ . ® 'N
\ MOVE
©
©

Fig. 9-14: Deleting An Entry (Simple List)

A L P H A B E T IC L IST

The alphabetic list, or “ tab le ” unlike the previous one, keeps all
its elem ents sorted in alphabetic order. This allows the use of
faster search techniques then the linear one. A binary search is
used here.

Searching
The search algorithm is a classical binary search. L et us recall
th a t the technique is essentially analogous to the one used to find a
name in a telephone book. One usually starts soinewhere in the middle
of the book, and then, depending on the entries found there, goes either
backwards or forwards to find the desired entry. This method is fast,
and it is reasonably simple to implement.
The binary search flow chart is shown in Fig. 9-17, and the pro­
gram is shown in Fig. 9-22.
This list keeps the entries in alphabetical order and retrieves
them by using a binary or “ logarithm ic” search. A n example is
shown in Fig. 9-18.
LINE 9 LOC CODE LINE

0042 4040 TABASE * 414

0409 4040 POINTS > 112
0444 4900 TAKEN ■ 414
0449 0000 OBJECT ■ 413
0444 0000 ENTLEN « 417
0447 0000 TENPTR > 418
0449 4000 ;
0409 4000 •*4404
0414 0600 ;
0411 0600 A9 10 SEARCH LDA TABASE .'INITIALIZE POINTER
0012 0602 99 12 STA POINTR
0413 0604 A9 11 LBA TABASE*1
0414 0606 99 13 STA POINTR*1
0419 0409 A4 14 LBX TABLEN •STORE TAKER AS A VARIABLE
0414 040A FO 29 BEO OUT ,
'CHECK FOR 4 TAKE
0417 040C AO 99 ENTRY LBV 40 .COMPARE FIRST LETTERS
0419 040E B1 13 LBA (OBJECT).Y
0419 0410 B1 12 CMP (POINTR).Y
0020 4412 BO OE ONE N0600B
0421 0614 C9 INY .'COMPARE SECOND LETTERS
0422 0613 B1 19 LBA (OBJECT),V
0423 0617 01 12 CMP (POINTR),Y
0024 0419 00 47 ONE N0600D
0423 0610 C9 INY •COMPARE TNIRB LETTERS
0426 461C 11 19 LBA (OBJECT),Y
0027 061E 01 12 CMP (POINTR),Y
0428 0620 FO 11 BEO FOUND
0429 0622 CA N0600D BEX ,'SEE ROU RASY EATIIES ARE LEFT
0434 4623 FO 10 BEO OUT
0431 0629 A3 17 LBA ENTLEN ;abb ertler to pointer
0432 0627 18 CLC
0433 4628 63 12 ADC POINTR
0434 062A 89 12 STA POINTR
0439 062C 90 DE BCC ENTRY
0436 062E E6 13 INC POINTR*l
0437 0630 4C OC 06 JHP ENTRY
0438 0633 49 FF 1FOUND LDA 84FF .CLEAR Z FLAS IF FOUND
0439 0633 60 |BUT RTS
0440 0636
0041 0636
0042 0636
0443 0636 20 00 06 NEU JSR SEARCH ,'SEE IF OBJECT IS THERE
0444 0639 BO ID BNE OUTE
0449 0630 A6 14 LDX TABLEN JCHECK FOR 0 TABLE
0046 4630 FO 00 BEO INSERT
0447 063F AS 12 LDA POINTR .'POINTER IS AT LAST ENTRY
0448 0641 18 CLC .'..MUST HOVE IT TO END OF TAKE
0449 0642 69 17 ADC ENTLEN
0494 0644 89 12 STA POINTR
0491 0646 90 02 BCC INSERT
0492 0648 E6 13 INC POINTS*)
0493 064A E6 14 INSERT INC TABLEN ,
'INCREMENT TAKE LEN8TH
0094 064C AO 00 LDY NO ;hove object to e nd of t a k e
0493 064E A6 17 LBX ENTLEN
0496 0690 B1 19 LOOP LOA (OBJECT),Y
0437 0692 91 12 STA (POINTR).Y
0438 0694 C8 INY
0439 0633 CA DEX
0460 4636 BO F8 BNE LOOP
0461 0638 60 OUTE RTS ;z SET IF UA8 DONE
0462 0639
0463 0699
0464 0699
0463 0699 20 00 06 DELETE JSR SEARCH .'FIND 9HERE OBJECT 18
0466 46SC FO 2D BEO OUTS jexit if not fooni
0467 469E C6 14 DEC TABLEN .'DECREMENT TAKE LENGTH
0468 0660 CA DEX I8EE HOW MANY ENTRIES ARE
0069 0661 F0 26 IE0 DONE AFTER ONE TO DE DELETED
0070 0663 65 12 6DDEN LD6 POINTR ;6ID ENTLEN TO POINTER AND
0071 0665 18 CLC J..SAVE AT TENP STORAGE
0072 0666 65 17 6DC ENTLEN
0073 0668 85 18 ST6 TENPTR
0074 066A 69 00 LD6 10
0075 066C 65 13 6DC POINTR+1 {ADO CARRY TO HIGH BYTE
0076 066E 85 19 ST6 TENPTR+1
0077 0670 64 17 LOT ENTLEN
0070 0672 88 LOOPE DEY
0079 0673 11 18 LD6 (TENPTR),Y JSHIFT ONE ENTRY OF HENORY DOUN
0080 0675 91 12 ST6 (POINTR)rY
008) 0677 CO 00 CPY 10
0002 0679 DO F7 BNE LOOPE
0083 0678 C6 DEX JIECRENENT ENTRY COUNTER
0004 067C F0 08 BEG DONE
0085 067E 65 18 LD6 TENPTR ;NOVE TENP TO POINTER
0086 0680 85 12 STA POINTR
0007 0682 65 19 LD6 TEHPTR+1
0080 0684 85 13 STA POINTR+1
0089 0686 4C 63 06 JHP ADDER
0090 0689 69 FF DONE LD6 MFF ;CLEAR Z FLA6 IF IT UAS DONE
0091 0600 60 OUTS RTS
0092 O60C ;
0093 068C »
0094 068C .END

E8RQRS * 0000 <0000>

SYNB8L TABLE

SYNDOL VALUE

ADDER 0663 DELETE 0659 IONE 0689 ENTLEN 0117

ENTRY 060C FOUND 0633 INSERT 064A LOOP 0650
LOOPE 0672 NEU 0636 NOSOOD 0622 OBJECT 0015
O0T 0635 OUTE 0658 OUTS O60B POINTR 0112
SEARCH 0600 TABASE 0010 TABLEN 0014 TENPTR 0111

END OF A88EHBLY

Fig. 9-16: Simple List Programs: Search, Enter, Delete (cont.)

 NOT FOUND

(ENTRY)

(NEXT) (LAST ONE)

(NEXT) (LAST O N I)

YES

CLOSE NOW =
COMMIES

YES

(ENTRY)

Fig. 9-17: Binary Search Flowchart (cont.)

The search is somewhat complicated by the need to keep track of
several conditions. The major problem to be avoided is searching for an
object that is not there. In such a case, the entries with the immediately
higher and lower alphabetic values could be alternately tested forever.
To avoid this, a flag is maintained in the program to preserve the value
of the carry flag after an unsuccessful comparison. When the INCMNT
value, which shows by how much the pointer will next be incremented,
reaches a value of “ 1” , another flag called “ CLOSE” is set to the value
of the CMPRS flag. Thus, since all further increments will be “ 1,” if
the pointer goes past the point where the object should be, CMPRES
will not longer equal CLOSE, and the search will terminate. This fea­
ture also enables the NEW routine to determine where the logical and
physical pointers are located, relative to where the object will go.
Thus, if the O B JE C T searched for is not in the table, and the
running pointer is increm ented by one, the CLOSE flag will be set.
On the next pass of the routine, the result of the com parison will be
opposite to the previous one. The tw o flags will no longer m atch,
and the program will exit indicating “ not found

IABASE
 The other m ajor problem th a t m u st be dealt w ith is the possibili­
ty of running off one end of the table when adding or su b tractin g
the increment value. This is solved by performing an “ add” or
“ subtract” test using the logical pointer and length value to determine
the actual number of entries, rather than using physical pointers to
determine their mere physical positions.
In sum m ary, two flags are used by the program to memorize in­
formation: CMPRES and CLOSE. The CMPRES flag is used to
preserve the fact that the carry was either “ 0” or “ 1” after the
most recent comparison. This determines if the element under test
was larger or smaller than the one to which it was compared. Whenever
the carry C is “ 1,” the entry is smaller than the object, and CMPRES
is set to “ 1.” Whenever the carry C is “ 0,” the entry is greater than the
object, and CMPRES will be set to “ FF.”
Also note that when the carry is “ 1” , the running pointer will point
to the entry below the OBJECT.
The second flag used by the program is CLOSE. This flag is set
equal to CMPRES when the search increment INCMNT
becomes equal to “ 1.” It will detect the fact that the element has
not been found if CMPRES is not equal to CLOSE the next time
around.
O ther variables used by the program are:
LOGPOS, which indicates the logical position in the table (ele­
m ent num ber).
INCM NT, which represents th e value by which the running
pointer will be increm ented or decrem ented if the next com parison
fails.
TA B LEN represents, as usual, the to ta l length of th e list.
LOGPOS and INCM NT will be com pared to TA B LEN in order to
ascertain th a t the lim its of the list are not exceeded.
The program called “ S E A R C H ” is shown in Fig. 9-22. I t resides
a t mem ory locations, 0600 to 06E3, and deserves to be studied
w ith care, as it is m uch m ore complex th an in the case of a linear
search.
A n additional com plication is due to the fact th a t the search
interval m ay a t tim es be either even or odd. W hen it is even, a cor­
rection must be introduced. It cannot, for instance, point to the middle
element of a 4-element list.
W hen it is odd, a “ tric k ” is used to point to the m iddle element:
the division by 2 is accomplished by a rig h t shift. The b it “ falling
o u t” into th e carry after the LSR instruction will be “ 1” if the in­
terval was odd. I t is m erely added back to the pointer:
(0615) D IV LSR A D IV ID E BY TWO
ADC #0 PIC K U P CARRY
STA LOGPOS N E W PO IN T E R
The O B JE C T is then m atched ag ain st the en try in the m iddle of
the new search interval. If the com parison succeeds, the program
exits. Otherw ise (“ NOGOOD” ), the carry is set to 0 if th e OB­
JE C T is less th a n the entry. W henever the INCM N T becomes “ 1” ,
the CLOSE flag (which had been initialized to “0 ” ) is then checked
to see if it was set. If it was not, it gets set. If it was set, a check is
run to determ ine w hether we passed the location where th e OB­
JECT should have been but was not found.

E lem ent Insertion

In order to in sert a new elem ent, a binary search is conducted. If

the elem ent is found in the table, it does n o t need to be inserted.
(We assum e here th a t all elem ents are distinct). If the elem ent was
not found in the table, it must be inserted. The value of the CMPRES
flag after the search indicates whether this element should be inserted
immediately before or immediately after the last element to which it
was compared. All the elements following the new location where it is
going to be placed are then moved down by one block position, and the
new element is inserted.
The insertion process is illu strated in Figure 9-19 and the corres­
ponding program appears on Figure 9-22.
The program is called “ NEW” , and resides at memory locations
06E3 to 075E.
N ote th a t indirect indexed addressing is used again for block
transfers:
(072A) LDY ENTLEN
A N OTH R DEY
LDA (POINTR), Y
STA (TEMP), Y
CPY #o
BN E A N O TH R
Observe the sam e a t m em ory location 0750.
 BEFORE AFTER

Fig. 9-19: Insert: “BAC”

E lem ent Deletion

Similarly, in order to delete an element, a binary search is conducted
to find the object. If the search fails, it does not need to be deleted. If
the search succeeds, the element is deleted, and all the following ele­
ments are moved up by one block position. A corresponding example is
shown in Fig. 9-20, and the program appears in Figure 9-22. The flow­
chart is shown in Fig. 9-21.
I t is called “ D E L E T E ,” and resides a t m em ory addresses
075F to 0799.

LINKED LIST
The linked list is assum ed to contain, as usual, the three alpha­
num eric characters for the label, followed by 1 to 250 bytes of data,
followed by a 2-byte pointer which contains the sta rtin g address of
the next entry, and lastly followed by a 1-byte marker. Whenever this
1-byte m arker is set to “ 1,” it will prevent the insert-routine from
su b stitu tin g a new en try in the place of the existing one.
 F urther, a directory contains a pointer to the first en try for each
le tte r of the alphabet, in order to facilitate retrieval. I t is assum ed
in the program th a t the labels are A S C II alphabetic characters.
All pointers a t the end of the list are set to a N IL value which has
been chosen here to be equal to the table base, as this value should
never occur w ithin the linked list.
The insertion and the deletion program perform the obvious pointer
manipulations. They use the flag INDEXD to indicate if a pointer
pointing to an object came from a previous entry in the list or
from the directory table. The corresponding programs are shown in
Fig. 9-27. the data structure is shown in Fig. 9-23.
A n application for this d a ta stru ctu re would be a com puterized
address book, where each person is represented by a unique
3-letter code (perhaps the usual initials) and the d a ta field contains
a simplified address, plus the telephone num ber (up to / 250
characters).

BEFORE

MOVE UP
ABC
i i

BAC

BAT

TAR

ZAP

DELETE
DELETE

OUTS

RTS
 LIM£ • IOC CODE LINE

0002 0000 CLOSE - 010

0003 0000 CNPRES • 011
0004 0000 TOIOSE >012
0003 0000 POINTR * 014
0006 0000 TAKEN • 016
0007 0000 L06P0S * 017
0008 0000 INCNNT • 018
0009 0000 TENP « 019
0010 0000 ENTLEN > 018
0011 0000 OBJECT * 01C
0012 0000
0013 0000 • « 0600
0014 0600
0013 0600 09 00 SEARCH LDA NO
0016 0602 83 10 ;ZERD FLAGS
STA CLOSE
0017 0604 85 11 STA CNPRES
0018 0606 05 12 LBA TABASE
0019 0608 85 14 JIN ITIA LIZ6 POINTER
STA POINTR
0020 0600 05 13 LDA TABASE+1
0021 06OC 85 15 STA POINTR*I
0022 060E 05 16 LDA TABLEN
0023 0610 00 03 ,*GET TABLE LENGTH
BNE DIV
0024 0612 4C EO 06 JNP OUT
0025 0615 40 DIV LSR A
0026 0616 69 00 .‘ DIVIDE IT BY 2
ADC 10 .’ ADD BACK IN I'S BIT
0027 0618 85 17 STA L06P0S
0028 0610 85 18 •STORE AS LOGICAL POSITION
STA INCNNT ,•STORE AS INCRENENT VALUE
0029 06IC 06 17 LDX L06P0S
0030 06 IE CO .•NULTIPLY ENTLEN BY LOGPOS
DEX ADDING RESULT TO POINTER
0031 06IF FO OE 8E0 ENTRY
0032 0621 05 18 LOOP LDA ENTLEN
0033 0623 18 CLC
0034 0624 65 14 ADC POINTR
0035 0626 85 14 STA POINTR
0036 0626 90 02 BCC LOPP
0037 0620 E6 15 INC POINTRM
0038 062C CO LOPP DEX
0039 0628 DO F2 BNE LOOP
0040 0 6 2 F 05 18 ENTRY LDA INCNNT
0041 0631 40 .’ DIVIDE INCRENENT VALUE BT 2
LSR A
0042 0632 69 00 ADC NO
0043 0634 85 18 STA INCNNT
0044 0636 00 00 LOT NO ; COMPARE FIRST LETTERS
0045 0638 II 1C LDA (OBJECT),Y
0046 0630 01 14 CNP (POINTR),Y
0047 063C DO 11 BNE NOGOOD
0048 063E C8 INY
0049 063F Bf 1C ,‘ CONPARE 2ND LETTERS
LDA (OBJECT),Y
0050 0641 81 H CNP (POINTR),Y
0051 0643 DO 00 BNE N0600D
0052 0645 C8 INY
0053 0646 81 1C ,-CONPARE 3RD LETTERS
LDA (OBJECT),Y
0054 0648 Dt 14 CNP (POINTR),Y
0055 0640 DO 03 BNE NOGOOD
0056 064C 4C E2 06 JNP FOUND
0057 064F 00 FF NOGOOD LDY NIFF ,*SET COMPARE RESULT FLAG
0058 0651 90 02 BCC TESTS
0059 0653 00 01 JIF OBJ < POINTR : C-0
LDY Nl
0060 0655 84 II TESTS STY CNPRES
0061 0657 04 18 LDY INCNNT
0062 0659 88 ; IS INCR. VALUE A 1?
DEY
0063 0650 DO 10 BNE NEXT
0064 065C 05 10 LDA CLOSE I CHECK CLOSE FLAG IF IT UAS
0065 065E FO 08 BEO NAKCLO
0066 0660 38 ;IF CLOSE FLAG NOT SET, GO DO IT
SEC
0067 0661 E5 11 SBC CNPRES
0068 0663 FO 07 ,*SEE IF GAVE PASSED UNERE OBJ.
BEO NEXT SHOULD BE BUT ISNT
0069 0665 4C EO 06 JNP OUT
0070 0668 AS 11 HAKCLO LBA CNPRES {SET CLOSE FLAB TO CNPRES
0071 066A 85 10 STA CLOSE
0072 066C 24 11 NEXT BIT CNPRES
0073 066E 30 33 BNI SUBIT
0074 0670 A5 16 LDA TABLEN ;SEE IF ADDITIION OF INCNNT
0075 0672 38 SEC {..UILL RUN FAST END OF TABLE
0076 0673 E5 17 SBC L06P0S
0077 0673 FO 69 BEQ OUT ;CHECK TO SEE IF IT END OF TAILE ILREIDY
0078 0677 E5 18 SBC INCNNT
0079 0679 90 IA ICC TOONI
0080 0671 A6 18 LDX INCNNT ;IS ALL RIGHT, INC POINTER IT
006! 067D A5 11 ADDER LDA ENTLEN {..PROPER ANOUNT
0082 067F 18 CLC
0083 0680 63 14 ADC POINTR
0084 0682 85 14 STA POINTR
0083 0684 90 02 BCC ADI
0086 0686 E6 13 INC POINTR-M
0087 0688 CA ADI BEX
0086 0689 10 F2 BNE ADDER
0089 0681 A3 17 LDA LO8P08 ;INCREMENT LOGICAL POSITION
0090 0681 18 CLC
0091 068E 65 18 ADC INCNNT
0092 0690 85 17 STA L06P08
0093 0692 4C 2F 06 JNP ENTRY
0094 0693 E6 17 TOOHI INC L08P08 {INCR. LOGICAL POSITION
0093 0697 A3 11 LDA ENTLEN {HOVE POINTER UP ONE ENTRY
0096 0699 11 CLC
0097 069A 63 14 ADC POINTR
0098 069C 85 14 STA POINTR
0099 069E 90 35 BCC SETCLO
0(00 06AO E6 13 INC POINTRH
0101 06A2 4C D3 06 JNP SETCLO
0102 06A5 A3 17 SUB1T LDA LOGPOS {SEE IF INC WILL GO OFF IOTTON
0103 06A7 38 SEC {..OF TAILE
0104 06A8 E5 18 SBC INCNNT
0105 06AA FO 17 BEQ TOOLOU
0106 06AC 90 15 BCC TOOLOU
0107 06AE 85 17 STA L08P08 {SAVE NEU LOGICAL POSITION
0108 0610 A6 18 LDX INCNNT
0109 06B2 A5 14 SUBLOP LDA POINTR {SUBTRACT PROPER ANT. FRON POINTER
0110 0614 38 SEC
0111 0615 E3 11 SBC ENTLEN
0112 0617 85 14 STA POINTR
0(13 06B9 10 02 BCS SUBO
0114 06IB C6 IS DEC POINTR+1
0113 06ID CA SUBO DEX
0116 06BE DO F2 BNE SUBLOP
0117 06C0 4C 2F 06 JNP ENTRY
one 06C3 A6 17 TOOLOU LDX L08P08 {SEE IF POS IS ALREADY 1
0119 06C3 CA DEX
0120 06C6 FO 18 BEO OUT
0121 06C8 C6 17 DEC LOSPOS
0122 06CA AS 14 LDA POINTR {SUB t ENTRY FRON POINTER
0123 06CC 38 SEC
0124 06CD E5 IB SBC ENTLEN
0123 06CF 85 14 STA POINTR
0126 0601 BO 02 BCS SETCLO
0127 06B3 C6 15 DEC POINTRH
0128 0615 A9 01 SETCLO LDA 11
0129 0617 85 18 STA INCNNT
0130 06D9 AS 11 LDA CNPRES
0131 06DI 85 10 STA CLOSE
0132 06DD 4C 2F 06 JNP ENTRY
0133 06E0 A2 FF OUT LDX NIFF {Z SET IF FOUND
0134 06E2 60 FOUND RTS
0135 06E3 J
0136 06E3 t
0137 06E3 t
0138 06E3 20 00 06 NEU JSR SEARCH {SEE IF OBJECT IS ALREADY THERE
 0139 06E6 FO 76 BEO OUTE
0140 06E8 A5 16 IDA TABLE*
0141 06EA FO 62 .•CHECK FOR 0 TABLE
BEO INSERT
0142 06EC 24 11 BIT CHPRES
0143 06EE 10 05 ; t est la st conpare r esu lt
BPL LOSIDE
0144 06F0 C6 17 DEC L08P0S
0145 06F2 4C 00 07 ;SET LOGICAL POSITION SO
JNP SETUP ,*..SUB UORKS LATER
0146 06F5 A5 IB LOSIDE LDA ENTLEN
0147 06F7 18 ,*SET POINTER ABOVE WHERE
CLC .'..OBJECT UILL GO
0148 0 6 F8 65 14 ADC POINTR
0149 06FA 85 14 STA POINTR
0150 06FC 90 02 BCC SETUP
0151 06FE E6 15 INC POINTR+1
0152 0700 A5 16 SETUP LDA TABLEN
0153 0702 38 .'SEE HOU HANY ENTRIES THERE
SEC .’ ..ARE AFTER UHERE OBJ. WILL GO
0154 0703 E5 17 SBC LOGPOS
0155 0705 FO 47 BEO INSERT
0156 0707 AA TAX
0157 0708 A8 TAT
0158 0709 88 DEY
0159 070A FO OE SEE IF ALREADY POINTING TO
BEO SETEHP ..LAST ENTRY
0160 070C AS IB UPLOOP LDA ENTLEN
0161 070E 18 HOVE POINTER TO LAST ENTRY
CLC
0162 070F 65 14 ADC POINTR
0163 0711 85 14 STA POINTR
0164 0713 90 02
BCC SETO
0165 0715 E6 15 INC POINTS!
0166 0717 88 SETO DEY
0167 0718 DO F2 BNE UPLOOP
0168 071A A5 14 SETENP LDA POINTR
0169 071C 18 JADD ENTLEN TO POINTER
CLC STORE AT TENP
0170 07ID 65 IB ADC ENTLEN
0171 071F 85 19 STA TENP
0172 0721 90 01 BCC SET1
0173 0723 C8 INY
0174 0724 98 ;r WAS ALREABT 0
SET1 TYA
0175 0725 18 CLC
0176 0726 65 15 ADC POINTR*1
0177 0728 85 1A STA TENP+1
0178 072A A4 IB NOVER LDY ENTLEN .'SET Y FOR SHIFT
0179 072C 88 ANOTHR DEY
0180 072D B1 14 LDA (POINTR),! ,*H0V£ A BYTE
0181 072F 91 J9 STA (TENP),Y
0182 0731 CO 00 CPY 10
0183 0733 DO F7 BNE ANOTHR
0184 0735 A5 14 LDA POINTR ,'DECR. POINTER AND TENP
0185 0737 38 SEC .'..BY ENTLEN
0186 0738 E5 IB SBC ENTLEN
0187 073A 85 14 STA POINTR
0188 073C BO 02 BCS N1
0189 073E C6 15 DEC POINTR*1
0190 0740 CA Nl DEX
0191 0741 DO D7 BNE SETEHP
0192 0743 A5 IB LDA ENTLEN .HOVE POINTER BACK TO
0193 0745 18 CLC
0194 0746 65 14 ,‘ UHERE OBJ. UILL 60
ADC POINTR
0195 0748 85 14 STA POINTR
0196 074A 90 02 BCC INSERT
0197 074C E6 15 INC POINTR+1
0198 074E AO 00 INSERT LDY 10
0199 0750 A6 IB ,'HOVE OBJECT INTO TABLE
LDX ENTLEN
0200 0752 Bf 1C INNER LDA (OBJECT),Y
0201 0754 91 14 STA (POINTR),Y
0202 0756 C8 INY
0203 0757 CA DEX
0204 0758 DO F8 BNE INNER
0205 075A E6 16 INC TABLEN .'INCREMENT TABLE LENGTH
0206 075C A2 FF LDX NIFF
0207 079E 00 OUTE RTS ;z SET IF NOT DINE
0208 07SF i
0209 07SF 1
0210 079F i
02tt 079F 20 00 00 8ELETE J88 SEARCH ;6ET ADOS OF OBJECT IN TAIL!
0212 0702 00 t o ONE OUTS ;SEE IF IT IS THERE
0213 0704 89 10 LOR T80LEN ;SEE HOU N8NY ENTRIES ARE
0 2H 0700 38 SEC I..LEFT AFTER OBJ. IN TABLE
0219 0707 E9 17 80C L06P0S
0210 0709 F0 28 8E0 OECER
0217 0708 89 (7 ST8 L06P0S ;STORE RESULT 88 A COUNTER
0218 0708 89 18 8I6L0P IDO ENTLEN ;8ET TEMP 8 ENTRY ABOVE 1 ENTRY ABOVE OBJ.
0219 070F 18 CLC
0220 0770 09 14 80C POINTS
0221 0772 69 19 ST8 TEMP
0222 0774 89 00 LD8 80 '
0223 0770 09 19 ROC POINTRH
0224 0778 89 18 8T8 TEHP*1
0229 0778 80 18 LDX ENTLEN ;SET COUNTERS
0220 077C 80 00 LOT 80
0227 077E 81 19 8VTC LOR <TENP),Y JHOVE 8 OYTE
0228 0780 91 14 8T8 (POINTS),V
0229 0782 C8 INY ;is BLOCK NBVEO YET?
0230 0783 C8 8EX
0231 0784 DO F8 ONE OYTE
0232 0780 89 18 LDA ENTLEN
0233 0788 18 CLC
0234 0789 09 14 ROC POINTS
0239 0788 89 14 ST8 POINTS
0230 0788 90 02 ICC 02
0237 078F EO 19 INC POINTS*!
0238 0791 CO 17 D2 DEC L08P0S
0239 0793 80 08 ONE 8I6L0P
0240 0799 CO 10 DECER DEC T8BLEN
0241 0797 89 00 LD8 80 ;z SET IF UAI DONE
0242 0799 00 OUTS RTS
0243 0798 .END

E8R088 • 0000 <0000>

8YNB0L TABLE

8THB0L VALUE

A01 0688 ADDER 0678 ANDTHR 072C BICLOP 074D

BYTE 077E CLOSE 0010 CHPRES 0011 D2 0791
OECER 0799 DELETE 075F DIV 0619 ENTLEN 0018
ENTRY 062F FOUND 06E2 INCNNT 0018 INNER 0752
INSERT 074E L06P0S 0017 LOOP 0621 LOPP 062C
L08I0E 06F9 HI 0740 N8KCL0 0668 HOVER 072A
NEU 06E3 NEXT 066C N0800D 064F OBJECT OOIC
OUT 06E0 OUTE 073E OUTS 0799 POINTR 0014
SEARCH 0600 SETO 0717 SET1 0724 SETCLO 0685
SETENP 0718 SETUP 0700 SUOO 0688 SUBIT 06A9
SUOLOP 06B2 TABASE 0012 TA8LEN 0016 TEHP 0019
TESTS 0699 TOOHI 0699 TOOLOU 06C3 UPLOOP O70C

EBB OF ASSENIIY
 L et us examine the stru ctu re in more detail in Fig. 9-23.
The en try form at is:

unique label data (1 to 250 bytes) pointer to

(ASCII) next I
occupied

A s usual the conventions are:

EN TLEN : total elem ent length (in bytes)
TA BASE: address of base of list
TABLEN : num ber of entries (1 to 256)

Here, R E FB A SE points to the base address of the directory, or

“ reference table.”
Each two-byte address w ithin this directory points to the first
occurrence of the letter to which it corresponds in the list. Thus
each group of entries w ith an identical first letter in their labels ac­
tually form a separate list w ithin the whole structure. This feature
facilitates searching and is analogous to an address book. Note
th a t no d ata are moved during an insert or a delete. Only pointers
are changed, as in every well-behaved linked list structure.
DIRECTORY
 If no en try s ta rtin g w ith a specific lette r is found, or if there is no
entry alphabetically following an existing one, their pointers will
point to the beginning of th e table (= “ N IL ”). A t the bottom of the
table, by convention, a value is stored such th a t the absolute value
of the difference betw een it and “ Z ” is greater th an the difference
betw een “ A ” and “Z .” This represents an E n d Of Table (EOT)
m arker. The EO T value is assum ed here to occupy the same
am ount of mem ory as a norm al en try b u t could be ju s t one b yte if
desired.
The letters are assum ed here to be alphabetic letters in A S C II
code. C hanging this would require changing the constant a t the
PR ETA B routine.
The E nd Of Table m arker is set to the value of the beginning of
the table (“ N IL ”).
By convention, the “ NIL pointers,” found either at the end of a
string or within a directory location which does not point to a string,
are set to the value of the table base to provide a unique identifica­
tion. A nother convention could be used. In particular, a different
m arker for EO T would result in some space savings, as no N IL
entries need be k ept for nonexisting entries.
Insertion and deletion are perform ed in the usual way (see P a rt I
of this chapter) by merely m odifying the required pointers. The
IN D E X D flag is used to indicate if the pointer to the object is in
the reference table or another strin g element.

Searching
The SEA RC H program resides a t mem ory locations 0600 to
0650. In addition, it uses subroutine PR ETA B a t address 06F8.
The search principle is straightforw ard:
1— G et the directory en try corresponding to the lette r of the
alphabet in the first position of the O B JE C T ’S label.
2— Get the pointer out of the directory. Access the element. If NIL,
the entry does not exist.
3— If not N IL, m atch the elem ent against the O B JECT. If a
m atch is found, th e search has succeeded. If not, g et the pointer to
the n ext entry down the list.
4— Go back to 2.
A n example is shown in Fig. 9-24.
 Fig. 9-24: Linked List: A Search

Element Insertion
The insertion is essentially a search followed by an insertion
once a “ N IL ” has been found. A block of storage for the new entry
is allocated p a s t the EO T m arker by looking for an occupancy
m arker set at “ available”. The program is called “ N E W ” and
resides a t addresses 0651 to 06BD. A n example is shown in Fig.
9-25.
BEFORE

AFTER
Element Deletion
The element is deleted by setting its occupancy m arker to “ available”
and adjusting the pointer text from either the directory or the
previous element. The program is called “ DELETE” and resides
at addresses 06BE to 06F7. An example o f a deletion is shown in Fig.
9-26.

A
B
C
D

DELETE

(AFTER)

A
B
C
D —

DOC POINTER "D O C "

NIL
r ------------------------- -
. DAF •
L - - - - - - j

NOTE DAF IS NOT ERASED. BUT "INVISIBLE”

Fig. 9-26: Example of Deletion (Linked List)

LINE • ioc C08E LINE

0#©2 0000 INDEX! »I10

OB03 0000 INILOC * 411
0*04 0000 POINTR = 113
0005 0000 OBJECT « 415
0004 0000 TEN! * 417
0002 0000 REFI4S * 419
0008 0000 OLI * 418
0009 0000 TA84SC * 41!
0010 0000 ENTLEN * 4IF
OOff 0000 j
0012 0000 • * 4400
0013 0400 ;
0014 0400 49 01 SEARCH LDA 11 UNITIALIZE FLAGS
0013 0402 85 10 ST4 INDEX!
0014 0404 20 F8 06 JSR PRETA! ;6ET REF. POINTER FOR START
0017 0407 • 1 11 LDA (INDLOC),Y {PUT IT IN POINTR
0018 0409 85 13 STA POINTR
0019 0401 C8 INY
0020 040C 11 It L84 (INDL0C),Y
0021 040E 85 14 STA POINTR*1
0022 0410 40 00 ENTRY LBY 10 ,*SEE IF ENTRY IS EOT VALUE
0023 0412 81 13 LSA (POINTR)VY
0024 0414 C9 7C CNP I47C
0025 0414 F0 34 BED NOTFN!
0024 0418 11 15 LDA (OBJECT),Y ICONPARE FIRST LETTERS
0027 0414 81 13 CNP (POINTR),Y
0028 041C 90 30 ICC NOTFND
0029 04 IE 80 12 BNE N06008
0030 0420 C8 INY {COMPARE SECOND LETTERS
0031 0421 81 15 LB4 (OBJECT),Y
0032 0423 81 13 CNP (POINTR),Y
0033 0425 90 27 8CC NOTFND
0034 0427 80 09 BNE N0600D
0033 0429 C8 INY {COHPARE THIRI LETTERS
0034 042A 81 15 L84 (OBJECT),!
0037 042C 81 13 CNP (POINTR),Y
0038 042E 90 IE BCC NOTFND
0039 0430 FO IE 8E0 FOUND
0040 0432 45 14 N0600D LDA POINTR+I {SAVE POINTR rOR POSSIBLE REF,
0041 0434 85 1C STA OLD+1
0042 0434 45 13 LDA POINTR
0043 0438 85 IB STA OLD
0044 0434 44 IF LOT ENTLEN ,*CET POINTER FROM ENTRY AN!
0045 043C B1 13 LDA (POINTR),Y {..LOAD IT INTO POINTR
0044 043E 44 TAX
0047 043F C8 INY
0048 0440 81 13 LDA (POINTR),Y
0049 0442 85 14 STA P01NTR+1
0050 0444 84 TXA
0051 0445 85 13 STA POINTR
0052 8447 49 00 LDA NO
0053 0449 85 10 STA INDEX! {RESET FLA6
0054 0448 4C 10 04 JNP ENTRY
0055 044E 49 FF NOTFND LDA N4FF
0054 0450 40 FOUND RTS {Z SET IF FOUND
0057 0451 J
0058 0451 »
0059 0451 r
0040 0451 20 00 04 NEU JSR SEARCH {SEE IF OBJ. IS ALREADY THERE
0041 0454 FO 47 BEO OUTE
0042 0454 45 18 LDA TABASE {LOOK FOR UNOCCUPIED ENTRY
0043 0458 18 CLC {..BLOCK
0044 0459 49 01 ADC 11 {JUMP PAST EOT VALUE
0045 0458 85 17 STA TENP
0044 0458 49 00 LDA NO
0047 045F 45 IE ADC TABASE+1
0048 0441 85 18 STA TEHP+J
0049 0443 44 IF LDT ENTLEN {SET Y TO POINT TO OCCUPANCY
0070 0445 C8 INY {..HARKER OF AN ENTRY
0071 0444 C8 INY
0072 0447 49 01 LOOP LD4 11 ;TEST FOR OCCUPANCY HARKER
0073 0449 81 17 CUP <TEHP),Y
0074 0448 DO 14 BNE INSERT
0075 044D 45 17 LD4 TEHP JIF IS USED, NOPE TENP TO NEXT
0074 044F 18 CLC {..ENTRY BLOCK
0077 0470 45 IF ROC ENTLEN
0078 0472 90 02 BCC HORE
0079 0474 E4 18 INC TEHP+1
0080 0474 49 03 MORE 4DC 13
0081 0478 85 17 ST4 TEHP
0082 0474 49 00 LIA NO
0083 047C 45 18 48C TEHP+1
0084 04/E 85 18 8T4 TENP+1
0085 0480 4C 47 04 JHP LOOP
0084 0483 88 IMSEKT DEY {SET Y BACK TO P0INTIN8 TO
0087 0484 88 DEY {..TO P OF DATA
0088 0485 88 LOPE DEY {HOVE OBJECT INTO SPACE
0089 0484 81 15 LD4 (OBJECT),Y
0090 0488 91 17 8T4 (TEHP),Y
0091 0484 CO 00 CPY •0
0092 048C 80 F7 8NE LOPE
0093 046C 44 IF LDY ENTLEN {PUT THE VALUE OF POINTR, THE
0094 0490 45 13 LD4 POINTR ; en try a f t e r o b j e c t , in to
0095 0492 91 17 ST4 (TEHP),Y {POINTER AREA OF OBJECT
0094 0494 C8 INY
0097 0495 45 14 LD4 POINTR*1
0098 0497 91 17 ST4 <TEHP),Y
0099 0499 C8 INY
0100 0494 49 01 LDA 11 ,*SET OCCUPANCY HARKER
0101 049C 91 17 ST4 ( TEHP) , V
01Q2 049E 45 10 LD4 INDEXD {TEST TO SEE IF REF. TABLE
0103 0440 DO 08 ONE SETINX NEEDS READJUSTING
0104 0442 88 DEY
0105 0443 45 18 LD4 TEHP+1 {NO, CHANGE PREVIOUS ENTRY'S
0104 0445 91 18 ST4 (OLD),Y POINTER
0107 0447 88 DEY
0108 0448 45 17 LD4 TEHP
0109 0444 91 18 8TA (OLD), Y
0110 044C 4C 88 04 JHP DONE
0111 044F 20 FB 04 8ETINX J8R PRETAB ; GET ADDRESS I F UNATS TO IE CHANGED
0112 0482 45 17 LD4 TEHP {LOAD ADDR. OF OBJ. THERE
0113 0484 91 11 8T4 (INDLOC),Y
0114 0484 C8 INY
0115 0487 45 18 LD4 TEHP+1
0114 0489 91 11 STA ( INDLOO, Y
0117 0488 49 FF DONE L84 •OFF
one 0480 40 OUTE RTS ;l CLEAR IF BONE
0119 048E t
0120 048E J
0121 048E f«
0122 04IE 20 00 04 DELETE JSR SEARCH ,*6ET ADDR OF OBJ.
0123 04C1 80 34 8NE OUTS
0124 04C3 44 IF LDT ENTLEN ; STORE POINTER AT END
0125 04C5 81 13 LD4 (POINTR),Y {..O F OBJECT
0124 04C7 05 17 8T4 TEHP
0127 04C9 C8 INY
0128 04C4 81 13 LIA (POINTR),r
0129 04CC •5 18 STA TEHP+1
0130 04CE C8 INY
0131 04CF 49 00 LD4 10 {CLEAR OCCUPANCY HANKER
0132 0411 91 13 STA (POINTR),Y
0133 0413 45 10 L84 INDEXD {SEE IF REF. TABLE NEEDS
0134 0485 FO 04 DEI PREINX {..READJUSTING
0135 0487 20 F I 04 JSR PRETA8
0134 0484 4C E4 04 JHP HOVEIT
0137 0488 45 18 PREINX LD4 OLD {SET FOR CHANIIIG PREVIOUS
0130 048F 18 CLC {..ENTRY
0129 04E0 09 IF Alt ENTLEN
0140 00E2 •9 11 STA INILOC
0141 OOEO 09 00 LM 10
0142 OOEO 09 1C ABC 0LI*1
0141 OOEI IS 12 STA INILOC*1
0144 OOEO OS 17 HOVEIT L M TEMP ;(HANtE UlAf REEDS CHANGING
0149 OOEC 00 00 LIT 10
0140 OOEE 91 11 STA (INILOC),T
0147 OOFO Cl INY
0141 00F1 09 11 LM TENP*1
OlOt OOFJ 91 11 STA (INILOC),Y
0190 00F9 09 00 LM 00
0191 00F7 00 0UT8 RTS {Z SET IF NONE
Of92 OOFS
0192 OOFI
0194 OOFO
0199 OOFI 00 00 PIETOI LIT 00
0190 OOFO 11 19 L M (OBJECT),Y
0197 OOFC N 8EC {REMOVE ASCII LEAKS FRON
0199 OOFI 19 41 O K 0141 {..FIRST LETTER IN OIJECT
0199 OOFF M AIL A {MULTIPLY IY 2
0100 0700 11 CLC
0101 0711 09 19 A K REFM8 {INDEX INTO REF. MILE
0162 0703 85 11 STA INILOC
0163 0705 A? 00 LlA 10
0164 0707 65 1A ADC R'CFBASH
0165 070? 85 12 STA INILOC*1
0166 0701 60 RTS
016 7 070C .END

ERRORS = 0000 '0000

SYMBOL TABLE

SYMBOL VALUE

DELETE 06IE DONE 06IB ENTLEN 001F ENTRY 0610

FOUND 0650 INDEXD 0010 INDLOC 0011 INSERT 0683
LOOP 0667 LOPE 0685 MORE 0676 HOVEIT 06EA
NEU 0651 N0600D 0632 NOTFND 064E OIJECT 0015
OLD 0011 OUTE 06ID OUTS 06F7 POINTR 0013
PREINX 06DD PRETAB 06F8 REFBAS 0019 SEARCH 0600
SETINX 06AF TOMSE 001D TEMP 0017
END OF ASSEHILY

Fig. 9-27: Linked List Program (cont.)

 BINARY TREE

We will now develop typical tree management routines. Our simple

structure is shown in Fig. 9-28. It is a binary tree, and the nodes are
names of persons. Names will be internally sorted by “ tags” which will
be the first three letters of every name. The memory representation of
this tree structure is shown in Fig. 9-29. The contents of the nodes are
shown, as well as the two links. The first link, to the left of the name, is
the “ left sibling” and thenext link, to its right, is the “ right sibling.”
For example, the entry for Jones contains two links: “ 2” and “ 4” . This
indicates that its left sibling is entry number 2 (Anderson), and its right
sibling is entry number 4 (Smith). A “ 0” in the link field indicates no
sibling. A left sibling’s tag comes alphabetically before its parent. A
right sibling’s tag comes after.

ANDERSON SMITH

ALBERT BROWN TIMOTHY

MURRAY

0 ) ( 3) 00 / 0 )
ZORK

( 8)
Fig. 9-28: Binary Tree

The tw o m ain routines for tree m anagem ent are the tree builder
and the tree traverser. The elem ent to be inserted will be placed in
a buffer. The tree builder will insert the content of the buffer into
the tree a t the appropriate node. The tree traverser is said to
traverse the tree recursively, and p rin ts the contents of each of its
nodes in alphanum eric order. The flow chart for th e tree builder is
shown in Fig. 9-30, and the flowchart for the tree traverser is shown in
Fig. 9-31.
LEFT RIGHT

V
ORDER
OF INSERTION
A B
 A

Fig. 9-30: The Tree Builder Flowchart (cont.)

Since the routine for the traversal is recursive, it does not lend itself well
to flowchart representation. Another description of the routine in a high-
level format is therefore shown in Fig. 9-32. An actual node of the tree
is shown in Fig. 9-33. It contains data of length ENTLEN, then two 16-
bit pointers (the right pointer and the left pointer). In order to avoid a
possible confusion, note that the representation of Fig. 9-29 has been
simplified and that the right pointer appears to the left of the left
pointer in the memory. The memory allocation used by this program is
shown in Fig. 9-34, and the actual program appears in Fig. 9-37.
The IN SE R T routine resides a t addresses 0200 to 0282. The ta g
of the object to be inserted is compared to that of the entry. If greater,
one moves to the right. If smaller, to the left, down by one position.
The process is then repeated until either an empty link is found or a
suitable “ bracket” is found for the new node (i.e., one node is greater
and the next one smaller, or vice versa). The new node is then inserted
by merely setting the appropriate links.

PROGRAM TREETRAVERSER;
BEGIN
CALL SEARCH (STARTPOINTER);
END.

ROUTINE SEARCH (WORKPOINTER);

BEGIN
IF WORKPOINTER = 0THEN RETURN;
SEARCH [LEFTPTR (WORKPOINTER)];
PRINT TREE (WORKPOINTER);
SEARCH [RIGHTPTR (WORKPTR)];
RETURN;
END.
 RIGHT PTR LEFT PTR
DATA: 'ENTLEN' BYTES L . H L . H

(n) (n + ENTLEN + 4)

Fig. 9-33: Data Units, or "Nodes” of Tree

PAGE0 HIGH MEMORY

$10 $200
FREPTR (LO) PROGRAM

FREPTR (HI)

WRKPTR (LO)
\
WRKPTR (HI) /

ENTLEN

STRTPT (LO)
\ $600
STRTPT (HI) /
$17

---------► TREE
BUFFER

$37 TOP OF TREE

 The TR A V E R SE routine resides a t addresses 0285 to 02D6. The
utility routines OUT, AD D and CLRPTR reside a t addresses 0207
to 02FE (see Fig. 9-37).
A n example of a tree insertion is shown in Fig. 9-35, and an ex­
am ple of a tree traversal in Fig. 9-36.

Fig. 9-35: Inserting an Element in the Tree

 ALBERT

ALBERT ANDERSON BROWN JONES MURRAY,

SMITH
TIMOTHY

Fig. 9-36: Listing the Tree

N ote on Trees
B inary trees m ay be constructed and traversed in m any ways.
For example, another representation for our tree could be.

Fig. 9-38 : Tree in Preorder

I t would then have to be traversed in “ preorder” :

1— list the root
2— traverse left subtree
3— traverse rig h t subtree
M any other techniques and conventions exist.
 0002 0000 ;tree management prog r a m .
0003 0000 ;2 ROUTINES! ONE, WHEN CALLED. PLACES
0004 0000 ;the contents of .the buffer into the
0005 0000 5TREE; AND THE SECOND TRAVERSES
0006 0000 {THE TREE RECURSIVELY, PRINTING ITS
0007 0000 INODE CONTENTS IN ALPHANUMERIC ORDER.
0008 0000 •NOTEs 'ENTLEN' MUST BE INITIALIZED
0009 0000 ,*AND 'FREPTR' MUST BE SET EQUAL TO
OOtO 0000 f'STRTPTR' BEFORE EITHER ROUTINE IS USED.
0011 0000
0012 0000 • = $10
0013 ooto FREPTR *=**2 {FREE SPACE POINTER: POINTS TO
0014 0012 {NEXT FREE LOCATION IN MEMORY.
0015 0012 MRKPTR ****2 {WORKING POINTER, POINTS TO CURRENT NODE.
0016 0014 ENTLEN • {TREE ENTRY LENGTH. IN BYTES.
0017 0015 STRTPT .WORD 9600
0018 0017 BUFFER ****20 {I/O BUFFER.
0019 0028
0020 002B * = 1200
0021 0200
0022 0200 {ROUTINE TO BUILD TREI
0023 0200 {OR NODE, TO TREE. MUi
0024 0200 {WITH DATA UNIT TO BE
0025 0200
0026 0200 A5 15 INSERT LDA STRTPT {WORKPOINTER <= FREEPOINTER.
0027 0202 85 12 STA URKPTR
0028 0204 A5 16 LDA STRTPT*1
0029 0206 85 13 STA WRKPTR+1
0030 0208 A5 10 LDA FREPTR {IF FREEPOINTER <>
0031 020A C5 15 CMP STRTPT {STARTING LOCATION POINTER,
0032 020C DO OD BNE INLOOP I60T0 INSERTION LOOP.
0033 020E AS 11 LDA FREPTR*!
0034 0210 C5 16 CMP STRTPT-*-1
0035 0212 DO 07 BNE INLOOP
0036 0214 20 D7 02 JSR ADD {LOAD BUFFER INTO CURRENT POSITION.
0037 0217 20 E4 02 JSR CLRPTR {SET POINTERS OF CURRENT NODE TO 0.
0038 021A 60 RTS {DONE ADDING 1ST NODE.
0039 02 IB AO 00 INLOOP LDY •0 {COMPARE BUFFER TA6 TO TAG OF CURRENT
0040 021D B9 17 00 CHPLP LDA BUFFER,Y {LOCATION...
0041 0220 D1 12 CMP (WRKPTR>,Y
0042 0222 90 33 BCC LESSTN ,
’BUFR TA6 LOWER: ADD BUFFER TO
0043 0224 {LEFT 5IDE OF TREE.
0044 0224 FO 02 BEG NXT {TAGS EQUAL, TRY NEXT CHR. IN TAGS.
0045 0226 BO 05 DCS GRTNEO ,
‘BUFR TAG GREATER, ADD BUFR TO
0046 0228 {RIGHT SII
0047 0228 C8 NXT INY
0048 0229 C9 04 CMP 04 {3 CHRS. COMPARED*
0049 022B DO FO BNE CMPLP {NO, CHECK NEXT CHR.
0050 022D A4 14 GRTNEO LDY ENTLEN {DOES
0051 022F B1 12 LDA (WRKPTR),Y {RIGHT POINTER OF CURRENT NODE = 0 *
0052 0231 DO 15 BNE NXRNOD {IF NOT, MOVE DOWN/RIGHT IN TREE.
0053 0233 C8 INY
0054 0234 Bt 12 LDA (WRKPTR>,Y
0055 0236 DO 10 BNE NXRNOD
0056 0238 AS 11 LDA FREPTRH {SET RIGHT POINTER OF CURRENT
0057 023A 91 12 STA (WRKPTR),Y {NODE = FREEPOINTER.
0058 023C 88 DEY
0059 023D AS 10 LDA FREPTR
0060 023F 91 12 STA (WRKPTR),Y
0061 0241 20 D7 02 JSR ADD {ADP BUFFER TO TREE.
0062 0244 20 E4 02 JSR CLRPTR {CLEAR POINTERS OF NEU NODE.
0063 0247 60 RTS {DONE, NEU RIGHT NODE ADDED.
0064 0248 A4 14 NXRNOD LDY ENTLEN {SET WORKING POINTER
0065 024A Bt 12 LDA 'WRKPTR *,Y{
0066 024C AA TAX
0067 024D C8 INY
0068 024E B1 12 LDA (WRKPTR),Y
0069 0250 85 13 STA WRKPTR*1
0070 0252 86 12 STX URKPTR
0071 0254 4C IB 02 JNP INLOOP {TRY NEU CURRENT NODE.
0072 0257 64 14 LESSTN LOT ENTLEN {DOES LEFT POINTER OF
0073 0259 C8 IKY {CURRENT NODE * 0 ?
0074 0238 C8 INY
0073 0238 81 12 106 (URKPTR),Y
0070 0238 80 13 ONE NXLMOB JIF SO, HOVE IONN/LEFT IN TREE.
0077 023F C8 INY
0071 0260 81 12 116 (URKPTR),Y
0070 0262 80 10 M E NXLNOI
0080 0264 63 11 186 FREPTN*1 {SET LEFT POINTER OF CURRENT NODE TO
0081 0244 91 12 8T6 (URKPTR),Y {POINT TO NEU NODE.
0082 0248 88 8EY
0083 0269 65 10 116 FIEPTR
0084 0268 91 12 SI6 (URKPTR),Y
0085 0248 20 87 02 JSR 680 {ADD NEU NODE CONTENTS.
0080 0270 20 E4 02 JSR CLRPTR {CLEAR POINTERS Of NEU NO»E.
0087 0273 60 RTS {DONE, NEU LEFT NODE ADDED.
0088 0274 64 14 NXLNdl LIT ENTLEN {SET U0RKIN6 POINTER *
0089 0276 C8 INY {LEFT POINTER OF CURRENT NODE.
0090 0277 C8 INY
0091 0278 81 12 L86 (URKPTR),V
0092 0276 66 T6X
0093 0278 C8 INY
0094 027C 81 12 L M (URKPTR),Y
0095 027E 85 13 ST6 URKPTR*1
0090 0280 86 12 STX URKPTR
0097 0282 4C 18 02 JNP INIOOP {TRY NEU CURRENT NODE.
0098 0285 9
0099 0285 ;TREE TR6VERSER t LISTS NODES OF TREE
0100 0285 ;IN 6LPH6NUNERIC6L ORDER.
0101 0285 ;OUTPUT ROUTINE TO XFER BUFFER TO OUTPUT
0102 0285 {DEVICE IS NEEDED.
0103 0285 *
0104 0285 AS IS TRVRSE LD6 8TRTPT {WORKING POINTER <= START POINTER.
0105 0287 85 12 ST6 URKPTR
0106 0289 65 16 LD6 STRTPU1
0107 028B 85 13 ST6 URKPTR*1
0108 0288 65 13 SE6RCH L06 URKPTR*1
0109 028F 66 12 L8X URKPTR {IF U0RKIN6 POINTER <> 0,
0110 0291 00 07 DNE OX {CONTINUE;
0111 0293 64 13 LOT URKPTR*1
0112 0295 DO 03 DNE OX
0113 0297 4C C6 02 JNP RETN {ELSE, RETURN.
0114 0296 48 OK PN6 {PUSH U0RKIN6 POINTER
0115 0298 86 TX6 {ONTO STACK.
0116 029C 48 PH6
0117 0290 64 14 LOT ENTLEN {SET U0RK1N6 POINTER *
0118 029F C8 INY {LEFT POINTER OF CURRENT NODE.
0119 02AO C8 INY
0120 0261 81 12 LD6 (URKPTR),Y
0121 0263 AA TAX
0122 0264 C8 INY
0123 0265 B1 12 LI6 (URKPTR)fT
0124 0267 85 13 STA URKPTR*1
0125 0269 86 12 STX URKPTR
0126 0268 20 80 02 JSR SEARCH {SEARCH NEU NODE, RECURSIVELY.
0127 026E 68 PL6 {POP OLD CURRENT NODE INTO U0IKIN6 POINTER
0128 02AF 85 12 STA URKPTR
0129 0281 68 PLA
0130 0282 85 13 STA URKPTR*1
0131 0284 20 C7 02 JSR OUT {OUTPUT CURRENT NODE CONTENTS.
0132 0287 64 14 LDY ENTLEN {SET U0RKIN6 POINTER «
0133 0289 81 12 LDA (URKPTR),Y {CURRENT NODE'S RI6HT POINTER.
0134 0288 66 TAX
0135 02BC C8 INY
0136 0280 B1 12 LDA (URKPTR),Y
0t37 02BF 85 13 STA URKPTR+1
0138 02C1 86 12 STX URKPTR
0139 02G3 20 80 02 JSR SEARCN {SEARCH NEU NODE.
>0140 02C6 60 RETN RTS {DONE, RETURN.

Fig. 9-37: Tree Search Program s (cont.)

0t4t 02C7 »
0142 02C7 ;BUFFER OUTPUT ROUTINE.
0143 02C7 1
0144 02C7 AO 00 OUT LDY 10
0145 02C9 B1 12 XFR LDA (URKPTRM {6ET CHR. FROM CURRENT NODE.
0144 02CB 99 17 00 STA BUFFERVY {PUT IN BUFFER.
0147 02CE C8 INY {REPEAT UNTIL...
0148 02CF C4 14 CPY ENTLEN {ALL CHARACTERS XFERRED.
0149 02D1 DO F4 BNE XFR
0150 02D3 EA NOP {INSERT CALL TO SUBROUTINE
0151 0264 EA NOP {WHICH OUTPUTS BUFFER HERE.
0152 02D5 EA NOP
0(53 02D4 40 RTS {DONE.
0(54 02D7 *
0155 02D7 .'ROUTINE WHICH PLACES BUFFER
0154 02D7 {CONTENTS IN NEU NODE.
0157 02D7 J
0158 0267 AO 00 ADD LDY 10
0159 0269 B9 17 00 NOV LDA BUFFER,Y {GET CHR. FROM BUFFER.
0140 02DC 91 10 STA (FREPTR),Y {STORE IN NEW NODE.
0141 02DE C8 INY {REPEAT UNTIL...
0142 02DF C4 14 CPY ENTLEN {ALL CHR6 XFERRED.
0143 02E1 DO F4 BNE NOV
0144 02E3 40 RTS {DONE.
0145 02E4 ?
0144 02E4 {ROUTINE TO CLEAR P0INTER8 OF NEU NODE,
0147 02E4 {AND UPDATE FREE SPACE POINTER.
0148 02E4 »
0149 02E4 A4 14 CLRPTR LDY ENTLEN {SET UP INDEX TO POINT
0170 02E4 {TO TOP OF POINTER LOCATIONS.
0171 02E4 A9 00 LDA RO
0172 02E8 A2 04 LDX 14 {LOOP 4X TO CLEAR POINTERS
0173 02EA 91 10 CLRLP STA (FREPTR),Y {CLEAR POINTER LOCATION.
0174 02EC C8 INY {POINT TO NEXT POINTER LOCATION,
0175 02ED CA DEX
0174 02EE DO FA BNE CLRLP {LOOP IF NOT DONE.
0177 02F0 AS 14 LDA ENTLEN {6ET ENTRY LENGTH,
0176 02F2 18 CLC {AND ADD 4 FOX POINTER SPACE.
0179 02F3 49 04 ADC 14
0(80 02F5 45 10 ADC FREPTR {ADD TO FREE SPACE POINTER TO
0181 02F7 90 02 BCC CC {UPDATE IT.
0182 02F9 E4 11 INC FREPTR*1 {TAKE CARE OF OVERFLOUS.
0183 02FB 85 10 CC STA FREPTR {RESTORE UPDATED FREE SPACE PTR,
0184 02FD 40 RTS {DONE.
0185 02FE .END

ERRORS * 0000 <0000>

END OF ASSEMBLY

Fig. 9-37: Tree Search Programs (cont.)

A H A S H IN G A L G O R ITH M
A common problem when creating data structures is how to place
identifiers w ithin a lim ited am ount of mem ory space in a sys­
tem atic way so th a t they can be retrieved easily. U nfortunately,
unless identifiers are d istinct sequential num bers (w ithout gaps),
they do not lend themselves to placem ent in the memory with­
out gaps. In particular, if names were to be placed in the memory so
that they could be most easily retrieved (i.e., if they were placed
alphabetically), this would require a huge amount of memory;
a single memory block would have to be reserved for every possible
name. This is clearly not acceptable. To solve this problem, a hashing
algorithm can be used to allocate a unique (or almost unique) number
to every name which has to be entered into memory. The mathematical
function used to perform the hashing should be simple so that the algo­
rithm can be fast, yet sophisticated enough to randomize the distri­
bution of the possible names over the available memory space. The re­
sulting number can then be used as an index to the actual location, and
fast retrieval will be possible. It is for this reason that hashing is com­
monly used for directives of alphabetic names.
Since no algorithm can guarantee that two names will not hash
into the same mem ory location (a “ collision” ) a technique m u st be
devised to resolve the problem of collisions. A good hashing algor­
ithm will spread nam es evenly over the available mem ory space,
and will allow efficient retrieval of their values once they have been
stored in a table. The hashing algorithm used here is a very simple
one, where we perform th e exclusive OR of all the b y tes of the key.
A ro tatio n is perform ed after every addition to improve the ran­
domization.
The technique used to resolve collisions is a simple sequential
one. I t is technically called a “ sequential open addressing tech­
nique; ” the n ext sequentially available block in the table is
allocated to the entry. This can be com pared to a pocket address
book. L et us assum e th a t a new entry m u st be entered for SM ITH .
However, the “ S ” page is full in our sm all address book. W e will
use the next sequential page (“ T ” here). Note th a t there will not
necessarily be another collision with a new entry starting with a “ T” ;
the entry for “ S” may be removed (“ whited out,” in our comparison)
before a “ T” ever needs to be entered.
Also note that there could be a chain of collisions. If the chain is
long, and the table is not full, the hashing algorithm is a bad de­
sign.
 Since it is convenient to use a power of two for th e d ata form at,
the length of the d a ta is eight characters; six are allocated to the
key, and two to the data. This is a typical situation when creating,
for example, the sym bol table for an assem bler. U p to six hexa­
decim al sym bols are allocated to the symbol, and tw o are allocated
to the address i t represents (2 bytes).
W hen retrieving elem ents from the hashing table, the tim e re­
quired by the search does n o t depend on the table size, b u t on the
degree to which the table has been filled. Typically, keeping the
table less than 80%full will insure a high access time (one or two
tries). It is the responsibility of the calling routine to keep track of the
degree of fullness of the table and prevent overflow.
The increase of the access time versus table fullness is shown in
Fig. 9-39. The main routines used by the program are the initialize
subroutine (INIT), shown in Fig. 9-40; the store routine, shown in
Fig. 9-41; the retrieve routine, shown in Fig. 9-42; and the hash routine,
shown in Fig. 9-43. The memory allocation is shown in Fig. 9-44,
and the program is given in Fig. 9-45. The program is intended to demon­
strate all the main algorithms used in an actual hashing
mechanism. If these programs are to be imbedded in an actual imple­
mentation, it is strongly suggested that the usual housekeeping
Fig. 9-40 : Initialize Subroutine

Rg. 9-41: “Store” Routine

functions required to prevent unexpected situations be added. In
particular, one should guard against the possibility of a full table
or of an incorrect key since these might cause infinite loops to oc­
cur in the program. The reader is strongly encouraged to study
this program. Not only will it demystify a hashing algorithm, but
it will also solve an important practical problem encountered when
designing an assembler, or any other structure where tables of
names with their equivalent values must be kept in an efficient
way.

$200
U K I LOC COSE LINE

0402 0000 {PR08R6H T8 STORE ASSEMBLER 8VHOOLS li *

0003 0000 ;T08LEv OCCESSEI 8T H6SNIK8. THE 8TNS0LS
0004 0000 {ARE 6 CNt8f 8010 2. THE N A X I H W M O W E R OF
0009 0000 {8-BYTE WRITS TO BE 8T0REI 1H T K T A H E
0000 0000 {SHOULD IE IR 'ERTRUR', 8E6IRRIR8 0D8RE88 OF
0007 0000 {TABLE SROULO BE IR 'TOOLE'. ROTE TROT
0008 0000 {TABLE RUST IE IRITIOLIZEI RITR ROUT I K
0000 oooo ; 'IHIT' PRIOR TO USE.
0010 0000 ;IT IS THE RESPOR8IOILITT OF T K COLLINS
0011 0000 ;PR06ROR RO TO E1CEEI T K TOOLE S H E .
0012 0000
0013 0000 • * 110
{START1NS 008RE8S OF TOOLE.
0014 0010 00 06 TOILE .UORI 0600
IRIX •*•♦1 {RUROER OF SOTO W I T TO BE 6CCESSED.
0015 0012
PTR •*•♦2 {POINTER TO OOTO UNIT IN TOOLE.
0016 0013
ERTRUR •*•♦1 {RUROER OF ENTRIES IN TOILE (256 NOX)
0017 0015
SUFFER •*•♦8 {INPUT/ OUTPUT SUFFER.
0018 0016
0019 001E 9
0020 001E • * 0200
0021 0200 ;
0022 0200 {ROUTINE 'IRIT' I II
0023 0200 {TO ZEROES.
0024 0200 9
0025 0200 ‘’65 15 IRIT LB6 ENTNUN
0026 0202 85 13 ST6 PTR {STORE 8 8F ENTRIES IN POINTER
0204 20 72 02 JSR SH6BB {HULTIPLT PTR«8, 000 TOOLE POINTER.
0027
0207 62 00 LBX •0 {CLEON X FOR INI1RECT 00B8ES8IN8.
0028
0029 0209 69 00 CLRLP LB6 80 {SET CLE0RIN8 CORSTORT
0030 0201 64 13 LBY PTR
IRE BECR {IF PTR <> 0 # DSR'T DECREIERT HI IYTE.
0031 0201 00 02
020F C6 14 DEC PTR*1 {I EC R E K H T HI OTTE OF POINTER.
0032
0033 0211 C6 13 DECR DEC PTR {OCCRENCNT LO BYTE.
0034 0213 81 13 ST6 (PTRfX) {CLEOR LOCOTIOR.
0035 0215 65 13 LB6 PTR {CHECK IF POINTER • TOILE POINTERv
0217 C5 10 CRP T6BLE {IF UNEOUOlt CLEOR NEXT LOCOTIOR.
0036
0037 0219 00 EE ONE CLRLP
0038 0218 65 14 LB6 PTR*1
0039 021D C5 11 CRP TABLE+1
0040 021F BO E8 IRE CLRLP
0041 0221 60 RTS
0042 0222
0043 0222 {ROUTINE 'STORE'S PLACES BUFFER CONTENTS IN
0044 0222 {TABLE, U8IR6 1ST 6 CHRS. OF BUFFER 6S 6
0045 0222 {'KEY' TO BETERNINE N 6 8 K B 6BBRESS IR
0046 0222 {TOILE.
0047 0222
0048 0222 62 00 STORE LBX 80 { C L E M X FOR INBEXEO 6BBREI8IN0.
0049 0224 20 90 02 JSR N68N {BET HASHER INBEX..
0050 0227 20 62 02 CNPR1 JSR LINIT {RAKE SURE I N K X 18 UITNIR B0INB8.
0051 0226 61 13 LB6 <PTR,X> {CHECK BATA UNIT...
0052 022C FO 05 BEO ERPTY {JUNP IF ENPTY.
0053 022E E6 12 INC IRIX {TRY NEXT UNIT.
0054 0230 4C 27 02 JNP CNPR1 {CHECK FOR K X T UNIT INDEX VALID.
0055 0233 60 07 ERPTY LBY 87 {LOOP OX TO L06I BATA UNIT.
0056 0235 89 16 00 FILL LB6 BUFFER,Y {SET CHR FRON BUFFER,
0057 0238 91 13 8T6 (PTR),Y {PLACE IT IN BUFFER.
0058 0236 88 BEY
0059 0231 10 F8 BPL FILL {XFER K X T CUR.
0060 023D 60 RTS {ADDITION DINE.
0061 023E
0062 023E {ROUTINE 'FINB' I
0063 023E {FINIS ENTRY UH08E KEY 18 IN BUFFER.
0064 023E {ENTRY . UNEN FOURS, IS COPIED INTO
0865 023E {BUFFERv 6L0N8 WITH 2 BYTES OF M T 6 .
0066 023E
0067 023E 62 00 FINB LBX 80 {CLEAR X FOR INIIRECT ABDIE88INS.
0068 0240 20 90 02 JSR H68N {SET NASH PRODUCT.
0069 0243 20 62 02 CNPR2 JSR LINIT {HAKE SURE RESULT 18 IIITNIN LIMITS
 0070 0246 AO 05 LDY NS
0071 0248 B1 13 ;IOOP AX TO COMPARE BUFFER TO DATA ITEM.
CHKLP LDA (PTR),Y ;GET CMR FRON TABLE.
0072 024A D9 16 00 CMP BUFFER,Y ;IS IT » BUFFER CHR?
0073 024D DO OE BNE BAD ,
‘IF MOT, TRY NEXT DATA UNIT.
0074 024F 88 DEY
0075 0250 10 F6 BPL CHKLP ;CHECK NEXT CHRS.
0076 0252 AO 07 NATCH LDY N7 tLOOP OX TO XFER CHRS TO BUFFER.
0077 0254 B1 13 XFER LDA (PTR),Y ;OET CHR. FRON TABLE.
0078 0 2 5 6 99 16 00 STA BUFFER.Y ISTORE IN BUFFER.
0079 0259 88 DEY
0080 025A 10 F8 BPL XFER ;loop to xfer c r r s .
0061 025C 60 RTS .•DONE sDATA UNIT FOUND, IN BUFFER.
0062 025D E6 12 BAD INC INDX ,*NOT FOUND, TRY NEXT DATA UNIT.
0083 025F 4C 43 02 JMP CMPR2 .•VALIDATE NEU DATA UNIT INDEX.
0084 0262
0085 0262 .
’ROUTINE TO MAKE SURE
0086 0262 ;BOUNDS SET BY ENTNUN,
0087 0262 tBY 8, AND ADD IT TO 1 POINTER. THE
0088 0262 ,
’RESULT IS PLACED IN 'PTR
' AS DATA UNIT ADDRESS.
0089 0262
0090 0262 A5 12 LIMIT LDA INDX ;6ET INDEX.
0091 0264 C5 15 TEST CMP ENTNUN ;INDEX > NUMBER O F DATA ITEMS?
0092 0266 90 06 BCC OK ,
’JUHP IF NOT.
0093 0268 38 SEC ;yes -
0094 0269 ES 15 SBC ENTNUN .•SUBTRACT I O F ITEMS UNTIL
0095 026B 4C 64 02 JMP TEST ;INDEX UITHIN BOUNDS.
0096 026E 85 13 OK STA PTR ;STORE GOOD INDEX IN POINTER.
0097 0270 85 12 STA INDX •SAVE UPDATED INDEX.
0098 0272 A9 00 SHADD LDA 10 .•CLEAR U P PER POINTER FOR SHIFT.
0099 0274 85 14 STA PTRM
0100 0276 06 13 ASL PTR ,
’SHIFT PTR 3X LEFT - MULTIPLY BY 8.
0101 0278 26 14 ROL PTR*t
0102 027A 06 13 ASL PTR
0103 027C 26 14 ROL PTR*1
0104 027E 06 13 ASL PTR
0105 0280 26 14 ROL PTRM
0106 0282 18 CLC
0107 0283 AS 10 LDA TABLE ,*ADD POINTER AND TABLE START
0108 0285 65 13 ADC PTR ADDRESS AND PLACE RESULT IN POINTER.
0109 0287 85 13 STA PTR
0110 0289 A5 11 LDA TABLE*1
0111 028B 65 14 ADC PTR*1
0112 028D 85 14 STA PTRM
0113 028F 60 RTS
0114 0290
0115 0290 ROUTINE TO GENERATE DATA UNIT INDEX IN TABLE
0116 0290 BY HASHING 'KEY', OR CHRS OF LABEL.
0117 0290
0118 0290 A9 00 HASH LDA 80 ,
’CLEAR LOCATION FOR INDEX.
0119 0292 18 CLC .•PREPARE TO ADD.
0120 0293 AO 05 LDY IS ,
‘LOOP 6X FOR EXCLUSIVE ORS.
0121 0295 59 16 00 EXOR EOR BUFFER.Y ,
’EXCLUSIVE-OR ACCUM. UITH BUFFER
0122 0298 2A ROL A ;MULTIPLY ACCUM. BY 2.
0123 0299 88 DEY ;COUNT DOUN CHRS.
0124 029A 10 F9 BPL EXOR ;6ET NEXT CHR.
0125 029C 85 12 STA INDX SAVE HASH PRODUCT AS INDEX.
0126 029E 60 RTS .
‘DONE.
0127 029F .END

ERRORS * 0000 <0000>

SYMBOL TABLE

SYNBOL VALUE

BAD 025D BUFFER 0016 CHKLP 0248 CLRLP 020F

CHPR1 0227 CMPR2 0243 DECR 0211 EMPTY 0233
ENTNUN 0015 EXOR 0295 FILL 0235 FIND 023E
HASH 0290 INDX 0012 INI T 0200 LIMIT 0262
MATCH 0252 OK 026E PTR 0013 SHADD 0272
STORE 0222 TABLE 0010 TEST 0264 XFER 0254

END OF ASSEMBLY
BUBBLE-SORT
Bubble-sort is a sorting technique used to arrange the elem ents
of a table in ascending or descending order. The bubble-sort tech­
nique derives its nam e from th e fact th a t the sm allest elem ent
“ bubbles u p ” to th e top of the table. E very tim e it “ collides” w ith
a “ heavier” elem ent, it jum ps over it.
A practical example of bubble-sort is shown in Fig. 9-46. The list
to be sorted contains: 10, 5, 0, 2, and 100, and m u st be sorted in
order (“ 0” on top). The algorithm is simple, and the
flow chart is shown in Fig. 9-47.
The top tw o (or bottom two) elem ents are compared. If the
lower one is less (“ lighter” ) th an the top one they are exchanged.
Otherwise, they remain the same. For practical purposes, the exchange,
if it occurs, will be noted for future use. Then, the next pair of elements
will be compared, etc., until all elements have been compared two by two.
This first pass is illustrated by steps 1, 2, 3, 4, 5, and 6 in Fig. 9-47,
going from the bottom up. (Equivalently, we would go from the top
down.)
If no elements have been exchanged in one pass, the sort is complete.
If an exchange has occurred, we start all over again.
Looking a t Fig. 9-47, it can be seen th a t four passes are neces­
sary in this example.
The process described above is simple, and is widely used.
One additional com plication resides in the actual m echanism of
the exchange. W hen exchanging A and B, one m ay not write:
A = B
B = A
as this would result in the loss of the previous value of A . (try it on
an exam ple.)
The correct solution is to use a tem porary variable or location to
preserve the value of A:
TEM P = A
A = B
B = TEM P
It works. (Again, try it on an example.) This is called a circular permu­
tation., and it is the way all programs implement the exchange. The
technique is illustrated in the flowchart of Fig. 9-47.
 10 10 10
5 5 5 1-2
0 0 **— 1 3 0 I 3
2 ■ *---- 1= 4 “* ---- 1 4
2 2
100 — 1= 5 100 100
10 0> 2 : 2 > 0
NO CHANGE 0< 5
NO CHANGE EXCHANGE'
© © ©

10 10 - e - i - i 0
0 0 1= 2
r i 10
5 «*— »
5 5
2 2 2
100 100 100
EXCHANGED 0 < 10: EXCHANGED
EXCHANGED END OF PASS 1

© © ©
END OF PASS I

0 0 0
10 10 10
5 5 <*— 1=3 2
2 < * --1 = 4
<*— 1= 5
2 <*— 1= 4 5 a
100 100 100
1 0 0> 2: 2 < 5:
NO CHANGE EXCHANGED EXCHANGED

© © ©
0 0 0 * i= i
10
2
5
<*— 1= 2
1=3
2
10
5
b 2

10
5
- 1= 2

100 100 100

2 < 10: 2 > 0:
EXCHANGED EXCHANGED
NO CHANGE

© © ©
END OF PASS 2
 0 0 0
2 2 2
10 10 ■ *— 1= 3 5
5 ■ *— 1= 4 5 1=4 10
100 * — 1= 5 100 100

100>5: 5 <10: EXCHANGED

NO CHANGE EXCHANGED

© © ©

0 0 ■ *— 1= 1 0
2 1= 2 2 ■ *— 1=2 2
5 1=3 5 5
10 10 1=4
10
100 100 100 1=5

5>2: 2 > 0: 100 > 10:

NO CHANGE NO CHANGE NO CHANGE

© © ©
END OF PASS 3

0 0 0 i=i
2 ■ *— 1=2 2 1=2
2
5 1= 3 5 ■ *— 1=3 5
10 * ---- 1= 4 10 10
100 100 100
10 >5: 5>2: 2>0:
NO CHANGE NO CHANGE NO CHANGE

© © ©
END

Fig. 9-46: Bubble-Sort Exam ple (cont.)

 The memory m ap corresponding to the bubble-sort program is
shown in Fig. 9-48. In th is program , every elem ent will be an 8-bit
positive num ber. The program resides a t addresses 200 and follow­
ing. R egister X is used to memorize the fact th a t an exchange has
or has not occurred, while register Y is used as the running pointer
w ithin the table. TAB is assum ed to be the beginning address of
th e table. The actual program appears in Fig. 9-49. Indirect in­
dexed addressing is used throughout for efficient accessing. Note
how sh o rt the program is, due to the efficiency of the indirect ad­
dressing mode of the 6502.

EXCHANGED?

Fig. 9-48: Bubble-Sort: Memory M ap

SORT.....PAGE OOOI

LINE I LOC COPE LINE

0002 0000 , ; BUBBLE SORT PROGRAM

0003 0000 j
0004 0000 • * to
0005 0000 ;
0006 0000 00 06 TAB •UORD 1600
0007 0002 j
OOOB 0002 • = 1200
0009 0200 ;
0010 0200 A2 00 SORT LDX 10 .*SET EXCHANGE 0' TO 0
OOtl 0202 At 00 LDA (TAB.X)
0012 0204 A8 TAY ;NUMBER OF ELEMENTS IS IN Y
0013 0205 It 00 LOOP LDA (TAB).Y ;read element Ed)
0014 0207 88 DEY .'DECREMENT NUMBER OF ELEMENTS TO READ.
0015 0208 FO 12 BEQ FINISH ;END IF NO MORE ELEMENTS
0016 020A Dt 00 CMP (TAB).Y ICONPARE TO E'(I)
0017 020C BO F7 BCS LOOP JGET NEXT ELEMENT IF E(I»E'U)
OOIS 020E AA EXCH TAX .'EXCHANGE ELEMENTS
0019 020F Bt 00 LDA (TAB).Y
0020 0211 C8 INY
0021 0212 91 00 STA (TAB).Y
0022 0214 BA TXA
0023 0215 88 DEY
0024 0216 91 00 STA (TAB),Y
0025 0218 A2 01 LDX It ;SET EXCHANGED TO I
0026 021A DO E9 BNE LOOP ,'GET NEXT ELEMENT
0027 02IC 8A FINISH TXA .'SHIFT EXCHANGED TO A REG. FOR COHPARE
0028 021D DO Ef BNE SORT JIF SOME EXCHANGES MADE. 00 ANOTHER PASS
0029 021F 60 RTS
0030 0220 .END

ERRORS - 0000 <0000>

SYMBOL TABLE

SYMBOL VALUE

EXCN 020E FINISH 021C LOOP 0205 SORT 0200

TAB 0000
ENB OF ASSEMBLY

<
<
A M ER G E A LG O R ITH M

A nother common problem consists in m erging tw o sets of d a ta

into a th ird one. We will assum e here th a t two tables of d ata have
been previously sorted, and we want to merge them into a third table. The
length of each of the two original tables will be limited to 256 bytes (one
page). The first entry of every table contains the length of the table,
of th e table.
The algorithm for m erging tw o tables is shown in Fig. 9-50. The
corresponding m em ory organization is shown in Fig. 9-51, and the
program appears in Fig. 9-52. Rem ember to set “ TA BLE 1”
“ T A B L E 2,” and “ D E S T B L ” before using it.
The algorithm itself is straightforw ard. Two running pointers
P T R l and P T R 2 , point to th e two source tables. PTR3 points to
the resulting table.

=^ * 0-

►0
-h

U 'V W 'N

IA B 1E3
LINE 1 L«C COSE LINE

0992 9999 {2-PAGE REUSE.

0993 9990 ;T4KE8 2 94T4 T49LE9 PREVI0N9LY SORTED,
0*04 9990 {AND NERSES THEN INIS 4 TNIR9 T49LE.
0403 0000 {EACH SOORCE T49LE C4N 9E 8P T8 ONE
0994 0000 {PASE (234 BYTES) IN LENSTN.
0907 0000 ;THE FIRST ELEMENT OF THE S08RCE
0999 0090 {TABLES RUST C0NT4IN THE T491E LENGTH.
0909 0900 {'PTR3' CONTAINS TNE LENSTN 9F TIE
0919 9900 ;9ESTIN4TI0N T49LE 4T RETURN.
091! 0000 »
0912 0000 • « 910
0913 0910 9EST9L •-•♦2 {POINTER TO 9E9IININ6 OF DESTIN4TI0N T49LE.
0014 0012 T49LE1 •■•♦2 {POINTER TO SOURCE T49LE 1.
0913 0014 T49LE2 •*•♦2 {POINTER TO SOURCE TAILE 2.
0914 0914 PTR1 ;TA9LE 1 IN9EX.
0917 0017 PTR2 •*•♦1 {TABLE 2 INDEX.
0919 9019 PTR3 •*•♦2 ;9E8TIR4TI0N TAILS IN9EX.
0919 0014 »
0920 0014 ♦ ■ 9290
0021 0200 *
0922 0200 45 11 L94 BE8TBLD {PTR3 - T4ILE3
0923 0202 83 19 ST4 PTR3D
0924 0204 43 10 L94 9E8T9L
0923 0204 95 19 ST4 PTR3
0924 0208 49 01 L94 91 {SET SOURCE TAILS POINTERS TO BEGINNING,
0927 0204 93 14 ST4 PTR1 {SKIPPING T49LE LENGTHS.
0029 020C 83 17 8TA PTR2
0929 020E 42 00 L9X 90 {CLEAR X FOR IN9IRECT 49DIES8ING.
0930 0210 41 14 CONPR L94 (TA9LE2,X) {IS T49LE 2 LENGTH <
0931 0212 C5 17 CNP PTR2 {TAILS 2 POINTER?
0932 0214 90 19 ICC TKTI1 {IF TCS, NET 9TTE FRON TABLE 1.
0933 0214 41 12 LI4 (TAILE1,X) {IS TABLE 1 LENSTN <
0934 0218 C3 14 CNP PTR1 {TABLE 1 POINTER?
0933 0214 90 04 9CC TKT92 {IF YES, SET BYTE FRON TABLE 2
0934 021C 44 14 LIT PTR1 {SET POINTER FOR TABLE 1.
0037 021E 91 12 LIA (TAILED,Y {USE IT TO FETCH BYTE.
0939 0220 44 17 LIT PTR2 {SET POINTEN FOR TABLE 2,
0939 0222 91 14 CNP (TABLE2),Y {USE IT TO FIN9 BYTE TO C0NP4RE
0940 0224 {TO TABLE 1 BYTE.
0941 0224 90 99 ICC TKT91 Sir TABLE 1 BITS LESS. TAKE IT.
0942 0224 44 17 TNT92 LIT PTR2 {GET POINTER FOR TABLE 2.
0943 0229 91 14 LB4 (TA9LE2),Y {BET NEXT BYTE FRON TABLE 2.
0944 0224 E4 17 INC PTR2 {INCREHENT POINTER FOR TABLE 2.
0043 022C 4C 33 92 JNP STORE {SO STORE BYTE IN BE8TINAT10N TABLE.
0944 022F 44 14 TRT91 LIT PTR1 {SET POINTER 1...
0947 0231 91 12 LB4 (TABLED,? {ARB U8E IT TO GET BYTE. FRON TABLE.
0049 0233 E4 14 IRC PTR1 {INCREHENT POINTER FOR TABLE 1.
0049 0233 81 18 STORE 8T4 (PTR3,X) {STORE BYTE AT NEXT LOCATION IN TABLE 3.
0930 0237 E4 19 IRC PTR3 {INCREHENT LO ORBER TABLE 3 POINTER.
0051 0239 90 02 IRE CC {IF NO OVERFLOU, SKIP
0932 0231 E4 19 INC PTR3+1 {INCREHENT HI ORDER TABLE 3 POINTER.
0953 0239 41 12 cc LIA (T4BLE1,X> {IS TABLE 1 LENGTH GREATER
0934 023F C3 14 CNP PTR1 {THAN OR EQUAL TO POINTER 1?
0935 0241 90 C9 ICS CONPR {IF YES, SET REIT BYTE.
0934 0243 41 14 LIA (TABLE2,X> {IS TABLE 2 LENSTN GREATER
0957 0245 C5 17 CAP PTR2 {THAN OR EQUAL TO POINTER 2T
0039 0247 90 C7 ICS CONPR {IF YES, SET IEXT BYTE.
0959 0249 49 00 LIA 90
0940 0249 83 19 STA PTR3D {CLEAR PTR3 HI ORDER.
0041 0241 18 CLC {NER6E DONE, NOW..
0042 024E 41 12 LBA (TABLE1,X) {AID TABLE 1 ANB 2 LENGTHS.
0043 0230 41 14 ABC (TABLE2,X)
0044 0252 83 18 STA PTR3 {STORE SUN IN TABLE 3 TEMPORARY POINTER.
0043 0234 90 04 ICC CCC .{AND..
0044 0254 49 01 LIA 91 {OVERFLOU IN...
0047 0238 85 19 STA PTR3*1 {HI BYTE.
0049 0254 40 ccc RTS
0949 0239 .END

Etna* • MM <MM>
EM OF MSIMLV .
Fig. 9-52: M erge Program
 The current entries in TA BLE 1 and TA BLE2 are com pared two
at a time. The smaller one is copied into TABLE3 and the corresponding
running pointer is incremented. The process is repeated and terminates
when both PTR1 and PTR2 have reached the bottom of their respective
tables.

SUM M ARY
The basic concepts relative to common d a ta structures, as well
as actual im plem entation exam ples have been presented.
Because of its powerful addressing modes, the 6502 lends itself
well to the m anagem ent of complex d a ta structures. Its efficiency
is dem onstrated by the terseness of the program s shown.
In addition, special techniques have been presented for hashing,
sorting and merging, which are typical of those required to solve
complex problem s involving actual d a ta structures.
The beginning program m er need not concern himself y e t w ith
th e details of d a ta stru ctu res im plem entation and m anagem ent.
However, for efficient programming of non-trivial algorithms, a good
understanding of data structures is required. The actual examples
presented in this chapter should help the reader achieve such an under­
standing and solve all the common problems encountered with reason­
able data structures.
PROGRAM DEVELOPMENT

INTRODUCTION
All the program s we have studied and developed so far have
been developed by hand w ithout the aid of any software or
hardware resources. The only improvement we have used over
stra ig h t binary coding has been the use of mnemonic symbols,
those of the assem bly language. For effective software develop­
m ent, it is necessary to understand the range of hardw are and
software developm ent aids. It is the purpose of th is chapter to
present and evaluate these aids.

BASIC P R O G R A M M IN G C H O IC E S
Three basic alternatives exist: w riting a program in binary or
hexadecimal, writing it in assembly-level language, or writing it
in a high-level language. Let us review these alternatives.

1. Hexadecimal Coding
The program will norm ally be w ritten using assem bly lan ­
guage mnemonics. However, m ost low-cost, one-board com puter
system s do not provide an assembler. The assem bler is th e pro­
gram which will autom atically tra n sla te the m nemonics used for
the program into the required binary codes. W hen no assem bler is
available, th is tran slatio n from mnemonics into binary m ust be
performed by hand. B inary is unpleasant to use and error-prone,
so th a t hexadecim al is norm ally used. It has been shown in Chap-
te r 1 th a t one hexadecim al digit will represent 4 binary bits. TWo
hexadecim al digits will, therefore, be used to represent the con­
ten ts of every byte. As an example, the table showing the
hexadecim al equivalent of the 6502 instructions appears in th e
Appendix.
In short, w henever the resources of the user are lim ited and no
assembler is available, he will have to translate the program by
hand into hexadecimal. This can reasonably be done for a sm all
num ber of instructions, such as, perhaps, 10 to 100. For larger
programs, this process is tedious and error-prone, so th a t it tends
not to be used. However, nearly all single-board microcomputers
require the entry of program s in hexadecim al mode. They are not
equipped w ith an assem bler and are not equipped w ith a full
alphanum eric keyboard, in order to lim it th eir cost.
In summary, hexadecim al coding is not a desirable way to e n te r
a program in a computer. It is simply an economical one. The cost
of an assem bler and th e required alphanum eric keyboard is
traded-off ag ain st increased labor to en ter the program in th e
memory. However, this does not change the way the program it­
self is written. The program is still written in assembly-level language
so that it can be not only meaningful, but also capable of inspection
and examination by the human programmer.

2. A ssem b ly L anguage Program m ing

Assembly-level programming covers programs that may be entered

in hexadecimal, as well as those that may be entered in symbolic
assembly-level form, in the system. Let us now directly examine the
entry of a program, in its assembly language representation. An
assembler program must be available. The assembler will read each of
the mnemonic instructions of the program and translate it into the re­
quired bit pattern using 1, 2 or 3 bytes, as specified by the encoding of
the instructions. In addition, a good assembler will offer a number of
additional facilities for writing the program. These will be reviewed in
the section on the assembler below. In particular, directives are available
which will modify the value of symbols. Symbolic addressing may be used,
and a branch to a symbolic location m ay be specified. D uring the
debugging phase w here a user m ay remove instructions or add
instructions, it will not be necessary to re-write the entire pro­
gram if an extra instruction is inserted between a branch and the

POWER OF
THE
LANGUAGE

A
APL
COBOL
FORTRAN HIGH-LEVEL
PL/M
PASCAL
BASIC
MINI-BASIC

MACRO
SYMBOLIC CONDITIONAL ASSEMBLY-LEVEL
ASSEMBLY

HEXADECIMAL/ )
OCTAL
> MACHINE-LEVEL
BINARY I

Fig. 10-1: Programming Levels

p o in t to w hich it b ranches, as long as sym bolic labels a re used.

The assembler will autom atically adjust all o f the labels during the
translation process. In addition, an assembler allows the user to debug
his/her program in symbolic form. A disassembler may be used to
examine the contents o f a memory location and reconstruct the
assembly-level instruction that it represents. The various software re­
sources normally available on a system will be reviewed below. Let us
now examine the third alternative.

3. H ig h -L e v el L a n g u a g e
A program m ay be w ritten in a high-level language such as
BASIC, APL, PASCAL, or others. Techniques for programming in
these various languages are covered by specific books and will not
be reviewed here. We will, therefore, only briefly review th is mode
of program m ing. A high-level language offers powerful instruc­
tions which m ake program m ing m uch easier and faster. These
instructions m u st th en be tra n sla ted by a complex program into
th e final binary representation th a t a microcom puter can execute.
Typically, each high-level instruction will be tra n sla ted into a
large num ber of individual binary instructions. The program
which perform s this autom atic tran slatio n is called a compiler or
an interpreter. A compiler will tra n sla te all th e instructions of a
program in sequence into object code. In a separate phase, the
resulting code will th en be executed. By contrast, an interp reter
w ill in te rp re t a single in stru ctio n and execute it, th e n
"tra n sla te ” th e next one and execute it. An in terp reter offers the
advantage of interactive response, b u t resu lts in low efficiency
compared to a compiler. These topics will not be studied fu rth er
here. Let us rev ert to the program m ing of an actual microproces­
sor a t the assembly-level language.

SOFTW ARE SU PPO R T

We will review here the m ain software facilities which are (or
should be) available in the complete system for convenient
software development. Some of the programs have already been intro­
duced, and definitions of these will be summarized below. Definitions
of other important programs will also be provided before we proceed.
The assembler is the program which tra n sla tes the mnemonic
representation of instructions into th e ir binary equivalent. It
norm ally tra n sla tes one symbolic instruction into one binary in ­
struction (which m ay occupy 1,2, or 3 bytes). The resulting binary
code is called object code. It is directly executable by the mi­
crocomputer. As a side effect, the assembler will also produce a
complete symbolic listing of the program , as well as the equiva­
lence tables to be used by the program m er and the symbol oc­
currence list in the program . Exam ples will be presented la te r in
th is chapter.
A compiler is th e program w hich tra n sla tes high-level lan ­
guage instructions into th e ir binary form.

An interpreter is a program similar to a compiler. It also trans­

lates high-level instructions into their binary form, but instead
o f keeping the interm ediate representations, it executes the instruc­
tions immediately. In fact, if often does not even generate any inter­
mediate code, but rather executes the high-level instructions directly.

A monitor is an indispensable program for using the hardware

resources o f this system. It continuously monitors the input devices
for input and also manages the rest o f the devices. As an example,
a minimal m onitor for a single-board microcomputer, equipped with
a keyboard and with LEDs, must continuously scan the keyboard for
user input and display the specified contents on the light-emitting-
diodes. In addition, it must be capable of understanding a num ber o f
limited commands from the keyboard, such as START, STOP, CON­
TIN UE, LOAD MEMORY, and EXAM INE MEMORY. On a large
system, the monitor is often qualified as the executive program. When
complex file m anagement or task scheduling is also provided, the
overall set o f facilities is called an operating system. In the case in
which files may be resident on a disk, the operating system is quali­
fied as the disk operating system, or DOS.

A n editor is the program designed to facilitate the en try and

the m odification of te x t or program s. I t allows the user to conve­
niently enter characters, append them , insert them , add lines, re­
move lines, and search for characters or strings. It is an important
resource for convenient and effective te x t entry.

A debugger is a facility necessary for debugging program s.

Typically, when a program does not work correctly, there may
be no indication w hatsoever of the cause. The program m er, there­
fore, wishes to insert break-points in his program in order to sus­
pend the execution of the program a t specified addresses and to
be able to examine the contents of registers or memory at these
points. This is the primary function of a debugger. The debugger
allows for th e possibility of suspending a program , resum ing
execution, examining, displaying and m odifying th e contents of
registers or memory. A good debugger will be equipped w ith a
num ber of additional facilities, such as the possibility of exam in­
ing d a ta in symbolic form, hex, binary, or other usual representa­
tions, as well as entering d a ta in th is form at.

A loader, or linking loader, will place various blocks of object

code a t specified positions in th e mem ory and adjust th e ir respect­
ive symbolic pointers so th a t they can reference each other. It is
used to relocate program s or blocks in various mem ory areas.
A simulator, or an emulator program is used to simulate the opera­
tion of a device, usually the microprocessor, in its absence, when
developing a program on a simulated processor prior to placing it
on the actual board. Using this approach, it becomes possible to suspend
the program, modify it, and keep it in RAM memory. The disadvantages
of a simulator are that:

1. It usually sim ulates only the processor itself, not in put/

output devices.
2. The execution speed is slow, and one must operate in simulated
time. It is therefore impossible to test real-time devices, which may
result in synchronization problems even though the logic of the
program may be found to be correct.

An emulator is actually a simulator in real time. It uses one

processor to sim ulate another one, and sim ulates it in complete
detail.

Utility routines are essentially all of the routines that the user
wishes the m anufacturer had provided! They m ay include m ulti­
plication, division and other arithm etic operations, block move
routines, character tests, in p u t/o u tp u t device handlers (or “ driv­
e rs ” ), and more.

THE PROGRAMDEVELOPMENT SEQUENCE

We will now exam ine a typical sequence for developing an

assembly-level program. In order to demonstrate their value, we will
assume that all the usual software facilities are available. If all of
them should not be available in a particular system, it would still be
possible to develop programs, but the convenience would be de­
creased, and therefore, the amount of time necessary to debug the
program would most likely be increased.
 The norm al approach is to first design an algorithm and define
th e d a ta structures for the problem to be solved. Next, a com­
prehensive set of flow-charts is developed which represents the
program flow. Finally, th e flow-charts are tra n sla ted into the as­
sembly-level language for the microprocessor; this is the coding
phase.
N ext, the program has to be entered on the computer. We will
examine in the following section the hardware options to be used in
th is phase.
The program is entered in RAM memory of the system under
the control of the editor. Once a section of the program, such as a
subroutine, has been entered, it will be tested.
First, the assembler will be used. If the assembler does not al­
ready reside in the system , it will be loaded from an external
memory, such as a disk. Then, the program will be assem bled, i.e.,
tran slated into a binary code. This results in the object program ,
ready to be executed.
One does not norm ally expect a program to work correctly th e
first tim e. To verify its correct operation, a num ber of breakpoints
will norm ally be set a t crucial locations where it is easy to te st
w hether the interm ediate results are correct. The debugger will
be used for th is purpose. B reakpoints will be specified a t selected
locations. A "Go” command will th en be issued so th a t program
execution is started. The program will autom atically stop a t each
of the specified breakpoints. The program m er can th en verify, by
examining the contents of the registers, or memory, that the data
so far is correct. If it is correct, we proceed u n til the next break­
point. W henever we find incorrect data, an error in the program
has been found. A t this point the program m er norm ally refers to
his program listing and verifies w hether his coding has been cor­
rect. If no error can be found in the program m ing, the error m ight
be a logical one that refers back to the flowchart. We will
assume here th a t the flow-charts have been checked by hand and
are assum ed to be reasonably correct. The error is likely to come
from the coding. It will, therefore, be necessary to modify a sec­
tion of th e program . If the symbolic representation of the program
is still in the memory, we will simply re-enter the editor and
modify th e required lines, th en go through th e preceding se­
quence again. In some system s, th e memory available m ay not be
large enough, so th a t it is necessary to flush out the symbolic
representation of th e program onto a disk or cassette prior to
executing the object code. N aturally, in such a case, one would
have to reload the symbolic representation of the program from
its support m edium prior to en tering the editor again.

The above procedure will be repeated as long as necessary u n til

the results of the program are correct. Let us stress th a t preven­
tion is m uch more effective th a n cure. A correct design will typi­
cally result very quickly in a program which ru n s correctly once
th e usual ty p in g m istakes or obvious coding errors have been
removed. However, sloppy design m ay resu lt in program s which
will ta k e an extrem ely long tim e to be debugged. The debugging
tim e is generally considered to be m uch longer th a n the actual
design tim e. In short, it is alw ays w orth investing more tim e in
the design in order to shorten the debugging phase.
Although using this approach makes it possible to test the overall or­
ganization of the program, it does not lend itself to testing the pro­
gram in terms of real time and input/output devices. If input/output
devices are to be tested, the direct solution consists of transferring the
program onto EPROMs and installing it on the board where it can
be watched to see whether it works or not.

There is an even better solution, and that is the use of an in-circuit

emulator. An in-circuit emulator uses the 6502 microprocessor (or
any other microprocessor) to emulate a 6502 in (almost) real time. It
emulates the 6502 physically. The emulator is equipped with a cable
terminated by a 40-pin connector, exactly identical to the pin-out of a
6502. This connector can be inserted on the real application board that one
is developing. The signals generated by the em ulator will be
exactly those of the 6502, only perhaps a little slower. The essen­
tia l advantage is th a t the program under test will still reside in
the RAM mem ory of the developm ent system. It will generate the
real signals which will com m unicate w ith the real in p ut/output
devices th a t one wishes to use. As a result, it becomes possible to
keep developing the program using all the resources of the devel­
opm ent system (editor, debugger, symbolic facilities, file system )
while testing inp u t/o u tp u t in real tim e.

In addition, a good em ulator will provide special facilities, such

as a trace. A trace is a recording of the last instructions or sta tu s
of various d a ta busses in th e system prior to a breakpoint. In
short, a trace provides th e film of the events th a t occurred prior to
the breakpoint or the malfunction. I t m ay even trigger a scope a t
a specified address or upon the occurrence of a specified combina­
tion of bits. Such a facility is of great value, since when an error is
found it is usually too late. The instruction, or the data, which
caused the error has occured prior to the detection. The availability
of a trace allows the user to find which segment of the program
caused the error to occur. If the trace is not long enough, we can
simply set an earlier breakpoint.

ROM RAM

T h is co m pletes our d e sc rip tio n of th e u s u a l sequence of

events involved in developing a program . L et u s now review the
hardw are alternatives available for developing program s.
THE HARDWARE ALTERNATIVES

1. Single-Board Microcomputer

The single-board m icrocom puter offers the lowest cost approach

to program development. It is norm ally equipped w ith a hexadec­
imal keyboard, some function keys, and 6 LEDs which can display
address and data. Since it is equipped with a small amount of
memory, no assembler is usually available. At best, it has a small
monitor and no editing or debugging facilities, except for a very
few commands. All programs must, therefore, be entered in hex­
adecimal form. They will also be displayed in hexadecimal form on
the LEDs. A single-board microcomputer has, in theory, the
same hardware power as any other computer. However, because
of its restricted memory size and keyboard, it does not support all
the usual facilities of a larger system, and this makes program
development much longer. The tediousness of developing programs
in hexadecimal format makes a single-board microcomputer
best suited for educational and training purposes where programs
of limited length are desirable. Single-boards are probably the
cheapest way to learn programming by doing. However, they
cannot be used for complex program development, unless additional
memory boards are attached and the usual software aids are made
available.

2. The Development System

A developm ent system is a microcom puter system equipped

w ith a significant am ount of RAM memory (32K - 48K) as well as
the required inp u t/o u tp u t devices, such as a CRT display, a
printer, disks, and usually a PROM programmer, as well as,
perhaps, an in-circuit em ulator. A developm ent system is
specifically designed to facilitate program developm ent in an in­
dustrial environm ent. It norm ally offers all, or most, of the
softw are facilities th a t we have m entioned in th e preceding sec­
tion. In principle, it is th e ideal softw are developm ent tool.

The lim itation of a microcom puter developm ent system is th a t

it m ay not be capable of supporting a compiler or an interpreter.
 Fig. 10-3: SYM 1 is a Typical M icrocom puter Board

Fig. 10-4: Rockwell System 65 is a Developm ent System

This is because a compiler typically requires a very large am ount
of memory, often m ore th a n is available in the system . However,
for developing programs in assembly-level language, the development
system offers all the required facilities. Unfortunately, because
development systems sell in relatively small numbers compared to.
hobby computers, their cost is significantly higher.

3. Hobby-Type Microcomputers

The hobby-type microcomputer hardware is analogous to that of a

development system. The main difference lies in the fact that the
hobby-type microcomputer is normally not equipped with the
sophisticated software developm ent aids which are available on
an industrial developm ent system . A s an example, m any hobby-
type m icrocom puters offer only elem entary assem blers, minimal
editors, m inim al file system s, no facilities to a tta ch a PROM pro­
gram m er, no in-circuit emulator, no powerful debugger. They rep­
resent, therefore, a n interm ediate step betw een th e single-board
m icrocom puter and the full microprocessor developm ent system.
For a user who wishes to develop program s of m odest complexity,
they are probably th e best compromise since they offer the advan­
tage of low cost and a reasonable a rra y of software developm ent
tools, even though they are quite lim ited as to th e ir convenience.

4. Time - Sharing Systems

Several companies rent terminals that can be connected to time­
sharing computer networks. These terminals share the time of the
larger computer and benefit from all the advantages of large installa­
tions. Cross assemblers are available for all microcomputers in
virtually all commercial time-sharing systems. A cross assembler is
simply an assembler for, say, a 6502, which resides, for example, in
an IBM370. Formally, a cross assembler is an assembler for micro­
processor X, which resides on processor Y. The nature of the com­
puter being used is irrelelvant. The user still writes a program in 6502
assembly-level language, and the cross assembler translates it into the
appropriate binary pattern. The only difficulty lies in the fact that this
program cannot be executed immediately. It can be executed by a
simulated processor, if one is available, but only if the program does
not use any input/output resources. Because of this drawback, there­
fore, time-sharing is practical only in industrial environments.

5. In-House Computer

W henever a large in-house com puter is available, cross as­

semblers may also be available to facilitate program devel­
opment. If such a computer offers time-sharing service, this option
is essentially analogous to th e one above. If it offers only batch
service, this is probably one of the m ost inconvenient m ethods of
program development, since subm itting program s in batch mode
a t the assem bly level for a microprocessor results in a very long
developm ent tim e.

Front Panel or No Front Panel?

The front panel is a hardware accessory often used to facilitate
program debugging. It has been the traditional tool for displaying the
binary contents of a register, or of memory, conveniently. However,
most of the functions of the control panel may now be accomplished
from a terminal through a CRT display. The CRT, with its ability to
display the binary value of bits, thus offers a service almost equiva­
lent to the control panel. The additional advantage of using the CRT
display is that one can switch at will from binary representation to
hexadecimal, to symbolic, to decimal (if the appropriate conversion
routines are available, naturally). The main disadvantage of the CRT
is that instead of turning a knob, one must hit several keys to obtain
the appropriate display. However, since the cost of providing a
control panel is quite substantial, most recent microcomputers have
abandonned this debugging tool in favor of the CRT. The value of
the control panel, then, is often evaluated more in function of
emotional arguments based on one’s own past experience rather than
by a rational choice. It is not indispensable.

SUMMARY OF HARDWARE RESOURCES

Three broad cases m ay be distinguished. If you have only a
m inim al budget, and if you wish to learn how to program , buy a
 one-board microcomputer. Using it, you will be able to develop all
th e simple program s of th is book and m any more. E ventually,
however, w hen you w ant to develop program s of more th a n a few
hundred instructions, you will feel the limitations of this ap­
proach.
If you are an in d u strial user, you will need a full developm ent
system . Any solution short of th e full developm ent system will
cause a significantly longer developm ent tim e. The trade-off is
clear: hardw are resources vs. program m ing tim e. N aturally, if th e
program s to be developed a re quite simple, a less expensive ap­
proach m ay be used. However, if complex program s are to be
developed, it is difficult to justify any hardw are savings w hen
buying a development system; the resultant programming costs will
far exceed any such savings.
For a personal com puterist, a hobby-type m icrocom puter will
typically offer sufficient, although m inim al, facilities. Good de­
velopm ent software is still to come for m ost of th e hobby com­
puters. The user will have to evaluate his system in view of the
comments presented in th is chapter.
L et us now analyze in m ore detail the m ost indispensable re­
source: the assem bler.

TH E ASSEM BLER

W e have used assem bly-level language throughout th is book

without presenting the formal syntax or definitions of assembly-
level language. The tim e h as come to present these definitions.
An assembler is designed to provide a convenient symbolic repre­
sentation of the user program, while at the same time providing a
simple means of converting these mnemonics into their binary
representation.

Assembler Fields
W hen typing in a program for the assem bler, we have seen th a t
fields are used. They are:
The label field, optional, which m ay contain a symbolic address
for the instruction th a t follows.
The instruction field, which includes the opcode and any oper­
ands. (A separate operand field m ay be distinguished.)
The comment field, to th e far rig h t, which is optional and is
intended to clarify the program .
 o
z
<
OL
LU
Q.
O

y m
§8

CD
s
co
o

o
<
Fig. 10-5: M icroprocessor Program ming Form
 Once the program has been fed to the assembler, the assembler will
produce a listing of it. When generating a listing, the assembler will
provide three additional fields, usually on the left of the page. An
example appears in Fig. 10-6. On the far left is the line number. Each
line which has been typed by the programmer is assigned a symbolic
line number.
The next field to the right is the actual address field, which shows
in hexadecimal the value of the program counter which will point to
that instruction.
The next field to the right is the hexadecimal representation of the
instruction.
This shows one of the possible uses of an assembler. Even if we are
designing programs for a single-board microcomputer which accepts
only hexadecimal, we can still write the programs in assembly-level
language, providing we have access to a system equipped with an as­
sembler. We can then run the programs on the system, using the as­
sembler. The assembler will automatically generate the correct hexa­
decimal codes, which we can simply type in on our system. This
shows, in a simple example, the value of additional software resources.

Tables

When the assembler translates the symbolic program into its binary
representation, it performs two essential tasks:

1. It translates the mnemonic instructions into their binary encoding.

2. It translates the symbols used for constants and addresses into
their binary representation.

In order to facilitate program debugging, the assembler shows at

the end of the listing each symbol used and its equivalent hexadecimal
value. This is called the symbol table.
Some symbol tables will not only list the symbol and its value, but
also the line numbers where the symbol occurs, an additional facility.

Error Messages

During the assembly process, the assembler will detect syntax er­
rors and list them as part of the final listing. Typical diagnostics in­
clude: undefined symbols, label already defined, illegal op­
code, illegal address, illegal addressing mode. Many more de­
tailed diagnostics are naturally desirable and usually provided.
They vary with each assembler.

The Assembly Language

Opcodes have already been defined. We will define here the
symbols, constants and operators which may be used as part of
the assembler syntax.
LINE • LOC CODE LINE
0057 0342 A9 00 LDA •400
0058 0344 8D OD AO STA ACR1 fTURN B01H TIMERS OFF
0059 0347 8D OB AC STA ACR2
0060 034A A2 20 LDX •OFFDEL (GET TONES-OFF DELAY CONSTANT
0061 034C 20 55 03 OFF JSR DELAY 1DELAY WHILE TONE IS OFF
0062 034F CA DEX
0063 0350 DO FA BNE OFF
0064 0352 4C 02 03 JMP DIGIT (GO BACK FOR NEXT DIGIT OF PHONE NUMBER
0065 0355 »
0066 0355 (THIS IS A SIMPLE DELAY ROUTINE FOR THE TONE ON AND OFF PERI
0067 0355 (
0068 0355 A9 FF DELAY LDA •DELCON (GET DELAY CONSTANT
0069 0357 38 WAIT SEC (DELAY FOR THAT LONG
0070 0358 E9 01 SBC •401
0071 035A DO FB BNE WAIT
0072 035C 60 RTS
0073 03SD 1
0074 035D 'THIS IS A TABLE OF THE CONSTANTS FOR THE TONE FREQUENCIES
0075 035D THE CONSTANTS ARE TWO BYTES
0076 035D
0077 0350
0078 0350 TABLE «BYIE 413**02*476.401 ITWO TONES FOR '0'
0078 035E
0078 035F
0076 0360 01
0079 0361 .BYTE 4CD*402*49E*401 (TWO TONES FOR '1'
0079 0362
007? 0363
0079 0364 01
0080 0365 .BYTE 4CD*402*476*401 I
0080 0366.
0080 0367
0080 0368
0081. 036? CD. •BYTE *£4*402*652*401 f
0081 036A
0081 036B
0081 036C
0082 0360 89 .BYTE 489*402.49E»401 I
0082 036E 02
0082 036E. ?E
0082 0370
0083 0371 .BYTE 489#402»076»001 »
0083 0372 02
0083 0373
0083 0374
0084 0375 £2 .BYTE-.489*402* 453*401 1
0084 0376
0084 0377
0084 0378 41
0085 0379 4B .BYTE 44B*402»49E.401 (
0085 037A 02
0085 037B. 9E.
0085 037C 01
0086 0370 4B .BYTE 44B*402*476»401 I '8'
037E 07

LINE • LOC C
4086. 037E 26
0086 0380 01
0087 0381 4B .BYTE 44B*402*453*401 I
4087 0382 42
0087 0383 S3
0087 0384 01

SYMBOL VALUE
ACR1 AOOD ACR2 ACOB DELAY 03E7 DELCON OOFF
DIGIT 0302 NOEND 030A NUMPTR OO l O OFF 034C
QEFDEL QQ2Q .ON. 031C ONDEL 0040 PHONi 0300
T1CH A005 T1LH A007 TILL A004 T2CH AC05
T2LH AC07 T2LL AC04 TABLE 035D WAIT 0357
END OF ASSEMBLY

Fig. 10-6: Assembler Output: An Example

Symbols
Symbols are used to represent num erical values, eith er d a ta or
addresses. Traditionally, symbols may include 6 characters, the
first one being alphabetical. One more restriction exists: the 56
opcodes utilized by the 6502 and the names of the registers
i.e., A, X, Y, S, P m ay n o t be used as symbols.
Assigning a Value to a Symbol
Labels are special symbols whose values need not be defined
by the programmer. They will automatically correspond to the
line number where they appear. However, other symbols used
for constants or memory addresses must be defined by the
program m er prior to th e ir use. The equal sign is used for th a t
purpose, or else a special “ directive.” I t is an instruction to the
assem bler which will n o t be tra n sla ted into an executable s ta te ­
m ent; it is called an assembler directive.
As an example, the constant ALPHA will be defined as:
ALPHA = $A000
This assigns th e value "A000” hexadecim al to variable
ALPHA. The assem bler directives will be exam ined in a late r
section.

Constants or Literals

Constants are traditionally expressed in either decimal, hexadecimal,

octal or binary. Except in the case of a decimal number, a prefix
is used to differentiate between a constant and the base used to re­
present a number. To load 18 into the accumulator we will simply write:

LDA # 1 8 (where # denotes a literal)

A hexadecim al num ber will be preceded by the symbol $.
An octal symbol will be preceded by th e symbol @
A binary symbol will be preceded by %.
For example, to load the value "11111111” into th e ac­
cum ulator, we will write:
LDA #%11111111.
L iteral ASCII characters m ay also be used in a literal field. In
older assem blers, it was trad itio n al to enclose the ASCII symbol
in quotes. In more recent assemblers, in order to have fewer charac­
ters to type in, th e alphanum eric type is indicated by a single
quote th a t precedes the symbol.
For example, to load the symbol "S” in the accum ulator (in
ASCII) we will write:
LDA # ’S
In order to be able to load the quote symbol itself, the conven­
tion is:
LDA # ”’
Exercise 10.1: Will the following two instructions load the same
value in the accumulator: LDA tf’5 and LDA #$5?

Operators
In order to fu rth er facilitate the w riting of symbolic program s,
assemblers allow the use of operators. A t a minimum they should
allow plus and m inus so th a t one can specify, for example:
LD A ADR1, and
LD X A D R 1+1 .
It is important to understand that the expression ADR1 +1 will be
com puted by the assem bler in order to determ ine w hat is the
actual mem ory address which m u st be inserted as the binary
equivalent. It will be computed at assembly-time, not at program
execution tim e.
In addition, more operators m ay be available, such as m ultiply
and divide, a convenience w hen accessing tables in memory. More
specialized operators may also be available, such as, greater
than and less than, which truncate a 2-byte value respectively
into its high and low byte. .
N aturally, an expression m ust evaluate to a positive value.
Negative numbers are not usually used and should be expressed in a
hexadecimal format.
Finally, a special symbol is traditionally used to represent the
current value of the address of the line:*. This sym bol should be
interpreted as “ current location” (value of PC).

Exercise 10.2: What is the difference between the following in­

structions?
LDA % 10101010
LDA #% 10101010
 Exercise 10.3: W hat is the effect o f the follow ing instruction?
BM I * - 2 ?
A ssem b ler Directives
Directives are special orders given by the programmer to the
assembler. Some of these orders result in the storage of values in
symbols or in the memory. Others are used to control the execution
or printing modes of the assembler.
To provide a specific example, let us review here the nine as­
sem bler directives available on th e Rockwell Developm ent Sys­
tem (“ System 65” ). They are: = , .BYT, .WOR, .GBY, .PA G E,
.SK IP, .OPT, .F IL E and .END.
Equate Directive
An equal sign is used to assign a num eric value to a symbol. For
example:
BASE = $1111
* = $1234
The effect of the first directive is to assign the value 1111
hexadecimal to BASE.
The effect of the second instruction is to force the line address to
the hexadecimal value “ 1234.” In other words, the next execut­
able instruction encountered will be stored at memory location
1234.

Exercise 10.4. W rite a d irective w hich w ill cause the program to

reside a t m em ory location 0 and up.

D irectives to In itialize M em ory

Three directives are available for this purpose: .BYT, .WOR, .GBY.
.BYT will assign the characters or values th a t follow in con­
secutive m em ory bytes.
Exam ple: RESERV .BYT 'SYBEX.’
This will resu lt in storing the letters "SYBEX” in consecutive
m em ory locations.
.WOR is used to store 2-byte addresses in the memory, low byte
first.
Example: .WOR $1234, $2345
.GBY is identical to .WOR, except th a t it will store a 16-bit
value, high b yte first. I t is norm ally used for 16-bit d a ta rath e r
th an 16-bit addresses.
The next th ree directives are used to control the input/output:

Input/Output Directives
The input/output directives are: .PAGE, .SKIP, .OPT.
PAGE causes the assem bler to finish the page, i.e., move to the
top of the next page. In addition a title m ay be specified for the
page. For example: .PAGE “ page title .”
S K IP is used to insert blank lines in the listing. The num ber of
lines to be skipped m ay be specified. For example: .S K IP 3.
O PT specifies four options: list, generate, errors, symbol. L ist
will generate a list. Generate is used to p rin t object code for
strin g s w ith the .BYT directive. Error specifies w hether error
diagnostics should be printed. Sym bol specifies w hether the sym ­
bol table should be listed.
The last two directives control the assem bler listing format:

. FILE and . END Directives

In the developm ent of a large program , several portions of the
program will typically be w ritten and debugged separately. A t
some point it will be necessary to assem ble these files together.
The la st statem en t of th e first file will th en include the directive
.FILE NAME/1, where 1 is the number of the disk unit, and
NAME is th e nam e of the next file. The next file m ay be linked, in
tu rn , to more files. A t the end of th e la st file, there will be the
directive: .END NAME/1, which is a pointer back to the first one.
Finally, a facility exists for inserting additional comments w ith
the listing:
"; ” m ay be used to en ter comments a t will w ithin a line ra th e r
th a n en ter an instruction. This is an im portant facility if pro­
gram s are to be correctly documented.

M ACROS
A macro facility is currently not available on m ost existing
6502 assemblers. However, we will define a macro here and
explain its benefits. It is hoped that a macro facility will
Fig. 10-7: AIM65 is a Board with Mini-Printer and Full Keyboard

Fig. 10-8: Ohio Scientific is a Personal Microcomputer

soon be available on m ost 6502 assem blers. ^ _
A macro is simply a name assigned to a group of instructions.
It is essentially a convenience to the programmer. For exam­
ple, if a group of five instructions is used several tim es in a pro­
gram , we could define a m acro instead of alw ays haying to w rite
these five instructions. As a n example, we could write:
SAVREG MACRO PH A
TXA
PHA
TYA
PHA
ENDM
Thereafter, we could write the name SAVREG instead of the above
instructions. ..
Any tim e th a t we w rite SAVREG, the five corresponding lines
will get substituted instead of th e nam e. An assem bler equipped
w ith a macro facility is called a m acro assembler. W hen the
m acro assem bler encounters SAVREG, it will perform a m ere
physical su b stitu tio n of th e equivalent lines.

Macro or Subroutine ?
A t this point, a macro m ay seem to operate in a way analogous
to a subroutine. This is not the case. W hen the assem bler is used
to produce the object code, any tim e th a t a m acro nam e is encoun­
tered, it will be replaced by th e actual instructions th a t it stands
for. A t execution tim e, th e group of instructions will appear as
m any tim es as the nam e of the m acro did.
By contrast, a subroutine is defined only once, and th e n it can
be used repeatedly: th e program will jum p to th e subroutine ad­
dress. A macro is called an assembly-time facility. A subroutine is
an execution-time facility. T heir operation is quite different.

Macro Parameters
Each macro m ay be equipped w ith a num ber of param eters. As
an example, let us consider th e following macro:
SWAP MACRO M, N, T
LDA M
STA T
LDA N
STA M
 LDA T
STA N
ENDM

This macro will resu lt in swapping (exchanging) the contents of

mem ory locations M and N. A swap betw een two registers, or two
mem ory locations, is a n operation which is not provided by the
6502. A macro m ay be used to implement it. “TV in this instance,
is sim ply the nam e for a tem porary storage location required by
the program . As a n example, let us swap the contents of m em ory
locations ALPHA and BETA. The instruction which does th is ap­
pears below:
SWAP ALPHA, BETA, TEM P
In th is instruction, TEM P is the nam e of some tem porary storage
location which we know to be available and which can be used by
the macro. The resulting expansion of the macro appears below:
LDA ALPHA
STA TEM P
LDA BETA
STA ALPHA
LDA TEM P
STA. BETA
The value of a macro should now be apparent: it is a tremendous
convenience for the programmer to be able to use pseudo-instructions
which have been defined with macros. In this way, the apparent
instruction set of the 6502 can be expanded at will. Unfortunately,
one must bear in mind that each macro directive will expand into what­
ever number of instructions were used. A macro will, therefore, run
m ore slowly th a n any single instruction. Because of its conven­
ience for the developm ent of any long program , a m acro facility
is highly desirable for such an application.

Additional Macro Facilities

M any other directives and syntactic facilities m ay be added to a
simple macro facility. For instance, macros may be nested, i.e., a
macro-call may appear within a macro definition. Using this facility,
a macro may modify itself with a nested definition! A first call will
produce one expansion, whereas subsequent calls will produce a
modified expansion of the same macro.
CONDITIONAL ASSEMBLY
Conditional assembly is another assembler facility which is
so far lacking on most 6502 assemblers. A conditional assem­
bler facility allows the programmer to use the special instructions
“ IF,” followed by an expression, then (optionally) “ ELSE,” and
terminated by “ ENDIF.” Whenever the expression following the IF
is true, then the instructions between the IF and the ELSE, or the IF
and the ENDIF (if there is no ELSE), will be assembled. In the case
in which IF followed by ELSE is used, either one of the twc blocks of
instructions will be assembled, depending on the value of the ex­
pression being tested.
With a conditional assembler facility, the programmer can de­
vise program s for a variety of cases, and then conditionally assem­
ble th e segm ents of codes required by a specific application. A s
an example, an industrial user m ight design program s to tak e
care of any num ber of traffic lights a t an intersection for a vari­
ety of control algorithms. He/she will then receive the specifications
from th e local traffic engineer, who specifies how m any traffic
lights there should be, and which algorithm s should be used. The
programmer will then simply set parameters in his/her program, and
assem ble conditionally. The conditional assem bly w ill resu lt in a
"customized” program w hich will re ta in only those routines
which are necessary for th e solution to th e problem.
Conditional assem bly is, therefore, of specific value to indus­
tria l program generation in a n environm ent w here m any options
exist and where the programmer wishes to assemble portions of
programs quickly and automatically in response to external para­
meters.

SUMMARY
This chapter has presented an explanation of the techniques and the
hardware and software tools required to develop a program, along with
the various trade-offs and alternatives.
These range a t the hardw are level from the single-board micro­
com puter to the full developm ent system . A t th e softw are level
they range from binary coding to high-level program m ing. You
will have to select from these tools and techniques in accordance
w ith your goals and budget.
 CHAPTER 11

CONCLUSION

We have now covered all im portant aspects of program m ing,

including the definitions and basic concepts, the internal manipula­
tions of the 6502 registers, the management of input/output devices,
and the characteristics of software development aids. What is the
next step? Two views can be offered, the first one relating to the de­
velopment of technology, the second one relating to the development
of your own knowledge and skill. Let us address these two points.

TE C H N O L O G IC A L D E V E L O P M E N T

The progress of integration in MOS technology makes it pos­

sible to implement more and more complex chips. The cost of im­
plementing the processor function itself is constantly decreasing.
The result is that many of the input/output chips, as well as the
peripheral-controller chips, used in a system, now incorporate a
simple processor. This means that most LSI chips now used in the
system are becoming programmable. An interesting conceptual
dilemma is thus developing. In order to simplify the software de­
sign task as well as to reduce the component count, the new I/O
chips now incorporate sophisticated programmable capabilities:
many programmed algorithms are now integrated within the
chip. However, as a result, the development of programs is com­
plicated by the fact that all these input/output chips are very
different and need to be studied in detail by the programmer!
Programming the system is no longer programming the micro-
 Fig. 11-1: PET is an Integrated Unit

Fig. 11-2: APPLE II uses a conventional TV

processor alone, but also programming all the various other chips
attached to i t The learning tim e for every chip can be s ig n if ic a n t
N aturally, th is is only a n apparent dilemm a. If these chips were
not available, th e complexity of th e interface to be realized, as
well as the corresponding program s, would be still greater. The
new complexity that is introduced is that one has to program
m ore th a n ju s t a processor, and learn the various features of the
different chips in a system to m ake effective use of them . How­
ever, it is hoped th a t th e techniques and concepts presented in
th is book should m ake th is a reasonably easy task.

TH E NEXT STEP
You have now learned th e basic techniques required in order to
program sim ple applications on paper. This was the goal of this
book. The next step is to actually practice. There is no su b stitu te
for it. I t is im possible to learn program m ing completely on paper,
and experience is required. You should now be in a position to
s ta r t w riting your own program s. I t is hoped th a t this journey
will be a pleasant one.
For those who feel they would benefit from the guidance of addi­
tional books, the companion volume to this one in the series is the
“ 6502 A pplications B ook” (ref D302), which presents a range of
actual applications which can be executed on a real microcompu­
ter. Next is the “6502 Games Book” (ref G402), which presents program­
m ing techniques for complex alg o rith m s. A 6502 assembler, writ­
ten in standard Microsoft BASIC is also available.
 HEXADECIMAL CONVERSION TABLE

HEX 0 1 ? ? 4 5 6 7 9 9 A P g P £ F 00 000
0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0
1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 256 4096
2 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 512 8192
3 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 768 12288
4 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 1024 16384
5 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 1280 20480
6 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 1536 24576
7 112 113 114 115 116 117 118 119 120 •121 122 123 124 125 126 127 1792 2 8 67 2
8 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 2 048 3 2 76 8
9 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 2 304 3 6 86 4
A 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 25 60 40960
B 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 2816 45056
C 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 30 72 49152
D 20 8 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 •3328 5 3 24 8
E 224 225 226 227 228 229 230 231 23 2 233 234 235 236 237 238 239 3 584 57 34 4
F 24 0 241 242 243 244 245 246 247 24 8 249 250 251 252 253 254 255 3 8 40 61440

5 4 3 2 1 0
HEX | DEC HEX | DEC HEx|| DEC HEXj| DEC HEX| DEC HExj| DEC
0 0 0 0 0 0 0 0 0 0 0 0
1 1,048,576 1 65,536 1 4,096 1 256 1 16 1 1
2 2,097,152 2 131,072 2 8,192 2 512 2 32 2 2
3 3,145,728 3 196,608 3 12,288 3 768 3 48 3 3
4 4,194,304 4 262,144 4 16,384 4 1,024 4 64 4 4
5 5,242,880 5 327,680 5 20,480 5 1,280 5 80 5 5
6 6,291,456 6 393.216 6 24,576 6 1,536 6 96 6 6
7 7,340,032 7 458,752 7 28,672 7 1,792 7 112 7 7
8 8,388,608 8 524,288 8 32,768 8 2,048 8 128 8 8
9 9,437,184 9 589,824 9 36,864 9 2,304 9 144 9 9
A 10,485,760 A 655,360 A 40,960 A 2,560 A 160 A 10
B 11,534,336 B 720,896 B 45,056 B 2,816 B 176 B 11
C 12,582,912 C 786,432 C 49,152 C 3,072 C 192 C 12
D 13,631,488 D 851,968 D 53,248 D 3,328 D 208 D 13
E 14,680,064 E 917,504 E 57,344 E 3,584 E 224 E 14
F 15,728,640 F 983,040 F 61,440 F 3,840 F 240 F 15
 6502 INSTRUCTIONS-ALPHABETIC

ADC Add with carry JSR Jump to subroutine

AND Logical AND LDA Load accumulator
ASL Arithmetic shift left LDX Load X
BCC Branch if carry clear LDY Load Y
BCS Branch if carry set LSR Logical shift right
BEQ Branch if result = 0 NOP No operation
BIT Test bit ORA Logical OR
BMI Branch if minus PHA Push A
BNE Branch if not equal to 0 PHP Push P status
BPL Branch if plus PLA Pull A
BRK Break PLP Pull P status
BVC Branch if overflow clear ROL Rotate left
BVS Branch if overflow set ROR Rotate right
CLC Clear carry RTI Return from interrupt
CLD Clear decimal flag RTS Return from subroutine
CLI Clear interrupt disable SBC Subtract with carry
CLV Clear overflow SEC Set carry
CMP Compare to accumulator SED Set decimal
CPX Compare to X SEI Set interrupt disable
CPY Compare to Y STA Store accumulator
DEC Decrement memory STX Store X
DEX Decrement X STY Store Y
DEY Decrement Y TAX TVansfer A to X
EOR Exclusive OR TAY TVansfer A to Y
INC Increment memory TSX Transfer SP to X
INX Increment X TXA TVansfer X to A
INY Increment Y TXS TVansfer X to SP
JMP Jump TYA TVansfer Y to A
BINARY LISTING OF 6502 INSTRUCTIONS

ADC OllbbbOl JSR 00100000

AND OOlbbbOl LDA lOlbbbOl
ASL OOObbblO LDX lOlbbblO
BCC 10010000 LDY lOlbbbOO
BCS 10110000 LSR OlObbblO
BEQ 11110000 NOP OlbbbllO
BIT OOlOblOO ORA OOObbbOl
BMI 00110000 PHA 01001000
BNE 11010000 PH P 00001000
BPL 00010000 PLA 01101000
BRK 00000000 PLP 00101000
BVC 01010000 ROL OOlbbblO
BVS 01110000 ROR OllbbblO
CLC 00011000 RTI 01000000
CLD 11011000 RTS 01100000
CLI 01011000 SBC lllbbbO l
CLV 10111000 SEC 00111000
CMP 1lObbbOl SED 11111000
CPX lllObbOO SEI 01111000
CPY llOObbOO STA, lOObbbOl
DEC llObbllO STX lOObbllO
DEX 11001010 STY lOObblOO
DEY 10001000 TAX 10101010
EOR 1lObbbOl TAY 10101000
INC lllb b llO TSX 10111010
INX 11101000 TXA 10001010
INY 11001000 TXS 10011010
JM P OlbOllOO TYA 10011000
 6502—INSTRUCTION SET: HEX AND TIMING
n = number of cycles 0 = number of bytes

(i ) Add 1 to n if crossing page boundary

 P R O CESSO R
(IND. X ) (IN D )Y 2. PAG E. X RELATIVE IN DIRECT Z. PAGE. Y
STATU S CO D ES

OP n 0 OP n « OP n 0 OP n 0 OP n 0 OP n 1 N V B D 1 Z C M N EM O N IC

61 6 2 71 5 2 75 4 2 • • • • A D C
21 6 2 31 5 2 35 4 2 • • A N D
16 6 2 • • • A S l
90 2 2 B C C
BO 2 2 B C S
F0 2 2 B E Q
M rM* • B 1 T
30 2 2 B M 1
DO 2 2 B N E
10 2 2 B P L
1 1 B R K
50 2 2 B V C
70 2 2 B V S
0 C l C
0 C LD
0 C 11
0 C L V
Cl 6 2 D1 5 2 D5 4 2 • • • C MP
• • • C P X
• • • C P Y
D6 46 2 • • D E C
• • D E X
• • D E Y
41 6 2 51 5 2 55 4 2 • • E O R
F6 6 2 • • • N C

• • 1N X
• • 1N Y
6C 5 3 J M P
J S R
Al 6 2 B1 5 2 B5 4 2 • • L D A
B6 4 2 • • l D X
B4 4 2 • • l D Y
56 6 2 o • • L S R
NO P
01 6 2 11 5 2 15 4 2 • • O R A
P H A
P H P
• • P L A
• • • • • • • • P L P
36 6 2 • • • R O l
76 6 2 • • • R OR
R T 1
R TS
El 6 2 FI 5 2 F5 4 2 • • • • S B C
1 S E C
S E D
1 S E 1
81 6 2 VI 6 2 95 4 2 S T A
96 4 2 S T X
94 4 2 S T Y
• • T A X
• • T A Y
• • T S X
• • T X A
T X S
• • T Y A

I2! Add 1 to n if branch within page

Add 2 to n if branch to another page
 APPENDIX E
ASCII CONVERSION TABLE
CODE CHAR CODE CHAR CODE CHAR CODE CHAR

00 NUL 20' 40 @ 605 '

01 SOH 21 ! 41 A 61 a
02 STX 22 " 42 B 62 b
03 ETX 23 n 43 C 63 c
04 EOT 24 $ 44 D 64 d
05 ENQ 25 % 45 E 65 e
06 ACK 26 & 46 F 66 f
07 BEL 27’ ' 47 G 67 9
08 BS 28 ( 48 H 68 h
09 TAB 29 ) 49 1 69 i
2A * 4A J 6A
0A LF i
0B VT 2B + 4B K 6B k
OC FF 2C3 4C L 6C 1
0D CR 2D - 4D M 6D m
0B1 SO 2E 4E N 6E n
OF SI 2F / 4F O 6F o
10 DLE 30 0 50 P 70 P
11 DC1 31 1 51 Q 71 q
12 DC2 32 2 52 R 72 r
13 DC3 33 3 53 S 73 s
14 DC4 34 4 54 T 74 t
15 NAK 35 5 55 U 75 u
16 SYN 36 6 56 V 76 V

17 ETB 37 7 57 w 77 w
18 CAN 38 8 58 X 78 X

19 EM 39 9 59 Y 79 y
1A SUB 3A 5A z 7A z
IB ESC 3B ; 5B t 7B {
1C FS 3C < 5C \ 7C 1
ID GS 3D = 5D ] 7D6 }
IE RS 3E > 5E * 7E
IF US 3F ? 5F4 <- 7F7 RUBOUT

'space ’comma ’accent mark 7orDEL

’single quote 4or underline 6or ALT MODE
 RELATIVE BRANCH TABLES

FORWARD RELATIVE BRANCH

\LSD
0 1 2 3 4 5 6 7 8 9 A B C D E F
M S tK
0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
2 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
3 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
4 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79
5 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95
6 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111
7 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127

BACKWARD RELATIVE BRANCH TABLE

N^LSD
0 1 2 3 4 5 6 7 8 9 A B C D E F
M S tK
8 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113
9 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97
A 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
B 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
C 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
D 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
E 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
F 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
 HEX OPCODE LISTING

^•P = zero page

 DECIM AL TO BCD CONVERSION

BCD DEC BCD DEC BCD

0 0000 10 00010000 90 10010000

1 0001 11 00010001 91 10010001
2 0010 12 00010010 92 10010010
3 0 0 11 13 00010011 93 10010011
4 0100 14 00010100 94 10010100
5 0101 15 00010101 95 10010101
6 0110 16 00010110 96 10010110
7 0111 17 00010111 97 10010111
8 1000 18 00011000 98 10011000
9 1001 19 00011001 99 10011001
 EXERCISE ANSW ERS

CHAPTER 1

1.1: 252

1.2 : 100000001

1.3: 19 -s- 2 = 9 remainder 1 -*• 1

9 + 2= 4 remainder 1 “*• 1
4 + 2= 2 remainder 0 — 0
2 + 2 = 1 remainder 0 -*■0
1+2 = 0 remainder 1 -*• 1
Answer: 10011
lx 1=1
lx 2=2
Ox 4=0
Ox 8=0
+ 1 x 16 = 16
Answer: 19

1.4: 0101 = 5
+ 1010 = 10
1111 = 15

1x1 = 1
1x2 = 2
1x4 = 4
+1x8=8
Answer: 15
1. 5: 1111
+ 0001
( 1)0000
Answer: No, the result does not hold in 4 bits.

1.6 : + 5 = 00000101
- 5 = 10000101

1.7: + 6 = 00000110
-6 = 11111001

1.8: +127 = 01111111

1.9: + 128 = 10000000

01111111 (one’s complement)
+_______ 1_________________
-1 2 8 = 10000000 (two’s complement)

1.10: Smallest: -128

Largest: +127

1. 11: + 20 = 00010100
11101011 (one’s complement)
+ 1
- 2 0 = 11101100 (two’s complement)
00010011 (one’s complement)
+_______ 1
20 = 00010100
Answer: Yes

1. 12: 10111111
+ 11000001
10000000
V: 0 C: 1
IE CORRECT
 11111010
+ 11111001
11110011
V: 0 C: 1
S I CORRECT

00010000
+ 01000000
01010000

V: 0 C: 0
SI CORRECT

01111110
+ 00101010
10101000

V: 1 C:0
S I ERROR

1.13: No, you cannot generate an overflow when adding a positive and a
negative number, because they will tend to cancel each other; thus,
the result will always be within range of 1 byte.

1.14: Largest: 32767

Smallest: -32768

1.15: -8388608

1.16: 29 = 00101001
91 = 10010001

1.17: 10100000 is not a valid BCD representation, because the high order
nibble is 1010, which is unused.
5 2 3 1 2 3
= 00000101 00010010 00110001 00100011
1.19: 222 =

111 =

222 X 111 = 24642

24642 =

1. 20: 9999 in BCD: 24 bits (3 bytes):

4 + 9 9 9 9

9999 in two’s complement: 14 bits (~ 2 bytes)

1. 21: 223 - 1 = 8388607. This is 6 digits of absolute accuracy, or 6+

digits.

1.22: 0 = 00110000 5 = 00110101

1= 10110001 6 = 00110110
2= 10110010 7 = 10110111
3= 00110011 8 = 10111000
4= 10110100 9 = 00111001

1.23: A = 01000001
B= 01000010
C = 11000011
D = 01000100
E = 11000101
F = 11000110

1.24: “A” =01000001

“T” = 01010100
“S” =01010011
“X” =01011000

1.25: 10101010 = AA (hexadecimal)

 1.26: FA = 11111010

1.27: 01000001 = 101 (octal)

1.28: Negative numbers represented in tw o’s complement produce

results that do not need to be corrected when added.

1.29: 1024 = 10000000000 (direct binary)

= 01000000000 (signed binary)
= 01000000000 (two’s complement)

1.30: The overflow (V) flag is set when the carry out of bit 6 does not
equal the carry out of bit 7 (exclusive OR). It should be tested after
any addition or subtraction involving numbers represented in two’s
complement notation.

1.31: +16 = 010000

+17 = 010001
+ 18 = 010010
-1 6 = 110000
-1 7 = 101111
-1 8 = 101110

1.32: M = 4D
E = 45
S = 53
S = 53
A = 41
G =47
E = 45

CHAPTER 3

3.1: Left to reader.

3.2: CLC
CLD
LDA ADR1
ADC ADR2
STA ADR3
LDA ADR1 + 1
ADC ADR2+1
STA ADR3 + 1

3.3: CLC
CLD
LDA A D R 1-1
ADC A D R 2-1
STA A D R 3-1
LDA ADR1
ADC ADR2
STA ADR3

3.4: CLD
SEC
LDA ADR1
SBC ADR2
STA ADR3

3.5: See text.

3.6: Yes, the CLC instruction only has to be executed before the
addition.

3.7: The only difference is that here the D flag is set, not clear, which
will affect the way the final answer is computed.

3.8: SEC
SED
LDA ADR1
SBC ADR2
STA ADR3
LDA ADR1 - 1
SBC A D R 2-1
STA A D R 3-1
 3.9: 0100 MPD 1x 0=0
x 0111 MPR 2x 0=0
0100 4x 1=4
0100 8x 1=8
0100 16 x 1 =16
0000_______ 32 X 0 =_0
0011100 28 V

3.10: Carry will equal 1.

3.11: When X decrements to zero, the next instruction to be executed is

‘BNE MULT’, but the branch will not occur.

3.12: Fill table (see text).

LDA m CLEAR ADDRESSES

STA RESAD
STA RESAD + 1
LDX #8 SET COUNTER
MULT LSR MPRAD GET A MULTIPLIER BIT
BCC NOADD TEST FOR A 1
LDA RESAD+1 ADD MULTIPLICAND
TO RESULT
CLC
ADC MPDAD
STA RESAD+1
NOADD ROR RESAD+1 SHIFT RESULT RIGHT
(RECOVERS CARRY)
ROR RESAD
DEX DECREMENT COUNTER
BNE MULT TEST FOR ZERO

This approach is faster, because the add of the partial product to

the result is eight bits instead of sixteen.

3.14: 157 /usee., assuming all addresses zero page, no page crossings, and
a 1MHz clock.
3.15: Left for reader.

3.16: TEST LDA $24

CMP #$2A
BEQ STAR

3.17: A subroutine requires a fixed overhead time in which to manipu­

late the stack.

3.18: In the case of both the call and the return, the same number of
values must be transferred to/from the stack in memory.

3.19: Yes. MULT modifies the X and A registers plus several flags.

3.20: A subroutine may call itself if it was designed to do so. It must

store data in the stack, though, to preserve it, as the registers will be
reused on each call. Also, there must be a conditional statement
that will limit the number of calls made; otherwise, the stack area
in memory will overflow.

3.21: Stack parameters are best for recursion. Fixed registers and mem­
ory locations will be changed by each iteration of the subroutine.
The stack can accommodate a string of parameters.

CHAPTER4

4.1: LDA WORD

AND #«7o01000010
STA WORD

4.2: No effect.

4.3: The final value of the accumulator would be 10101 111.

4.4: The result would always be $FF.

4.5: No effect.
CHAPTERS

5.1: LDX #NUMBER

NEXT DEX
BNE DONE
LDA BASE.X
STA DEST.X
JMP NEXT
DONE .

OR
LDX ^NUMBER
NEXT DEX
LDA BASE.X
STA DEST.X
TXA
BNE NEXT

BLKADD LDY # N B R -1
NEXT CLC
LDA PTRl.Y
ADC PTR2,Y
STA PTR3,Y
DEY
BPL NEXT

Bytes Cycles
2 2
1 2 ’
3 4
3 4 . Repeated NBR
3 5 times
1 2
2 -1 jJ
15 20XNBR+1 20 (loop total)
 BLKADD LDY #NBR —1
NEXT CLC
LDA (LOCl),Y
ADC (LOC2),Y
STA (LOC3),Y
DEY
BPL NEXT

Bytes Cycles
2 2
1 2
2 5
2 5
2 6
1 2
2 -1 _3
12 23 X NBR +1 23

LDA m INITIALIZE SUM

STA SUMLO
STA SUMHI
LDY m Y IS COUNTER
CLC
ADDLP LDA BASE,Y ADD
ADC SUMLO
STA SUMLO
BCC NOCARRY TRANSFER CARRY
TO NEXT BYTE
INC SUMHI
CLC
NOCARRY DEY
BPL ADDLP
RTS

5.4: Yes. However, this method would be cumbersome, requiring 10

additions.
 5.5: LDX #0 INITIALIZE INDEX REGISTERS
LDY #9
LOOP LDA BASE.X
STA REVER.Y
INX
DEY
BPL LOOP
RTS

5.6: Left to reader.

5.7: Left to reader.

CHAPTER6

6.1: 2 + 5 x 255 - 1 = 1,276//sec or 1.276 msec.

The minimum possible delay is 6 //sec; therefore, 1 //sec delay is
not possible.

6.2: 2 + 5 X 20 - 1 = 101
NEXT LDY #20
DEY
BNE NEXT

6.3: LDX #$9C

NEXT LDY #$7F
LOOP DEY
BNE LOOP
DEX
BNE NEXT
Execution time = 99997 // sec or 99.997 msec.

6.4: Cycles
LDY #0 2
WATCH LDA STATUS 2
BPL WATCH 2 (FAIL)
STA (POINTER),Y 6
INC POINTER 5
DEC COUNT 5
BNE WATCH 3/2
 The total number of cycles for the input loop, assuming that the
status is always true, is 2 + 2 + 6 + 5 + 5 + 3 = 23, or 23 ^sec with a 1
MHz clock. This implies an input rate of

----- ------ = 43.35Kbytes/sec

23 ixsec
The actual difference in rates is

— 1— - — 1— = 12.08K bytes/sec
18/^sec 23/isec
or less than 22%.

6.5: 146 ^sec/byte

~6.8K bytes/sec

6.6: Bit 7 is used for status because it can be easily tested through the sign
flag. Bit 0 is used for data because it can be easily shifted into the
carry.

6.7: Assuming status is represented in bit 7 of a memory location, the

BIT instruction would transfer it into the sign flag without affecting
the accumulator.

6.8: LDA #$00

LOOP BIT INPUT
BPL LOOP
LSR INPUT
ROL A
BCC LOOP
PHA
LDA #$01
DEC COUNT
BNE LOOP
Original: 146f/sec/byte; 25 bytes
New version: 149 ^sec/byte; 18 bytes

6.9: START LDA #$01

LOOP BIT INPUT
BPL LOOP
LSR INPUT
 ROL A
BCC LOOP
PHA
DEC COUNT
BNE START

6.10: LDX #o
START LDA #$01
LOOP BIT INPUT
BPL LOOP
LSR INPUT
ROL A
BCC LOOP
STA BASE.X
INX
DEC COUNT
BNE START

6.11: LDX #0
START LDA #$01
LOOP BIT INPUT
BPL LOOP
LSR INPUT
ROL A
BCC LOOP
CMP #$53
BEQ DONE
STA BASE.X
INX
DEC COUNT
BNE START
DONE #

6.12: SERIAL LDA #$00

STA WORD
LOOP LDA INPU T+1
LSR A
BCC LOOP
LDA INPUT
 LSR A
ROL WORD
BCC LOOP
LDA WORD
PHA
LDA #$01
STA WORD
DEC COUNT
BNE LOOP

6.13: CHARPR LDX #N

LOOP LDA CHAR.X
WAIT BIT STATUS
BPL WAIT
STA PRINTD
DEX
BNE LOOP

6.14: CHARPR LDX #N

LOOP LDA CHAR.X
WAIT BIT STATUS
BPL WAIT
STA PRINTD
CMP #$0D
BEQ DONE
DEX
BNE LOOP
DONE #

6.15: Hex LED Code Hex LED Code

0 3F 9 67
1 06 A 77
2 5B B 7C
3 4F C 39
4 66 D 5E
5 6D E 79
6 7D F 71
7 07
8 FF
6.16: LEDS STX T1
STY T2

LDX T1
LDY T2
OUT RTS

6.17: LEDS TXA

PHA
TYA
PHA

PLA
TAY
PLA
TAX
OUT RTS

6.18: LDX #$5A

NEXT LDY #$13
LOOP DEY
BNE LOOP
DEX
BNE NEXT
Execution time: 9.09 msec

6.19: PRINTC LDA #$00 OUTPUT START BIT

STA TTYBIT
JSR DELAY 9.09 MSEC DELAY
LDX #$08 BIT COUNTER
NEXT ROR CHAR GET A BIT
ROL A INTO ACCUMULATOR
STA TTYBIT OUTPUT IT
JSR DELAY
DEX
BNE NEXT WORD TRANSMITTED?
 LDA #$01 YES, OUTPUT STOP BITS
STA TTYBIT
JSR DELAY
STA TTYBIT
JSR DELAY
RTS

6.20: TTYIN LDA TTYBIT TEST FOR START BIT

LSR A
BCS TTYIN
ROL A RECOVER BIT
STA TTYBIT OUTPUT IT
JSR DELAY

6.21: 26 sec lost.

6.22: 256 locations - 64 interrupts

4 locations/interrupt

6.23: 256 locations = 42 interrupts

6 locations/interrupt

6.24: Left for reader.

6.25: a) Hardware senses the interrupt request, compares with the

mask, sets mask, and preserves regiser (P,PC). Software
unsets the mask, preserves registers (A,X,Y), identifies the
device, executes the routine, restores registers, and returns.
b) The mask inhibits unwanted interrupts.
c) All registers that are changed by the interrupt routine should
be preserved.
d) The interrupt device is usually identifed by polling if there is
more than one possiblity.
 e) The RTI instruction restores processor status while the RTS
does not.
f) Inhibiting interrupts would allow those executing to finish
and withdraw their addresses from the stack.
g) The overhead is the stack manipulations and the running of
the routine itself, both of which detract from the speed of the
mainline program.

CHAPTER8

LDA #0
JSR CHECK
LDA #$FF
JSR CHECK
LDA #$55
JSR CHECK
LDA #$AA
JSR CHECK
JM P DONE
CHECK LDX #0
LOOP STA BASE.X
DEX
BNE LOOP
NEXT CMP BASE.X
BNE ERROR
DEX
BNE NEXT
RTS
DONE

ERROR

STRING LDX #0
NEXT JSR GETCHAR
CMP #SPC
BEQ OUT
 JSR SENDCHAR ECHO CHARACTER
STA BUFFER,X
INX
BNE NEXT IF X IS BACK TO ZERO,
RETURN
OUT RTS

8.3:

BCC TOOLOW
CMP #$BA
BCS TOOHIGH
OUT CLC

8.4: Left to reader.

8.5: JSR PARITY

AND #$80 MASK ALL BUT 7 BIT
CMP EXPECT IS PARITY THE ONE EXPECTED?
RTS Z FLAG HOLDS ANSWER

8.6: LDA BCDCHAR

AND #$30 SET LEFT NIBBLE TO 3
STA CHAR

8.7: LDA BCDCHAR

tax;
AND #$OF MASK OFF HIGH NIBBLE
STA BINCHAR
TXA
LSR A SHIFT HIGH NIBBLE TO LOW ORDER
LSR A
LSR A
LSR A
STA TEMP STOREX
ASL A X TIMES 2
 ASL A X TIMES 4
ADC TEMP X TIMES 5
ASL A X TIMES 10
ADC BINCHAR ADD LOW NIBBLE
STA BINCHAR STORE BINARY RESULT

8.8: MAX LDY m

STY INDEX
LDA (BASE),Y
TAY
LDA #$80 MOST NEGATIVE NUMBER
STA BIG
LOOP EOR (BASE),Y COMPARE SIGN BITS
BPL SAME
LDA BIG IF + / - INVOLVED,
BPL NOSWITCH CHECK IF MAX IS POSITIVE
JMP SWITCH
SAME LDA BIG
CMP (BASE),Y
BCS NOSWITCH
SWITCH LDA (BASE),Y
STA BIG
STY INDEX
NOSWITCH DEY
BNE LOOP
RTS

8.9: Yes, the program will work on ASCII characters with a consistent
parity bit (always 0 or 1).

8.10: See Figure 9.49.

8.11: Left for reader.

8.12: (c)

BCC NO CARRY
LDA #0
 ADC SUMHI INCREMENT SUMHI
SUCH THAT CARRY
BCS OVER IS AFFECTED
NOCARRY DEY
BNE ADLOOP
CLV
RTS
OVER LDA #$40
ADC #$40 FORCE OVERFLOW
RTS ERROR: RETURN

(b)

ZLOOP LDA (ADDR),Y

AND #$7F MASK OUT PARITY BIT
CMP #$41 ‘A CHARACTER
BCC NOTZ
CMP #$5B ‘[’ CHARACTER
BCS NOTZ
INX
NOTZ DEY

CHAPTER 9

9.1: Address Contents

15 00
16 05

9.2: FIRST
PTR3

BLOCK 3

BLOCK
CHAPTER 10

10.1: No. LDA #’5 will load hexadecimal value 35 as a representative of

the ASCII character “5*. LDA 0$5 will load the numerical value of 5
into the accumulator.

10.2: LDA Vo10101010 loads the accumulator with the contents of the
memory location AA16. LDA 10101010 loads the accumulator
with the actual value AAi6.

10.3: Assuming the N flag is set, the program counter will be jumped to
the memory location where the branch instruction starts. This will
result in an infinite loop.

10.4: * = 0
 INDEX

BCD addition 63,66

BCD flags 67
A 187 BCD mode 67,108
abbreviations 112 BCD subtraction 66
absolute 197 BCS 109,120
absolute addressing 66,190,191,195 benchmark 220
accumulator 41,48,55,110,122,133,143, BEQ 109,121
152,165,178,182,183,185,190,263 binary 12, 1 3 ,1 4 ,3 3 ,34,35,36,37,64,
ADC 62,113 343,346,358,361,373
addition 54,59,67 binary digit 10,12
address 39,149,188,189,191,192,306 binary division 86
address bus 39,44,45,49 binary mode 108
address field 358 binary representation 12,33,358
addressing 188,189 binary searching 283,290,294,295,
addressing modes 188,200 296,299
addressing techniques 188 binary tree structure 313,320
algorithm 7, 8, 69,275, 318, 320, 340 BIT 110,122
alphabetic list 290,301,302,303,304,305 bit 10,12,33, 54,59,100,122,167,169
alphabetical order 269,372 bit serial transfer 221,223
alphanumeric 31 block 203,204,205,208,276,277,279,280
ALU ' 39,41 block transfer routine 203,204,205
AND 87,104,110,115 BMI 109,123,208
APL 345 BNE 77,, 109,,124,, 207,208,264
arithmetic 41,67,100,103,117 bootstrap 40
arithmetic logical unit 39,41 BPL 109,125
arithmetic operation 41,100 bracket testing 265
arithmetic programs 54 branch 101,119, 120, 121, 123,124,125,
ASCII 31, 32,267,268, 360, 376 127,,128, 191,196,264
ASL 106,117 branches 196
assembler 55,343, 345,346, 356,358,359 branching 191
assembler directives 362
branching point 69
assembly level language 344,356,358,359 break 102, 108,126,251
assembly time 361,365 break point 108,251,349
asynchronous 216,221,228 BRK 108, 111, 126,251
bubble sort 333,,334, 335, 336,337,338
B buffer 255
buffered 41
BASIC 16, 345 busses 39
basic concepts 7 BVC 109,127
baud 235 BVS 109,128
BCC 74, 109,119 byte 10,11,27,62
BCD 26,27,64, 65,103,268, 379
C data 39,255
data bus 39,45
c 43 data direction register 255,256,259
call 101 data processing 100,103
carry 19,21,22,43,57,75,,109, 113,119,
120, 129,173,175,191 data structures 275, 284, 300
central processing unit 39 data transfer 67,99,102
characters 31,265,266 data transfer rate 221
checksum 270 data units 319
chronological structure 47 debugger 347
circular list 280, 281 debugging 10, 347
classes of instruction 99 DEC 139
CLC 57,63,67,129 decimal 12,13,14, 35,36, 58, 108,
CLD 58,130 130, 176, 379
clear 57,58,111,119,, 127,129,130, decimal adjust 64
131,132,191 decimal mode 176
CLI 131 decoding logic 41,45
clock 40,45,73 decrement 100,103,139,141 ,142,207,214
CLV 132 delay 213,214
CMP 110,133 deleting 287,301,309
code conversion 268 design examples 284
coding 8, 349 destination 39
collision 321 352
development system
combination chips 41 248, 348
device handler
combinations 194 77,141,207
DEX
commands 8 DEY 142, 207
comment field 55,356 direct addressing 82, 190,191
comparisons 106 direct binary 11,37
compiler 346 directive 95, 360, 362
complement 14, 30, 54 directories 277, 306
conditional assembly 367 disassembler 345
constants 66, 360 disk operating system 347
control bus 39 displacement 110,189,191
control instructions 102,111
control lines 255 DMA 239
control register 255, 257 documenting 55
control signals 51 DOS 347
control unit 39,45 doubly linked lists 281,282
counter 71,214 drivers 41
counting 213 duration 217
CPU 39
CPX 111,135
CPY 111,137 E
cross assemblers 354
crystal 40 EBCDIC 31
current location 361 echo 234,237
editor 347
D element deletion 299
element insertion 298
D 58,108 emulator 348, 350
 EOR 22, 87, 104, 105, 143 incircuit emulator 350, 352
error messages 358, 363 inclusive OR 161
executive 347, 360 increment 100, 103, 145,147,148
execution speed 42, 45, 82, 348 indexed addressing 191, 197, 238
exponent 28, 29 indexed indirect addressing 198,199,209
extended addressing 191 index registers 47,191,200,289
external device 39 indirect addressing 193,194,198,276
indirect indexed addressing 192,199
indirection pointer 276
initialization 70
fetch 44,45,46,47 input/output 102,211,228,239, 363
fields 356 input/output devices 39,102,211,228,
FIFO 279 238,239,254, 263
file system 277 input/output instructions 111
input ports 41
flags 22,102,106,130,132,297
inserting 287, 298, 308, 320
flip-flop 42
instruction 11,55, 112, 372, 373
floating point 28,29,31,100
instruction field 356
flow charting 8, 9,10,69, 86, 89,214,
instruction register 45
219,223,240,273, 288,289,291,
instruction set 99,374, 375
294, 301,315,316,317, 339
front panel instruction types 67
33,355
interface chips 40
internal control register 190,257
G internal organization 10,41,42
interpreter 346
generate a signal 212, 363 interrupt 48,102,108,131,171,177,216,
242,243,255
H interrupt handling routine 249
interrupt levels 251
half carry 65 interrupt-mask 108,244
handshaking 228,229, 255,261 interrupt request 51
hardware concepts38,227,239,355 interrupt vector 245, 248
hardware delays 216 INX 147
hardware stack 48 INY 148
hashing algorithm 320, 321, 322, 329, IR
330, 331, 332 45
hexadecimal 33, 34,35,343,358,361, IRQ 51,111,244,245
371,374,375 iteration 201
hexadecimal coding 36,343,344
high level language 345 J
hobby type microcomputers 354
JMP 110,149
JSR 95,110,151
jump 95,101,149,151,200
I 244
immediate addressing 66,190,195
K
implicit addressing 190
implied addressing 194
K 16,49
improved multiplication 82 keyboard 264
INC 145,207 KIM 261
L multiplicand 75,77,81,83
multiplication 68,69, 80, 82
label field 356
largest element 268
LDA 55,67, 152, 268 N
LDX 154
LDY 156 N 43, 107,110
LED 33,230,231 negative 16,17,18,23,43
level activated 244 nested 366
levels 95 nested calls 93
LIFO 47, 276, 280 next instruction 43,46
light emitting diode 230 nibble 10, 27,100
358 NMI 51, 111,244,245
line number
278. 280.299. 306 nodes 319
linked list
308.309.310.311.312 non-maskable interrupt 51,244
linking loader 347 NOP 111, 160
listing 95,322,359, 378 normalize 28
lists 276, 285, 286, 287, 292, 293, 363 normalized mantissa 28
literal 65,66, 189, 190,360
load 55,152,154, 156,257,259
loader 347
location 73 object code 346
logarithmic searching 283,290 octal 33,34, 35,36,360
logical 41,104,115,158 oneK 49
logical operations 41,87, 100 one’s complement 17,19
long branch 200 one-shot 216
longer delays 215 opcode 41, 189
loops 53, 191,240 operand 41,54, 59,61,356
LSR 106,158 operand field 356
operating system 347
operators 361
M ORA 87,104,161
oscillator 40
macros 363,365,366 overflow 20, 21,22,23 51,107,
macro parameters 365 127,128,132
main program 91 overhead 247, 253
mantissa 28,29,31
masking 131 p
master directory 277
memory 39,44,45, 55,57,97,122,145, P 60,244
178,180, 181, 218, 272, 276, 285, 314 packed BCD 27,63
memory mapped I/O 102, 337,351 pageO 49
memory test 263,319 paging 49,50
merge 339,340, 341 parallel input/output chips 40
mnemonics 343,358 parallel word transfer 218,219
monitor 40, 347 parameters 365
MOS Technology 261 parity 31,32,267
MPU 38, 39,40 parity generation 267
multiple interrupts 248, 249 partial product 71,72
multiple precision 59 PASCAL 345
 PC 43, 244, 361 R
PCH 43
PCL 43 RAM 40,41,44, 349, 352
PHA 163 Random Access Memory 40
PHP 164 RDY 51
physical address 75 read only memory 40, 256
PIA 256, 257, 259, 260 read write memory 40, 256
PIC 249 recursion 96
PIO 40, 254, 255,256, 258 register 33, 39, 73,75, 83,96, 97,106,
PIT 213 135,154 , 156,190,247,256
PLA 165 register management 53
PLP 166 regular interrupt line 244
pointers 97,194, 275, 276, 278, 297 relative addressing 191,196
polling 216,219, 240, 247, 248, 263 relay 212
pop 48 representation of information 33, 35
port 40, 254, 255 RES 51
positional notation 12 reset 256
positive 16,17,23,269 restoring method 86
post indexing 192 retrieval 280, 328
power failures 40 return 90,171,172
precision 27 Rockwell 261,353
pre-indexing 192 ROL 167
printer 35,229,241,279 ROM 40,44
printing a string 238 ROR 169
priority 245, 246 rotate 72,77,101,167,169
priority interrupt controller 249 rotation 77, 100
process control 40 routines 262
program 8,40 round robin 280,281
programming 7,8,81 RTI 110,171,245,246
program counter 43,45 , 47,244, 358 RTS 95,110,172
program development 343, 348 RW 51
program loop 70
programmable interval timer 213
programming alternative 81 S
programming form 357
programming hints S 47,184,186
67
SBC 62,173
programming language 8,345
scheduling 239
programming techniques 53
PROM programmer scope 351
354
pseudo instructions searching and sorting 282
58
pull 48, 100,165,166 search techniques 283, 286,290,307
pulse counting SEC 63,175
216
SED 67, 176
pulses 212,213,217
SEI 177
push 48,100,163,164
sending a character 229
sensing pulses 216
Q sequencing 38,46
sequential block access 200
quartz 40 sequential lists 276
queue 279,280 sequential searching 282
serial search 286 symbol table 358
set 120, 128,175, 176, 177 SYNC 51
shift 71,72,76,77, 100, 101, 117, 158 synchronization 39,102,348
shift operations 106 synchronous 221
short address 189,195, 200 Synertek Systems 261
sign 107 syntax 281
signed binary 16,17,18 system architecture 38
sign extension 100 system 65 362
simulator 348
simultaneous interrupts 249
simple list 286,290 T
single board microcomputer 344,352
table 191,197,202, 276,277,285,288,
6502 38,194, 350,372
289,290,,291,326, 358,377
6502 peculiarities 57
TAX 182
6522 258
TAY 183
6530 257,258
teletype input-output 233,235,236,237
6532 261
ten's complement 66
skew 100
test and branch 102,106,109
skip 102
testing 8
SO 51
timer 216,258
software stack 48
time sharing system 354
software support 346
trace 350,351
sort 269
transfer 182,183 , 184,185,186,187
source 39
translation 55
STA 67, 103,178,207
tree builder 313,315,316
stack 47,97,166,244,250,275,280
tree search 323,324,325
stack operations 49,103
trees 281,282,313 ,319,320,321,322
stack overflow 253
standard PIO 254 tree traverser 313,317,318,320
start bit 235,236,255 truncations 25
status flags 42 TSX 184
status manipulation 67 two's complement 17,18,19,29,63,
status register 244 100, 107
stop bit 235 TXA 185
store 103, 178,180,181,327 TXS 186
string 230, 271, 272 TYA 187
STX 180
STY 181
subroutines 48,90,92,95,96,151,
U
172,327, 365 UART 227
subroutine call 91,95 unconditional jump 95
subroutine level 95,96 underflow 24
subroutine library 98 utility programs 262
subtract 62,173 utility routines 262,348
subtraction 14,67
sum of n elements 269
SYM 261 V
symbol 360, 363 versatile interface adapter 258
symbolic label 75, 345 VIA 258
symbolic representation 35,356 volatile 40
W

working registers 73,195

X 47, 135, 141,147, 154,180, 182,184

185,186

Y 47,137,142,148,156,181,183,187,207

z 43,107,108,110
zero 43,108,121,124,271
zero page addressing 195
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