AD8307
AD8307
AD8307
Logarithmic Amplifier
AD8307
FEATURES FUNCTIONAL BLOCK DIAGRAM
Complete Multistage Logarithmic Amplifier
92 dB Dynamic Range: –75 dBm to +17 dBm AD8307
to –90 dBm Using Matching Network VPS BANDGAP REFERENCE ENB
Single Supply of 2.7 V Min at 7.5 mA Typical SUPPLY 7.5mA
AND BIASING ENABLE
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1999
AD8307–SPECIFICATIONS (V = +5 V, T = 25ⴗC, R ≥ 1 M⍀, unless otherwise noted)
S A L
–2– REV. A
AD8307
ABSOLUTE MAXIMUM RATINGS* *Stresses above those listed under Absolute Maximum Ratings may cause perma-
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.5 V nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
Input Voltage (Pins 1, 8) . . . . . . . . . . . . . . . . . . . . . . VSUPPLY section of this specification is not implied. Exposure to absolute maximum rating
Storage Temperature Range, N, R . . . . . . . . –65°C to +125°C conditions for extended periods may effect device reliability.
Ambient Temperature Range, Rated Performance Industrial,
AD8307AN, AD8307AR . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . +300°C
ORDERING GUIDE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although WARNING!
the AD8307 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
ESD SENSITIVE DEVICE
recommended to avoid performance degradation or loss of functionality.
REV. A –3–
AD8307–Typical Performance Characteristics
8 3
7
2
6
SUPPLY CURRENT – mA
1
5
ERROR – dB
TEMPERATURE ERROR @ +858C
4 0
3
–1 TEMPERATURE ERROR @ +258C
0 –3
1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 –80 –60 –40 –20 0 20
VENB – Volts INPUT LEVEL – dBm
Figure 1. Supply Current vs. VENB Voltage (5 V) Figure 4. Log Conformance vs. Input Level (dBm) at 25 °C,
85 °C, –40 °C
8 3
6
SUPPLY CURRENT – mA
2
5
VOUT – Volts
3
1 INPUT FREQUENCY 300MHz
2
0 0
1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 –80 –60 –40 –20 0 20
VENB – Volts INPUT LEVEL – dBm
Figure 2. Supply Current vs. VENB Voltage (3 V) Figure 5. VOUT vs. Input Level (dBm) at Various Frequencies
3 1.5
2 1.0
ERROR – dB
0 0
–3 – 1.5
–80 –60 –40 –20 0 20 – 80 – 60 – 40 – 20 0 20
INPUT LEVEL – dBm INPUT LEVEL – dBm
Figure 3. Log Conformance vs. Input Level (dBm) @ Figure 6. Log Conformance vs. CFO Values at 1 kHz Input
100 MHz, 300 MHz Frequency
–4– REV. A
AD8307
3.0 3
ERROR – dB
VOUT – Volts
+ INPUT
10MHz, INT = –87.71dBm
1.5 0
0.5 –2
0 –3
–80 –70 –60 –50 –40 –30 –20 –10 0 10 20 –80 –60 –40 –20 0 20
INPUT LEVEL – dBm INPUT LEVEL – dBm
Figure 7. VOUT vs. Input Level at 5 V Supply; Showing Figure 10. Log Conformance vs. Input Level at 100 MHz;
Intercept Adjustment Showing Response to Alternative Inputs
3.0 3
INT VOLTAGE
2.5 INT = 1.0V, INT = –86dBm 2
500MHz
ERROR – dB
VOUT – Volts
1.5 0
1.0 –1
100MHz
0.5 –2
INT VOLTAGE
INT = 2.0V, INT = –78dBm
0 –3
–80 –70 –60 –50 –40 –30 –20 –10 0 10 –90 –70 –50 –30 –10 10
INPUT LEVEL – dBm
INPUT LEVEL – dBm
Figure 8. VOUT vs. Input Level at 3 V Supply Using AD820 Figure 11. Log Conformance vs. Input at 100 MHz, 500 MHz;
as Buffer, Gain = +2; Showing Intercept Adjustment Input Driven Differentially Using Transformer
2.5 3
2
2.0
500MHz
1
ERROR – dB
VOUT – Volts
–1
10MHz
0.5
–2
100MHz @ +858C
0 –3
–80 –60 –40 –20 0 20 –70 –60 –50 –40 –30 –20 –10 0 10 20
INPUT LEVEL – dBm INPUT LEVEL – dBm
Figure 9. VOUT vs. Input Level at Three Temperatures Figure 12. Log Conformance vs. Input Level at 3 V Supply
(–40°C, +25 °C, +85 °C) Using AD820 as Buffer, Gain = +2
REV. A –5–
AD8307
2V
VOUT
Ch1 200mV Ch1 500mV
VOUT CH 1
CH 1
CH 1 GND
VENB
CH 2 INPUT SIGNAL
CH 2 CH 2 GND
GND
Ch2 2.00V 500ns Ch2 1.00V 200ns
Figure 13. Power-Up Response Time Figure 16. VOUT Rise Time
INPUT SIGNAL
VENB CH 2 CH 2 GND
CH 2 VOUT
CH 1
CH 1 GND
GND
Ch2 2.00V 500ns Ch2 1.00V 200ns
Figure 14. Power-Down Response Time Figure 17. Large Signal Response Time
Figure 15. Test Setup For Power-Up/Power-Down Figure 18. Test Setup For VOUT Pulse Response
Response Time
–6– REV. A
AD8307
LOG AMP THEORY continue indefinitely in both directions. The dotted line shows
Logarithmic amplifiers perform a more complex operation than that the effect of adding an offset voltage VSHIFT to the output is
that of classical linear amplifiers, and their circuitry is signifi- to lower the effective intercept voltage VX. Exactly the same
cantly different. A good grasp of what log amps do, and how alteration could be achieved raising the gain (or signal level)
they do it, will avoid many pitfalls in their application. The ahead of the log amp by the factor VSHIFT/VY. For example, if
essential purpose of a log amp is not to amplify, though amplifi- VY is 500 mV per decade (that is, 25 mV/dB, as for the AD8307),
cation is utilized to achieve the function. Rather, it is to com- an offset of +150 mV added to the output will appear to lower
press a signal of wide dynamic range to its decibel equivalent. It the intercept by two tenths of a decade, or 6 dB. Adding an
is thus a measurement device. A better term might be logarith- offset to the output is thus indistinguishable from applying an
mic converter, since its basic function is the conversion of a input level that is 6 dB higher.
signal from one domain of representation to another, via a precise The log amp function described by Equation 1 differs from that
nonlinear transformation. of a linear amplifier in that the incremental gain ∂VOUT/∂VIN is a
Logarithmic compression leads to situations that may be con- very strong function of the instantaneous value of VIN, as is
fusing or paradoxical. For example, a voltage offset added to apparent by calculating the derivative. For the case where the
the output of a log amp is equivalent to a gain increase ahead of logarithmic base is e, we have:
its input. In the usual case where all the variables are voltages,
and regardless of the particular structure, the relationship between ∂VOUT VY
= (2)
the variables can be expressed as: ∂VIN VIN
VOUT = VY log (VIN /VX) (1) That is, the incremental gain is inversely proportional to the
where: instantaneous value of the input voltage. This remains true for
VOUT is the output voltage, any logarithmic base, which is chosen as 10 for all decibel-
related purposes. It follows that a perfect log amp would be
VY is called the slope voltage; the logarithm is usually taken required to have infinite gain under classical small-signal (zero-
to base-ten (in which case VY is also the volts-per-decade), amplitude) conditions. Less ideally, this result indicates that,
VIN is the input voltage, whatever means are used to implement a log amp, accurate
and response under small-signal conditions (that is, at the lower end
of the dynamic range) demands the provision of a very high
VX is called the intercept voltage. gain-bandwidth product. A further consequence of this high
All log amps implicitly require two references, here VX and VY, gain is that, in the absence of an input signal, even very small
which determine the scaling of the circuit. The absolute accu- amounts of thermal noise at the input of a log amp will cause a
racy of a log amp cannot be any better than the accuracy of its finite output for zero input, resulting in the response line curving
scaling references. Equation 1 is mathematically incomplete in away from the ideal shown in Figure 19 toward a finite baseline,
representing the behavior of a demodulating log amp such as which can be either above or below the intercept. Note that the
the AD8307, where VIN has an alternating sign. However, the value given for this intercept may be an extrapolated value, in
basic principles are unaffected, and we can safely use this as our which case the output may not cross zero, or even reach it, as is
starting point in the analyses of log amp scaling which follow. the case for the AD8307.
While Equation 1 is fundamentally correct, a simpler formula is
VOUT
appropriate for specifying the calibration attributes of a log amp
5VY
like the AD8307, which demodulates a sine wave input:
4VY VOUT = VSLOPE (PIN – P0) (3)
VSHIFT
where:
3VY
LOWER INTERCEPT VOUT is the demodulated and filtered baseband (video or
2VY RSSI) output,
VSLOPE is the logarithmic slope, now expressed in volts/dB
VY
(typically between 15 and 30 mV/dB),
LOG VIN
VOUT = 0 PIN is the input power, expressed in decibels relative to some
VIN = 10–2VX VIN = VX VIN = 102VX VIN = 104VX reference power level,
–40dBc 0dBc +40dBc +80dBc
and
–2VY P0 is the logarithmic intercept, expressed in decibels relative
to the same reference level.
Figure 19. Ideal Log Amp Function
The most widely used reference in RF systems is decibels above
Figure 19 shows the input/output relationship of an ideal log 1 mW in 50 Ω, written dBm. Note that the quantity (PIN – P0) is
amp, conforming to Equation 1. The horizontal scale is loga- just dB. The logarithmic function disappears from the formula
rithmic and spans a wide dynamic range, shown here as over because the conversion has already been implicitly performed in
120 dB, or six decades. The output passes through zero (the stating the input in decibels. This is strictly a concession to popu-
log-intercept) at the unique value VIN = VX and would ideally lar convention: log amps manifestly do not respond to power
become negative for inputs below the intercept. In the ideal (tacitly, power absorbed at the input), but, rather, to input
case, the straight line describing VOUT for all values of VIN would
REV. A –7–
AD8307
voltage. The use of dBV (decibels with respect to 1 V rms) would in the case of the AD8307, VY is traceable to an on-chip band-
be more precise, though still incomplete, since waveform is gap reference, while VX is derived from the thermal voltage kT/q
involved, too. Since most users think about and specify RF and later temperature-corrected.
signals in terms of power—even more specifically, in dBm re 50 Ω Let the input of an N-cell cascade be VIN, and the final output
—we will use this convention in specifying the performance of VOUT. For small signals, the overall gain is simply AN. A six-
the AD8307. stage system in which A = 5 (14 dB) has an overall gain of
Progressive Compression 15,625 (84 dB). The importance of a very high small-signal gain
Most high speed high dynamic range log amps use a cascade of in implementing the logarithmic function has been noted; how-
nonlinear amplifier cells (Figure 20) to generate the logarithmic ever, this parameter is of only incidental interest in the design of
function from a series of contiguous segments, a type of piece- log amps.
wise-linear technique. This basic topology immediately opens From here onward, rather than considering gain, we will analyze
up the possibility of enormous gain-bandwidth products. For the overall nonlinear behavior of the cascade in response to a
example, the AD8307 employs six cells in its main signal path, simple dc input, corresponding to the VIN of Equation 1. For
each having a small-signal gain of 14.3 dB (×5.2) and a –3 dB very small inputs, the output from the first cell is V1 = AVIN;
bandwidth of about 900 MHz; the overall gain is about 20,000 from the second, V2 = A2 VIN, and so on, up to VN = AN VIN. At
(86 dB) and the overall bandwidth of the chain is some 500 MHz, a certain value of VIN, the input to the Nth cell, VN–1, is exactly
resulting in the incredible gain-bandwidth product (GBW) of equal to the knee voltage EK. Thus, VOUT = AEK and since there
10,000 GHz, about a million times that of a typical op amp. are N–1 cells of gain A ahead of this node, we can calculate that
This very high GBW is an essential prerequisite to accurate VIN = EK /AN–1. This unique situation corresponds to the lin-log
operation under small-signal conditions and at high frequencies. transition, labeled 1 on Figure 22. Below this input, the cascade
Equation 2 reminds us, however, that the incremental gain will of gain cells is acting as a simple linear amplifier, while for higher
decrease rapidly as VIN increases. The AD8307 continues to values of VIN, it enters into a series of segments which lie on a
exhibit an essentially logarithmic response down to inputs as logarithmic approximation (dotted line).
small as 50 µV at 500 MHz.
VX A A A A VW (4A-3) EK
(3A-2) EK
Figure 20. Cascade of Nonlinear Gain Cells (A-1) EK
To develop the theory, we will first consider a slightly different (2A-1) EK
scheme to that employed in the AD8307, but which is simpler
to explain and mathematically more straightforward to analyze. AEK RATIO
OF A
This approach is based on a nonlinear amplifier unit, which we LOG VIN
may call an A/1 cell, having the transfer characteristic shown in 0
Figure 21. The local small-signal gain ∂VOUT/∂VIN is A, main- EK/AN–1 EK/AN–2 EK/AN–3 EK/AN–4
tained for all inputs up to the knee voltage EK, above which the Figure 22. The First Three Transitions
incremental gain drops to unity. The function is symmetrical: the
same drop in gain occurs for instantaneous values of VIN less Continuing this analysis, we find that the next transition occurs
than –EK. The large-signal gain has a value of A for inputs in the when the input to the (N–1) stage just reaches EK; that is, when
range –EK ≤ VIN ≤ +EK, but falls asymptotically toward unity for VIN = EK /AN–2. The output of this stage is then exactly AEK,
very large inputs. In logarithmic amplifiers based on this ampli- and it is easily demonstrated (from the function shown in Figure
fier function, both the slope voltage and the intercept voltage 21) that the output of the final stage is (2A–1) EK (labeled ➁ on
must be traceable to the one reference voltage, EK. Therefore, in Figure 22). Thus, the output has changed by an amount (A–1)EK
this fundamental analysis, the calibration accuracy of the log amp for a change in VIN from EK /AN–1 to EK /AN–2, that is, a ratio
is dependent solely on this voltage. In practice, it is possible to change of A. At the next critical point, labeled ➂, we find the
separate the basic references used to determine VY and VX and input is again A times larger and VOUT has increased to (3A–2)EK,
that is, by another linear increment of (A–1)EK. Further analysis
shows that right up to the point where the input to the first cell
is above the knee voltage, VOUT changes by (A–1)EK for a ratio
change of A in VIN. This can be expressed as a certain fraction
of a decade, which is simply log10(A). For example, when A = 5
AEK a transition in the piecewise linear output function occurs at
OUTPUT
SLOPE = 1
A/1 regular intervals of 0.7 decade (that is, log10(A), or 14 dB divided
by 20 dB). This insight allows us to immediately write the Volts
SLOPE = A
per Decade scaling parameter, which is also the Scaling Voltage
VY, when using base-10 logarithms, as:
( A − 1)E
0
EK INPUT
Linear Change in VOUT K
VY = =
log ( A)
(4)
Decades Change in VIN 10
Figure 21. The A/1 Amplifier Function
–8– REV. A
AD8307
Note that only two design parameters are involved in determin-
A EK
ing VY, namely, the cell gain A and the knee voltage EK, while VY =
N, the number of stages, is unimportant in setting the slope of ( )
log 10 A (6)
the overall function. For A = 5 and EK = 100 mV, the slope
would be a rather awkward 572.3 mV per decade (28.6 mV/dB). Preference for the A/0 style of log amp, over one using A/1 cells,
A well designed log amp will have rational scaling parameters. stems from several considerations. The first is that an A/0 cell
can be very simple. In the AD8307 it is based on a bipolar-
The intercept voltage can be determined by using two pairs of
transistor differential pair, having resistive loads RL and an
transition points on the output function (consider Figure 22).
emitter current source, IE. This will exhibit an equivalent knee-
The result is:
voltage of EK = 2 kT/q and a small signal gain of A = IERL /EK.
EK The large signal transfer function is the hyperbolic tangent (see
VX = dotted line in Figure 23). This function is very precise, and the
A(
N +1/ ( A−1) ) (5)
deviation from an ideal A/0 form is not detrimental. In fact, the
For the case under consideration, using N = 6, we calculate rounded shoulders of the tanh function beneficially result in a
VZ = 4.28 µV. However, we need to be careful about the inter- lower ripple in the logarithmic conformance than that obtained
pretation of this parameter, since it was earlier defined as the using an ideal A/0 function.
input voltage at which the output passes through zero (see Fig- An amplifier built of these cells is entirely differential in struc-
ure 19). But clearly, in the absence of noise and offsets, the ture and can thus be rendered very insensitive to disturbances
output of the amplifier chain shown in Figure 21 can be zero on the supply lines and, with careful design, to temperature
when, and only when, VIN = 0. This anomaly is due to the finite variations. The output of each gain cell has an associated
gain of the cascaded amplifier, which results in a failure to maintain transconductance (gm) cell, which converts the differential out-
the logarithmic approximation below the lin-log transition (point ➀ put voltage of the cell to a pair of differential currents, which are
in Figure 22). Closer analysis shows that the voltage given by summed simply by connecting the outputs of all the gm (detec-
Equation 5 represents the extrapolated, rather than actual, tor) stages in parallel. The total current is then converted back
intercept. to a voltage by a transresistance stage, to generate the logarith-
Demodulating Log Amps mic output. This scheme is depicted, in single-sided form, in
Log amps based on a cascade of A/1 cells are useful in baseband Figure 24.
applications, because they do not demodulate their input signal. AVIN A2 VIN A3 VIN A4 VIN
However, baseband and demodulating log amps alike can be
made using a different type of amplifier stage, which we will call VIN A/0 A/0 A/0 A/0 VLIM
an A/0 cell. Its function differs from that of the A/1 cell in that
the gain above the knee voltage EK falls to zero, as shown by the gm gm gm gm gm
solid line in Figure 23. This is also known as the limiter func-
tion, and a chain of N such cells is often used to generate a IOUT
hard-limited output, in recovering the signal in FM and PM Figure 24. Log Amp Using A/0 Stages and Auxiliary Sum-
modes. ming Cells
The chief advantage of this approach is that the slope voltage
may now be decoupled from the knee-voltage EK = 2 kT/q,
SLOPE = 0 which is inherently PTAT. By contrast, the simple summation
AEK of the cell outputs would result in a very high temperature coef-
OUTPUT
REV. A –9–
AD8307
We can model these detectors as being essentially linear gm cells, Offset Control
but producing an output current independent of the sign of the In a monolithic log amp, direct-coupling between the stages is
voltage applied to the input of each cell. That is, they imple- used for several reasons. First, this avoids the use of coupling
ment the absolute-value function. Since the output from the capacitors, which may typically have a chip area equal to that of
later A/0 stages closely approximates an amplitude-symmetric a basic gain cell, thus considerably increasing die size. Second,
square wave for even moderate input levels (most stages of the the capacitor values predetermine the lowest frequency at which
amplifier chain operate in a limiting mode), the current output the log amp can operate; for moderate values, this may be as
from each detector is almost constant over each period of the high as 30 MHz, limiting the application range. Third, the para-
input. Somewhat earlier detectors stages produce a waveform sitic (back-plate) capacitance lowers the bandwidth of the cell,
having only very brief dropouts, while the detectors nearest the further limiting the applications.
input produce a low level almost-sinusoidal waveform at twice But the very high dc gain of a direct-coupled amplifier raises a
the input frequency. These aspects of the detector system result practical issue. An offset voltage in the early stages of the chain
in a signal that is easily filtered, resulting in low residual ripple is indistinguishable from a ‘real’ signal. If it were as high as, say,
on the output. 400 µV, it would be 18 dB larger than the smallest ac signal
Intercept Calibration (50 µV), potentially reducing the dynamic range by this amount.
All monolithic log amps from Analog Devices include accurate This problem is averted by using a global feedback path from
means to position the intercept voltage VX (or equivalent power the last stage to the first, which corrects this offset in a similar
for a demodulating log amp). Using the scheme shown in Figure fashion to the dc negative feedback applied around an op amp.
24, the basic value of the intercept level departs considerably The high frequency components of the signal must, of course,
from that predicted by the simpler analyses given earlier. How- be removed, to prevent a reduction of the HF gain in the for-
ever, the intrinsic intercept voltage is still proportional to EK, ward path.
which is PTAT (Equation 5). Recalling that the addition of an In the AD8307, this is achieved by an on-chip filter, providing
offset to the output produces an effect which is indistinguishable sufficient suppression of HF feedback to allow operation above
from a change in the position of the intercept, we can cancel the 1 MHz. To extend the range below this frequency, an external
left-right motion of VX resulting from the temperature variation of capacitor may be added. This permits the high pass corner to be
EK by adding an offset having the required temperature behavior. lowered to audio frequencies using a capacitor of modest value.
The precise temperature-shaping of the intercept-positioning Note that this capacitor has no effect on the minimum signal
offset results in a log amp having stable scaling parameters, frequency for input levels above the offset voltage: this extends
making it a true measurement device, for example, as a cali- down to dc (for a signal applied directly to the input pins). The
brated Received Signal Strength Indicator (RSSI). In this appli- offset voltage will vary from part to part; some will exhibit essen-
cation, one is more interested in the value of the output for an tially stable offsets of under 100 µV, without the benefit of an
input waveform which is invariably sinusoidal. The input level offset adjustment.
may alternatively be stated as an equivalent power, in dBm, but Extension of Range
here we must step carefully. It is essential to know the load The theoretical dynamic range for the basic log amp shown in
impedance in which this power is presumed to be measured. Figure 24 is AN. For A = 5.2 (14.3 dB) and N = 6, it is 20,000
In RF practice, it is generally safe to assume a reference imped- or 86 dB. The actual lower end of the dynamic range is largely
ance of 50 Ω, in which 0 dBm (1 mW) corresponds to a sinusoi- determined by the thermal noise floor, measured at the input of
dal amplitude of 316.2 mV (223.6 mV rms). The intercept may the chain of amplifiers. The upper end of the range is extended
likewise be specified in dBm. For the AD8307, it is positioned upward by the addition of top-end detectors. The input signal is
at –84 dBm, corresponding to a sine amplitude of 20 µV. It is applied to a tapped attenuator, and progressively smaller signals
important to bear in mind that log amps do not respond to are applied to three passive rectifying gm cells whose outputs are
power, but to the voltage applied to their input. summed with those of the main detectors. With care in design,
The AD8307 presents a nominal input impedance much higher the extension to the dynamic range can be seamless over the full
than 50 Ω (typically 1.1 kΩ at low frequencies). A simple input frequency range. For the AD8307 it amounts to a further 27 dB.
matching network can considerably improve the sensitivity of The total dynamic range is thus theoretically 113 dB. The speci-
this type of log amp. This will increase the voltage applied to the fied range of 90 dB (–74 dBm to +16 dBm) is that for high
input and thus alter the intercept. For a 50 Ω match, the voltage accuracy, calibrated operation, and includes the low end degra-
gain is 4.8 and the whole dynamic range moves down by 13.6 dB dation due to thermal noise, and the top end reduction due to
(see Figure 33). Note that the effective intercept is a function of voltage limitations. The additional stages are not, however,
waveform. For example, a square-wave input will read 6 dB redundant, but are needed to maintain accurate logarithmic
higher than a sine wave of the same amplitude, and a Gaussian conformance over the central region of the dynamic range, and
noise input 0.5 dB higher than a sine wave of the same rms in extending the usable range considerably beyond the specified
value. range. In applications where log-conformance is less demand-
ing, the AD8307 can provide over 95 dB of range.
–10– REV. A
AD8307
PRODUCT OVERVIEW junction capacitances associated with them, due to active
The AD8307 comprises six main amplifier/limiter stages, each devices or ESD protection; these may be neither accurate nor
having a gain of 14.3 dB and small signal bandwidth of 900 MHz; stable. Component numbering in each of these interface dia-
the overall gain is 86 dB with a –3 dB bandwidth of 500 MHz. grams is local.
These six cells, and their associated gm-styled full-wave detec- Enable Interface
tors, handle the lower two-thirds of the dynamic range. Three The chip-enable interface is shown in Figure 26. The currents
top-end detectors, placed at 14.3 dB taps on a passive attenua- in the diode-connected transistors control the turn-on and turn-
tor, handle the upper third of the 90 dB range. Biasing for these off states of the bandgap reference and the bias generator, and
cells is provided by two references: one determines their gain; are a maximum of 100 µA when Pin 6 is taken to 5 V, under
the other is a bandgap circuit that determines the logarithmic worst case conditions. Left unconnected, or at a voltage below
slope and stabilizes it against supply- and temperature-variations. 1 V, the AD8307 will be disabled and consume a sleep current
The AD8307 may be enabled/disabled by a CMOS-compatible of under 50 µA; tied to the supply, or a voltage above 2 V, it will
level at ENB (Pin 6). The first amplifier stage provides a low be fully enabled. The internal bias circuitry is very fast (typically
voltage noise spectral density (1.5 nV/√Hz). <100 ns for either OFF or ON), and in practice the latency
The differential current-mode outputs of the nine detectors are period before the log amp exhibits its full dynamic range is more
summed and then converted to single-sided form in the output likely to be limited by factors relating to the use of ac coupling
stage, nominally scaled 2 µA/dB. The logarithmic output voltage at the input or the settling of the offset-control loop (see follow-
is developed by applying this current to an on-chip 12.5 kΩ ing sections).
resistor, resulting in a logarithmic slope of 25 mV/dB (i.e.,
500 mV/decade) at OUT. This voltage is not buffered, allowing
AD8307
the use of a variety of special output interfaces, including the 40kV
addition of post-demodulation filtering. The last detector stage ENB
TO BIAS
includes a modification to temperature-stabilize the log intercept, STAGES
REV. A –11–
AD8307
In most applications, the signal will be single-sided, and may be The offset feedback is limited to a range ± 400 µV; signals larger
applied to either Pin 1 or Pin 8, with the other pin ac-coupled to than this override the offset control loop, which only impacts
ground. Under these conditions, the largest input signal that can performance for very small inputs. An external capacitor re-
be handled by the AD8307 is +10 dBm (sine amplitude of ± 1 V) duces the high pass corner to arbitrarily low frequencies; using
when operating from a 3 V supply; a +16 dBm may be handled 1 µF this corner is below 10 Hz. All ADI log amps use an offset-
using a 5 V supply. The full 16 dBm may be achieved for sup- nulling loop; the AD8307 differs in using this single-sided form.
plies down to 2.7 V, using a fully balanced drive. For frequencies Output Interface
above about 10 MHz, this is most easily achieved using a matching The outputs from the nine detectors are differential currents,
network (see below). Using such a network, having an inductor having an average value that is dependent on the signal input
at the input, the input transient noted above is eliminated. Occa- level, plus a fluctuation at twice the input frequency. The cur-
sionally, it may be desirable to use the dc-coupled potential of rents are summed at nodes LGP and LGN in Figure 29. Fur-
the AD8307. The main challenge here is to present signals to ther currents are added at these nodes, to position the intercept,
the log amp at the elevated common-mode input level, requiring by slightly raising the output for zero input, and to provide
the use of low noise, low offset buffer amplifiers. Using dual temperature compensation. Since the AD8307 is not laser-
supplies of ±3 V, the input pins may operate at ground potential. trimmed, there is a small uncertainty in both the log slope and
Offset Interface the log intercept. These scaling parameters may be adjusted (see
The input-referred dc offsets in the signal path are nulled via the below).
interface associated with Pin 3, shown in Figure 28. Q1 and Q2 For zero-signal conditions, all the detector output currents are
are the first stage input transistors, with their corresponding equal. For a finite input, of either polarity, their difference is
load resistors (125 Ω). Q3 and Q4 generate small currents, converted by the output interface to a single-sided unipolar
which can introduce a dc offset into the signal path. When the current nominally scaled 2 µA/dB (40 µA/decade), at the output
voltage on OFS is at about 1.5 V, these currents are equal, and pin OUT. An on-chip 12.5 kΩ resistor, R1, converts this cur-
nominally 16 µA. When OFS is taken to ground, Q4 is off and rent to a voltage of 25 mV/dB. C1 and C2 are effectively in
the effect of the current in Q3 is to generate an offset voltage of shunt with R1 and form a low-pass filter pole, with a corner
16 µA × 125 Ω = 2 mV. Since the first stage gain is ×5, this is frequency of about 5 MHz. The pulse response settles to within
equivalent to a input offset (INP to INM) of 400 µV. When 1% of the final value within 300 ns. This integral low-pass filter
OFS is taken to its most positive value, the input-referred offset provides adequate smoothing in many IF applications. At
is reversed, to –400 µV. If true dc-coupling is needed, down to 10.7 MHz, the 2f ripple is 12.5 mV in amplitude, equivalent to
very small inputs, this automatic loop must be disabled, and the ± 0.5 dB, and only 0.5 mV (± 0.02 dB) at f = 50 MHz. A filter
residual offset eliminated using a manual adjustment, as explained capacitor CFLT added from OUT to ground will lower this cor-
in the next section. ner frequency. Using 1 µF, the ripple is maintained to less than
In normal operation, however, using an ac-coupled input signal, ± 0.5 dB down to input frequencies of 100 Hz. Note that COFS
the OFS pin should be left open. Any residual input-offset volt- (above) should also be increased in low frequency applications,
age is then automatically nulled by the action of the feedback and will typically be made equal to CFLT.
loop. The gm cell, which is gated off when the chip is disabled, It may be desirable to increase the speed of the output response,
converts any output offset (sensed at a point near the end of the with the penalty of increased ripple. One way to do this is sim-
cascade of amplifiers) to a current. This is integrated by the on- ply by connecting a shunt load resistor from OUT to ground,
chip capacitor CHP, plus any added external capacitance COFS, which raises the low pass corner frequency. This also alters the
so as to generate an error voltage, which is applied back to the logarithmic slope, for example to 7.5 mV/dB using a 5.36 kΩ
input stage in the polarity needed to null the output offset. From resistor, while reducing the 10%-90% rise time to 25 ns. The
a small-signal perspective, this feedback alters the response of ripple amplitude for 50 MHz input remains 0.5 mV, but this is
the amplifier, which, rather than behaving as a fully dc-coupled now equivalent to ± 0.07 dB. If a negative supply is available,
system, now exhibits a zero in its ac transfer function, resulting the output pin may be connected directly to the summing
in a closed-loop high-pass corner at about 700 kHz. node of an external op amp connected as an inverting-mode
transresistance stage.
VPS
125V
INPUT VPS
STAGE
MAIN GAIN TO LAST 3pF 1.25kV 1.25kV
STAGES DETECTOR 8.25kV
Q1 LGP
FROM ALL 400mV
16mA AT
Q2 BALANCE S gm DETECTORS 60kV
LGM INT
1.25kV 1.25kV
AVERAGE 2mA/dB
OFS ERROR 0-220mA
BIAS, 1.2V
Q3 Q4 CURRENT
–12– REV. A
AD8307
USING THE AD8307 Figure 31 shows the output versus the input level, in dBm when
The AD8307 has very high gain and a bandwidth from dc to driven from a terminated 50 Ω generator, for sine inputs at
over 1 GHz, at which frequency the gain of the main path is still 10 MHz, 100 MHz and 500 MHz; Figure 32 shows the typical
over 60 dB. Consequently, it is susceptible to all signals within logarithmic conformance under the same conditions. Note that
this very broad frequency range that find their way to the input +10 dBm corresponds to a sine amplitude of 1 V, equivalent to
terminals. It is important to remember that these are quite indis- an rms power of 10 mW in a 50 Ω termination. But if the termi-
tinguishable from the “wanted” signal, and will have the effect nation resistor is omitted, the input power is negligible. The use
of raising the apparent noise floor (that is, lowering the useful of dBm to define input level therefore needs to be considered
dynamic range). For example, while the signal of interest may carefully in connection with the AD8307.
be an IF of 50 MHz, any of the following could easily be larger
3
than the IF signal at the lower extremities of its dynamic range:
60 Hz hum, picked up due to poor grounding techniques; spuri-
ous coupling from a digital clock source on the same PC board; 2.5
should be added at the input for the same reason. For the case 1
REV. A –13–
AD8307
Narrow-Band Matching Table I. Narrow-Band Matching Values
Transformer coupling is useful in broadband applications. How-
ever, a magnetically-coupled transformer may not be convenient FC ZIN C1 C2 LM Voltage
in some situations. At high frequencies, it is often preferable to MHz Ω pF pF nH Gain (dB)
use a narrow-band matching network, as shown in Figure 33. 10 45 160 150 3300 13.3
This has several advantages. The same voltage gain is achieved, 20 44 82 75 1600 13.4
providing increased sensitivity, but now a measure of selectively 50 46 30 27 680 13.4
is also introduced. The component count is low: two capacitors 100 50 15 13 330 13.4
150 57 10 8.2 220 13.2
and an inexpensive chip inductor. Further, by making these 200 57 7.5 6.8 150 12.8
capacitors unequal the amplitudes at INP and INM may be 250 50 6.2 5.6 100 12.3
equalized when driving from a single-sided source; that is, the 500 54 3.9 3.3 39 10.9
network also serves as a balun. Figure 34 shows the response for 10 103 100 91 5600 10.4
a center frequency of 100 MHz; note the very high attenuation 20 102 51 43 2700 10.4
at low frequencies. The high-frequency attenuation is due to the 50 99 22 18 1000 10.6
input capacitance of the log amp. 100 98 11 9.1 430 10.5
150 101 7.5 6.2 260 10.3
0.1mF 4.7V
200 95 5.6 4.7 180 10.3
VP, 2.7V – 5.5V 250 92 4.3 3.9 130 9.9
AT 8mA 500 114 2.2 2.0 47 6.8
50V INPUT C1
–88dBm TO NC
+3dBm Slope and Intercept Adjustments
INP VPS ENB INT Where higher calibration accuracy is needed, the adjustments
LM AD8307 shown in Figure 35 can be used, either singly or in combination.
ZIN = 50V
INM COM OFS OUT The log slope is lowered to 20 mV/dB by shunting the nominally
NC OUTPUT 12.5 kΩ on-chip load resistor (see Figure 29) with 50 kΩ,
C2
25mV/dB adjusted by VR1. The calibration range is ± 10% (18 mV/dB to
NC = NO CONNECT 22 mV/dB), including full allowance for the variability in the
Figure 33. High Frequency Input Matching Network value of the internal load. The adjustment may be made by
alternately applying two input levels, provided by an accurate
14 signal generator, spaced over the central portion of the log amp’s
13 dynamic range, for example –60 dBm and 0 dBm. An AM-
12
modulated signal, at the center of the dynamic range, can also
11
GAIN be used. For a modulation depth M, expressed as a fraction, the
10
9
decibel range between the peaks and troughs over one cycle of
8 the modulation period is given by:
DECIIBELS
7
1+ M
6 ∆ dB = 20 log 10 (7)
5 1− M
4
3 For example, using an rms signal level of –40 dBm with a 70%
INPUT
2 modulation depth (M = 0.7), the decibel range is 15 dB, as the
1 signal varies from –47.5 dBm to –32.5 dBm.
The log intercept is adjustable over a ± 3 dB range, which is
0
–1
60 70 80 90 100 110 120 130 140 150 sufficient to absorb the worst-case intercept error in the AD8307
FREQUENCY – MHz
plus some system-level errors. For greater range, set RS to zero.
Figure 34. Response of 100 MHz Matching Network VR2 is adjusted while applying an accurately known CW signal
near the lower end of the dynamic range, in order to minimize
the effect of any residual uncertainty in the slope. For example,
Table I provides solutions for a variety of center frequencies FC
and matching impedances ZIN of nominally 50 Ω and 100 Ω. to position the intercept to –80 dBm, a test level of –65 dBm
may be applied and VR2 adjusted to produce a dc output of
The unequal capacitor values were chosen to provide a well-
15 dB above zero at 25 mV/dB, which is +0.3 V.
balanced differential drive, and also to allow better centering of
the frequency response peak when using standard value compo- 0.1mF
4.7V
VP, 2.7V – 5.5V
nents; this generally results in a ZIN that is not exact. The full VR2
RS AT 8mA
AD8307 HF input impedance and the inductor losses were C1 = CC
50kV
REV. A –15–
AD8307
1 W to 1 kW 50 ⍀ Power Meter The AD603 has a very low input referred noise: 1.3 nV/√Hz at
The front-end adaptation shown in Figure 39 provides the mea- its 100-Ω input, or 0.9 nV/√Hz when matched to 50 Ω, equivalent
surement of power being delivered from a transmitter final am- to 0.4 µV rms, or –115 dBm, in a 200 kHz bandwidth. It is also
plifier to an antenna. The range has been set to cover the power capable of handling inputs in excess of 1.4 V rms, or +16 dBm.
range –30 dBm (7.07 mV rms, or 1 µW) to +60 dBm (223 V rms, It is thus able to cope with a dynamic range of over 130 dB in
or 1 kW). A nominal voltage attenuation ratio of 158:1 (44 dB) is this particular bandwidth.
used; thus the intercept is moved from –84 dBm to –40 dBm and Now, if the gain control voltage for the X-AMP is derived from
the AD8307, scaled 0.25 V/decade of power, will now read 1.5 V the output of the AD8307, the effect will be to raise the gain of
for a power level of 100 mW, 2.0 V at 10 W and 2.5 V at 1 kW. this front-end stage when the signal is small and lower it when it
The general expression is: is large, but without altering the fundamental logarithmic nature
P (dBm) = 40 (VOUT – 1) of the response. This gain range is 40 dB, which, combined with
the 90 dB range of the AD8307, again corresponds to a 130 dB
The required attenuation could be implemented using a capaci- range.
tive divider, providing a very low input capacitance, but it is
difficult to ensure accurate values of small capacitors. A better VP , +5V
50V R2 R1
approach is to use a resistive divider, taking the required precau- INPUT 28kV 187kV
BANDPASS 4.7V
FILTER* 0.1mF
tions to minimize spurious coupling into the AD8307 by placing –105dBm
TO
0.65V
it in a shielded box, with the input resistor passing through a +15dBm
NC
hole in this box, as indicated in the figure. The coupling capaci- GPOS VPOS R3
tors shown here are suitable for f ≥ 10 MHz. A capacitor may be L1
750nH
330V INP VPS ENB INT
GNEG VOUT R4 AD8307
added across the input pins of the AD8307 to reduce the re- AD603 464V INM COM OFS OUT
sponse to spurious HF signals which, as already noted, extends C1
VINP VNEG
VR1
to over 1 GHz. 150pF 5kV NC 0.3V
COMM FDBK TO
INT 1nF
68dB 2.3V
The mismatch caused by the loading of this resistor will be R7
R6
trivial; only 0.05% of the power delivered to the load will be VN , –5V 80.6kV
20kV
absorbed by the measurement system, a maximum of 500 mW R5 0.15V TO 1.15V OUTPUT
at 1 kW. The post-demodulation filtering and slope-calibration 100kV 10mV/dB
* E.G., MURATA SFE10.7MS2G-A
arrangements should be chosen from other applications described NC = NO CONNECT
here, to meet the particular system requirements. The 1 nF
Figure 40. 120 dB Measurement System
capacitor lowers the risk of HF signals entering the AD8307 via
the load. Figure 40 shows how these two parts can work together to pro-
vide state-of-the-art IF measurements in applications such as
TO spectrum/ network analyzers and other high dynamic range
ANTENNA
instrumentation. To understand the operation, note first that
100kV
0.1mF
the AD8307 is used to generate an output of about 0.3 V to
1/2W VP
22V
+5V
2.3 V. This 2 V span is divided by 2 in R5/R6/R7 to provide the
51pF
NC
1 V span needed by the AD603 to vary its gain by 40 dB. Note
LEAD-
that an increase in the positive voltage applied at GNEG (Pin 2)
VR1
2kV
INP VPS ENB INT THROUGH lowers the gain. This feedback network is tapped to provide a
INT 63dB AD8307 CAPACITORS,
1nF convenient 10 mV/dB scaling at the output node, which may be
INM COM OFS OUT
50V INPUT
FROM P.A.
604V buffered if necessary.
2kV
1mW TO NC VOUT
1kW 51pF OUTPUT
The center of the voltage range fed back to the AD603 is 650 mV
1nF
and the ± 20 dB gain range is centered by R1/R2. Note that the
NC = NO CONNECT
intercept calibration of this system benefits from the use of a
well regulated 5 V supply. To absorb the insertion loss of the
Figure 39. 1 µ W to 1 kW 50-Ω Power Meter filter and center the full dynamic range, the intercept is adjusted
Measurement System with 120 dB Dynamic Range by varying the maximum gain of the AD603, using VR1.
The dynamic range of the AD8307 can be extended further— Figure 41 shows the AD8307 output over the range –120 dBm
from 90 dB to over 120 dB—by the addition of an X-AMP™ to +20 dBm and the deviation from an ideal logarithmic re-
such as the AD603. This type of variable gain amplifier exhibits sponse. The dotted line shows the increase in the noise floor
a very exact exponential gain control characteristic, which is that results when the filter is omitted; the decibel difference is
another way of stating that the gain varies by a constant number about 10log10(50/0.2) or 24 dB, assuming a 50 MHz band-
of decibels for a given change in the control voltage. For the width from the AD603. An L-C filter may be used in place of
AD603, this scaling factor is 40 dB/V, or 25 mV/dB. It will be the ceramic filter used in this example.
apparent that this property of a linear-in-dB response is charac-
teristic of log amps; indeed, the AD8307 exhibits the same
scaling factor.
–16– REV. A
AD8307
2.50 is 125 ms. (See also Figure 38 for a more elaborate filter). Finally,
2.25 to improve the law-conformance at very low signal levels and at
2.00
low frequencies, C4 has been added to the offset compensation
WITHOUT
FILTER
loop.
1.75 2
+5V
ERROR – dB
1.50 1
VOUT – Volts
4.7V
1.25 0 0.1mF
C1 R1
1.00 –1 10mF 5kV
ERROR VIN NC
(WITH FILTER)
0.75 –2 0.5mV FOR SLOPE AND
TO 20V INP VPS ENB INT INTERCEPT ADJUSTMENTS
0.50 SINE C3 SEE FIGURE 35
WITH FILTER AD8307
AMPLITUDE 750pF
0.25 INM COM OFS OUT
0 VOUT
–100 –80 –60 –40 –20 0 20 25mV/dB
C2 R2 C4 C5
INPUT LEVEL – dBm 5kV
10mF 1mF 1mF NC = NO CONNECT
Figure 41. Results for 120 dB Measurement System
Operation at Low Frequencies Figure 42. Connections for Low Frequency Operation
The AD8307 provides excellent logarithmic conformance at DC-Coupled Applications
signal frequencies that may be arbitrarily low, depending only It may occasionally be necessary to provide response to dc in-
on the values used for the input coupling capacitors. It may also puts. Since the AD8307 is internally dc-coupled, there is no
be desirable to add a low-pass input filter in order to desensitize fundamental reason why this is precluded. However, there is a
the log amp to HF signals. Figure 42 shows a simple arrange- practical constraint, which is that its inputs must be positioned
ment, providing coupling with an attenuation of 20 dB; the about 2 V above the COM potential for proper biasing of the
intercept is shifted up by this attenuation, from –84 dBm to first stage. If it happens that the source is a differential signal at
–64 dBm, and the input range is now 0.5 mV to 20 V (sine this level, it may be directly connected to the input. For ex-
amplitude). ample, a microwave detector can be ac-coupled at its RF input
A high pass 3 dB corner frequency of nominally 3 Hz is set by and its baseband load then automatically provided by the “float-
the 10 µF coupling capacitors C1 and C2, which are preferably ing” RIN and CIN of the AD8307, at about VP/2.
tantalum electrolytics (note the polarity) and a low pass 3 dB Usually, the source will be a single-sided ground-referenced
corner frequency of 200 kHz (set by C3 and the effective resis- signal, and it will thus be necessary to provide a negative supply
tance at the input of 1 kΩ). The –1% amplitude error points for the AD8307. This can be achieved as shown in Figure 43.
occur at 20 Hz and 30 kHz. These are readily altered to suit The output is now referenced to this negative supply, and it is
other applications by simple scaling. When C3 is zero, the low necessary to provide an output interface that performs a differ-
pass corner is at 200 MHz. Note that the lower end of the dy- ential-to-single-sided conversion. This is the purpose of the
namic range is improved by this capacitor, which provides es- AD830. The slope may be arranged to be 20 mV/dB, when the
sentially an HF short circuit at the input, thus significantly output ideally runs from zero, for a dc input of 10 µV, to +2.2 V
lowering the wideband noise; the noise reduction is about 2 dB for an input of 4 V. The AD8307 is fundamentally insensitive to
compared to the case when the AD8307 is driven from a 50 Ω the sign of the input signal, but with this biasing scheme, the
source. maximum negative input is constrained to about –1.5 V. The
To ensure that the output is free of post-demodulation ripple, it transfer function after trimming and with R7 = 0, is
is necessary to lower the low-pass filter time-constant. This is VOUT = (0.4 V) log10 (VIN /10 µV)
provided by C5; with the value shown, the output time-constant
R1
4.7V +5V FOR 20mV/dB
+5V +10V FOR 50mV/dB
C1 +15V FOR 100mV/dB
0.1mF VR2
VOUT
50kV –5V
R2 R5
3.3kV INP VPS ENB INT * VP INT NC VN
VIN AD830
C2 AD8307 * 51kV FOR R7
1mF INM COM OFS OUT 20mV/dB X1 X2 Y1 Y2
TEMP 5k FOR
100mV/dB R7,R8:
SEE TEXT
20mV/dB
R6
AD589 VR1 R8
Q1 32.4kV
2kV
2N3904 C3 VR3 R9
R3
0.1mF 50kV 250V
1kV –5V
–2V NC = NO CONNECT
REV. A –17–
AD8307
The intercept can be raised, for example, to 100 µV, with the requires adjusting the output to 0.68 V; for the 100 mV/dB
rationale that the dc precision does not warrant operation in the scaling, this becomes 3.4 V. If a 100 µV intercept is preferred
first decade (from 10 µV–100 µV). Likewise, the slope can be (usefully lowering the maximum output voltage), these become
raised to 50 mV/dB, using R7 = 3 kΩ, R8 = 2 kΩ, or to 100 mV/ 0.28 V and 1.4 V respectively.
dB, to simplify decibel measurements on a DVM, using R7 = Finally, the slope must be adjusted. This can be performed by
8 kΩ, R8 = 2 kΩ, which raises the maximum output to +11 V, applying a low frequency square wave to the main input, having
thus requiring a +15 V supply for the AD830. The output may precisely determined upper and lower voltage levels, provided
be made to swing in a negative direction by simply reversing by a programmable waveform generator. A suitable choice is a
Pins 1 and 2. Low-pass filtering capacitor C3 sets the output 100 Hz square wave with levels of 10 mV and 1 V. The output
rise time to about 1 ms. will be a low-pass filtered square wave, and its amplitude should
6.0
be 0.8 V, for 20 mV/dB scaling, or 4 V for 100 mV/dB scaling.
5.5 Operation Above 500 MHz
5.0 The AD8307 is not intended for use above 500 MHz. However,
4.5 it does provide useful performance at higher frequencies.
4.0 1.0 Figure 45 shows a plot of the logarithmic output of the AD8307
3.5 0.5
for an input frequency of 900 MHz. The device shows good
ERROR – dB
VOUT – V
1.0 2
0.5 1.8
0
10m 100m 1m 10m 100m 1 10 1.6
VIN
1.4
1.2
the DC-Coupled AD8307 at 50 mV/dB 1
Figure 44 shows the output and the law-conformance error in 0.8
the absence of noise and input offset, for the 50 mV/dB option.
0.6
Note in passing that the error ripple for dc excitation is about
twice that for the more usual sinusoidal excitation. In practice, 0.4
both the noise and the internal offset voltage will degrade the 0.2
accuracy in the first decade of the dynamic range. The latter is
0
now manually nulled, by VR1, using a simple method that en- –60 –50 –40 –30 –20 –10 0 10
PIN – dBm
sures very low residual offsets.
A temporary ac signal, typically a sine wave of 100 mV in ampli- Figure 45. Output vs. Input Level for a 900 MHz Input Signal
tude at a frequency of about 100 Hz, is applied via the capacitor Evaluation Board
at node TEMP; this has the effect of disturbing the offset-nulling An evaluation board, carefully laid out and tested to demon-
voltage. The output voltage is then viewed on an oscilloscope strate the specified high speed performance of the AD8307 is
and VR1 is adjusted until the peaks of the (frequency-doubled) available. Figure 46 shows the schematic of the evaluation board.
waveform are exactly equal in amplitude. This procedure can For ordering information, please refer to the Ordering Guide.
provide an input null down to about 10 µV; the temperature
Figures 47 and 49 show the component-side and solder-side
drift is very low, though not specified since the AD8307 is not
silkscreens of the evaluation board. The component-side and
principally designed to operate as a baseband log amp, and in ac
solder-side layouts are shown in Figures 48 and 50.
modes this offset is continuously and automatically nulled.
For connection to external instruments, side-launched SMA
Next, it is necessary to set the intercept. This is the purpose of
type connectors are provided. Space is also provided on the
VR2, which should be adjusted after VR1. The simplest method
board for the installation of SMB or SMC type connectors.
is to short the input and adjust VR2 for an output of 0.3 V,
When using the top-mount SMA connector, it is recommended
corresponding to the noise floor. For more exacting applica-
that the stripline on the outside 1/8" of the board edge be re-
tions, a temporary sinusoidal test voltage of 1 mV in amplitude,
moved (i.e., scraped using a blade) as this unused stripline acts
at about 1 MHz, should be applied, which may require the use
as an open stub, which could degrade the overall performance of
of a temporary onboard input attenuator. For 20 mV/dB scaling,
the evaluation board/device combination at high frequencies.
a 10 µV dc intercept (which is 6 dB below the ac intercept)
–18– REV. A
AD8307
+VS
C3 C4 A B
10mF 0.1mF
LK1
INPUT R2
C2 50kV
0.1mF LK2
INP VPS ENB INT
R1
52.3V AD8307
C1 INM COM OFS OUT
0.1mF
LOG
OUTPUT
LK4 LK3
LK5 C5 R3
0.1mF 12.5kV
C6
1nF
REV. A –19–
AD8307
Table II. Evaluation Board Link Options
C3065a–0–3/99
LK2 Open Intercept Adjust. When Pin LK2 is left open, the AD8307 has a nominal logarithmic
intercept of –84 dBm. Putting LK2 in place connects the wiper of potentiometer R2 to Pin 5
(INT). By varying the voltage on INT, the position of the intercept can be adjusted. The inter-
cept varies by about 8 dB/V.
LK3 Open Slope Adjust. When this link is open, the nominal slope of the output is 25 mV/dB. Putting this
link in place connects a ground referenced 12.5 kΩ load resistor (R3) to the logarithmic out-
put. The parallel combination of this resistor and an internal 12.5 kΩ resistor reduces the
logarithmic slope to 12.5 mV/dB. R3 may be adjusted for other scaling factors.
LK4 Open Corner Frequency of Low-Pass Demodulating Filter. When this link is open, the corner fre-
quency of the low pass post demodulation filter has a nominal value of 4 MHz. This is set by
an on-chip load impedance of 12.5 kΩ and an on-chip load capacitance of 3.5 pF. The load
capacitance (e.g., of an oscilloscope probe) must be added to this capacitance, and will lower
the internal video bandwidth, to a nominal 1 MHz for a total of 13.5 pF. Putting LK4 in place
connects an external load capacitance (C5) of 0.1 µF to the output, reducing the corner fre-
quency of the low-pass filter to about 125 Hz. For large values of C5, the corner frequency can
be calculated using the equation, f ≈ 12.7 Hz/C5 (µF).
LK5 Open Offset Control Loop. When this link is open, the internal offset control loop gives the circuit an
overall high pass corner frequency of about 1 MHz. With LK5 link in place, a 1 nF capacitor
(C6) is connected to the OFS pin, reducing the high pass corner frequency to allow accurate
operation down to 10 kHz. To reduce the minimum operational frequency even further, a
larger capacitor can replace C6 (e.g., a 1 µF capacitor allows operation down to 10 Hz). Note
that that external capacitor C6 has no effect on the minimum signal frequency for input levels
that exceed the offset voltage (typically 400 µV). The range for such signals extends down to dc
(for signals applied directly to the input pins).
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8 5
8 5
0.280 (7.11) 0.1574 (4.00) 0.2440 (6.20)
0.240 (6.10) 1 4
0.1497 (3.80) 0.2284 (5.80)
PRINTED IN U.S.A.
1 4 0.325 (8.25)
0.300 (7.62)
PIN 1 0.060 (1.52)
0.015 (0.38) PIN 1 0.0688 (1.75) 0.0196 (0.50)
0.210 (5.33) 0.195 (4.95) 3 458
0.0098 (0.25) 0.0532 (1.35) 0.0099 (0.25)
MAX 0.115 (2.93)
0.130 0.0040 (0.10)
0.160 (4.06) (3.30)
0.115 (2.93) MIN
0.015 (0.381) 88
0.022 (0.558) 0.100 0.070 (1.77) SEATING 0.0500 0.0192 (0.49)
PLANE 0.008 (0.204) SEATING (1.27) 08
0.0098 (0.25) 0.0500 (1.27)
0.014 (0.356) (2.54) 0.045 (1.15) PLANE BSC 0.0138 (0.35) 0.0075 (0.19)
BSC 0.0160 (0.41)
–20– REV. A