AN4277

Application note
Using STM32 device PWM shut-down features
for motor control and digital power conversion

Introduction
The purpose of this application note is to describe the STM32 device timer break feature. It
details its use with other STM32 internal resources for an over-current and over-voltage
protection. Namely, in applications related to the motor control and the digital power
conversion such as lighting, SMPS and induction heating.
This application note:
• provides an overview of the timer break feature
• details how the timer break input is connected to different break sources
• enumerates the different break event sources
• provides some scenarios of the PWM output signal response to break events coming from
an internal source, an external source or a combination of both internal and external break
signals
• shows how to implement over-current and over-voltage protections using the timer break
feature and other embedded peripherals (such as, comparators and DAC).
This document applies to the products listed in Table 1.

Table 1. Applicable products

Type Product series

STM32F0 series, STM32F1 series, STM32F2 series, STM32F3 series,

STM32F4 series, STM32F7 series, STM32L4 series, STM32U5 series,
Microcontrollers
STM32L5 series, STM32G0 series, STM32G4 series, STM32C0 series,
STM32H7 series, STM32H5 series, STM32WB series, STM32WL series

January 2023 AN4277 Rev 6 1/32

www.st.com 1
Contents AN4277

Contents

1 General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Break function overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4 Break implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 TIM1/8/20 break implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2 TIM15/16/17 break implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5 Break sources summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7 Using the break function with other MCU resources . . . . . . . . . . . . . . 22

7.1 Break function used for over-current protection . . . . . . . . . . . . . . . . . . . . 22
7.2 Break function used for over-voltage protection . . . . . . . . . . . . . . . . . . . . 23
7.3 Using an external emergency signal together with the
internal comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.4 Filtering the break input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.5 Locking the selected configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Appendix A How to use the DAC to define thresholds . . . . . . . . . . . . . . . . . . . . 29

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2/32 AN4277 Rev 6

AN4277 List of tables

List of tables

Table 1. Applicable products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Reference documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Timers and break input availability in STM32 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Comparator peripherals availability per STM32 device . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. Break input sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 6. Scenarios of PWM output status in response to internal/external break events. . . . . . . . . 19
Table 7. Comparator output connected internally to break inputs . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 8. Comparator output connected externally to break inputs,
with low break polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 9. Comparator output connected externally to break inputs,
with high break polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 10. Register locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 11. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

AN4277 Rev 6 3/32

3
List of figures AN4277

List of figures

Figure 1. Break feature implementation in advanced timers for STM32F0/F1/F2/F4/F7

series devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 2. Break feature implementation in advanced timers for STM32F3 series devices . . . . . . . . 12
Figure 3. Break feature implementation in advanced timers for STM32L4 series devices . . . . . . . . 13
Figure 4. Break feature implementation in advanced timers for STM32U5 series devices . . . . . . . . 13
Figure 5. Output redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6. Break feature implementation for TIM15, TIM16 and TIM17 for STM32F1
series devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Break feature implementation for TIM15, TIM16 and TIM17 for STM32F3
series devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. Break feature implementation for TIM15, TIM16 and TIM17 for STM32L4 and STM32H7 se-
ries devices 16
Figure 9. Break feature implementation for TIM15, TIM16 and TIM17 in STM32U5 series devices . 17
Figure 10. Over-current protection network implemented with STM32F3 series devices . . . . . . . . . . 22
Figure 11. Over-voltage protection network implemented with STM32F3 series devices . . . . . . . . . . 23
Figure 12. Combining external and internal protection concept. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 13. Comparator chain configuration locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 14. Inverting input selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4/32 AN4277 Rev 6

AN4277 General information

1 General information

This document applies to Arm®(a)-based devices.

2 Reference documents

The following documents are available on www.st.com.

Table 2. Reference documents

Reference Title

AN4013 STM32 cross-series timer overview

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

AN4277 Rev 6 5/32

31
Break function overview AN4277

3 Break function overview

The break function is available in TIM1, TIM8, TIM20, TIM15, TIM16 and TIM17 timers. These timers are able to generate
complementary PWM signals with a dead time insertion for driving power switches in a half bridge topology.
The purpose of the break function is to protect power switches driven by PWM signals generated with these timers. When triggered
by a fault, the break circuitry shuts down the PWM outputs and forces them to a predefined safe state.
Table 3 summarizes the break inputs availability.

Table 3. Timers and break input availability in STM32 devices

- TIM1 TIM8 TIM20 TIM15 TIM16 TIM17

BRK
STM32F0 - - - - -
BRK_ACTH

BRK BRK BRK BRK

STM32F1 - -
BRK_ACTH BRK_ACTH BRK_ACTH BRK_ACTH

BRK BRK
STM32F2
- - - -
STM32F4
BRK_ACTH BRK_ACTH

BRK BRK BRK BRK BRK BRK

STM32F3 BRK2 BRK2 BRK2 BRK_ACTH BRK_ACTH BRK_ACTH

BRK_ACTH BRK_ACTH BRK_ACTH - - -

BRK BRK
STM32F7
BRK2 BRK2 - - - -

BRK_ACTH BRK_ACTH

STM32L4 BRK BRK BRK BRK BRK

STM32L5
STM32U5 BRK2 BRK2 System break System break System break
STM32H7 -
STM32H5(1)
System break System break - - -

BRK BRK BRK

STM32C0
STM32WB BRK2 - - - System break System break
STM32WL
System break - -

BRK BRK BRK BRK

STM32G0 BRK2 - - System break System break System break

System break - - -

BRK BRK BRK BRK BRK BRK

STM32G4 BRK2 BRK2 BRK2 System break System break System break

System break System break System break - - -

BRK

STM32H503 BRK2 - - - - -

System break

BRK

STM32L0 - - - - - -

1. Excluding STM32H503

6/32 AN4277 Rev 6

AN4277 Break function overview

The BRK input can either disable the PWM outputs (inactive state) or force them to a
predefined safe state, either active or inactive, after a dead time insertion. This allows to
prevent any shoot-through in the half bridge. The BRK2 only disables the PWM outputs
(inactive state).
BRK has higher priority than BRK2. When both protections are triggered, the predefined
safe state related to BRK circuitry overrides the inactive state related to the BRK2 input.
Typically, a permanent magnet 3-phase brushless motor drive uses the protections as
follows:
• The BRK2 input as an over-current protection, opening the six switches from the power
stage.
• The BRK input as an over-voltage protection, overriding the over-current and closing
the three low-side switches to avoid current regeneration to build up the bus voltage
and exceed the capacitor rated voltage.
As an example in STM32F303xB/C/D/E devices, for a dual motor drive, the comparators 1,
2 and 3 can be dedicated to over-current monitoring of the three phases of motor 1 (BRK2
input of TIM1). The comparators 4, 5 and 6 can be dedicated to over-current monitoring of
the three phases of motor 2 (BRK2 input of TIM8), while the comparator 7 is used for over-
voltage monitoring (driving BRK inputs of both TIM1 and TIM8).
BRK_ACTH input is connected only to internal signals such as, CSS, PVD output.
On newer devices as STM32U5 it is marked as tim_sys_brk (system break interconnect) or
as internal source but this serves the same purpose. For more details, refer to Section 4:
Break implementation.

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8/32

Break function overview

The availability of break inputs and the break sources depends on the selected STM32 family.
This is summarized in Table 4 and in the application note STM32 cross-series timer overview (AN4013) which details the available timers.

Table 4. Comparator peripherals availability per STM32 device(1)

STM32G0
STM32F0 STM32F3 STM32L4 (4) STM32G4 STM32H5

STM32F302xB/C/D/E

STM32F334x4/6/8
STM32F303xB/C

STM32F303xD/E
STM32F303x6/8

STM32F302x6/8
STM32F301x6/8

STM32G051/61
STM32G071/81
STM32G0B1/C
STM32F358xC

STM32F398xE
STM32F05xxx
STM32F07xxx

STM32F328x8

STM32F318x8

STM32F37xxx
STM32L1 STM32L0
STM3209xxx

STM32G4x1

STM32G4x3

STM32H503
- STM32L5 STM32U5 STM32WB STM32WL STM32H7

STM32L4+
(2) (3)

STM32L4
Filter - - - - - - - - - - DFSDM DFSDM MDF(5) - - - - - - - DFSDM
AN4277 Rev 6

COMP
X X - X X - - X X X X X X X X X X X X X X
1

COMP
X X X X X X X X X X X(6) X X X X X X X X - X
2

COMP
- X - X - - - - - - - - - - - - X X X - -
3

COMP
- X X X X X X - - - - - - - - - - X X - -
4

COMP
- X - X - - - - - - - - - - - - - - X - -
5

COMP
- X X X X X X - - - - - - - - - - - X - -
6

COMP
- X - X - - - - - - - - - - - - - - X - -
7

1. Comparator availability may be limited by the package pin count.

2. These devices feature comparators, but no advanced timers with break inputs.
3. These devices feature comparators, but no advanced timers with break inputs. STM32L010 value line has no comparators either.
4. STM32G0x0, STM32G031 and STM32G041 have no comparators.
5. ADF does not feature a break output.

AN4277
6. STML412/L422 does not have COMP2.
AN4277 Break implementation

4 Break implementation

4.1 TIM1/8/20 break implementation

The source for break BRK channel is an external source connected to one of the BKIN pin
(as per selection done in the AFIO controller), with polarity selection and optional digital
filtering.
The source of break2 BRK2 channel is an external source connected to one of the BKIN2
pin (as per selection done in the AFIO controller), with polarity selection and optional digital
filtering.
The source for BRK_ACTH (or system break interconnect) is an internal signal coming from:
– comparator output (on STM32Fx)
– clock security system
– lockup of Cortex®-M family CPUs
– PVD output
– SRAM ECC/parity error signal
– flash ECC error

BRK
– In all series, the input signal on BRK is connected to the BKIN pin.
– In STM32F3 series, the input signal on BRK is a logical OR between the input
signals on BKIN pin and the used comparator (4 or 7) output if configured and
used internally. If BKIN alternate function is disabled, the resulting break signal is
the comparator (4 or 7) output.
– In STM32L4 and STM32H7 series, the input signal on BRK is a logical OR
between the input signals on BKIN pin, the used comparator (1 or 2) output and
the DFSDM break output if configured and used internally. Each application break
source has its own polarity configuration.
– In STM32U5 series, the input signal on BRK is a logical OR between the
comparators (including MDF) break outputs and external sources.
The polarity feature is available for the BRK input. The filter feature is available as well but
only on STM32F3/F7/L4/U5 devices.

BRK_ACTH (or system break)

– In STM32F1/F2/F4/F7 series, this input only gathers the system level fault signals.
– In STM32F0 series, BRK_ACTH is connected to the system level fault signals and
the comparators outputs (1 and 2).
– In STM32F3 series, BRK_ACTH is connected to the system level fault signals and
the comparators (1, 2, 3, 5 and 6).
– For any non-Fx series, the system break request is connected to the system level
fault signals.

AN4277 Rev 6 9/32

31
Break implementation AN4277

When this input is used, the polarity selection and filter features are not available. It is
always active high.
BRK_ACTH is enabled using the same bit as BRK (BKE in TIMx_BDTR, x= 1, 8, 20).
If there are several system break input sources, the resulting input signal is an OR between
all the input signals. With the exception of the CSS fault signal, the inputs can be individually
disabled using the system control block registers.
Other break inputs, external, filter or comparator are also ORed together and then with the
system break inputs. In case of comparator and external signals, polarity must be observed
for the logical OR to work as intended.

BRK2
– In STM32F3 series, this input signal is a logical OR between the input signal on
BKIN2 pin and the used comparators outputs (1, 2, 3, 4, 5, 6 and 7). If BKIN2
alternate function is disabled (input not used), the resulting break signal is solely
related to the comparators.
– In STM32F7 series, the input signal on BRK2 is connected to the BKIN2 pin.
– In STM32L4 series, the input signal on BRK2 is a logical OR between the input
signals on BKIN2 pin, the used comparator (1 or 2) output and the DFSDM break
output if configured.
– In STM32U5 series, the input signal on BRK2 is a logical OR between
comparators (1 or 2) and MDF1.
– In STM32L4 and STM32L5 series, it is possible to configure the polarity of each
break source in addition except the DFSDM break output to the polarity
configuration inside the timer peripheral using BKCMP1P, BKCMP2P, BKINP in
TIMx_OR2 register and BK2CMP1P, BK2CMP2P, BK2INP in TIMx_OR3 register.
– In STM32U5 and STM32H7 series, it is possible to configure the polarity of each
break source in addition except the MDF1 (DFSDM) break output to the polarity
configuration inside the timer peripheral using BKCMP1P, BKCMP2P, BKINP in
TIMx_AF1 register and BK2CMP1P, BK2CMP2P, BK2INP in TIMx_AF2 register.
– In STM32G4 series, it is possible to configure the polarity of COMP1-4 using
BKCMPxP bits in TIMx_AF1 register and BK2CMPxP in TIMx_AF2 register. The
rest of the internal inputs have individual polarity fixed to active high, though the
collective polarity is still configurable (BKP, BK2P).
– On other series, polarity is individually configurable for all their available COMPx
and BKIN/BKIN2 inputs.
Figure 1 shows the break feature implementation for TIM1, TIM8 in STM32F0/F1/F2/F4/F7
series devices.
Figure 2 shows the break feature implementation for TIM1, TIM8 and TIM20 in STM32F3
series devices.
Figure 3 shows the break feature implementation for TIM1 and TIM8 in STM32L4 series
devices.
Figure 4 shows the break feature implementation for TIM1 and TIM8 in STM32U5 series
devices.

10/32 AN4277 Rev 6

AN4277 Break implementation

Figure 1. Break feature implementation in advanced timers for STM32F0/F1/F2/F4/F7

series devices

System level fault

+ COMP1_Output
-

+ COMP2_Output
BRK_ACTH
-

BRK Filter/Polarity
BKIN PWM
TIM1, 8
Output

BRK2 Filter/Polarity
BKIN2

MSv41059V2

AN4277 Rev 6 11/32

31
Break implementation AN4277

Figure 2. Break feature implementation in advanced timers for STM32F3 series

devices

+ COMP1_Output
-
+ COMP2_Output
-
+ COMP3_Output
-
+ COMP5_Output
-
+ COMP6_Output
-

PVD output

CSS clock failure event

SRAM parity error signal

Cortex-M4 LOCKUP output

BRK_ACTH

BKIN

+ COMP4_Output BRK PWM

Filter/Polarity TIM1, 8, 20
- Output

+ COMP7_Output
- BRK2 Filter/Polarity

BKIN2

+ COMP1_Output
-
+ COMP7_Output
-

MSv41060V2

12/32 AN4277 Rev 6

AN4277 Break implementation

Figure 3. Break feature implementation in advanced timers for STM32L4 series

devices

System level fault

BRK_ACTH
BKIN Polarity

+ COMP1_Output
Polarity
- BRK
Filter/Polarity TIM1, 8 PWM
+ Output
COMP2_Output
Polarity
-

DFSDM break output BRK2

Filter/Polarity

BKIN2 Polarity

+ COMP1_Output
Polarity
-

+ COMP2_Output
Polarity
-

DFSDM break output

MSv41061V2

Figure 4. Break feature implementation in advanced timers for STM32U5 series

devices

System level fault

BKIN Polarity

COMP1_Output
+ System break interconnect
Polarity
- BRK Filter/
Polarity
PWM
+ COMP2_Output TIM1,8 Output
Polarity BRK2
- Filter/
Polarity

MDF1 break
output

BKIN2 Polarity

COMP1_Output
+
Polarity
-

+ COMP2_Output
Polarity
-

MDF2 break
output

MSv70058V1

AN4277 Rev 6 13/32

31
Break implementation AN4277

Bidirectional break inputs

For example in STM32L4 and STM32U5 series, the timer 1 and timer 8 are featuring
bidirectional break input/outputs combining the comparator output (to be configured in open
drain) and the Timer BKIN input, as represented in Figure 5.
This feature allows information about the global break available for external MCU’s with a
single-pin.

Figure 5. Output redirection

BKINP = 1

To the timer break input

(active high) AFI

AF input enabled (active low)

TIMx_BKINy_COMPz
+ (x=1,8; y=N/A,2; z=1,2)
COMP

-
AFO AF output configured as open drain

MS35330V2

4.2 TIM15/16/17 break implementation

The source for break BRK channel is an external source connected to one of the BKIN pin
(as per selection done in the AFIO controller), with polarity selection and optional digital
filtering.
The source for BRK_ACTH is an internal signal coming from:
– clock security system
– lockup of Cortex®-M family CPUs
– PVD output
– SRAM ECC/parity error signal
– flash ECC error

Inputs from available comparators are ORed with BRK_ACTH signals (on STM32Fx series)
or with the external BRK input with polarity selection option.
BRK
– In all series: the input signal on BRK is connected to the BKIN pin.
– In STM32L4 series: the input signal on BRK is a logical OR between the input
signals on BKIN pin, the used comparator (1 or 2) output and the DFSDM break
output if configured.
– In STM32U5 series: the input signal on BRK is a logical OR between BKIN pin, the
used comparator (1 or 2) output and MDF1 break output.
The polarity selection feature is available for BRK source.

14/32 AN4277 Rev 6

AN4277 Break implementation

In STM32L4 series, it is possible to configure the polarity of each break source in addition
except the DFSDM break output to the polarity configuration inside the timer peripheral
using BKCMP1P, BKCMP2P, BKINP in TIMx_OR2 register.
In STM32U5 series, it is possible to configure the polarity of each break source in addition.
Thus, except the MDF1 break output to the polarity configuration inside the timer peripheral.
This is done using BKCMP1P, BKCMP2P, BKINP in TIMx_AF1 register.
Note: On TIM15-17, the filter feature is only available for STM32Gx, STM32Hx and STM32U5
devices.

BRK_ACTH (or system break)

– In STM32F1/L4 series, this input only gathers the system level fault signals (CSS,
PVD output, SRAM parity error and the Hardfault).
– In STM32F3 series, BRK_ACTH is connected to the system level fault signals and
the comparators (1 and 2) for the STM32F37xxx devices and the comparators
outputs (3, 5 and 7) for the rest of STM32F3 series.
– In other series, system break interconnected sources are CSS, flash and SRAM
ECC errors, PVD and core lockup detection.
When this input is used, the polarity selection and filter features are not available. It is
always active high.
BRK_ACTH is enabled using the same bit BRK (BKE in TIMx_BDTR, x= 15, 16, 17).
When using BRK_ACTH as break input, the polarity must be configured high. Otherwise,
there is no PWM generation independently of the break signal coming from the internal
source.
Figure 6 shows the break feature implementation for TIM15, TIM16 and TIM17 in STM32F1
series devices.
Figure 7 shows the break feature implementation for TIM15, TIM16 and TIM17 in STM32F3
series devices.
Figure 8 shows the break feature implementation for TIM15, TIM16 and TIM17 in STM32L4
series devices.
Figure 9 shows the break feature implementation for TIM15, TIM16 and TIM17 in STM32U5
series devices.

Figure 6. Break feature implementation for TIM15, TIM16 and TIM17 for STM32F1
series devices

Internal break sources BRK_ACTH

PWM
TIM15,16,17
Output

BRK
BKIN Polarity

MSv41062V1

AN4277 Rev 6 15/32

31
Break implementation AN4277

Figure 7. Break feature implementation for TIM15, TIM16 and TIM17 for STM32F3
series devices

+ COMP1_Output
-

+ COMP2_Output
-

+ COMP3_Output
-
+ COMP5_Output
-
+ COMP7_Output
-

PVD output

CSS clock failure event

SRAM parity error signal BRK_ACTH

Cortex-M4 LOCKUP output TIM15,16,17 PWM

Output
BRK
BKIN Polarity

MSv41063V2

Figure 8. Break feature implementation for TIM15, TIM16 and TIM17 for STM32L4 and
STM32H7 series devices

System level fault

BRK_ACTH
BKIN Polarity
PWM
+ TIM15,16,17
COMP1_Output Output
Polarity
- BRK
Filter/Polarity
+
COMP2_Output
Polarity
-

DFSDM break output

MSv41064V2

– If only an internal break source is used, the polarity must be configured to high in
the software.
– If there are several break input sources, the resulting input signal is an OR
between all the input signals.
– If both internal break source and BKIN are used, the resulting break signal is an
OR between the signal pin and the internal break signal.

16/32 AN4277 Rev 6

AN4277 Break implementation

– If the alternate function AF of the BKIN or BKIN2 pin is not activated, the BRK or
the BRK2 is connected to the ground. If the state of the BRK or BRK2 polarity is
low, in this case if the break function is enabled, the timer output is disabled. Thus
it must to configure the break polarity to high. Only in STM32F1 series it must to
configure the break polarity to low.

Figure 9. Break feature implementation for TIM15, TIM16 and TIM17 in STM32U5
series devices
System level fault

BKIN Polarity
System break interconnect
COMP1_Output
+
Polarity
- BRK Filter/ TIM15,16, PWM
Polarity 17 Output

+ COMP2_Output
Polarity
-

MDF1 break
output

MSv70059V1

1. STM32G0, STM32H7, STM32WB and STM32WL are similar to STM32U5, except for MDF.

AN4277 Rev 6 17/32

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Break sources summary AN4277

5 Break sources summary

Table 5 summarizes the available break sources and their connections externally or
internally to timers (1, 8, 20, 15, 16, and 17) break inputs.

Table 5. Break input sources

BRK_ACTH
- BRK BRK2
(or system break)

External
connection to BKIN No corresponding I/O BKIN2
pin
In STM32F3: Available signals from: In STM32F3:
- Comparators 4 and 7 for
- Comparators 1, 2, 3, 4, 5, 6
TIM1/8/20
- Clock failure event generated and 7
- NA for TIM15/16/17
by CSS In STM32L4 and STM32H7:
Internal In STM32L4 and STM32H7:
- PVD output - Comparators 1 and 2
connection to - Comparators 1 and 2 - RAM parity error signal
- DFSDM break output.
- DFSDM break output - Cortex-M4 LOCKUP output
(Hardfault) In STM32U5:
In STM32U5:
- Comparator outputs (on - Comparators 1 and 2
- Comparators 1 and 2
STM32Fx series) - MDF1 break output
- MDF1 break output
Polarity feature
in case of Configurable for most inputs: Configurable for some inputs:
Always active high
internal active high or active low active high or active low
connection
Polarity feature
in case of
Available NA Available
external break
event
Not available in STM32F0,
STM32F1. STM32F2&F4 and Not available in STM32F0,
Filter feature NA
only available in STM32F3 STM32F1. STM32F2&F4
advanced timers
TIM1/8/20 in STM32F3, TIM1/8
Available in TIM1/8/20/15/16/17 TIM1/8/20/15/16/17
in other series
Resulting
break signal in
case of parallel
It is an OR between the external break signals and the internal ones
external or/and
internal break
sources

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AN4277 Examples

6 Examples

Table 6 shows the PWM output status for TIMx (where x= 1, 8, 20, 15, 16, 17) in response to
internal/external break events.
In the following waveforms:
• PWM signal is the reference waveform (internal signal, before BRK protection).
• COMP_OUT signal represents the BRK input signal, in our case it is the comparator
output.
• BIN signal is the input signal on BKIN.
• PWM_BRK signal is the resulting PWM signal on the timer output after break detection.
Color legend for Table 5: green = PWM signal, blue = COMP_OUT signal, yellow = BKIN
signal, purple = PWM_BRK signal.

Table 6. Scenarios of PWM output status in response to internal/external break events

Progra-
Configuration mmed Result
polarity

The PWM generation is stopped when the comparator output is at the high level, as
shown in the following screen shot:

Comparator 1
output is
connected
internally to
TIM1
High
BRK_ACTH
and TIM1 BKIN
alternate
function is
disabled.

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Examples AN4277

Table 6. Scenarios of PWM output status in response to internal/external break events (continued)
Progra-
Configuration mmed Result
polarity

The break input signal is an OR between the signal on BKIN and the comparator output.
The following screen shot shows an example (polarity = High):

Comparator 1
output is
connected
internally to
TIM1 High/
BRK_ACTH Low
and TIM1 BKIN
alternate
function is
enabled.

Note: In order to show the effect of the two break sources, the bit AOE in
BDTR register is set, allowing to re-start the PWM at the next
update event.

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AN4277 Examples

Table 6. Scenarios of PWM output status in response to internal/external break events (continued)
Progra-
Configuration mmed Result
polarity

The PWM signal is stopped during the break signal low level, as shown in the following
screen shot:

Comparator 4
output is
connected
internally to Low
TIM1 BRK and
filter is not
configured.

During the window defined by the filter duration, the break event has no impact on the
PWM generation even if the break condition is verified.
This is the case of the following example (screen shot) where the PWM signal is
generated normally when the break signal is at high level during the window defined by
the filter.
– The filter duration is 7.111 µs (BKF = 1111b, filter duration is (32*8/fDTS),
fDTS = 36 MHz).
Comparator 4 – The comparator output high level duration is 7.111 µs.
output is
connected
internally to High
TIM1 BRK and
filter is
configured.

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Using the break function with other MCU resources AN4277

7 Using the break function with other MCU resources

Note: This section is dealing with the STM32F3 series, but some parts are also applicable for
other STM32 series, especially the STM32G4. Sometimes using analogous resources, such
as system level fault instead of BRK_ACTH.

7.1 Break function used for over-current protection

The STM32F3 series microcontroller embeds a set of peripherals designed to resolve
common motor control issues by reducing the number of required external components.
This section describes how to use these peripherals to implement over-current protection.
Figure 10 shows the over-current protection network that can be implemented using the
internal resources of the STM32F3 series.

Figure 10. Over-current protection network implemented with STM32F3 series

devices

+Vdd

R1
R2 COMP
+
BRK2
- TIM1,8,20 6 PWM
V+ V-
RShunt
I
OP AMP
+
- ADC

Current measurement

STM32F3xx

MS31664V2

The principle of this over-current protection mechanism can be summarized as follows:

• The phase current of the motor flows in the power transistor of the inverter bridge and
passes through the shunt resistor (RShunt) producing a voltage drop (V+).
• This voltage drop is compared with a threshold (V-) defining the maximum admissible
current.
• If the threshold is exceeded, a break signal stops the PWM generation putting the
system in a safe state.

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AN4277 Using the break function with other MCU resources

All of these actions can be performed using the internal resources of the STM32F3 series
and, in particular, the embedded comparators and advanced timer break function (BRK2). In
the basic implementation, the only external component required is the shunt resistor that
must be sized depending on the current to be monitored and the shunt resistor power rating.
The two dotted line boxes in Figure 10 show the components required to measure current:
• The R1/R2 resistive network to add an offset necessary to measure AC currents.
• An operational amplifier with a built-in gain setting network.
The amplification network can be implemented externally for specific use cases where the
built-in gain settings are not adequate.

7.2 Break function used for over-voltage protection

Figure 11 shows the over-voltage protection network that can be implemented using the
internal resources of the STM32F3 series.

Figure 11. Over-voltage protection network implemented with STM32F3 series

devices
BUS voltage

COMP
+
BRK
- TIM1,8,20 6 PWM
V+ V-

ADC

Bus voltage measurement

STM32F3xx
MSv31666V2

In this case, the principle is similar to the one described in Section 7.1:
• A resistive voltage divider provides a signal proportional to the bus voltage.
• This reading is compared to an over-voltage threshold to generate a fault signal.
See also: Appendix A: How to use the DAC to define thresholds.
• If the threshold is exceeded, a break signal stops the PWM generation putting the
system in a safe state.
As mentioned before, these actions can be performed automatically using the internal
comparator of the STM32F3 series. In this case, it is possible to use the second break
functionality (BRK) of the advanced timer in order to differentiate the action to perform on
the PWM signals in case of an over-current.

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Using the break function with other MCU resources AN4277

In the basic implementation, the only external component required is the voltage divider
which must be sized depending on the bus voltage range requested by the target
application, so that it never exceeds the MCU’s input maximum admissible voltage level.
The dotted line box in Figure 11 shows the components required for the bus voltage
measurement. In this case, amplifying the signal V+ is usually not required (the resistive
divider is adjusted for full-range reading), so this signal is fed directly to the analog-to-digital
converter.

7.3 Using an external emergency signal together with the

internal comparator
Commonly in MC applications, gate driver ICs, such as ST’s L639x family or Intelligent
power modules (IPMs) - such as ST’s SLLIMM (small low-loss intelligent molded module)
family - have integrated comparators that can protect the inverter (ST’s smart shutdown
function) while sending an error signal to the microcontroller.
This section shows the possibility to combine these two concepts, as shown in Figure 12, as
to enhance by redundancy the functional safety offered by the “break function”.
A first option is when the break function is triggered by internal comparators output only: the
error signal coming from ICs or IPMs must not be connected to the microcontroller, thus
saving the pin. The configuration to set in this case is summarized in the following table.

Table 7. Comparator output connected internally to break inputs

Description Register Bit Configuration(1)

TIM1/8/20
TIMx_BDTR BKP or BK2P 1 (active high)
BRK_ACTH/BRK/BRK2 polarity
0 (not inverted), comparators input connected
Comparator output polarity COMPx_CSR COMPxPOL
as shown in previous sections
GPIOxAFRL
TIM1/8/20 BKIN and BKIN2 AF or - AF not enabled on BKIN1/2 related pins
GPIOxAFRH
TIM1/8/20 BRK and BRK2
TIMX_BDTR BKE or BK2E 1
enable
0001: TIM1 BRK or TIM1 BRK_ACTH(2)
0010: TIM1 BRK2
0011: TIM8 BRK or TIM8 BRK_ACTH(3)
0100: TIM8 BRK2
COMPx out selection COMPx_CSR COMPxOUTSEL
0101: TIM1 BRK2 + TIM8 BRK2
1100: TIM20 BRK or TIM20 BRK_ACTH(4)
1101: TIM20 BRK2
1110: TIM1 BRK2 + TIM8 BRK2 + TIM20 BRK2
1. Some newer STM32 series, such as STM32U5 abandoned the use of BRK_ACTH identifier using name system level or
internal fault instead. The functionality remains analogous.
2. TIM1 BRK in case of COMP4 and COMP7, or TIM1 BRK_ACTH in case of COMPx, x = 1, 2, 3, 5 and 6.
3. TIM8 BRK in case of COMP4 and COMP7, or TIM8 BRK_ACTH in case of COMPx, x = 1, 2, 3, 5 and 6.
4. TIM20 BRK in case of COMP4 and COMP7, or TIM20 BRK_ACTH in case of COMPx, x= 1, 2, 3, 5 and 6.

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AN4277 Using the break function with other MCU resources

On the contrary, the user may prefer to make use of the external error signal in conjunction
with the internal one: the result is an OR between the two. Depending on the external
comparator logic, the possible configurations to write are summarized in the following
tables.

Table 8. Comparator output connected externally to break inputs,

with low break polarity
Description Register Bit Configuration

0 (active low), it means that the external signal

TIM1/8/20 BRK polarity TIMx_BDTR BKP
goes low during the fault
0 (not inverted), comparators input connected
Comparator output polarity COMPx_CSR COMPxPOL
as shown in previous sections
GPIOxAFRL
AF enabled on BKIN pin selected among
TIM1/8/20 BKIN AF or -
available
GPIOxAFRH
TIM1/8/20 BRK enable TIMX_BDTR BKE 1
0001: TIM1 BRK
COMPx out selection COMPx_CSR COMPxOUTSEL 0011: TIM8 BRK
1100: TIM20 BRK

Table 9. Comparator output connected externally to break inputs,

with high break polarity
Description Register Bit Configuration

1 (active high), it means that the external signal

TIM1/8/20 BRK/BRK2 polarity TIMx_BDTR BKP or BK2P
goes high during the fault
0 (not inverted), comparators input connected
Comparator output polarity COMPx_CSR COMPxPOL
as shown in previous sections
GPIOxAFRL
AF enabled on BKIN/BKIN2 pin selected among
TIM1/8/20 BKIN/BKIN2 AF or -
available
GPIOxAFRH
TIM1/8/20 BRK/BRK2 enable TIMX_BDTR BKE or BK2E 1
0001: TIM1 BRK
0010: TIM1 BRK2
0011: TIM8 BRK
0100: TIM8 BRK2
COMPx out selection COMPx_CSR COMPxOUTSEL
0101: TIM1 BRK2 + TIM8 BRK2
1100: TIM20 BRK
1101: TIM20 BRK2
1110: TIM1 BRK2 + TIM8 BRK2 + TIM20 BRK2

The comparators output can be optionally enabled as alternate function on the related GPIO
pin, in push-pull or open-drain mode, for signaling to other devices or for debugging
purposes.

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Using the break function with other MCU resources AN4277

Figure 12. Combining external and internal protection concept

TIM1, 8, 20

-
V

MS31665V3

7.4 Filtering the break input

Programmable filters are available to prevent break functions of advanced timers from being
triggered on spurious events (switching noise for instance).
The digital filter feature is available on BRK and BRK2. It is not available on BRK_ACTH.
That means that the digital filter is:
• available when the break source is external and comes from the external inputs
BKIN/BKIN2
• available when the break source is internal and connected to BRK or BRK2,
• not available when the break source is internal and connected to BRK_ACTH.

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AN4277 Using the break function with other MCU resources

7.5 Locking the selected configuration

Electrical motor drives require a high level of reliability and robustness for the potential
damages that may be caused in case of failure.
To increase robustness against software runaways, the STM32F3 series microcontroller
comes with a chain of peripherals featuring the lock feature, beginning from the mode of the
GPIO pins used for sensing through comparators, operational amplifiers (opamp) and
advanced timers, down to the GPIO pins used for driving, as shown in Figure 13.
In particular, BRK and BRK2 configurations can be locked using the LOCK bits in
TIMx_BDTR register. At least LOCK level 1 is recommended to freeze
DTG/BKE/BKP/AOE/BKF/BK2F/BK2E/BK2P bits in TIMx_BDTR register and OISx/OISxN
bits in TIMx_CR2 register until the next reset.

Figure 13. Comparator chain configuration locking

GPIO pin locked

analog
mode
locked
+ locked
Configuration
GPIO pin locked PWM
analog BRK1/2 GPIO pins
mode
locked
- AF mode
(PP/OD)
locked
locked
TIM1/8/20

BRK1/2
Behavior locked

STM32F3xx

MS31667V2

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Using the break function with other MCU resources AN4277

Table 10 summarizes the recommended settings for comparators.

Table 10. Register locking mechanism

Peripheral Feature Register Comment

GPIOx_MODER register,
Inverting input,
GPIO Port x, pin y MODERy bit to be configured in -
pin mode selection
analog mode
GPIOx_LCKR register, specific MODERy bit (in
Inverting input, pin
GPIO Port x, pin y write sequence coded with GPIOx_MODER register) now
configuration locking
LCKy bit frozen until next reset
GPIOw_MODER register,
Non inverting input, Not needed if an internal
GPIO Port w, pin z MODERz bit to be configured in
pin mode selection reference is selected
analog mode
GPIOw_LCKR register, specific MODERz bit (in
Non inverting input, pin
GPIO Port w, pin z write sequence coded with GPIOw_MODER register) now
configuration locking
LCKz bit frozen until next reset
LOCK level 1 (at least)
recommended: DTG bits in
TIMx_BDTR register, OISx and
BKIN / BKIN2 TIMx_BDTR register,
TIMER 1/8/20 OISxN bits in TIMx_CR2
configuration locking LOCK bits
register and BKE/BKP/AOE bits
in TIMx_BDTR register frozen
until next reset

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AN4277 How to use the DAC to define thresholds

Appendix A How to use the DAC to define thresholds

Concerning the network shown in Figure 10 and Figure 11, it is important to properly set the
comparator inverting input voltage (V-) to define the threshold levels for over-current
protection and over-voltage protection.
As shown in Figure 14 below, in the STM32F3 series microcontroller it is possible to set
three different sources as inverting input for the comparator:
• an external reference (GPIO)
• a fixed internal reference (Vref, ¾ Vref, ½ Vref, ¼ Vref)
• a programmable internal reference (DAC)

Figure 14. Inverting input selection

GPIO +

GPIO
DAC1_CH1 COMP

DAC1_CH2
-
VREFINT
¾ VREFINT
½ VREFINT
¼ VREFINT
MS31663V1

Practical example: over-current protection using the offset network

This is the case of Figure 10 when the components inside the dotted line boxes are present.
In this case, the formula to compute the over-current threshold is the following:
Equation 1
R2
V – ⎛ V dd × --------------------⎞
-
⎝ R 1 + R 2⎠
I th = -------------------------------------------------------
R1
R shunt × ⎛ --------------------⎞
⎝ R 1 + R 2⎠
Usually the R1 and R2 values are used to satisfy the current measurement needs. It is clear
that using the internal reference for V- can lead to a threshold value Ith which is not exactly
coincident with the required one. As explained in this practical example, the internal
reference can be used only when there is no need to fine-tune the over-current threshold.
Otherwise, it is necessary to use the external reference or the variable internal reference.
The latter is recommended, because it does not require any external components.
The STM32F3 series microcontroller includes two 12-bit DAC channels that can be used for
this purpose. For three-phase motor drives, it is possible to group three comparators to
protect each leg of the inverter bridge versus over-current by setting the same DAC channel
for all three inverter inputs.
The same can be done in case of dual motor control with also having the possibility to define
two different levels of protection, one for each motor.

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Revision history AN4277

Revision history

Table 11. Document revision history

Date Revision Changes

25-Nov-2013 1 Initial release.

Updated cover page with STM32F3 series and adding RM references.
Updated the whole document adding TIM20 and replacing
STM32F30x/31 x by STM32F3 series.
Updated Section 1: Break function overview adding Table 3:
05-Mar-2015 2 Peripherals availability per STM32 devices.
Updated Figure 1: Break feature implementation for TIM1, TIM8 and
TIM20.
Updated Figure 11: Comparator chain configuration locking.
Updated Table 9: Register locking mechanism.
Updated Section 2.2: TIM15/16/17 break implementation removing the
filter feature in BRK and BRK_ACTH paragraphs.
Updated Figure 5: Break feature implementation for TIM15, TIM16
30-Jun-2015 3 and TIM17 for STM32F1 series devices replacing filter/polarity by
polarity.
Updated Table 4: Break input sources adding “NA for TIM15/16/17” for
2 lines in BRK column.
Updated cover page title and introduction with the application note
applying to STM32 devices.
Added Table 1: Applicable products.
Updated Section 1: Break function overview.
Added Table 2: Timers and break input availability in STM32 devices.
Updated Table 3: Peripherals availability per STM32 devices.
Updated Section 2: Break implementation.
Updated Figure 1, Figure 2, Figure 3, Figure 5, Figure 6 and Figure 7.
03-May-2016 4
Updated Table 4: Break input sources.
Updated Table 5: Scenarios of PWM output status in response to
internal/external break events.
Updated Section 5: Using the break function with other MCU
resources adding a note.
Updated Section : BRK_ATCH.
Added Section : Bidirectional break inputs.
Added Figure 4: Output redirection.

30/32 AN4277 Rev 6

AN4277 Revision history

Table 11. Document revision history (continued)

Date Revision Changes

Updated all document with STM32U series in:

Section 1: General information
Section 4: Break implementation
Section 5: Break sources summary
Section 7: Using the break function with other MCU resources.
09-Mar-2022 5
Added:
Figure 4: Break feature implementation in advanced timers for
STM32U5 series devices
Figure 9: Break feature implementation for TIM15, TIM16 and TIM17
in STM32U5 series devices
Updated the whole document to add STM32 series information in:
Section Table 1.: Applicable products
Section Table 3.: Timers and break input availability in STM32 devices
Section Table 4.: Comparator peripherals availability per STM32
05-Jan-2023 6
device
Section 4.1: TIM1/8/20 break implementation.
Section 4.2: TIM15/16/17 break implementation.
Section 5: Break sources summary.

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 AN4277

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