1.introduction To Microprocessor of 8085 - 2024
1.introduction To Microprocessor of 8085 - 2024
Introduction to
microprocessor and
organisation of 8085
12th Computer Science
Maharashtra Board
Marks Distribution
2
Evolution of Microprocessors
2. Registers
3. Control unit
Arithmetic / Logic unit (ALU)
2. Transfer data to and from memory and to and from I/O section.
4. provide overall timing and control signals for the entire system.
3. Program counter
4. Instruction decoder
9. Interrupt control.
Address Bus
• The address bus is group of 16 lines generally
identified as A0 to A15.
• 28 = 256 numbers.
• Eg. MOV A, M
Instruction Decoder
• This unit interprets the contents of
instruction register.
C000 H Instruction 1
C001 H
C001 H Instruction 2
Program Counter
C002 H Instruction 3
Stack Pointer
• Stack pointer is also a 16 bit
register.
C001 H C000 H
Stack Pointer
C001 H
C002 H
Stack
Timing and control unit
• This section receives signals from the
instruction decoder to determine the nature
of instruction to be executed.
1. Address Bus
6. The 8085 has a special signal called ALE (Address Latch Enable) for
informing the peripheral when the address / data bus is sending an
address and when it is functioning as a data bus.
Control and Status signals
This group of signals includes two control signals RD
and WR, three status signals IO/M, S1 and S0 and one
special signal ALE.
1. ALE:
4. IO/M:
8. X₁ and X₂:
• A crystal having frequency 6 MHz is connected at
these two pins.
• The frequency is internally divided by two.
• The system operates at 3 MHz
Power supply and clock frequency
4. CLK (OUT):
• This is clock output.
• This signal can be used as the system clock for
other devices.
Externally Initiated signals
1. INTR:
• This is the interrupt request signal.
• This is a general purpose interrupt.
Externally Initiated signals
3. TRAP:
• This is a nonmaskable interrupt and has the highest
priority.
Externally Initiated signals
4. INTA:
• This is an interrupt acknowledgement.
• The microprocessor acknowledges an interrupt request
by the INTA signal.
• In addition to the interrupts, three pins - RESET, HOLD
and READY accept the externally initiated signals as
inputs.
5. Ready:
• If the signal at this READY pin is low, the microprocessor
enters into a wait state.
• This signal is used primarily to synchronize slower
peripherals with the microprocessor.
Externally Initiated signals
6. HOLD:
• When a HOLD pin is activated by an external signal.
• The microprocessor relinquishes (Releases) control
of buses and allows the external peripherals to use
them.
• For example HOLD signal is used in Direct memory
Access (DMA) data transfer.
7. HLDA:
• This is an acknowledgement.
• Microprocessor acknowledges the hold request by
HLDA.
Externally Initiated signals
8. RESET IN:
• When the signal on this pin goes low,
the program counter is set to zero, the buses are
tri-stated and the MPU is reset.
9.RESET OUT:
• This signal indicates that the MPU is being reset.
• The signal can be used to reset other devices.
Serial I/O Ports
● The 8085 has two pins to implement serial
transmission, SID (Serial input data) and SOD
(serial output data).
● A single bit can be serially inputted through
SID.
● The output pin SOD is set or reset as per
8085 SIM instruction.
Functional Block diagram of 8085
Functional Block diagram of 8085
The block diagram includes :
● The flags (flip flops) are set or reset according to the result of
operations.
Arithmetic and logic unit (ALU)
● In most of the arithmetic and logic operations, the result is stored
in accumulator.
• Sign flag
• Zero flag
• Auxiliary carry flag
• Parity flag
• Carry a flag
1. S-sign flag:
● The zero flag is set to 1 if the ALU operation results in 0, and the flag is reset if
the result is not 0.
● The flag is used only internally for BCD (Binary Coded Decimal)
operations and is not available for the programmer to change the sequence of a
program with a jump instruction.
4. P Parity flag:
● If the - accumulator holds an even number of 1s, it is said that even parity
exists and the parity flag is set to 1.
● If the accumulator holds an odd number of is (called odd parity), the parity flag
is reset to 0.
● The output of the decoder, gated by timing signals, controls the register,
ALU and data and address buffers.
● The output of the decoder and internal clock generator produce the state
and machine cycle timing signals.
Interrupts
Interrupts