INTRODUCTION

Electronic design automation (EDA) or electronic computer-aided design

software (ECAD) designs and develops electronic systems such as printed circuit boards
(PCBs) and integrated circuits (ICs). It allows designers to build out different alternatives and
options and compare them to each other. It also generates manufacturing documentation as
part of the specification used to source, fabricate, and produce PCBs. The rapidly growing
EDA industry is best understood by looking at the definition of EDA. Electronics includes
anything electronic, from computer chips and cell phones to controls for automobiles, etc.
Everything made by the electronics industry results from designers using EDA tools and
services. Design is the part of the production cycle where creativity, ingenuity, and new ideas
are most valued. Designers build models to understand the behaviour and complex
interactions of millions of constituent parts in their designs to ensure completeness,
correctness, and manufacturability of the final product. Many of the designers in this field
include electrical and software engineers. Automation demonstrates the increasing
complexity in the electronics industry today. This complexity is enabled by Moore's Law
(which states that the number of transistors in integrated circuits doubles every 18 months),
which drives the need for automation. Engineers need to validate their concepts, model and
analyze their designs, and identify and eliminate problems before making production
commitments. EDA helps ensure correct designs. Very Large Scale Integration (VLSI) VLSI
is the process of creating an integrated circuit (IC) by combining thousands of transistors into
a single chip. VLSI began in the 1970s when complex semiconductor and communication
technologies were being developed. Before the introduction of VLSI technology most ICs
had a limited set of functions they could perform. The functionality of electronics
equipment’s and gadgets has achieved a phenomenal while their physical sizes and weights
have come down drastically. The major reason is due to the rapid advances in integration
technologies, which enables fabrication of millions of transistors in a single Integrated Circuit
(IC) or chip. IC is a device having multiple transistors with interconnects manufactured on a
single silicon substrate. Integration with a complexity of 10’s of transistors is called Small
Scale Integration, with 100’s is Medium Scale Integration (MSI), with 1000’s is Large Scale
Integration (LSI), with 10,000 it is Very Large Scale Integration (VLSI) Systems of systems
can be implemented in a VLSI IC. However, with this rise in functionality of VLSI ICs,
design problem has become huge and complex. To address this complexly issue, after the
design specifications are complete almost all the other steps are automated using CAD tools.
However, even designs automated using CAD tools may have bugs. Also, due to extremely
large size of the design space it is not possible to verify correctness of the design under all
possible situations. So, technique are required that can verify, without exercising exhaustive
input-output combinations, that the design meets all the input specifications; this technique is
called formal verification.
 In VLSI designs millions of transistors are packed into a single chip. This leads to
manufacturing defects and all the chips need to be physically tested by giving input signals
from a pattern generator and comparing responses using a logic analyzer; this process is
called Testing. So, in the process of manufacturing a VLSI IC there are three broad steps:
Design-Verification-Test.
VLSI ICs can be divided into analog, digital or mixed-signal (both analog and digital on the
same chip) based on their functionality.
 Digital ICs can contain logic gates, flip-flops, multiplexers. Work using binary
mathematics to process "one" and "zero" signals.
 Analog ICs, such as current mirrors, voltage followers, filters, OPAMPs etc. work by
processing continuous signals.
 When single IC has both analog and digital components it is called mixed signal IC e.g,
Analog to Digital Converter (ADC).
The automation algorithms and CAD tools are mainly available for digital ICs because
transformation of design specifications to silicon implementation can be accomplished using
logical procedures (which can be converted to algorithms and tools). However, most of the
analog circuits design is like an “art” which is best performed by designers with “aid” of
some CAD tools (which provides feedback to designer if the manual design is progressing
fine etc.)
VLSI Design flow The VLSI IC circuits design flow is shown in the figure below.
 Specifications comes first, they describe abstractly the functionality, interface, and the
architecture of the digital IC circuit to be designed.
 Architectural design is then created to analyze the design in terms of functionality,
performance, compliance to given standards, and other specifications.
 RTL Description is done using HDLs. This RTL Description is simulated to test
functionality. From here onwards we need the help of EDA tools.
 RTL Description is then converted to a gate-level netlist using logic synthesis tools. A gate-
level net list is a Description of the circuit in terms of gates and connections between them,
which are made in such a way that they meet the timing, power and area specifications.
 Finally , a physical layout is made, which will be verified and then sent to fabrication.
 The Figure provides a more simplified view of the VLSI design flow, taking into
account the various representations, or abstractions of design – behavioural logic, circuit and
mask layout. Note that the verification of design plays a very important role in every step
during this process. The failure to properly verify a design in its early phases typically causes
significant and expensive re-design at a later stage, which ultimately increases the time-to-
market.

Fig .1.1 : Design Flow

In the following, we will examine design methodologies and structured
approaches which have been developed over the years to deal with both complex hardware
and software projects. Regardless of the actual size of the project, the basic principles of
structured design will improve the prospects of success. Some of the classical techniques for
reducing the complexity of IC design are: Hierarchy, regularity, modularity and locality.
DESIGN STYLES :
In 1980s when industry observed the possibility of automating the VLSI
physical design using CAD tools, a new design methodology has been introduced. This new
design methodology was called semi-custom VLSI design, where the design on silicon is
customized as per the required application, reducing the design time and cost involved. In
comparison with full custom VLSI where the complete layout will be hand drawn and every
cell is designed as per the requirements the semi-custom has the following advantages.
 Separated design approach, front end and back end
 Reduced cost as the basic cells are reused
 Less design turnaround time.
In today ASIC industry the design is portioned into front end and back end as
explained below.
1. Front end :
a. Enter the design in one standard format (which EDA tools can understand)
b. Analyzing the requirements and high level design (identifying various blocks
in design)
c. RTL design evolving the necessary micro architecture for each block
d. VHDL, Verilog, other HDLs, Netlist etc.
e. Developing necessary test benches for functional verification.
f. Simulation and model verification using standard simulators
g. Integration of all the blocks and top level simulation.
2. Back end :
a. Synthesizing the design, fixing any bugs (if any part of code is not
synthesizable)
b. Floor planning as the targeted silicon area
c. Invoking the ASIC back end tools (Mapping extracted Netlist cells to
technology specific cells)
d. Place and root as per the required timing and clock constraints
e. Extraction of models from synthesis outputs
f. Timing simulation and functional verification
g. Sending the design to the FAB and getting the chip manufactured
 1. Introduction to HDL

This section is a brief introduction to hardware design using a Hardware

Description Language (HDL). A language describing hardware is quite different from C,
Pascal, or other software languages. A computer program is dynamic, i.e., sharing the same
resources, allocating resources when needed and not always optimized for maximum speed,
optimal memory management, or lowest resource requirements. The main focus is
functionality, but it is still not uncommon that software programs can behave quite
unexpected. When problems arise, new versions of the programs are distributed by the
vendor, usually with a new version number and a higher price tag. The demands on hardware
design are high compared to software. Often it is not possible, or at least very tricky, to patch
hardware after fabrication. Clearly, the functionality must be correct and in addition how the
code is written will affect the size and speed of the resulting hardware. Each mm2 of a chip
costs money, lots of money. The amount of logic cells, memory blocks and input/output
connections will affect the size of the design and therefore also the manufacturing cost. A
software designer using a HDL has to be careful. The degrees of freedom compared with
software design have dramatically increased and must be taken into account.
Hardware description languages such as Verilog differ from software
programming languages because they include ways of describing the propagation time and
signal strengths (sensitivity). There are two types of assignment operators; a blocking
assignment (=), and a non-blocking (<=) assignment.
The non-blocking assignment allows designers to describe a state-machine
update without needing to declare and use temporary storage variables. Since these concepts
are part of Verilog's language semantics, designers could quickly write descriptions of large
circuits in a relatively compact and concise form. At the time of Verilog's introduction
(1984), Verilog represented a tremendous productivity improvement for circuit designers
who were already using graphical schematic capture software and specially written software
programs to document and simulate electronic circuits. The designers of Verilog wanted a
language with syntax similar to the C programming language, which was already widely used
in engineering software development. Like C, Verilog is case-sensitive and has a basic
preprocessor (though less sophisticated than that of ANSI C/C++). Its control flow keywords
(if/else, for, while, case, etc.) are equivalent, and its operator precedence is compatible with
C. Syntactic differences include: required bit-widths for variable declarations, demarcation of
procedural blocks (Verilog uses begin/end instead of curly braces {}), and many other minor
differences. Verilog requires that variables be given a definite size. In C these sizes are
assumed from the 'type' of the variable (for instance an integer type may be 8 bits).
 A Verilog design consists of a hierarchy of modules. Modules encapsulate design
hierarchy, and communicate with other modules through a set of declared input, output, and
bidirectional ports. Internally, a module can contain any combination of the following:
net/variable declarations (wire, reg, integer, etc.), concurrent and sequential statement blocks,
and instances of other modules (sub-hierarchies). Sequential statements are placed inside a
begin/end block and executed in sequential order within the block. However, the blocks
themselves are executed concurrently, making Verilog a dataflow language. Verilog's concept
of 'wire' consists of both signal values (4-state: "1, 0, floating, undefined") and signal
strengths (strong, weak, etc.). This system allows abstract modeling of shared signal lines,
where multiple sources drive a common net. When a wire has multiple drivers, the wire's
(readable) value is resolved by a function of the source drivers and their strengths. A subset
of statements in the Verilog language is synthesizable. Verilog modules that conform to a
synthesizable coding style, known as RTL (register-transfer level), can be physically realized
by synthesis software. Synthesis software algorithmically transforms the (abstract) Verilog
source into a netlist, a logically equivalent description consisting only of elementary logic
primitives (AND, OR, NOT, flipflops, etc.) that are available in a specific FPGA or VLSI
technology. Further manipulations to the netlist ultimately lead to a circuit fabrication
blueprint (such as a photo mask set for an ASIC or a bitstream file for an FPGA). HDL
simulators are better than gate level simulators for 2 reasons: portable model development,
and the ability to design complicated test benches that react to outputs from the model under
test. Finding a model for a unique component for your particular gate level simulator can be a
frustrating task; with an HDL language you can always write your own model. Also most
gate level simulators are limited to simple waveform based test benches which complicate the
testing of bus and microprocessor interface circuits.  Verilog is a great low level language.
Structural models are easy to design and Behavioral RTL code is pretty good. The syntax is
regular and easy to remember. It is the fastest HDL language to learn and use. However
Verilog lacks user defined data types and lacks the interface-object separation of the VHDL's
entityarchitecture model.  VHDL is good for designing behavioral models and incorporates
some of the modern object oriented techniques. It's syntax is strange and irregular, and the
language is difficult to use. Structural models require a lot of code that interferes with the
readability of the model.
 2. Xilinx Manual

2.1.Introduction

Xilinx Tools is a suite of software tools used for the design of

digital circuits implemented using Xilinx Field Programmable Gate Array (FPGA) or
Complex Programmable Logic Device (CPLD). The design procedure consists of (a)
design entry, (b) synthesis and implementation of the design, (c) functional simulation
and (d) testing and verification. Digital designs can be entered in various ways using the
above CAD tools: using a schematic entry tool, using a hardware description language
(HDL) – Verilog or VHDL or a combination of both. In this lab we will only use the
design flow that involves the use of Verilog HDL. The CAD tools enable you to design
combinational and sequential circuits starting with Verilog HDL design specifications.
The steps of this design procedure are listed below:
1. Create Verilog design input file(s) using template driven editor.
2. Compile and implement the Verilog design file(s).
3. Create the test-vectors and simulate the design (functional simulation) without using a
PLD (FPGA or CPLD).
4. Assign input/output pins to implement the design on a target device.
5. Download bitstream to an FPGA or CPLD device.
6. Test design on FPGA/CPLD device.
A Verilog input file in the Xilinx software environment consists of the following
segments:
1. Header: module name, list of input and output ports.
2. Declarations: input and output ports, registers and wires.
3. Logic Descriptions: equations, state machines and logic functions.
4. End: end module All your designs for this lab must be specified in the above Verilog
input format.
Note that the state diagram segment does not exist for combinational logic designs.

Creating a New Project Xilinx Tools can be started by clicking on the Project Navigator
Icon on the Windows desktop. This should open up the Project Navigator window on
your screen. This window shows (see Figure 1) the last accessed project.

Figure 2.1: Xilinx Project Navigator window (snapshot from Xilinx ISE software)

2.1.1 Opening a project

Select File->New Project to create a new project. This will bring up a new project
window (Figure 2) on the desktop.
Fill up the necessary entries as follows:
 Project Name: Write the name of your new project
 Project Location: The directory where you want to store the new project (Note: DO
NOT specify the project location as a folder on Desktop or a folder in the Xilinx\bin
directory.

Your H: drive is the best place to put it. The project location path is NOT to have any
spaces in it eg: C:\Nivash\TA\new lab\sample exercises\o_gate is NOT to be used) Leave
the top level module type as HDL. Example: If the project name were “o_gate”, enter
“o_gate” as the project name and then click “Next”.

Figure 2.2: New Project Initiation window (snapshot from Xilinx ISE software)
Clicking on NEXT should bring up the following window:

Figure 2.3: Device and Design Flow of Project (snapshot from Xilinx ISE software)

For each of the properties given below, click on the ‘value’ area and select from the list of
values that appear.
 Device Family: Family of the FPGA/CPLD used. In this laboratory we will be using
the Spartan3 EFPGA’s.
  Device: The number of the actual device. For this lab you may enter XC3S250E  (this
can be found on the attached prototyping board)
 Package: The type of package with the number of pins. The Spartan FPGA used in this
lab is packaged in CP132package.
 Speed Grade: The Speed grade is“-4”.
 Synthesis Tool: XST[VHDL/Verilog]
 Simulator: The tool used to simulate and verify the functionality of the design.
Model sim simulator is integrated in the Xilinx ISE. Hence choose “Model sim-
XE Verilog” as the simulator or even Xilinx ISE Simulator can be used.
 Then click on NEXT to save the entries.
All project files such as schematics, netlists, Verilog files, VHDL files, etc., will be stored
in a subdirectory with the project name. A project can only have one top level HDL
source file (or schematic). Modules can be added to the project to create a modular,
hierarchical design. In order to open an existing project in Xilinx Tools, select File-
>Open Project to show the list of projects on the machine. Choose the project you want
and click OK. Clicking on NEXT on the above window brings up the following window:

Figure 2.4: Create new source window (snapshot from Xilinx ISE software)
If creating a new source file, Click on the NEW SOURCE.
2.1.2. Creating a Verilog HDL input file for a combinational logic design
In this lab we will enter a design using a structural or RTL description
using the Verilog HDL. You can create a Verilog HDL input file (.v file) using the HDL
Editor available in the Xilinx ISE Tools (or any text editor). In the previous window,
click on the NEW SOURCE A window pops up as shown in Figure 2. 4. (Note: “Add to
project” option is selected by default. If you do not select it then you will have to add the
new source file to the project manually).

Figure 2.5: Creating Verilog-HDL source file (snapshot from Xilinx ISE software)
Select Verilog Module and in the “File Name:” area, enter the name of the Verilog source
file you are going to create. Also make sure that the option Add to project is selected so
that the source need not be added to the project again. Then click on Next to accept the
entries. This pops up the following window (Figure 2.5). In the Port Name column, enter
the names of all input and output pins and specify the Direction accordingly.
A Vector/Bus can be defined by entering appropriate bit numbers in the
MSB/LSB columns.
 Then click on Next>to get a window showing all the new source
information (Figure 2.6). If any changes are to be made, just click on Next > Next >
Finish to continue.

Figure 2.6: Define Verilog Source window (snapshot from Xilinx ISE software)

Figure 2.7: New Project Information window(snapshot from Xilinx ISE software)
 Once you click on Finish, the source file will be displayed in the sources window
in the Project Navigator (Figure 1). If a source has to be removed, just right click on the
source file in the Sources in Project window in the Project Navigator and select Remove
in that. Then select Project -> Delete Implementation Data from the Project Navigator
menu bar to remove any related files.

2.1.3. Editing the Verilog source file

The source file will now be displayed in the Project Navigator window
(Figure 2.8).The source. File window can be used as a text editor to make any necessary
changes to the source file. All the input/output pins will be displayed. Save your Verilog
program periodically by selecting the File->Save from the menu. You can also edit
Verilog programs in any text editor and add them to the project directory using “Add
Copy Source”.

Figure 2.8: Verilog Source code editor window in the Project Navigator (from Xilinx ISE
software)
2.2. Functional Simulation of Combinational Designs
2.2.1. Adding the test vectors :
To check the functionality of a design, we have to apply test vectors and
simulate the circuit. In order to apply test vectors, a test bench file is written. Essentially
it will supply all the inputs to the module designed and will check the outputs of the
module.

Example: For the 2 input OR Gate, the steps to generate the test bench are as follows: In
the Sources window (top left corner) right click on the file that you want to generate the
test bench for and select ‘New Source’ Provide a name for the test bench in the file name
text box and select ‘Verilog test fixture’ among the file types in the list on the right side
as shown in figure 2.9.

Figure 2.9: Adding test vectors to the design (snapshot from Xilinx ISE software)
Click on ‘Next’ to proceed. In the next window select the source file with which you want
to associate the test bench.
 Figure 2.10: Associating a module to a testbench (snapshot from Xilinx ISE software)
Click on Next to proceed. In the next window click on Finish.
You will now be provided with a template for your test bench. If it does not open
automatically click the radio button next to Simulation .

You should now be able to view your test bench template.

2.2.2 Simulating and Viewing the Output Waveforms
Now under the Processes window (making sure that the test bench file in the
Sources window is selected) expand the Model Sim simulator Tab by clicking on the add
sign next to it. Double Click on Simulate Behavioral Model. You will probably receive a
complier error. This is nothing to worry about – answer “No” when asked if you wish to
abort simulation. This should cause ModelSim to open. Wait for it to complete execution.
If you wish to not receive the compiler error, right click on Simulate Behavioral Model
and select process properties. Mark the checkbox next to “Ignore PreComplied Library
Warning Check
 Figure 2.11: Simulating the design (snapshot from Xilinx ISE software)

2.2.3. Saving the simulation results

To save the simulation results, Go to the waveform window of the Modelsim simulator,
Click on File -> Print to Postscript -> give desired filename and location. Note that by
default, the waveform is “zoomed in” to the nanosecond level. Use the zoom controls to
display the entire waveform. Else a normal print screen option can be used on the
waveform window and subsequently stored in Paint.
 Figure 2.12: Behavioral Simulation output Waveform (Snapshot from ModelSim)

2.2.4. Synthesis and Implementation of the Design

The design has to be synthesized and implemented before it can be
checked for correctness, by running functional simulation or downloaded onto the
prototyping board. With the toplevel Verilog file opened (can be done by double-clicking
that file) in the HDL editor window in the right half of the Project Navigator, and the
view of the project being in the Module view , the implement design option can be seen in
the process view. Design entry utilities and Generate Programming File options can also
be seen in the process view. The former can be used to include user constraints, if any and
the latter will be discussed later. To synthesize the design, double click on the Synthesize
Design option in the Processes window. To implement the design, double click the
Implement design option in the Processes window. It will go through steps like Translate,
Map and Place & Route. If any of these steps could not be done or done with errors, it
will place a X mark in front of that, otherwise a tick mark will be placed after each of
them to indicate the successful completion. If everything is done successfully, a tick mark
will be placed before the Implement Design option. If there are warnings, one can see
mark in front of the option indicating that there are some warnings. One can look at the
warnings or errors in the Console window present at the bottom of the Navigator window.
Every time the design file is saved; all these marks disappear asking for a fresh
compilation.
 Figure 2.14: Implementing the Design (snapshot from Xilinx ISE software)
The schematic diagram of the synthesized verilog code can be viewed by
double clicking View RTL Schematic under Synthesize-XST menu in the Process
Window. This would be a handy way to debug the code if the output is not meeting our
specifications in the proto type board.
By double clicking it opens the top level module showing only input(s) and
output(s) as shown below.

Figure .2.15: Top Level Hierarchy of the design

By double clicking the rectangle, it opens the realized internal logic as shown below.

Figure 2.16: Realized logic by the XilinxISE for the verilog code
 EXPERIMENT 1
REALIZATION OF A BOOLEAN FUNCTION

OBJECTIVE
Design and simulate the HDL code to realize three and four variable
Boolean functions
RESOURCES
PC installed with Xilinx tool
PROGRAM LOGIC
A multi variable Boolean function can be implemented through Verilog HDL in
two ways. First one is using primitive gates and the second one is using assign statements.
Gate primitives are predefined in Verilog, which are ready to use. They are instantiated
like modules. There are two classes of gate primitives: Multiple input gate primitives and
Single input gate primitives. Multiple input gate primitives include and, nand, or, nor,
xor, and xnor. These can have multiple inputs and a single output. Single input gate
primitives include not, buf, notif1, bufif1, notif0, and bufif0. These have a single input
and one or more outputs. Assign statements are used to define signal values as Boolean
expressions. In the example: ' out AS BS   , out is defined by the function ' AS BS  ,
but must be written in Verilog using the AND operator ( “&” ), OR operator (“|”), the
XOR operator (“^”) and the NOT operator (“~”). It is important to remember that an
assignment statement is identical to the corresponding schematic with gates wired to the
inputs and outputs to define the Boolean function. In fact, assign statements are known as
“continuous assignments” because, unlike assignment statements in a regular
programming language, they are executed continuously, just like the corresponding gates
in a schematic. 1.4.

PROCEDURE
1. Create a module with required number of variables and mention it’s input/output.
2. Write the description of given Boolean function using operators or by using the built in
primitive gates.
3. Create another module referred as test bench to verify the functionality.
4. Follow the steps required to simulate the design and compare the obtained output with
the corresponding truth table.
PROGRAM CODE
module p1(c,a,b);
input a;
input b;
output [0:6] c;
assign c[0]= a & b;
assign c[1]= a | b;
assign c[2]= ~(a & b);
assign c[3]= ~(a | b);
assign c[4]= a ^ b;
assign c[5]= ~(a ^ b);
assign c[6]= ~ a;
endmodule

//boolean function

module p1(a,b,c,f1,f2);
input a,b,c;
output f1,f2;
assign f1=(~a)&b|a&(~b)&(~c)|a&(~b)&c;
assign f2=((~a)|b)&(a|b|(~c))&(a|(~b)|c);
endmodule

EXPERIMENT 2
 FULL ADDER AND FULL SUBTRACTOR DESIGN MODELING

OBJECTIVE
To write a HDL code to describe the functions of a full Adder and subtractor.

RESOURCES
PC installed with Xilinx tool 5.3.

PROGRAM LOGIC
A full adder consists of 3 inputs and 2 outputs. Fig 2.1 shows truth table of full adder.
Use “assign” keyword to represent design in dataflow style. The output signal expressions
can be obtained from the truth table using K-maps.

Fig . 2.1. One Bit Full Adder

 Table . 2.1. Truth Table for One Bit Full Adder
This is not practical to perform subtraction only between two single bit binary
numbers. Instead , binary numbers are always multibits. The subtraction of two binary
numbers is performed bit by bit from right (LSB) to left (MSB). During subtraction of
same significant bit of minuend and subtrahend, there may be one borrow bit along with
difference bit. This borrow bit (either 0 or 1) is to be added to the next higher significant
bit of minuend and then next corresponding bit of subtrahend to be subtracted from this. It
will continue up to MSB. The combinational logic circuit performs this operation is called
full subtractor. Hence, full subs tractor is similar to half substractor but inputs in full subs
tractor are three instead of two. Two inputs are for the minuend and subtrahend bits and
third input is for borrowed which comes from previous bits subtraction. The outputs of
full adder are similar to that of half adder, these are difference (D) and borrow (b). The
combination of minuend bit (A), subtrahend bit (B) and input borrow (bi) and their
respective differences (D) and output borrows (b) are represented in a truth table 5.2. The
output signal expressions can be obtained from the truth table using K-maps.

Table 2.2. True Table for One Bit Subtractor

PROCEDURE
Create a module with required number of variables and mention it’s input/output. 2. Write the
description of the full adder in 3 styles. 3. Create another module referred as test bench to
verify the functionality. 4.
Follow the steps required to simulate the design and compare the obtained output with the
required one.
CODE
// full adder
module p10(a,b,c,sum,carry);
output sum,carry;
input a,b,c;
wire y0,y1,y2;
xor g1(y0,a,b);
and g2(y1,a,b);
xor g3(sum,y0,c);
and g4(y2,y0,c);
or g5(carry,y2,y1);
endmodule

//full subtractor
module p11(a ,b ,c ,diff ,borrow );
output diff, borrow ;
input a,b,c;
assign diff = a ^ b ^ c;
assign borrow = ((~a) & b) | (b & c) | (c & (~a));
endmodule
 Full Adder

Full Subtractor
 EXPERIMENT 3
DESIGN OF 8-BIT ARITHMETIC LOGIC UNIT
OBJECTIVE
To design a model to implement 8-bit ALU functionality
RESOURCES
PC installed with Xilinx tool
PROGRAM LOGIC
An arithmetic logic unit (ALU) is a combinational digital electronic circuit
that performs arithmetic and bitwise operations on integer binary numbers. This is in contrast
to a floating-point unit (FPU), which operates on floating point numbers. An ALU is a
fundamental building block of many types of computing circuits, including the central
processing unit (CPU) of computers, FPUs, and graphics processing units (GPUs). A single
CPU, FPU or GPU may contain multiple ALUs

Fig . 3.1. Arithmatic Logic Unit

The inputs to an ALU are the data to be operated on, called operands, and a code
(opcode) indicating the operation to be performed and, optionally, status information from a
previous operation; the ALU's output is the result of the performed operation. In many
designs, the ALU also exchanges additional information with a status register, which relates
to the result of the current or previous operations . A number of basic arithmetic and bitwise
logic functions are commonly supported by ALUs. Basic, general purpose ALUs typically
includes these operations in their repertoires:
 Arithmetic operations
 Bitwise logical operations
 Bit shift operations .
In this lab, students have to design an 8-bit ALU to implement the following operations:

Table 3.1 also illustrates the encoding of the control input

The 4 - bit ALU has the following inputs:
 A: 4-bit input
 B: 4-bit input
 Cin: 1-bit input
 Output: 4-bit output
 Cout: 1-bit output
 Control: 2-bit control input
The following points should be taken care of:
 Use a case statement (or a similar ‘combinational’ statement) that checks the input
combination of “Code” and acts on A, B, and Cin as described in Table1.
 The above circuit is completely combinational. The output should change as soon as the
code combination or any of the input changes.
 You can use arithmetic and logical operators to realize your design.
PROCEDURE
1. Create a module with required number of variables and mention it’s input/output.
2. Write the description of the ALU by using case statements.
3. Create another module referred as test bench to verify the functionality
4. Follow the steps required to simulate the design and compare the obtained output with the
required one.

CODE
//8 bit ALU
module p13(z,a,b,sel);
input [7:0]a,b;
input [3:0]sel;
output [7:0]z;
reg [7:0]z;
always@(sel,a,b)
begin
case(sel)
4'b0000: z=a+b;
4'b0001: z=a-b;
4'b0010: z=b-1;
4'b0011: z=a*b;
4'b0100: z=a&&b;
4'b0101: z=a||b;
4'b0110: z=!a;
4'b0111: z=~a;
4'b1000: z=a&b;
4'b1001: z=a|b;
4'b1010: z=a^b;
4'b1011: z=a<<1 ;
4'b1100: z=a>>1;
4'b1101: z=a+1;
4'b1110: z=a-1;
end case
end
end module
 EXPERIMENT 4
DESIGN OF CODE CONVERTERS
OBJECTIVE
To Design and simulate the HDL code for the following combinational circuits
a. 4 - Bit binary to gray code converter
b. 4 - Bit gray to binary code converter
RESOURCES
PC installed with Xilinx tool
PROGRAM LOGIC
Binary to gray code converter logic
This conversion method strongly follows the EX-OR gate operation between binary bits. The
steps to perform binary to grey code conversion are given below.
a. To convert binary to grey code, bring down the most significant digit of the given binary
number, because, the first digit or most significant digit of the grey code number is same as
the binary number. b. To obtain the successive grey coded bits to produce the equivalent grey
coded number for the given binary, add the first bit or the most significant digit of binary to
the second one and write down the result next to the first bit of grey code, add the second
binary bit to third one and write down the result next to the second bit of grey code, follow
this operation until the last binary bit and write down the results based on EX-OR logic to
produce the equivalent grey coded binary. Gray to binary code converter logic This
conversion method also follows the EX-OR gate operation between grey & binary bits. The
steps to perform grey code to binary conversion are given below. a. To convert grey code to
binary, bring down the most significant digit of the given grey code number, because, the first
digit or the most significant digit of the grey code number is same as the binary number
b. To obtain the successive second binary bit, perform the EX-OR operation between the first
bit or most significant digit of binary to the second bit of the given grey code. c. To obtain the
successive third binary bit, perform the EX-OR operation between the second bit or most
significant digit of binary to the third MSD (most significant digit) of grey code and so on for
the next successive binary bits conversion to find the equivalent.
PROCEDURE
1. Create a module with required number of variables and mention it’s input/output.
2. Write the description of the code converter using data flow model or gate level model.
3. Create another module referred as test bench to verify the functionality.
4. Follow the steps required to simulate the design and compare the obtained output with the
required one.
CODE
// binary to gray code converter
module p7(b,g);
input [3:0] b;
output [3:0] g;
reg [3:0] g;
always@(b)
begin g[3]=b[3];
g[2]=b[3]^b[2];
g[1]=b[2]^b[1];
g[0]=b[1]^b[0];
end
end module
//gray to binary converter
module p8(g,b);
input [3:0] g;
output [3:0] b;
reg [3:0] b;
always@(g)
begin
b[3]=g[3];
b[2]=b[3]^g[2];
b[1]=b[2]^g[1];
b[0]=b[1]^g[0];
end
end module
 EXPERIMENT 6
1:8 DEMUX , 3:8 DECODER , 2 BIT COMPARATOR

OBJECTIVE
To write HDL codes for SR, JK, D, T flip flops and verify its functionality.
RESOURCES
PC installed with Xilinx tool
PROGRAM LOGIC

De-multiplexer

A De-multiplexer is a combinational circuit that has only 1 input line and 2 N output lines.
Simply, the multiplexer is a single-input and multi-output combinational circuit. The
information is received from the single input lines and directed to the output line. On the
basis of the values of the selection lines, the input will be connected to one of these outputs.
De-multiplexer is opposite to the multiplexer.

Unlike encoder and decoder, there are n selection lines and 2 n outputs. So, there is a total of
2n possible combinations of inputs. De-multiplexer is also treated as De-mux.

There are various types of De-multiplexer which are as follows:

1×2 De-multiplexer:

In the 1 to 2 De-multiplexer, there are only two outputs, i.e., Y 0, and Y1, 1 selection lines, i.e.,
S0, and single input, i.e., A. On the basis of the selection value, the input will be connected to
one of the outputs. The block diagram and the truth table of the 1×2 multiplexer are given
below.
The logical expression of the term Y is as follows:

Y0=S0'.A
Y1=S0.A

Logical circuit of the above expressions is given below:

DECODER
 EXPERIMENT 7
HDL MODEL FOR FLIP FLOPS
OBJECTIVE
To write HDL codes for SR, JK, D, T flip flops and verify its functionality.
RESOURCES
PC installed with Xilinx tool
PROGRAM LOGIC
Each flip-flop stores a single bit of data, which is emitted through the Q output
on the output section side. Normally, the value can be controlled via the inputs to the input
side. In particular, the value changes when the clock input, marked by a triangle on each flip-
flop, rises from 0 to 1 (or otherwise as configured); on this rising edge, the value changes
according to the tables below

Table 5.1 Truth tables of D, T, SR, JK flip flops

 Another way of describing the different behaviour of the flip-flops is in English text. D Flip-
Flop: When the clock triggers, the value remembered by the flip-flop becomes the value of
the D input (Data) at that instant. T Flip-Flop: When the clock triggers, the value remembered
by the flip-flop either toggles or remains the same depending on whether the T input (Toggle)
is 1 or 0. J-K Flip-Flop: When the clock triggers, the value remembered by the flip-flop
toggles if the J and K inputs are both 1, remains the same if they are both 0; if they are
different, then the value becomes 1 if the J (Jump) input is 1 and 0 if the K (Kill) input is 1.
S-R Flip-Flop: When the clock triggers, the value remembered by the flip-flop remains
unchanged if R and S are both 0, becomes 0 if the R input (Reset) is 1, and becomes 1 if the S
input (Set) is 1. The behaviour in unspecified if both inputs are 1.
PROCEDURE
1. Create a module with required number of variables and mention it’s input/output. 2. Write
the description of the flip flops using behavioural model 3. Create another module referred as
test bench to verify the functionality. 4. Follow the steps required to simulate the design and
compare the obtained output with the required one.
CODE
//SR flipflop
module p14(s,r,clk,q,qb);
input s,r,clk;
output q,qb;
reg q,qb;
reg [1:0]sr;
wire qp=1'b0;
always@(posedge clk)
begin
sr={s,r};
begin
case (sr)
2'd0:q=qp;
2'd1:q=1'b0;
2'd2:q=1'b1;
2'd3:q=1'bX;
end case
end
qb=~q;
end
end module

//JK flipflop

module p15(j,k,clk,q,qb);
input j,k,clk;
output q,qb;
reg q,qb;
reg [1:0]jk;
wire qp=1'b0;
always@(posedge clk)
begin jk={j,k};
begin
case (jk)
2'd0:q=qp;
2'd1:q=1'b0;
2'd2:q=1'b1;
2'd3:q=~q;

end case
end
qb=~q;
end
endmodule
//D flipflop
module p16(q,din,clk);
output q;
reg q;
input din ;
wire din ;
input clk ;
always @ (posedge (clk))
begin
q = din ;
end
end module

//T flipflop
module p17(q,t,clk);
output q;
reg q;
input t ;
input clk ;
always @ (posedge (clk))
begin
q = ~t;
end
end module
T FF

S R FF

JK FF

EXPERIMENT 6
DESIGN OF COUNTERS
OBJECTIVE
To write HDL codes for the following counters :
a. Binary counter
b. BCD counter (Synchronous reset and asynchronous reset)
RESOURCES
PC installed with Xilinx tool
PROGRAM LOGIC
Counter is a sequential circuit. A digital circuit which is used for counting
pulses is known as counter. Counter is the widest application of flip-flops. It is a group of
flipflops with a clock signal applied. Counters are of two types.
 Asynchronous or ripple counters.
 Synchronous counters.
Asynchronous counters are called as ripple counters, the first flip-flop is
clocked by the external clock pulse and then each successive flip-flop is clocked by the
output of the preceding flip-flop. The term asynchronous refers to events that do not have a
fixed time relationship with each other. An asynchronous counter is one in which the flip-
flops within the counter do not change states at exactly the same time because they do not
have a common clock pulse In synchronous counters, the clock inputs of all the flip-flops are
connected together and are triggered by the input pulses. Thus, all the flip-flops change state
simultaneously (in parallel).
A counter is a register capable of counting the number of clock pulses
arriving at its clock input. Count represents the number clock pulses arrived. A specified
sequence of states appears as the counter output. The name counter is generally used for
clocked sequential circuit whose state diagram contains a single cycle. The modulus of a
counter is the number of states in the cycle. A counter with m states is called a modulo-m
counter or divide-by-m counter.

A counter with a non-power-of-2 modulus has extra states that are not used
in normal operation. There are two types of counters, synchronous and asynchronous. In
synchronous counter, the common clock is connected to all the flip-flops and thus they are
clocked simultaneously.
 Fig. 6.1 General structure of a counter’s state diagram – a single cycle
Asynchronous Decade Counters
The modulus is the number of unique states through which the counter will sequence. The
maximum possible number of states of a counter is 2nwhere n is the number of flip-flops.
Counters can be designed to have a number of states in their sequence that is less than the
maximum of 2n . This type of sequence is called a truncated sequence. One common
modulus for counters with truncated sequences is 10 (Modules10). A decade counter with a
count sequence of zero (0000) through 9 (1001) is a BCD decade counter because its 10-state
sequence produces the BCD code. To obtain a truncated sequence, it is necessary to force the
counter to recycle before going through all of its possible states. A decade counter requires
4flip-flops. One way to make the counter recycle after the count of 9 (1001) is to decode
count 10 (1010) with a NAND gate and connect the output of the NAND gate to the clear
(CLR) inputs of the flip-flops, as shown in Figure 6.1

Figure 6.2 Asynchronous Decade Counter

Synchronous Decade Counters

 Figure 6.3 Synchronous Decade Counter
It can be seen from Figure 8.2, that the external clock pulses (pulses to be
counted) are fed directly to each of the J-K flip-flops in the counter chain and that both the J
and K inputs are all tied together in toggle mode, but only in the first flip-flop, flipflop FFA
(LSB) are they connected HIGH, logic “1” allowing the flip-flop to toggle on every clock
pulse.
Then the synchronous counter follows a predetermined sequence of states in response to the
common clock signal, advancing one state for each pulse. The J and K inputs of flip-flop FFB
are connected directly to the output QA of flipflop FFA, but the J and K inputs of flip-flops
FFC and FFD are driven from separate AND gates which are also supplied with signals from
the input and output of the previous stage. These additional AND gates generate the required
logic for the JK inputs of the next stage. If we enable each JK flip-flop to toggle based on
whether or not all preceding flipflop outputs (Q) are “HIGH” we can obtain the same
counting sequence as with the asynchronous circuit but without the ripple effect, since each
flip-flop in this circuit will be clocked at exactly the same time.
PROCEDURE
1. Create a module with required number of variables and mention it’s input/output.
2. Write the description of the counter to count required number of states and to satisfy its
conditions.

3. Create another module referred as test bench to verify the functionality.

 4. Follow the steps required to simulate the design and compare the obtained output with the
required one.

CODE
// binary counter
module p18(clk,count );
output [3:0] count ;
reg [3:0] count ;
input clk ;
wire clk ;
initial count = 0;
always @ (posedge (clk))
begin
count <= count + 1;
end
end module
//BCD counter
module p19(clk ,reset ,dout );
output [3:0] dout ;
reg [3:0] dout ;
input clk ;
wire clk ;
input reset ;
wire reset ;

initial
dout = 0 ;
always @ (posedge (clk))
begin
if (reset)
dout <= 0;
else if (dout<=9)
begin
dout <= dout + 1;
end
else if (dout==9)
begin
dout <= 0;
end
end
end module