Lecture 2 (Parallelism)
Lecture 2 (Parallelism)
lecture 2 (Parallelism)
Reference:
ADVANCED COMPUTER ARCHITECTURE AND PARALLEL PROCESSING
Outlines
• Some Elementary Concepts.
• Parallelism physical effect.
• Parallelism Reasons (Motivations).
• Challenges.
• Transparency in Distributed Systems.
Event p and q are independent, can’t have mutual effect because no one
from them can happen in case future of another.
Look in s1 see at first event p and then q.
Look in s3 will be change order in opposite.
Look in s2 can form that both events happen together.
Note: have never information about which event occur before.
For exact describe event in distributed system can’t use full (linear) ordering
(format), while for a lot of practical cases like this model is suitable.
Not each two events show ordering in time.
Not each distributed system give:
Parallelism Reasons
Physical restriction.
Reliability, Accessibility.
-HA (High Availability)
Efficiency
-HPC (High Performance Computing)
Synchronization restriction.
Physical Restriction:
1. System, which is his spirit(matter)- “from nature” physically distributed, ex.
Sensor Network,
2. Sequence system here can’t use. Ex branches of organization.
4. System reflects natural distributed inputs, which are data and control
process. Ex. systolic array, Industrial Process Monitoring.
https://www.mdpi.com/2227-9717/5/3/35/htm
5. For example, // system control breaks when haven’t response for his input
immediately not until finish his assigned time.
Note:
Control system has wide technological processes:
Reliability:
1. Distribution system can be open additional redundant component for raising
all dependency.
3. Can increase quality service and efficiency, decrease response time but
functionality remains.
Performance:
1. May be major reason examination and exploitation.
Time critical application (ex. Reactive system with strait time restriction,
weather, finances).
Time-consuming; big data or long loop.
More rising demand application than efficiency machine.
9. Highest execute is can obtain from usable multiple processors at same time
(simultaneously).
Synchronies circuit:
What do processor between two edge clocks?
**** Wait***** (Clock restriction)
Asynchronies circuit:
Never clock:
1- Smaller needed (mobile equipment).
2- Less emitting (noise).
3- More execute (mean speed component).
4- Different work can execute simultaneously, different speeds.
5- Less dimension, more complex application.
Negotiable solution: mixed circuits.
Intel Pentium 4 has some parts asynchronous.
SUNFLEETzero- prototype asynchronous chips.
6- Better scalability.
Security
Denial of service attacks
Mobile code
Scalability
Transparency