Rajiv Gandhi University of Knowledge Technologies

(Act No. 8 of 2016 of Telangana Government)

Basar (Village and Mandal), Nirmal District, Telangana State – 504107, India
Website: www.rgukt.ac.in

Laboratory Manual
EC2801 Analog Circuits Lab

Department of Electronics & Communication Engineering

 List of Experiments

1. Clipping and Clamping circuits

2. LC, CLC filters
3. Voltage Regulators
4. RC-coupled amplifier (single stage & two-stage)
5. Darlington Emitter follower
6. Power amplifiers (Class-B push pull power amplifier)
7. Feedback amplifiers:
(i) Voltage series feedback amplifier
(ii) Voltage shunt feedback amplifier
(iii) Current shunt feedback amplifier
(iv) Current series feedback amplifier
8. Oscillators:
(i) RC-phase shift oscillator
(ii) Wein-bridge oscillator
(iii) Hartley oscillator
(iv) Colpits oscillator
9. Parameters of Operational Amplifiers (Input bias current, Input Offset current,
Input Offset voltage & CMMR
10. Applications of Operational Amplifiers
(i) Inverting op-amp & Non-Inverting op-amp
(ii) Voltage follower, Summing amplifier
(iii) ZCD, Schmitt trigger
(iv) Full wave precision rectifier
11. Wave form generators by using op-amp
(i) Monostable Multi vibrator
(ii) Astable Multi vibrator
12. Digital to Analog converters
13. Analog to Digital converter
14. Switched capacitor circuit
 1. CLAMPING CIRCUITS
AIM:

To design and verify the characteristics of different clamping circuits with different reference
voltage.

COMPONENTS REQUIRED:
1. Capacitor 10 μ F (1 No)
2. Diode IN4007 (1 No)
3. Bread Board
4. Connecting wires
5. CRO & Probes
6. Function Generator

THEORY:

“A clamping circuit is one that takes an input waveform and provides an output that is
a faithful replica of its shape but has one edge tightly clamped to the zero voltage
reference point”.

There are various types of Clamping circuits, which are mentioned below:
1. Positive Clamping Circuit.
2. Negative Clamping Circuit.
3. Positive Clamping with positive reference voltage.
4. Negative Clamping with positive reference voltage.
5. Positive Clamping with negative reference voltage.
6. Negative Clamping with negative reference voltage.
 CIRCUIT DIAGRAM: MODEL GRAPH:

INPUT WAVEFORM OUTPUT WAVEFORM

1. Positive Clamping Circuit:

2. Positive Clamping with negetive reference voltage:

3. Positive Clamping with Positive reference voltage:

4. Negative Clamping Circuit:

5. Negative Clamping with positive reference voltage:

6. Negative Clamping with negative reference voltage:

PROCEDURE:
1. Connect the circuit elements as shown in the Circuit Diagram.
2. A Sinusoidal voltage of 10V and frequency of 1kHz Hz is applied
to the circuit as an input.
3. Note down the corresponding output wave forms in C.R.O and
plot the graph.

RESULT:
Hence different clamping circuits were designed and outputs were verified.
 1. CLIPPING CIRCUITS
AIM:

To design and verify waveforms of different clipping circuits with different reference
voltage.
COMPONENTS REQUIRED:
1. Resistors 1kΩ (1No.)
2. Diode 1N4007 (2No.)
3. Bread Board
4. Connecting wires
5. CRO & Probes
6. Function Generator
7. Regulated Power Supply (0 - 30V)
THEORY:

The non-linear semiconductor diode in combination with resistor can function as clipper
circuit. Energy storage components like capacitor etc. are not required in the basic process of
clipping. These circuits will select part of an arbitrary waveform which lies above or below
some particular reference voltage level and that selected part of the waveform is used for
transmission. So they are referred as voltage limiters, current limiters, amplitude selectors orslicers.

There are three different types of clipping circuits.

1) Positive Clipping circuit.
2) Negative Clipping.
3) Positive and Negative Clipping (slicer).
In positive clipping circuit positive cycle of Sinusoidal signal is clipped and negative
Portion of sinusoidal signal is obtained in the output. If reference voltage is added, instead of
complete positive cycle that portion of the positive cycle which is above the reference voltage value
is clipped.
In negative clipping circuit instead of positive portion of sinusoidal signal, negative
Portion is clipped.
In slicer both positive and negative portions of the sinusoidal signal are clipped.
 Operation can be explained based on equations as shown below:
1. When Vi < VR + Vγ, Diode is reverse biased (OFF). Output follows the input.
2. When Vi > VR + Vγ, Diode is forward biased (ON). And the Output is equal to (V R + Vγ).
Here Vi is Supplied input voltage, VR is connected reference voltage, Vγ is diode cut-in voltage

CIRCUIT DIAGRAMS MODEL GRAPHS

Input Waveforms Output waveforms

1) Positive clipper:

2) Positive clipper with positive reference voltage:

3) Positive clipper with negative reference voltage:

4) Negative clipper:

5) Negative clipper with negative reference voltage:

6) Negative clipper with positive reference:

7) Slicer (Two level clippers):

 PROCEDURE:
1. Connect the circuit elements as shown in the Circuit Diagram.
2. A Sinusoidal voltage of 10V and frequency of 1kHz is applied
to the circuit as an input.
3. Note down the corresponding output wave forms from C.R.O and
Enter the values in table.
4. Plot the graph from above readings.

Tabular column:

RESULT:
Hence different clipping circuits were designed and corresponding outputs were verified.
 2. HALF WAVE RECTIFIER WITH LC, CLC FILTERS &
WITHOUT FILTER

Aim: To plot and examine the input and output wave forms and various parameters of half wave
rectifier with LC, CLC filters and without filters.
Apparatus:

1. Bread board
2. Diodes 1N4007 – 1 No
3. Digital multi meters – 2 No’s
4. Resistor’s – 3 No.
5. Capacitor’s – 3 No.
6. Inductor’s – 3 No.
7. CRO with probes
8. Connecting wires
9. Transformer (09–0–09V/1A) – 1 No.
Circuit Diagram

Half Wave Rectifier Without Filter

Half Wave Rectifier With “L”- Section Filter

Half Wave Rectifier With “π” Section Filter

Procedure

Procedure For Without Filter

1. Connect the circuit as per the circuit diagram shown in fig.1.
2. Note down the Vm (AC Volts) at the secondary of the transformer by using digital
multimeter and also measure the no load voltage (VNL as DC Volts) by removing the
load from the circuit.
3. Now connect the load of 1kΩ then measure the values of Idc, Vdc, Iac and Vac.
4. Take the above readings by varying the RL in steps of 1kΩ.
5. Observe the output wave forms of rectifiers by using CRO.
6. Draw the wave forms on the graph sheet.

Observation Table: Half Wave Rectifier Without Filter

Vm =__ V(AC) VNL =___V(DC)

Vdc Idc Vac RL =

RL Ripple Factor %regulation =
(V) (mA) (V) Vdc/Idc
r = Vac/Vdc
(VNL-VFL)x100 / VFL

Expected Graphs: Half Wave Rectifier Without Filter

Procedure For With Filter
1. Connect the circuit L-Section filter to half wave rectifier as per the circuit diagram.
2. Note down the Vm (AC Volts) at the secondary of the transformer by using digital multi
meter and also measure the no load voltage (VNL as DC Volts) by removing the load
from the circuit.
3. Now connect the load of 1kΩ then measure the values of Idc, Vdc, Iac and Vac.
4. Take the above readings by varying the RL in steps of 1kΩ.
5. Repeat the above steps 1, 2, 3 and 4 for ∏-section filter.
6. Observe the output wave forms of rectifiers by using CRO.
7. Draw the wave forms on the graph sheet.
Half Wave Rectifier With Filter
Vm =……..V(AC) VNL =…….V (L-section) VNL = ……. V ( ∏- section )
Vdc Idc Vac RL =
RL r=
Filter (V) (mA) (V) Vdc/ Idc %regulation =
Vac/Vdc
(VNL-VFL)x100 / VFL

L-
Section

∏-
section

Half Wave Rectifier With ∏-Filter

Result: Input & Output Waveforms of Half Wave Rectifier with L &  section
filters are studied for various loads and observations are put in the tabular form.
 2. FULLWAVE RECTIFIER WITH LC, CLC FILTERS &
WITHOUT FILTER

Aim: To plot and examine the input and output wave forms and various parameters of full wave
rectifier with LC, CLC filters and without filters.
Apparatus:

1. Bread board
2. Diodes 1N4007 – 4 No
3. Digital multi meters – 2 No’s
4. Resistor’s – 3 No.
5. Capacitor’s – 1 No.
6. Inductors – 3 No.
7. CRO with probes
8. Connecting wires
9. Transformer (09–0–09V/1A) – 1 No.
Circuit diagram

Full Wave Rectifier Without Filter

Full wave rectifier with “L”- section filter

Full Wave Rectifier with “ ” Section Filter

procedure for without filter

1. Make the connections as per the circuit diagram.

2. Note down the Vm (AC Volts) at the secondary of the transformer by using digital
multimeter and also measure the no load voltage (VNL as DC Volts) by removing the
load from the circuit.
3. Now connect the load of 1kΩ then measure the values of Idc, Vdc, Iac and Vac.
4. Take the above readings by varying the RL in steps of 1kΩ.
5. Observe the output wave forms of rectifiers by using CRO.
6. Draw the wave forms on the graph sheet.
Observation Table: Full Wave Rectifier Without Filter
Vm = V(AC) VNL = V(DC)

RL = Ripple
Vdc Idc Vac %regulation = (VNL-
RL Factor
(V) (mA) (V) Vdc/Idc
r=
VFL)x100 / VFL
Vac/Vdc

Expected Graphs: Full Wave Rectifier Without Filters

Procedure for with filter
1. Connect the circuit L-Section filter to full wave rectifier as per the circuit diagram.
2. Note down the Vm (AC Volts) at the secondary of the transformer by using digital multi
meter and also measure the no load voltage (VNL as DC Volts) by removing the load
from the circuit.
3. Now connect the load of 1kΩ then measure the values of Idc, Vdc, Iac and Vac.
4. Take the above readings by varying the RL in steps of 1kΩ.
5. Repeat the above steps 1, 2, 3 and 4 for ∏-section filter.
6. Observe the output wave forms of rectifiers by using CRO.
7. Draw the wave forms on the graph sheet.
Full Wave Rectifier With Filter

Vm =……..V(AC) VNL =…….V L-section VNL = ……. V ∏- section

RL = %regulation =
Vdc Idc Vac
RL Vdc/ r=
Filter (V) (mA) (V)
Idc Vac/Vdc (VNL-VFL)x100
/ VFL

L- Section

∏- section

Full Wave Rectifier With ∏-Filter

Result: Input & Output Waveforms of Full Wave Rectifier with L &  section
filters are studied for various loads and observations are put in the tabular form.
 3. VOLTAGE REGULATORS

Aim: To study zener diode as voltage regulator

Apparatus: Zener diode, resistor, rheostat, voltmeter, ammeter, DC source and bread board.

Theory:

A zener diode functions as an ordinary diode when it is forward biased. It is a

specially designed device to operate in the reverse bias. When it is in the reverse
breakdown region, the zener voltage Vzremains almost constant irrespective of the current Iz
through it. A series resistor Rs is used to limit the zener current below its maximum
current rating. The current through Rs is given by the expression Is = Iz + IL, where IL is the
current through the load resistor RL. The value of RS must be properly selected to fulfil the
following condition requirements.

When the input voltage, VI increases IL remains the same, IS and Iz increases.
Similarly if input voltage decreases, IL remains the same, IS and Iz decreases. But if Iz falls
lower than the minimum zener current enough to keep the zener in the breakdown region,
the regulation will cease and output voltage decreases. A low input voltage can cause the
regulator fail to regulate. The series resistance should be selected between RSmax and RSmin
which are given by the expressions,

RSmin = [Vlmax −
Vz]⁄Izmax RSmax = [Vlmin
− Vz]⁄[Izmin + L]

Procedure

1. Wire up the circuit on the bread board after testing all the components.

2. Keep the load constant. Note down the output voltage varying input from 8V to
14V in steps of 1V. Plot the line regulation graph with Vi along x-axis and Vo
along y-axis. Calculate percentage line regulation using the expression
(LVo⁄LVi)x100%.

3. Keep the input voltage constant (say 10V) and note down the output voltage for
various values of load current starting from 0 to 5 mA, by varying RL using a
rheostat. Plot the load regulation graph with IL along x-axis and Vo along y-axis.
 4. To calculate percentage load regulation, mark VNL and VFL on y-axis on the load
regulation graph. VNL is the output voltage in the absence of load resistor and VFL is
the output voltage corresponding to rated IL (here, 5 mA). Calculate the percentage
load regulation VR as per the equation,

𝑉𝑁𝐿 − 𝑉𝐹𝐿
𝑉𝑅 = × 100%
𝑉𝑁𝐿

Circuit Diagram

Tabular Column

Line Regulation

Keeping load current constant at IL = 5mA, The input voltage is varied from 8 V to
14V and corresponding observations are made.

Vin (volts) Vo (volts)

Load Regulation

Keeping input voltage at 10V, the load current is varied from 0 to 5 mA and
observations are made. For taking reading corresponding to no load ( IL = 0 ), the loading
rheostat may be disconnected.

IL mA Vo(volts)

Expected Output Plots

Line Regulation Load Regulation

Precautions

(a) Connections should be tight

(b) Handle the equipment with care

Result: Studied how Zener diode is used as a voltage regulator.

 4. RC COUPLED AMPLIFIER

Aim: To design a RC coupled single stage & two stage FET/BJT amplifier and determination of
the gain-frequency response, input and output impedances.

Apparatus:

Transistor - BC 107, capacitors, resistor, power supply, CRO, function generator, multimeter, etc.

Theory:

Single Stage
RC coupled amplifier is a basic type of amplifier with the various stages present in it. In
other words, if we describe RC coupled amplifier we can say that an amplifier that consists of
resistors and capacitors which acts a voltage divides and couplers to form multiple/single stage for
better amplification. These are the basic circuits that are present in the various types of electronic
equipment especially in RF signal or other communication devices as it helps in improving the
signal strength through amplification. Single-stage RC coupled amplifier can be termed as a pre
amplification circuit. Because these circuits are designed to improve the strength of the weak
signals for the further amplification process.

Two Stage
The experiment performed here is consists of a two-stage RC coupled amplifier. This is
very efficient in terms of gain. The output of the first stage is coupled to the second stage as input
through the capacitor. The capacitor is also known for blocking the DC signals and providing the
smoothing effect to the signals obtained at the output. As the gain obtained at the two stages will
be different this gain values obtained are plotted on the curve with the frequency values. The final
gain will be calculated with the product of the individual gains obtained at each stage. The curve
obtained from this is known as the frequency response of the amplifier.
Circuit Diagram

RC Coupled Amplifier Single Stage

RC Coupled Amplifier Two Stage

Design
Procedure

1. The input signal is applied with the function generator.

2. The values of the voltage are observed and noted at the first stage and the second stage.
3. Based on the values noted the gains at the individual stages are calculated.
4. This is continued for multiple frequencies.
5. Finally, the graph is plotted in between the gain values and the multiple frequencies
applied to the circuit.

Model Graph (Frequency Response)

Tabular Column

Sl No. Frequency VO(volts) Gain=VO/Vi Gain(dB)=20log VO/Vi

Result:
 5. DARLINGTON EMITTER FOLLOWER

To design a BJT Darlington Emitter follower and determine the gain, input and
Aim: output impedances.

Apparatus:

Transistor - BC 107, capacitors, resistor, power supply, CRO, function generator,

multimeter, etc.

Theory:
In Darlington connection of transistors, emitter of the first transistor is directly
connected to the base of the second transistor. Because of direct coupling dc output current of
the first stage is (1+hfe )Ib1.If Darlington connection for n transistor is considered, then due to
direct coupling the dc output current foe last stage is (1+hfe ) n times Ib1 .Due to very large
amplification factor even two stage Darlington connection has large output current and output
stage may have to be a power stage. As the power amplifiers are not used in the amplifier
circuits it is not possible to use more than two transistors in the Darlington connection. In
Darlington transistor connection, the leakage current of the first transistor is amplified by the
second transistor and overall leakage current may be high, which is not desired.

Circuit Diagram
DC Analysis

Procedure

1. Connect the circuit as per the circuit diagram.

2. Set Vi = 1 volt (say), using the signal generator

3. Keeping the input voltage constant, vary the frequency from 0Hz to 1MHz in regular
steps of 10 and note down corresponding output voltage.

4. Plot the frequency response: Gain (dB) vs Frequency (Hz).

5. Find the input and output impedance.

6. Calculate the bandwidth from the graph.

7. Note down the phase angle, bandwidth, input and output impedance.
Design:

Given VCEQ = VCE2 = 6v

ICQ = IC2 = 5mA

Assume β for SL100 = 100

VCC = 12v

VE2 = VCC  12 = 6v
2 2

IE2RE = VE2

VE2 6
RE =   1.2k [ IE2  IC2 ]
IE2 5 103

R E  1.2k

VB1  VBE1  VBE2  VE2

VB1  0.7  0.7  6

VB1  7.4v

IC2  5 103
IB2    0.05mA
β 100

IC1 IB2 0.05

IB     0.0005mA
1
β β 100

10IB1R1  VCC - VB1

12 - 7.4
 R1   920k [Use R1  1M]
10  0.0005 10-3

VB1
R 2  1644k
9I
B

R 2  1.5M


General Procedure for Calculation:

1. Input Impedance

a. Connect a Decade Resistance Box (DRB) between input voltage source and
the base of the transistor (series connection).
b. Connect ac voltmeter (0-100mV) across the biasing resistor R2.
c. Vary the value of DRB such that the ac voltmeter reads the voltage half of
the input signal.
d. Note down the resistance of the DRB, which is the input impedance.

2. Output Impedance

a. Measure the output voltage when the amplifier is operating in the mid-band
frequency with load resistance connected (V load).
b. Measure the output voltage when the amplifier is operating in the mid-band
frequency without load resistance connected (V no-load).
Vload Vnoload
O  100%
c. Substitute these values in the formula Z Vload

3. Bandwidth

a. Plot the frequency response

b. Identify the maximum gain region.
c. Drop a horizontal line bi –3dB.
d. The –3dB line intersects the frequency response plot at two points.
e. The lower intersecting point of –3dB line with the frequency response plot
gives the lower cut-off frequency.
f. The upper intersecting point of –3dB line with the frequency response plot
gives the upper cut-off frequency.
g. The difference between upper cut-off frequency and lower cut-off
frequency is called Bandwidth. Thus Bandwidth = fh – fl.

4. To Find Q-Point

a. Connect the circuit as per circuit diagram

b. Switch on the DC source [switch off the AC source]
c. Measure voltage at VB2, VE2 & VC2 with respect to ground
& also measure
VCE2  VC2 - VE2
IC2  IE2  VE2
R
E
Q - Point  [VCE2 , IC2 ]
Model Graph: (Frequency Response)

Tabular Column

Sl No. Frequency VO (volts) Gain = VO/Vi Gain (dB) =20log VO/Vi

Result:

Theoretical Practical

Input impedance

Output impedance

Gain (Mid band)

Bandwidth
 6. TESTING OF CLASS B (TRANSFORMER LESS) PUSH
PULL POWER AMPLIFIER

Aim: Testing of a complementary symmetry Class B (Transformer less) Push Pull power
amplifier.

Apparatus:

Power Transistors (SL100 and SK100), Resistors, load resistor, Capacitors, function
generator, DC power supply and CRO. Q1-SL100 Q2-SK100 R1=R2=1KΩ R3=100Ω
C1=C2=10FRL=12 Ω

Theory:

Class B amplifier is one which gives half (180º) cycle as output signal for one
complete cycle (360º) of input signal. Complementary symmetry class B power amplifier
needs two power transistors, among that one is NPN and other is pnp power transistor. The
main advantage of this amplifier is that the absence of the transformer which is more
expensive, bulky and heavy. This type of transformer has maximum efficiency equal to
78.5%. A single input signal is applied to the base of both transistors, the transistors, being
opposite type, will conduct on opposite half cycles of the input. Both the transistors are
biased at cut off regions of their output characteristics, so that one of the transistors conducts
during each half cycle. During a complete cycle of the input a complete cycle of output signal
is developed across the load. One disadvantage of the circuit is the need for two separate
voltage supplies.

Procedure:

1. Make the connections as shown in the Fig. and take proper care while giving biasing
voltage.
2. Apply the input signal at a frequency of 1 kHz-10 kHz.
3. Adjust the input voltage (peak) equal to DC supply i.e. Vm=VCC. If the output voltage is
sine wave then note the magnitude of output voltage, otherwise decrease the input till the
output remain sinusoidal and then note the magnitude of output voltage.
4.Calculate Power input, output and efficiency.
Circuit Diagram

IDC

Tabular Column

Vo (p-p) in
RL( ) IDC (A) PAC (W) PDC (W)
volts

Calculation

1. The DC input power is calculated as

PiDC = Vdc IDC, VDC=VCC.

2. Ac output power is PoAC = VM2/2RL.

3. Efficiency is calculated as = PoDC/PiDC.
Waveforms

Result:
 7. FEEDBACK AMPLIFIERS
Aim:

To design and test the current-series and voltage shunt feedback amplifier and to calculate
the following parameters with and without feedback.
1. Mid band gain.
2. Bandwidth and cut-off frequencies.
3. Input and output impedance

Apparatus:

S.NO APPARATUS SPECIFICATION QUANTITY

1. Power supply (0-30)V 1
2. Function Generator (0-20M)Hz 1
3. CRO 1
4. Transistor BC107 1
5. Resistor
6. Capacitor
7. Connecting Wires

Theory:

 Series Feedback Amplifier

The current series feedback amplifier is characterized by having shunt sampling and
series mixing. In amplifiers, there is a sampling network, which samples the output and gives
to the feedback network. The feedback signal is mixed with input signal by either shunt or
series mixing technique. Due to shunt sampling the output resistance increases by a factor of
‘D’ and the input resistance is also increased by the same factor due to series mixing. This is
basically trans conductance amplifier. Its input is voltage which is amplified as current.
 Shunt Feedback Amplifier

In voltage shunt feedback amplifier, the feedback signal voltage is given to the
base of the transistor in shunt through the base resistor R B. This shunt connection tends to
decrease the input resistance and the voltage feedback tends to decrease the output
resistance. In the circuit RB appears directly across the input base terminal and output
 collector terminal. A part of output is feedback to input through R B and increase in IC
decreases IB. Thus negative feedback exists in the circuit. So this circuit is also called
voltage feedback bias circuit. This feedback amplifier is known a transresistance amplifier.
It amplifies the input current to required voltage levels. The feedback path consists of a
resistor and a capacitor.

Procedure

1. Connect the circuit as per the circuit diagram.

2. Keeping the input voltage constant, vary the frequency from 50Hz to 3MHz in regular
steps and note down the corresponding output voltage.
3. Plot the graph: Gain (dB) Vs Frequency
4. Calculate the bandwidth from the graph.
5. Calculate the input and output impedance.
6. Remove Emitter Capacitance, and follow the same procedures (1 to 5).

Design Procedure/ Design Calculations

(i) Current Series Feedback Amplifier: Without Feedback:

𝑉𝐶𝐶 = 12𝑉; 𝐼𝐶 = 1𝑚𝐴; 𝑓𝐿 = 50𝐻𝑧; 𝑆 = 2; 𝑅𝐿 = 4.7𝐾Ω

26𝑚𝑉
𝑟𝑒 = =
𝐼𝑐
𝑉 𝑐𝑐
𝑉𝑐𝑒 = 2 =
𝑉𝐶𝐶⁄
𝑉𝐸 = 10 ℎ𝑖𝑒 = ℎ𝑓𝑒𝑟𝑒;

Applying KVL output loop, we get 𝑉𝑐𝑐 = 𝐼𝐸𝑅𝐸 + 𝐼𝐶𝑅𝐶 + 𝑉𝑐𝑒;

𝑅𝐶 =
𝑅𝐿 = 4.7𝐾Ω

Since 𝐼𝑉𝐵𝐸 is very small when

𝑅
compare with 𝐼𝐶, 𝐼𝐶 ≈ IE
𝑅 = ; 𝑆=1+ 𝐵
𝐸 𝐼𝐸 𝑅𝐸
𝑅𝐵 =
𝑉 𝑅
𝑉𝐵= 𝐶𝐶 2 𝑅 = 𝑅 //𝑅
(𝑅1+𝑅2) 𝐵 1 2
𝑅1 = 𝑅2 =
ℎ𝑖𝑒//𝑅𝐵 1 𝑅𝐶//𝑅𝐿 1
𝑋𝐶𝑖 = 10 𝐶𝑖 = 𝑋𝐶𝑜 = 10
𝐶𝑜 =
2𝜋𝑓𝑋𝑐𝑖 2𝜋𝑓𝑋𝑐𝑜
With Feedback (Remove The Emitter Capacitor, Ce)

Feedback factor, β = -RE =

Gm = -hfe / (hie + RE) =
Desensitivity factor, D = 1 + β Gm =
Transconductance with feedback, G mf = Gm / D =
Input impedance with feedback, Zif = Zi D
Output impedance with feedback, Z0f = Z0 D

(ii) Voltage Shunt Feedback Amplifier: Without Feedback

Vcc = 12V 𝐼𝑐 = 1𝑚𝐴; 𝐴𝑣 = 30; 𝑅𝑓 = 2.5𝐾Ω; 𝑠 = 2;

26𝑚𝑉
𝑟𝑒 = =
𝐼𝑐
1
𝛽= =
𝑅𝑓
ℎ𝑓𝑒 =
ℎ𝑖𝑒 = ℎ𝑓𝑒𝑟𝑒;
𝑉 𝑐𝑐
𝑉𝑐𝑒 = 2 =
𝑉
𝑉𝐸 = 𝐶𝐶⁄10 ;

Applying KVL to output loop, we get𝑉𝑐𝑐 = 𝐼𝐸𝑅𝐸 + 𝐼𝐶𝑅𝐶 + 𝑉𝑐𝑒;

𝑅𝐶 =
Since𝑉𝐸𝐼𝐵 is very𝑅 𝐵small when compare with 𝐼𝐶, 𝐼𝐶 ≈ IE
𝑅 = ;= 1 +
𝐸 𝐼𝐸 𝑅𝐸
𝑅𝐵 =
𝑉𝐶𝐶 𝑅2
𝑉𝐵 = 𝑅𝐵 = 𝑅1//𝑅2
(𝑅 1 + 𝑅2 )
𝑅1 = 𝑅2 =

With Feedback

𝑅𝑂 = 𝑅𝐶//𝑅𝑓𝑅𝑖 = (𝑅𝐵//ℎ𝑖𝑒)𝑅𝑓
𝑅𝑚 = −(ℎ𝑓𝑒(𝑅𝐵//𝑅𝑓)(𝑅𝐶//𝑅𝑓))/((𝑅𝐵//𝑅𝑓) + ℎ𝑖𝑒)
𝑅𝑜
Desensitivity factor,= 1 + 𝛽𝑅 𝑅𝑖𝑓 =
𝑅𝑖 𝑅 = 𝑅 =
𝑅𝑚
𝑚 𝐷 𝑜𝑓 𝐷 𝑚𝑓 𝐷
𝑅
𝑖𝑓 1 𝑅 1
𝑋𝐶𝑖 = 10 𝐶𝑖 = 2𝜋𝑓𝑋 𝑋𝐶𝑜 = 𝑜𝑓 𝐶𝑜 = 2𝜋𝑓𝑋
𝑅 +ℎ 𝑐𝑖 10 1 𝑐𝑜
𝑅 = 𝑅 //( 𝐵 𝑖𝑒) 𝑋 = 𝑅 /10 𝐶 =
𝐸′ 𝐸 𝐶𝐸 𝐸′ 𝐸 2𝜋𝑓𝑋𝑐𝐸
1+ℎ𝑓𝑒
1
𝑋 = 𝑅𝑓/10𝐶𝑓 =
2𝜋𝑓𝑋 𝑐𝑓
Circuit Diagram:
Current Series Feedback Amplifier: Without Feedback

Current Series Feedback Amplifier: With Feedback

Voltage Shunt Feedback Amplifier: Without Feedback

Voltage Shunt Feedback Amplifier: With Feedback

b) Model Graph:

Current Series Feedback Amplifier

Voltage Shunt Feedback Amplifier

e) Tabulation:

(i) Without Feedback

Gain = 20
Frequency (Hz) Gain = V0/Vi
Vo (Volts) log(V0/Vi) (dB)
 (ii) With Feedback

Gain = 20
Frequency (Hz) Gain = V0/Vi
Vo (Volts) log(V0/Vi) (dB)

Conclusion:

On completion of the experiment students will be able to design and construct current shunt and
voltage series feedback amplifiers

Result:

Thus the current series and voltage shunt feedback amplifiers are designed and constructed and
the parameters are calculated.
 8(i). RC PHASE SHIFT OSCILLATOR

AIM

To setup RC phase shift oscillator for 1 KHz and

(i) plot the output waveform

(ii) measure the frequency of oscillation

OBJECTIVES

On completion of the experiment students will be able to construct an RC phase shift

oscillator for a given frequency

EQUIPMENTS / COMPONENTS

Sl. no. Name and specification Quantity

1. Capacitor 0.01 µF 3 nos.

1 µF 1 no.
22 µF 1 no.

2. Resistor 470 Ω 1 no.

1.8 KΩ 1 no.
4.7 KΩ 2 nos.
10 KΩ 1 no.
47 KΩ 1 no.

3. Variable resistor – 10 KΩ 1 no.

Potentiometer (lin)
4. Transistor BC 548 1 no.

5. Power supply 12 V 1 no.

6. Oscilloscope 0 to 20 1 no.
MHz
7. Multimeter 1 no.

8. Breadboard 1 no.

9. Connecting wires

PRINCIPLE

An oscillator is an electronic circuit for generating ac signal voltage with a dc supply

as the only input requirement. The frequency of the generated signal is decided by the circuit
elements. An
oscillator requires an amplifier a frequency selective network and positive feedback from
the output othe input. The Barkhausen criteria for sustained oscillator is Aβ = 1, where A
is gain of the amplifier and β is the feedback factor.

If common emitter amplifier is used with resistive collector load, there is

o
an 180 phaseshift between input and output. The feedback network introduces an
additional 180ophaseshift at a particular frequency. The three section RC network offers
180ophaseshift and the β of . Hence for unity gain feedback, the gain of the amplifier
should be 29. The phaseshift oscillator is particularly useful as audio frequency generator.
The frequency of oscillation is given by .

PROCEDURE

1) Test the components

2) Assemble the amplifier part of the circuit in a breadboard
3) Connect the feedback network
4) Connect the output of the circuit to an oscilloscope
5) Adjust the 10 KΩ pot and observe the output
6) Measure the frequency and amplitude of the output
7) Plot output waveform

CIRCUIT DIAGRAM
 From the given component values, the frequency of oscillation

f= = =

OBSERVATIONS

1. DC conditions of amplifier section

(i) VCC =
(ii) VBE =
(iii) VCE =

2. Output waveform

Time period, T =
1
Frequency, f = T =

RESULT:
 8(ii). WIEN BRIDGE OSCILLATOR USING OPAMP
AIM: To design a Wien Bridge oscillator using op-amp for a given frequency of 1kHz.

APPARATUS: OP Amp IC 741, Power Supply, Oscilloscope, Resistors, Capacitors.

THEORY:
An oscillator is a circuit that produces periodic electric signals such as sine wave or
square wave. The application of oscillator includes sine wave generator, local oscillator for
synchronous receivers etc. An oscillator consists of an amplifier and a feedback network.
1. 'Active device' i.e. op amp is used as an amplifier.
2. Passive components such as R-C or L-C combinations are used as feedback network.
To start the oscillation with the constant
amplitude, positive feedback is not the only
sufficient condition. Oscillator circuit must satisfy
the following two conditions known as
Barkhausen conditions:
1. Magnitude of the loop gain (Av β) = 1,
where, Av = Amplifier gain and
β = Feedback gain. Fig 1. Basic oscillator block diagram
2. Phase shift around the loop must be 360°
or 0°.
Wien bridge oscillator is an audio frequency sine wave oscillator of high stability and
simplicity. The feedback signal in this circuit is connected to the non-inverting input terminal
so that the op-amp is working as a non-inverting amplifier. Therefore, the feedback network
need not provide any phase shift. The circuit can be viewed as a Wien bridge with a series
combination of R1 and C1 in one arm and parallel combination of R2 and C2 in the adjoining
arm. Resistors R3 and R4 are connected in the remaining two arms. The condition of zero phase
shift around the circuit is achieved by balancing the bridge.
The series and parallel combination of RC network form a lead-lag circuit. At high
frequencies, the reactance of capacitor C1 and C2 approaches zero. This causes C1 and C2
appears short. Here, capacitor C2 shorts the resistor R2. Hence, the output voltage Vo will be
zero since output is taken across R2 and C2 combination. So, at high frequencies, circuit acts as
a 'lag circuit'. At low frequencies, both capacitors act as open because capacitor offers
very high reactance. Again, output voltage will be zero because the input signal is dropped
across the R1 and C1 combination. Here, the circuit acts like a 'lead circuit'. But at one
particular frequency between the two extremes, the output voltage reaches to the maximum
value. At this frequency only, resistance value becomes equal to capacitive reactance and
gives maximum output. Hence, this frequency is known as oscillating frequency (f).
 Circuit diagram of Wien bridge oscillator using op-amp.

Vo (s)


1
sC1
ZS
R1

Vf (s)

ZP
 1
sC2
R1

Circuit diagram of Wien bridge oscillator using opamp.

Consider the feedback circuit On applying voltage divider rule,

𝑉𝑜 (𝑠) × 𝑍𝑃 (𝑠)
𝑉𝑓 (𝑠) =
𝑍𝑃 (𝑠) + 𝑍𝑆 (𝑠)
1 1
where, ZS (s)  R1  and ZP (s)  R2 ǁ 
sC1 sC2

Let, R1 = R2 = R and C1 = C2 = C. On solving, 

Vf (s) 
feedback gain,    
RsC (1)
Vo (s)  RsC   3RsC 1
2
 Since the op-amp is operated in the non-inverting configuration the voltage gain,

𝑉𝑜 (𝑠) 𝑅3
𝐴𝑣 = =1+
𝑉1 (𝑠) 𝑅4

Applying the condition for sustained oscillations, 𝐴𝑣𝛽 = 1

Substitute equations (1) & (2), we get,

𝑅3 𝑅𝑠 𝐶
(1 + )( )=1
𝑅4 (𝑅𝑠 𝐶)2 + 3𝑅𝑠 𝐶 + 1
 
Substitute s = jω




𝑅3 𝑗𝜔𝑅𝐶
(1 + )( 2 2 )=1
𝑅4 −𝑅 𝐶 𝜔2 + 3𝑗𝜔𝑅𝐶 + 1
𝑅3 2
(1 + ) 𝑗𝜔𝑅𝐶 = (−𝑅2 𝐶 𝜔2 + 3𝑗𝜔𝑅𝐶 + 1)
𝑅4
𝑅3 2
𝑗𝜔 ⌊(1 + ) 𝑅𝐶 − 3𝑅𝐶⌋ = 1−𝑅2 𝐶 𝜔2 
𝑅4
To obtain the frequency of oscillation equate the real part to zero.

1 R2C22  0
1

RC
1
f
2 RC
To obtain the condition for gain at the frequency of oscillation, equate the imaginary
part to zero.
𝑅
𝑗𝜔 ⌊(1 + 𝑅3 ) 𝑅𝐶 − 3𝑅𝐶⌋ = 0
4

𝑅
𝑗𝜔 (1 + 𝑅3 ) 𝑅𝐶=𝑗𝜔3𝑅𝐶
4

𝑅
(1 + 𝑅3 )
4

𝑅3
=2 
𝑅4


Therefore, R3 = 2 R4 is the required condition.

SIMPLEFIED DESIGN:
1
Frequency of oscillation, f 
2 R1C1R2C2

Let, R1 = R2 = R and C1 = C2 = C

1
f 
2 RC
Given frequency, f = 1 kHz. assume C = 0.01μF

1
1000 
2 R  0.01106
then R = 15.9 kΩ

Take R1 = R2 = 15 kΩ (nearest standard value)

R3
Also, 2
R4

Let R4 = 1 kΩ, then R3 = 2 kΩ. (Use 4.7kΩ potentiometer for fine corrections).

PROCEDURE:
 Test the op-amp by giving a sine wave at the inverting terminal, ground at the non-
inverting terminal to obtain a square wave at the output.
 Set up the circuit as shown in the figure.
 Obtain the sine wave at the output. Check for the frequency obtained.

OUTPUT (TO BE OBTAINED):

f = 1 kHz

RESULT:
A Wien bridge oscillator was designed and setup for a frequency of 1kHz and the
output waveform is observed.
 8(iii). HARTELY OSCILLATOR

Aim:
Study of the operation of Hartley Oscillator

Required Apparatus:
1. Analog board of AB68.
2. DC power supply
3. Oscilloscope
4. 2 mm patch cords

Theory:

Oscillators are circuits that produce periodic waveforms without input other
than perhaps a trigger. They generally use some form of active device, lamp, or
crystal, surrounded by passive devices such as resistors, capacitors, and inductors, to
generate the output.
There are two main classes of oscillator: Relaxation and Sinusoidal.
Relaxation oscillators generate the triangular, sawtooth and other nonsinuoidal
waveforms. Sinusoidal oscillators consist of amplifiers with external components
used to generate oscillation, or crystals that internally generate the oscillation. The
focus here is on sine wave oscillators, created using operational amplifiers Op-
Amps. Sine wave oscillators are used as references or test waveforms by many
circuits.
An oscillator is a type of feedback amplifier in which part of the output is fed
back to the input via a feedback circuit. If the signal fed back is of proper
magnitude and phase, the circuit produces alternating currents or voltages. Two
requirements for oscillation are:
1. The magnitude of the loop gain AVB must be at least 1, and
2. The total phase shift of the loop gain A VB must be equal to 0° or 360°.
If the amplifier causes a phase shift of 180°, the feedback circuit must
provide an additional phase shift of 180° so that the total phase shift
around the loop is 360°.
Hartley Oscillator

The Hartley oscillator is one of the simplest and best known oscillators and
is used extensively in circuits, which work at radio frequencies. The transistor is in
voltage divider bias which sets up Q-point of the circuit. The output voltage is fed
back to the base and sustains oscillations developed across the tank circuit, provided
there is enough voltage gain at the oscillation frequency.

The resonant frequency of the Hartley oscillator can be calculated from the
tank circuit used. We can calculate the approximately resonant frequency as
𝟏
Fr= ……………. (1)
𝟐𝝅√𝑳𝑻𝑪

Here, the Inductor used is the equivalent Inductance. In Hartley oscillator the
circulating current passes through the series combination of L1 and L2.
Therefore equivalent Inductance is,

LT = L1 + L2 + 2 M……………..(2)

Where, M is the mutual inductance between two inductors.

M = K √ L1 L2 ……………(3)

Where, K is the coefficient of coupling, lies between 0 to 1.The coefficient

of coupling gives the extent to which two inductors are couple.
Starting condition for oscillations is
AB > l

Where,
B is approximately equal to L2/L1.
The feedback should be enough to start oscillations under all conditions as
different transistor, temperature, voltage, etc. but it should not be much that
you lose more output than necessary. The resonant frequency can be changed by
either changing the value of inductor or changing the value of capacitor but
the combination of the three components should satisfy the above given two
conditions for oscillation.
Circuit diagram:

Hartley Oscillator

Procedure:
1. Connect +12V DC power supplies at their indicated position from
external source
2. Switch on the Power Supply.
3. Connect Oscilloscope between Vout and ground on kit.
4. Record the value of output frequency on oscilloscope.
5. Calculate the resonant frequency using equation 1.
6. Compare measured frequency with the theoretically calculated value.
7. Switch off the supply.
Output (To Be Obtained):

Result:
 8(iv). COLLPITTS OSCILLATOR USING OPAMP

Aim: To examine and the operation of Colpitts oscillator and to verify

oscillation conditions

Apparatus:
1. Power- supply
2. Oscilloscope
3. Operational amplifier (A741)
4. Capacitors
5. Inductors
6. 100 ohm resistor
7. Potentiometer of 100kohm

Theory:
High frequency oscillators are generally LC oscillator, for example
Colpitts oscillator and Hartley oscillator. The frequency of the oscillation

is proportional to1/ . The circuit diagram for Colpitts oscillator is

shown in Fig.(1) . The Colpitts oscillator must have a loop gain of unity
and will have zero degree phase shift at frequency (fo) of the tuned circuit.
The output developed across the tank circuit. The positive feedback
required for oscillation is derived by capacitive tapping of the tank.
The oscillation frequency can be derived to be:

1
 
LC1C2 / C1  C2 
 1 if C1=C2=C
Therefore,  
2

LC

In practice, normally reactance of C1 is kept small so it is not

shunted by the input impedance of the amplifier. So, always Cl is taken
larger than C2.

Hence,   and the capacitor C1 controls feedback portion while

LC

C2 affects the frequency of oscillation.

The same analysis can be done for the Hartley oscillator whose
circuit is shown in Fig.(2).
The frequency of oscillation is:

 


Circuit Diagram

Colpitts oscillator
 Procedure

fo 
 2 LC
 Test the op-amp by giving a sine wave at the inverting terminal,
ground at the non- inverting terminal to obtain a square wave at the
output.
 Set up the circuit as shown in the figure.
 Obtain the sine wave at the output. Check for the frequency
obtained.

Output (To Be Obtained)

Result:
 9. PARAMETERS OF OPERATIONAL AMPLIFIERS

Aim: Measurement of op-amp parameters viz. Input offset voltage, Bias current, Slew rate and
CMRR.

Apparatus: IC 741, Resistors, Function generator, CRO, CRO probes, Dual power supply.

Theory:

Input Bias Current And Input Offset Current

The 741 contains a differential amplifier input stage. The BJTs that form this differential
amplifier require bias currents through their bases. The current is quite small in the 741; the
worst-case input bias current in the 741 is 500nA. Figure 1 shows the symbol and pin
designations of the 741 Op amp. The input bias currents flow through the bases of T1 and T2.
Both currents should be equal because both T1 and T2 are identical and their emitter currents are
the same. However, if they are not, then there will be an input offset current. The input offset
current is the difference between the two currents. This difference may exist as a direct result of
internal differences within the BJTs of the Op amp.

Input Offset Voltage

The 741 OP amp has been designed so that the final stage produces an output voltage of 0
Volts, when the two inputs are at the same potential level. Internal defects can lead to a DC offset
at the output. The DC offset can be nulled by one of the following two ways. A DC voltage can
be placed in one input terminal when the Op amp is wired as a negative feedback amplifier. The
voltage placed on the input is the input offset voltage. In addition, the 741 has nulling terminals
where a potentiometer can be connected. The external connections pins 1 and 5 are to the emitters
of some internal transistors.
Common Mode Rejection Ratio (CMRR):

The ability of the op-amp to reject the signal on both terminals such as noise is called
as CMRR. Ideally gain of common mode is zero ,hence the ideal value of CMRR
is∞..Mathematically it is the ratio of the Differential Gain to common mode gain.

CMRR = Ad/Acm
Where, Ad =differential gain

Acm = common mode gain.

CMRR in dB= 20logAd/Acm

Circuit Diagram

R1 (1 K) RF (100K)

U1 IDEAL

RL (10K)

Fig 1: Input offset voltage

Fig 2: Bias current

 +12 V
2 7
6
741 Vo
3
-12 V

Vin

Fig.3 Measurement of Slew rate

Fig 4: Common Mode for CMRR

R1 Rf
1k 10k

U1
IDEAL
R2
1k

+
Vs1
10V R3 RL
- 10k 10k

Fig 5: Differential Mode for CMRR

Procedure :- For Input Offset Voltage

1. Make connections as shown in figure.

2. Measure the output voltage.
3. Calculate the value of input offset voltage.

For Input Bias Current

1. Make connections as shown in figure.

2. Measure the output voltage.
3. Calculate the value of input bias current by using given formula.

For Slew Rate

1. Make connections as shown in figure.

2. Note down the value of Vpeak.
3. Vary the frequency of input voltage & observe the output waveform.
4. Note the value of frequency at which output waveform start distorting.
5. Calculate the value of slew rate using given formula.

For CMRR

1. Make connections as shown in the figure.

2. Give i/p voltage of 1v peak to peak.
3. Measure the differential & common mode output.
4. Calculate Ad, Acm, & CMRR in db using formula.

Observation : For Input offset voltage and Bias current

Voo (For Vios) Vo (For Ib)

For Slew rate

Input frequency Remark

For CMRR

Vo1= Vo2=

Formulae : For Input offset voltage

Vio= Voo /(1+ Rf/R1)

For bias current

Vo= IB*RF

IB=Vo/RF

For Slew rate

2  f max V p
SR  V
10 6 s
For CMRR

CMRR=20 log(Ad/Ac)

Ad = Vo1/Vin

Acm = Vo2/Vin

CMRR=20 log(Vo1/Vo2)

Result:
Sr. No. Op Amp Parameter Theoretical value Calculated Value
for IC 741
1 Input Offset Voltage
2 Input Bias Current
3 Slew Rate
4 CMRR
 10(i). INVERTING AND NON-INVERTING AMPLIFIER
USING OPAMP
Aim: To study the following op-amp circuits
1.Inverting amplifier
2.Non-inverting amplifier

Apparatus: Op-Amp – µA 741, capacitors, resistor, Dual power supply, Regulated

powersupply, CRO, function generator, multimeter, etc.

Theory:

An inverting-amplifier circuit is built by grounding the positive input of the

operational amplifier and connecting resistors R1 and R2, called the feedback networks,
between the inverting input and the signal source and amplifier output node,
respectively. With assumption that reverse-transfer parameter is negligibly small, open-
circuit voltage gain Av, input resistance Zin and output resistance Zo can be calculated.

The operational amplifier can also be used to construct a non-inverting amplifier

with the circuit indicated below. The input signal is applied to the positive or non-
inverting input terminal of the operational amplifier, and a portion of the output signal
is fed back to the negative input terminal. Analysis of the circuit is performed by
relating the voltage at V2 to both the input voltage Vin and the output voltage Vo.

The output is applied back to the inverting (-) input through the feedback circuit (closed
loop) formed by the input resistor R1 and the feedback resistor R2. This creates ve
feedback as follows. Resistors R1 and R2 form a voltage-divider circuit, which reduces
Vo and connects the reduced voltage V2 to the inverting input.
Design:

1. Design for inverting amplifier

The expression for gain is ACL = -(RF/R1)

Let amplifier to be designed with a gain of (-10), select input resistance R1=10Kω
Feedback resistance, RF = - (ACLXR1)
= - (-10X10X103)=100kꭥ

2. Design for non- inverting amplifier

𝑅𝑓
The expression for gain is ACL = 1 + 𝑅1

Let amplifier to be designed with a gain 11 and select R1 = 10Kω

Feedback resistance, RF = (ACL – 1)R1
= (10-1X10X103)=100kꭥ


Rf 100 k
Vi

+15V
R1 10 k
Vi 7 t
2-
6
LM 741 Vo
+ 4
3 Vo
10 k -15V

Fig 1.Circuit diagram of inverting amplifier Fig 2. Input and output

waveforms of inverting amplifier
 Fig 3. Circuit diagram of non-inverting amplifier Fig 4. Input and output waveforms of
non-inverting amplifier

Procedure:

1. Inverting Amplifier
Set up the circuit as shown in Fig 1. The circuit gives a closed loop gain
ACL = -(RF/R1)

This gain is very small compared to the open loop gain of the op-amp. Test the
circuit by applying the input signal of suitable amplitude (say 1V peak to peak)
from a function generator. Observe the output waveform on the CRO and determine
actual gain.

2. Non-Inverting Amplifier

The circuit of a non-inverting amplifier is shown in Fig 3. Its closed loop gain is
𝑅𝑓
ACL = 1 + 𝑅1. The circuit is tested by applying the input signal of suitable

amplitude

(say 1V peak to peak) from a function generator. Observe the output waveform on the
CRO and determine actual gain.
Observations:

Inverting Amplifier

Input Frequency Input voltage (p-p) Output voltage (p-p) Gain

F Vi Vo V
A  o
L
C
kHz V V Vi

Non-Inverting Amplifier

Input Frequency Input voltage (p-p) Output voltage (p-p) Gain

f Vi Vo Vo
A
L
C
kHz V V Vi

Result: The basic op-amp circuits of inverting & non-inverting amplifiers were designed
set up and output waveforms were obtained in a CRO. The gain obtained are

Inverting amplifier:

Gain = .…

Non-inverting amplifier:

Gain = .…
 10(ii). VOLTAGE FOLLOWER
Aim: To design and study the op-amp as a Voltage Follower.

Apparatus:

Function generator, CRO, Regulated Power supply, 741 IC, connecting wires.

Theory:

Op-Amp As A Voltage Follower

A unity gain buffer amplifier may be constructed by applying a full series negative feedback
(Fig. 1) to an op-amp simply by connecting its output to its inverting input, and connecting
the signal source to the non-inverting input (Fig. 2). In this configuration, the entire output
voltage (β = 1 in Fig. 1) is placed contrary and in series with the input voltage. Thus the two
voltages are subtracted according to KVL and their difference is applied to the op-amp
differential input. This connection forces the op-amp to adjust its output voltage simply equal
to the input voltage (Vout follows Vin )so the circuit is named op-amp voltage follower.
Used as a buffer amplifier to eliminate loading effects (e.g., connecting a device with a high
source impedance to a device with a low input impedance).

Vout=Vin

Zin=∞

Circuit Diagram

A negative feedback amplifier

An op-amp–based unity gain buffer amplifier or op-amp as a VOLTAGE FOLLOWER

The importance of the circuit is due to the input and output impedances of the op-
amp. The input impedance of the op-amp is very high, meaning that the input of the op-amp
does not load down the source or draw any current from it. Because the output impedance of
the op-amp is very low, it drives the load as if it were a perfect voltage source. Both the
connections to and from the buffer are therefore bridging connections, which reduce power
consumption in the source, distortion from overloading, crosstalk and other electromagnetic
interference.

The voltage follower is often used for the construction of buffers for logic circuits.

Voltage follower circuit design has been implemented on the virtual breadboard using
following specifications:

 Power Supply: +12v and -12v

 Function generator: Selected wave with following specifications:

Frequency =1 kHz
Amplitude: 2V
Duty cycle = 50%

Observations

1. Observe the output waveform from CRO.

2. Measure the frequency and the voltage of the output waveform in the CRO. The
output will be same as the input.
3. Observe outputs of the voltage follower using different input voltages and wave type.
Precautions

1. Connections should be verified before clicking run button.

2. The frequency should be in appropriate range for all voltage used so that the slew rate
distortion does not affect the output.

Result:

The diode limiter circuit is designed and been studied successfully.

 10(ii). SUMMING AMPLIFIER USING OP-AMP
Aim: To design and setup a summing amplifier circuit with OP AMP 741C for a gain of 2
and verify the output.

Apparatus: Function Generator, CRO , Dual RPS , Bread Board , Resistors , IC 741

Theory:

The Summing Amplifier is a very flexible circuit indeed, enabling us to effectively

“Add” or “Sum” (hence its name) together several individual input signals. If the inputs
resistors, R , R , R etc, are all equal a “unity gain inverting adder” will be made. However, if
the input resistors are of different values a “scaling summing amplifier” is produced which
will output a weighted sum of the input signals.

Circuit Diagram

Procedure
1. Check the components.
2. Setup the circuit on the breadboard and check the connections.
3. Switch on the power supply.
4. Give V1 =V2 = +1.5V DC with polarity as shown in fig.1.
5. Make sure that the CRO selector is in the D.C. coupling position.
6. Observe input and output on two channels of the oscilloscope simultaneously.
 7. Note down and draw the input and output waveforms on the graph.
8. Verify that the output voltage is -6VDC

Design

The output voltage of an inverting summing amplifier is given by

Vo = -( Rf / Ri )(V1+V2)

Let Ri = 1.1KΩ
Then Rf = 2.2KΩ ,
Vo = -2(V1+V2)

Observation

V1= 1.5 DC
V2= 1.5 DC
Then VO=?

Model Waveform

Result:
 10(iii). ZCD AND SCHMITT TRIGGER

Aim:

To design and test using Operational amplifiers for the performance of (1) Zero Crossing
Detector, (2) Schmitt Trigger for different hysteresis values.

Apparatus:

Op-Amp – µA 741, capacitors, resistor, Dual power supply, Regulated power

supply, CRO, function generator, multimeter, etc.

Theory:

Zero crossing detector is a voltage comparator that changes the o/p between
+Vsat & –Vsat when the i/p crosses zero reference voltage. In simple words, the comparator
is a basic operational amplifier used to compare two voltages simultaneously and changes the
o/p according to the comparison. In the same way, we can say ZCD is a comparator. Zero
crossing detector circuit is used to produce an o/p stage switch whenever the i/p crosses the
reference i/p and it is connected to the GND terminal. The o/p of the comparator can drive
various outputs such as an LED indicator, a relay, and a control gate.

A Schmitt trigger circuit is also called a regenerative comparator circuit. The circuit is
designed with a positive feedback and hence will have a regenerative action which will make
the output switch levels. Also, the use of positive voltage feedback instead of a negative
feedback, aids the feedback voltage to the input voltage, instead of opposing it. The use of a
regenerative circuit is to remove the difficulties in a zero-crossing detector circuit due to
low frequency signals and input noise voltages.
Circuit Diagram
Procedure

1. Connect the circuit as per the circuit diagram.

2. For a zero crossing detector, connect the non-inverting terminal to ground.

3. Switch on the dual power supply.

4. Observe the output waveform on the CRO

5. Draw the output and input waveforms.

6. For Schmitt Trigger set input signal (say 1V, 1 KHz) using signal generator.

7. Observe the input and output waveforms on the CRO.

8. Plot the graphs: Vi vs Time, VO vs Time.

Wave Forms

Result: UTP and LTP is measured and compared with the designed value.
 10(iv). FULL WAVE PRECISION RECTIFIER

Aim: To test for the performance of Full wave Precision Rectifier using Operational
Amplifier.

Apparatus:

Op-Amp – µA 741, capacitors, resistor, Dual power supply, Regulated power

supply, CRO, function generator, multimeter, etc.

Theory:

In PFWR, for both the half cycles output is produced & in one direction only. The
diagram below shows an inverting type of Precision FWR with positive output. It is also
called as absolute value circuit because output signal swing is only in positive direction. So
we get absolute value of input signal.

Circuit Diagram
Design/Calculations

In positive half cycle of applied ac input signal, output of first op-amp (A1) is Negative.
Therefore, diode D2 is forward biased & diode D1 is reverse biased. Here op-amp A1 works
as an inverting amplifier with gain =(-R/R)=-1
Therefore output of op-amp A1 is ,V=(-1) Vin=-Vin

Op-amp A2 works as an inverting adder. The two inputs to the op-amp A2 are voltage V
(output of A1) and input voltage Vin. Thus output of op-amp A2i.e. Output voltage is given
as
∴Vo=-[R/R Vin+R/(R⁄2) V ]
∴Vo=-[Vin+2V]
Substituting V=-V_in
∴Vo=Vin

In negative half cycle of applied ac input signal, output of first op-amp (A1) is positive.
Therefore, diode D2 is reversed biased & diode D1 is forward biased.
Due to virtual ground concept output of op-amp A1is zero. (∴V=0)
Thus output of op-amp A2, i.e. Output voltage is given as
∴Vo=-[R/R Vin+R/(R⁄2) V ]
∴Vo=-[R/R Vin+R/(R⁄2) (0) ]

But in negative half cycle input magnitude is negative therefore we get,

∴Vo=-[R/R (-Vin ) ]
∴Vo=Vin
Thus in both the half cycles output is positive & in one direction & also have same
magnitude. Thus it is also called as non-saturating type of PFWR because op-amp A1 is not
going in saturation.
Procedure

1. Connect the circuit as per the circuit diagram.

2. Give a sinusoidal input of VPP, 1 KHz from a signal generator.
3. Switch on the power supply and note down the output from CRO.
4. Without Connecting Rf 2, the wave form of the half wave rectifier is produced.
5. At some value of Rf 2 the wave form of a full wave rectifier is obtained.
6. Repeat the above procedure by reversing the diodes.

Wave Forms

The transfer characteristics and input-output waveforms of PFWR are shown below

Result: The operation of the precision rectifier is studied using µA 741.

 11(i). MONOSTABLE MULTI VIBRATOR USING OP-AMP

Aim: To construct Monostable multi vibrator using Op-Amp and observe their performance.

Apparatus:

Sl. No. Apparatus / Range Quantity

Equipment
1. IC741 - 1
2. Resistors 1KΩ,10KΩ,48.3KΩ, 1,2,1,2
100KΩ
3. Capacitors 0.01 μF 2
4. Diode IN4007 2
5. AFO 30 MHz 1
6. Power supply (0- 15)v 1
7. CRO 30 MHz 1
8. Connecting wires - As required

Theory:

The mono stable multi vibrator has one stable state and other is quasi state. This is
useful for generating single output pulse of adjustable time duration in response to a
triggering signal. The width of pulse depends only on the external components connected to
the op-amp. Diode D2 produces a negative going triggering pulse and supply to the just
slightly. The diode D2 id used to avoid the malfunctioning by blocking the positive noise
spikes the may be present at the differentiated triggered input.
Circuit Diagram

Circuit diagram of Mono stable multi vibrator

Procedure

1. The connections are given as per the circuit diagram.

2. Set the input voltage using AFO and output waveform observed in CRO.
3. Tabulate the reading in tabular column.

Tabulation

Vin (v) Time (ms) VO (V) Time (ms) VUT (V) VLT (V) Time (ms)
Model Graph

Result: Thus an Monostable multi vibrator using Op-amp its performance is observed.
 11(ii). ASTABLE MULTI VIBRATOR USING OP-AMP

Aim: To construct an Astable multi vibrator using Op-Amp and observe their performance.

Apparatus:

Sl. No. Apparatus / Range Quantity

Equipment
1. IC741 - 1
2. Resistors 1KΩ,10KΩ,48.3KΩ, 1,2,1,2
100KΩ
3. Capacitors 0.01 μF 2
4. Diode IN4007 2
5. AFO 30 MHz 1
6. Power supply (0- 15)v 1
7. CRO 30 MHz 1
8. Connecting wires - As required

Theory:

The Astable multi vibrator is also called as a free running oscillator. The principle of
op-amp is to force an op-amp to operate in the saturation region. The output of the op-amp in
the circuit will be positive and negative saturation level depending on the differential voltage
across the capacitor. At any instant the DC supply voltage +Vcc & - Vcc are applied. This
means the voltage at the inverting terminal is zero initially at the same time. The voltage V at
the non-inverting terminal a small infinite value. The voltage V1 will be started to drive the
op-amp in to the saturation soon as voltage is more than V1, the output forced to switch to –
Vsat the voltage is negative then input drives the op-amp + Vsat.
Circuit Diagram

Procedure

1. The connections are given as per the circuit diagram.

2. The capacitor voltage waveform is observed and the frequency of the output
waveform is measured
3. Tabulate the reading in tabular column.

Tabulation

Vin (v) Time (ms) VO (V) Time (ms) VUT (V) VLT (V) Time (ms)
Model Graph

Result: Thus an Astable multi vibrator using Op-amp its performance is observed.
 12. DIGITAL TO ANALOG CONVERSION

Aim: Study of Digital to Analog converter (R-2R Ladder Type)

Apparatus:

1. Dual regulated DC power supply

2. Bread Board & connecting wires
3. Resistors
4. IC 741
5. Multimeter

Theory:

The purpose of a digital-to-analog converter is to convert a binary word to a

proportional current or voltage.

The DAC circuits has some practical limitations. The biggest problem is the large
difference in resistor values between the LSB and MSB, especially in high resolution DACs.
One of the most widely used DAC circuits that uses resistance’s fairly close in value is the
R/2R ladder network. Here the resistance values span a range of only 2 to 1.

Pin Configuration of Op-amp IC 741:

Circuit Diagram:

R-2R Ladder DAC schematic

Procedure:

1. Assemble the circuit on bread board as shown in circuit diagram.

2. Switch on the power supply.
3. Check the supply voltage to op-amp IC 741.
4. Apply the digital logic inputs at A1 – A4. Note the corresponding analog output Vout.

Observations
For Digital to Analog Converter (DAC)
A 1 A 2 A 3 A 4 Analog output
MSB LSB Vout = 5 (A 1 /2+ A 2 /4 +

A3/8----------+ A 8/256)

0 0 0 0
0 0 0 1

1 1 1 1

Result: For input 0000 analog output is ----- V

For input 1111 analog output is ------- V

 12. DIGITAL TO ANALOG CONVERSION

Aim: Study of Digital to Analog converter (Weighted Resistor Type)

Apparatus:

1. Dual regulated DC power supply

2. Bread Board & connecting wires,
3. Resistors
4. IC 741
5. Multimeter

Theory:

The purpose of a digital-to-analog converter is to convert a binary word to a

proportional current or voltage.

The binary weighted resistors produce binary-weighted current which are summed up
by the op-amp to produce proportional output voltage. The binary word applied to the
switches produces a proportional output voltage. There are several methods and circuits for
producing the D/A operation

Pin Configuration of Op-amp IC 741:

Circuit Diagram:

Binary-weighted resistor DAC schematic

Procedure:

1. Assemble the circuit on bread board as shown in circuit diagram.

2. Switch on the power supply.
3. Check the supply voltage to op-amp IC 741.
4. Apply the digital logic inputs at A1 – A4. Note the corresponding analog output Vout.

Observations
For Digital to Analog Converter (DAC)
A 1 A 2 A 3 A 4 Analog output
MSB LSB Vout = 5 (A 1 /2+ A 2 /4 +

A3/8----------+ A 8/256)

0 0 0 0
0 0 0 1

1 1 1 1

Result: For input 0000 analog output is ----- V

For input 1111 analog output is ------- V

 13. ANALOG TO DIGITAL CONVERSION
Aim: Study of Analog to Digital converter (Flash type)

Apparatus:
1.Dual regulated DC power supply
2. Bread board and connecting wires and Multimeter
3. Resistors
4. IC 741
5. IC 7400

Theory:
An analog-to-digital converter (abbreviated ADC, A/D or A to D) is a device which
converts a continuous quantity to a discrete time digital representation. An ADC may also
provide an isolated measurement. The reverse operation is performed by a digital-to-analog
converter (DAC). Typically, an ADC is an electronic device that converts an input analog voltage
or current to a digital number proportional to the magnitude of the voltage or current. However,
some non-electronic or only partially electronic devices, such as rotary encoders, can also be
considered ADCs.

Flash ADC has a bank of comparators sampling the input signal in parallel, each firing for
their decoded voltage range. The comparator bank feeds a logic circuit that generates a code for
each voltage range. Direct conversion is very fast, capable of gigahertz sampling rates, but
usually has only 8 bits of resolution or fewer, since the number of comparators needed, 2N - 1,
doubles with each additional bit, requiring a large expensive circuit. ADCs of this type have a
large die size, a high input capacitance, high power dissipation, and are prone to produce glitches
on the output (by outputting an out-of-sequence code). Scaling to newer sub micrometre
technologies does not help as the device mismatch is the dominant design limitation. They are
often used for video, wideband communications or other fast signals in optical storage.

Pin Configuration of Op-amp IC 741:

Circuit Diagram:

Design: Number of comparators required = 2n-1

Where n = desired number of bits
C1, C2 & C3 = Comparator o/p
D0 & D1 = Encoder (Coding network) O/P
Procedure:

1. Assemble the circuit on bread board as shown in circuit diagram.

2. Switch on the power supply.
3. Check the supply voltage to op-amp IC 741 and IC 7400.
4. Verify the digital O/P for different analog voltages.

Tabular Column:

Analog I/P C3 C2 C1 D1 D0
Vin
0 to v/4 0 0 0 0 0
V/4 to V/2 0 0 1 0 1
V/2 to 3V/4 0 1 1 1 0
3V/4 to V 1 1 1 1 1

Result:
 14. SWITCHED CAPACITOR CIRCUIT

Aim:

The objective of this exercise is to explore the concepts of Switched Capacitor based circuits.

Apparatus:

ADALM2000 Active Learning Module

Solder-less breadboard
Jumper wires
1 - CD4007 ( configured as SPDT analog switch )
1 - 0.0047uF capacitor
1 - 100pF capacitor

Theory:

A switched capacitor is an electronic circuit element used in discrete time signal

processing systems. It works by transferring charge into and out of a capacitor when switches
are opened and closed. Usually, non-overlapping signals are used to control the switches,
often termed Break before Make switching, so that all switches are open for a very short time
during the switching transitions. Filters implemented with these elements are termed
'switched-capacitor filters'. Unlike analog filters, which must be constructed with resistors,
capacitors and sometimes inductors whose values are accurately known, switched capacitor
filters depend only on the ratios between capacitances and the switching frequency. This
makes them much more suitable for use within integrated circuits, where the accurately
specified absolute value of components such as resistors and capacitors are not economical to
construct.

Circuit Diagram

Switched Capacitor RC low pass filter

The Schematic And Pinout For The Cd4007

CD4007 CMOS transistor array pinout

Procedure

Switched capacitor RC low pass filter

1. The breadboard connections are as per circuit diagram.

2. If the power supplies from the ADALM2000 hardware be sure that they are turned
off or disconnected while construct the circuit.
3. The scope inputs should be connected to measure the input and output of the RC
filter.
4. The circuit will operate from the +/- 5V supplies provided from the ADALM2000
board but better performance will be observed if a +/- 5V bench power supply is used.
 5. A +/- 5V square wave digital signal from AWG2 drives the CD4007 inverter input at
pin 6 and the gate of switch devices M5 and M6. The inverted output at pins 8,13
drives the gates of switch devices M3 and M4.

6. Turn on the power supplies and enable both AWG channels.

7. Using the oscilloscope display observe the output amplitude of the filter relative to the
input as you change the input frequency, AWG1.

8. Also note any changes in the output amplitude as you change the switching frequency
by adjusting the frequency of AWG2.

9. Stop and close the Oscilloscope screen and now open the Network Analyzer
instrument ( Bode plotter ).

10. You will need to disable AWG channel 1 on the waveform generator screen but keep
channel 2 enabled and set to 100 KHz, 10 V amplitude peak-to-peak, zero offset as it
was previously.

11. Set up the Analyzer to sweep the filter input from 100 Hz to 10 KHz. Run sweeps
with AWG2 set to 100 KHz, 200 KHz and 500 KHz. Export the data for each sweep
to a .csv file and using a spreadsheet program like Excel make plots of the amplitude
and phase vs. frequency similar to the expected plots.

Hardware Setup
Waveform generator W1 should be configured as a 100 Hz sine wave with a 1 mV amplitude
peak-to-peak and zero offset to start out. Waveform generator W2 should be configured as a
100 KHz square wave with a 10 V amplitude peak-to-peak and zero offset. Scope channel 1
should be connected to the input of the filter and Scope channel 2 should be connected to the
output of the filter.

Expected Plots:

Amplitude plot
 Phase plot

Result: