DESIGN COVER SHEET

TITLE: CARD,CLK,BI,FPGA,5 POWER,2 VREF,8DIG 85-0148

ENG: L. ZIEGLER
Status > PROD
Design Rev > OI A B C

DWG/DOC No. SIZE DSK Name, Description Revisions

-000 A FINAL ASSEMBLY 1 1 1 1
-000-BOM A BILL OF MATERIALS 1 1 1 1
-000-WRL A WIRELIST 1 1 1 1

-001 A FINAL ASSEMBLY OF CARD, CLK, BI, FPGA, 5 POWER DRIVERS, 2 VREF 1 2 2 3
-001-SCH-01 A SCHEMATIC 1 1 1 1
-001-SCH-02 A SCHEMATIC 1 1 1 1
-001-SCH-03 A SCHEMATIC 1 1 1 2
-001-BOM A BILL OF MATERIALS 1 2 2 3
-001-CUT A CUTS LIST 1 1 1 1
-001-WRL A WIRELIST 1 1 2 3
-001-MAP A ROAD MAP OF PCB 1 1 1 1
-001-ART FILMS OF PCB ARTWORK 1 1 1 1
-001-ZIP 3.5" ZIP FILE OF PCB ARTWORK 1 1 1 1

-002 A FINAL ASSEMBLY OF CARD, CLK, BI, FPGA, 8 DIGITAL DRIVERS, 2 DACS 1 1 1 1
-002-SCH-01 A SCHEMATIC 1 1 1 1
-002-SCH-02 A SCHEMATIC 1 1 1 1
-002-SCH-03 A SCHEMATIC 1 1 1 1
-002-BOM A BILL OF MATERIALS 1 1 1 1
-002-WRL A WIRELIST 1 1 1 1
-002-MAP A ROAD MAP OF PCB 1 1 1 1
-002-ART FILMS OF PCB ARTWORK 1 1 1 1
-002-ZIP 3.5" ZIP FILE OF PCB ARTWORK 1 1 1 1

-003 A FINAL ASSEMBLY OF CARD, CLK, BI, FPGA, WIRE PROGRAMMING CARD 1 1 1 1
-003-SCH A SCHEMATIC 1 1 1 1
-003-BOM A BILL OF MATERIALS 1 1 1 1
-003-ART FILMS OF PCB ARTWORK 1 1 1 1
-003-ZIP 3.5" ZIP FILE OF PCB ARTWORK 1 1 1 1

-004 A FINAL ASSEMBLY OF CARD, CLK, BI, FPGA, 85-0148-001 DEBUG FIRMWARE 1 1 1 1
-004-SCH A SCHEMATIC 1 1 1 1
-004-DBG A DEBUG INSTRUCTIONS 1 2 2 2
-004-BIN 3.5" BINARY CODE 1 1 1 1

-005 A FINAL ASSEMBLY OF CARD, CLK, BI, FPGA, AUX 5 INPUT BANANA PANEL 1 1 1 1
-005-BOM A BILL OF MATERIALS 1 1 1 1

-006 A FINAL ASSEMBLY OF CARD, CLK, BI, FPGA, 85-0148-002 DEBUG FIRMWARE 1 1 1 1
-006-SCH A SCHEMATIC 1 1 1 1
-006-DBG A DEBUG INSTRUCTIONS 1 2 2 2
-006-BIN 3.5" BINARY CODE 1 1 1 1
-006-SIN 3.5" SINE WAVE DATA 1 1 1 1

-007 A FINAL ASSEMBLY OF CARD, CLK, BI, FPGA, 85-0148-003 WIRE CARD REINFORCING BAR 1 1 1 1
-007-BOM A BILL OF MATERIALS 1 1 1 1

-008 A FINAL ASSEMBLY OF CARD, CLK, BI, FPGA, 85-0148-001 POWER CARD REINFORCING B 1 1 1 1
 TED#: 85-0148-000-BOM REV 1
BILL OF MATERIALS PAGE 1 OF 1
ENG: L. ZIEGLER
TITLE: CARD, CLK, BI, FPGA DATE: 8/21/2002

ITEM # QTY PART NO. DESCRIPTION NOTES REF1 REF2 REF3 REF4

1 1 85-0148-001 CARD, CLK, BI, FPGA, 5 POWER DRIVERS, 2 VREF

2 1 85-0148-002 CARD, CLK, BI, FPGA, 8 DIGITAL DRIVERS, 2 DACS
3 1 85-0148-003 CARD, CLK, BI, FPGA, WIRE PROGRAMMING CARD
4 1 85-0148-004 CARD, CLK, BI, FPGA, 85-0148-001 DEBUG FIRMWARE
5 1 85-0148-005 CARD, CLK, BI, FPGA, AUX 5 INPUT BANANA PANEL
6 1 85-0148-006 CARD, CLK, BI, FPGA, 85-0148-002 DEBUG FIRMWARE
7 2 HARDWARE,SCRW,RND HD,#4-40 X .38 LG
8 2 HARDWARE,NUT, #4
9 A/N 22AWG STR WIRE, BLU
TED#: 85-0148-000-WRL REV 1
WIRE LIST PAGE 1 OF 1
TITLE: CARD,CLK,BI,FPGA,5 POWER,2 VREF,8DIG ENG: L. ZIEGLER DATE: 8/21/2002

For Details See PCB Assembly Drawing

WIRE # FROM TO SIGNAL NOTES WIRE TYPE

1 85-0148-005 X1V 85-0148-001 X1V EXTERNAL SOURCE 1 POSITIVE 22AWG,BLU,STR

2 85-0148-005 X1G 85-0148-001 X1G EXTERNAL SOURCE 1 NEGATIVE 22AWG,BLU,STR
3 85-0148-005 X2V 85-0148-001 X2V EXTERNAL SOURCE 2 POSITIVE 22AWG,BLU,STR
4 85-0148-005 X2G 85-0148-001 X2G EXTERNAL SOURCE 2 NEGATIVE 22AWG,BLU,STR
5 85-0148-005 X3V 85-0148-001 X3V EXTERNAL SOURCE 3 POSITIVE 22AWG,BLU,STR
6 85-0148-005 X3G 85-0148-001 X3G EXTERNAL SOURCE 3 NEGATIVE 22AWG,BLU,STR
7 85-0148-005 X4V 85-0148-001 X4V EXTERNAL SOURCE 4 POSITIVE 22AWG,BLU,STR
8 85-0148-005 X4G 85-0148-001 X4G EXTERNAL SOURCE 4 NEGATIVE 22AWG,BLU,STR
9 85-0148-005 X5V 85-0148-001 X5V EXTERNAL SOURCE 5 POSITIVE 22AWG,BLU,STR
10 85-0148-005 X5G 85-0148-001 X5G EXTERNAL SOURCE 5 NEGATIVE 22AWG,BLU,STR
 DESIGN COVER SHEET
TITLE: CARD, CLK, BI, FPGA, 5 POWER DRIVERS, 2 VREF 85-0148-001
ENG: L. ZIEGLER

Status > PROD

Design Rev > OI

DWG/DOC No. SIZE DSK Name, Description Revisions

-001 A FINAL ASSEMBLY 1
-001-SCH-01 A SCHEMATIC 1
-001-SCH-02 A SCHEMATIC 1
-001-SCH-03 A SCHEMATIC 1
-001-BOM A BILL OF MATERIALS 1
-001-CUT A CUTS LIST 1
-001-WRL A WIRELIST 1
-001-MAP A ROAD MAP OF PCB 1
-001-ART FILMS OF PCB ARTWORK 1
-001-ZIP 3.5" ZIP FILE OF PCB ARTWORK 1
 1 of 3
TED#: 85-0148-001-BOM REV 3
BILL OF MATERIALS 8/21/2002
ENG: L. ZIEGLER
TITLE: CARD, CLK, BI, FPGA, 5 POWER DRIVERS, 2 VREF

ITEM # QTY PART NO. DESCRIPTION NOTES REF1 REF2 REF3 REF4

1 1 AWG18 2 PIN TESTPOINT LOOP WITH AWG18 GND1

2 1 P9929-ND (DIGI-KEY) BUZZER,85DB,PANASONIC:EFB-RD22C41 BZ1
3 2 P5155-ND (DIGI-KEY) PANASONIC,M SERIES,CAP,470UF,25V,ALUMINUM RADIAL C6 C1
4 5 P5329-ND (DIGI-KEY) PANASONIC,M SERIES,CAP,470UF,160V,ALUMINUM RADIAL C4 C5 C2 C3
C7
5 10 101373 CAP,CC.50V,+/-5%,100PF C74 C78 C77 C76
C75 C69 C73 C72
C71 C70
6 44 101366 CAP,CC.50V,+/-10%,.1UF C44 C59 C83 C82
C45 C66 C65 C84
C67 C27 C28 C29
C30 C31 C32 C33
C34 C35 C36 C37
C38 C39 C40 C41
C42 C43 C54 C55
C46 C47 C48 C49
C50 C51 C52 C53
C58 C56 C57 C63
C64 C60 C61 C62
7 16 101364 CAP,CC.50V,+/-10%,1000PF C26 C24 C20 C21
C23 C22 C19 C18
C17 C16 C15 C14
C13 C12 C11 C81
8 5 101395 CAP,TA,35V,+/-20%,47UF C10 C80 C8 C68
C25
9 2 101387 CAP,TA,50V,+/-20%,4.7UF C79 C9
10 1 929974-01-36-ND (DIGI-KEY) CONN,HEADER,FEMALE,BAR,0.1INCH,SINGLE ROW,8PIN AT 4 LOC J1
11 1 929974-01-36-ND (DIGI-KEY) CONN,HEADER,FEMALE,BAR,0.1INCH,SINGLE ROW,36PIN J3
12 1 929975-01-36-ND (DIGI-KEY) CONN,HEADER,FEMALE,DUAL ROW,28PIN P1
13 2 1N5820CT-ND (DIGI-KEY) DIODE,SCHOTTKY,3A,20V,D0201AD D16 D15
14 4 BAS70-04DICT-ND (DIGI-KEY) DIODE,SCHOTTKY,SMD,IF=200MA,RRT=4NS,DUAL,BAS70-04 D3 D4 D1 D2
15 5 101065 DIODE,ZENER,1W,16V,1N4745 VR5 VR3 VR1 VR4
VR2
16 2 F1219CT-ND (DIGI-KEY) FUSE,SMD,HLDR & FAST ACTING FUSE,.25 A,OMNI-BLOK:F1219CT F1 F2
17 5 F1149CT-ND (DIGI-KEY) FUSE,SMD,VERY FAST ACTING FUSE,5 A,NANO2SMF F3 F5 F6 F7
F4
18 1 158-1050-ND (DIGI-KEY) IC,BUFFER/DRIVER,DUAL,1.5A,FET,TC426CPA U13
19 5 101462 IC,COMPARATOR,DUAL, P/N:LM319M U11 U10 U9 U8
U12
20 5 101501 IC,DIFF-AMP,HI-CMV RANGE,BURR-BROWN:INA117P U25 U23 U24 U27
U26
21 1 52F1921 (NEWARK) IC,FPGA,ALTERA,EPF8282ALC84-4 U14
22 1 AM27C256-120DC-ND (DIGI-KEY) IC,MEMORY,EPROM,256K,150NS,AM27256 U15
23 4 LT1413CN8-ND (DIGI-KEY) IC,OPAMP,DUAL,SINGLE SUPPLY,LINEAR TECH:LT1413CN8 AR4 AR1 AR2 AR3
24 5 101398 IC,OPTO,COUPLER,TEXAS INSTR:TIL111 U16 U17 U20 U18
U19
25 5 101475 IC,OPTO,PHOTOVOLTAIC CELL,DUAL, P/N:DIG-12-06-100 U33 U29 U31 U32
U30
26 5 101402 IC,OPTO,TRIAC,DIP6,MOTOROLA,MOC3022 U4 U5 U7 U6
U3
27 1 101399 IC,REGULATOR,+5V,TO-92,78L05 U22
28 1 101483 IC,REGULATOR,+5V,TO-220AB,7805 U21
29 1 07F7548 (NEWARK) IC,REGULATOR,+8V,TO-220AB,7808 U34
 2 of 3
TED#: 85-0148-001-BOM REV 3
BILL OF MATERIALS 8/21/2002
ENG: L. ZIEGLER
TITLE: CARD, CLK, BI, FPGA, 5 POWER DRIVERS, 2 VREF

30 1 07F7772 (NEWARK) IC,REGULATOR,NEG8V,TO-220AB,7908 XWIRE LEADS 7908-1 & 7908 U1

2 INTO U1-2 & U1-1
RESPECTIVELY
31 1 101722 IC,TTL,HEX SCH/T INV,74LS14 U28
32 1 05F7072 (NEWARK) IC,VOLTAGE REFERENCE,SHUNT,1.2V,ANAL DEV:AD589JH VR8
33 1 101446 IND,FERRITE BEAD, P/N:FB43-101 FB1
34 1 TK4422-ND (DIGI-KEY) IND,FIXED,50KHZ,Q=100,12MA,56MH,TOKO L1
35 1 67-1220-ND (DIGI-KEY) LED, RT ANGLE,GREEN,LUMEX: SSFLXH100LGD ENBLD
36 9 67-1219-ND (DIGI-KEY) LED, RT ANGLE,RED,LUMEX: SSFLXH100LID PS2 PS1 OC PS4
UV PS3 PS5 STATUS
DIG
37 1 101758 OSCILLATOR,20MHZ,VECTRON:C0238B U2
38 5 RES,MF,1/2W,1%,10M R63 R62 R32 R61
R60
39 4 101632 RES,NTWRK,BUS,5/4W,2%,SIP10,4.7K REMOVE R22-7, R22-10, R21- R21 R23 R34 R22
4, R21-6, R21-8 PRIOR TO
INSTALLATION
40 1 4116R-1-681-ND (DIGI-KEY) RES,NTWRK,ISO,2.25W,2%,DIP16,680 R97
41 5 43FR10-ND (DIGI-KEY) RES,PWR,3W,PCB MNT,1%,0.1,OHMITE,43FR10 R24 R29 R28 R27
R25
42 16 RES,TF,1/8W,1%,1.00K R42 R46 R45 R43
R47 R38 R49 R50
R41 R48 R51 R30
R39 R37 R44 R40
43 5 RES,TF,1/8W,1%,4.75K R15 R16 R17 R14
R26
44 2 RES,TF,1/8W,1%,4.99K R35 R36
45 3 RES,TF,1/8W,1%,9.53K R98 R96 R95
46 8 RES,TF,1/8W,1%,10.0K R106 R20 R19 R108
R107 R104 R105 R111
47 2 RES,TF,1/8W,1%,15.0K R110 R109
48 5 RES,TF,1/8W,1%,20.0 R33 R76 R77 R75
R78
49 5 RES,TF,1/8W,1%,51.1K R56 R55 R31 R58
R57
50 5 RES,TF,1/8W,1%,90.9K R1 R3 R4 R5
R2
51 9 RES,TF,1/8W,1%,100 R7 R18 R13 R12
R9 R10 R11 R8
R94
52 7 RES,TF,1/8W,1%,100K R99 R100 R80 R81
R102 R103 R101
53 15 RES,TF,1/8W,1%,332 R86 R87 R85 R84
R88 R90 R91 R92
R93 R89 R82 R59
R83 R64 R79
54 2 RES,TF,1/8W,1%,681 R54 R6
55 10 101552 RES,TRIMPOT,25T,1/2W,10%,1K R69 R74 R67 R66
R65 R72 R73 R70
R68 R71
56 2 101557 RES,TRIMPOT,25T,1/2W,10%,50K R53 R52

57 1 CT2093MS-ND (DIGIKEY) SWITCH,CTS,DIP-6PIN-3POS,209MS SW4

58 2 CT2096MS-ND (DIGIKEY) SWITCH,CTS,DIP-12PIN-6POS,209MS SW3 SW2
59 1 CT2098MS-ND (DIGI-KEY) SWITCH,CTS,DIP-16PIN-8POS,209MS SW1
 3 of 3
TED#: 85-0148-001-BOM REV 3
BILL OF MATERIALS 8/21/2002
ENG: L. ZIEGLER
TITLE: CARD, CLK, BI, FPGA, 5 POWER DRIVERS, 2 VREF

60 2 CKN4003-ND (DIGIKEY) SWITCH,MO,C&K:TP11SH9ABE ENA RST

61 56 101539 TESTPOINT,SINGLE,104-30-02 STAT +5V OUT3 CPCLK
DIG4 +8V -12V OUT5
-8V UV1 OUT2 OUT1
OCTRIP5 OCTRIP4 OCTRIP3 OCTRIP2
OCTRIP1 OC5 OC4 OC3
OC2 OC1 UVTRIP3 BUZ
DFLT VREG2 IN1 FLT
UVTRIP5 D5_6 DIG7 DIG6
D3_4 +5VREF UVTRIP4 UV2
UV3 UV4 UV5 UVTRIP1
UVTRIP2 CLK
D1_2 DIG1 IN2 DIG2
DIG3 +12V VREG1 IN3
DIG8 D7_8 DIG5 IN4
OUT4 IN5
62 3 101095 TRAN,NPN,40V,2N2222A,MOT Q6 Q7 Q8
63 1 06F8477 (NEWARK) TRANS,MOSFET,P-CHANNEL,TO-220,IRF9540 Q5
64 1 101418 HARDWARE,HEAT SNK,TO-220,WAKEFIELD :289AB U21
65 1 HARDWARE,SCRW,RND HD,#4-40 X .38 LG U21
66 1 HARDWARE,NUT, #4 U21
67 1 HARDWARE,WSHR, LOCK, #4 U21
68 1 A347-ND (DIGI-KEY) SOCKET,IC,DIP28,600MI,ARIES,ZIF,LO-PROFILE XU15
69 10 A9306-ND (DIGI-KEY) SOCKET,IC,DIP6,300MIL XU16 XU17 XU20 XU18
XU19 XU3 XU7 XU6
XU4 XU5
70 15 101419 SOCKET,IC,DIP8,300MIL XU25 XU23 XU24 XU27
XU26 XU13 XU30 XU29
XAR4 XAR1 XAR2 XAR3
XU33 XU31 XU32
71 5 101420 SOCKET,IC,DIP14,300MIL XU11 XU10 XU9 XU8
XU12
72 1 A2125-ND(DIGI-KEY) SOCKET,PLCC 84, AMP:821573-1 XU14
73 1 85-0148-001 PCB,SUPPLY MON,BURN-IN,FPGA
74 10 V1075-ND (DIGI-KEY) VECTOR,KLIPWRAP TERMINAL,T49/C XR25(2) XR24(2) XR27(2) XR28(2)
XR29(2)
75 4 101406 TRANSISTOR,N-CH FET,IRF640,200V,TO220 Q1 Q2 Q3 Q4
76 2 RES,CC,1/4W,5%,4.7K R112 R113
77 1 85-0148-008 POWER CARD REINFORCING BAR

78 5 RES,MF,1/2W,1%,604 Pull down resistors on 5 R114 R115 R116 R117

"SEQ_EN" lines. See wirelist
R118
TED#: 85-0148-001-WRL REV 3
WIRE LIST PAGE 1 OF 1
TITLE: CARD, CLK, BI, FPGA, 5 POWER DRIVERS, 2 VREF ENG: L. ZIEGLER DATE: 8/21/2002

For Details See PCB Assembly Drawing

WIRE # FROM TO SIGNAL NOTES WIRE TYPE

1 TP-DFLT R34-4 DigFault Pull-up 24Awg,BLU,SLD

2 U1-1 7908-2 -12V Bend pin of 7908-2 into U1-1, use shrink tube A/N N/A
3 U1-2 7908-1 GND Bend pin of 7908-1 into U1-2, use shrink tube A/N N/A
4 U14-83 R22-2 nEN_VREG1 24Awg,BLU,SLD
5 U14-45 or Via near R22-1 R22-3 nEN_VREG2 Via near R22-1 is preferable 24Awg,BLU,SLD
6 R112-1 R22-2 Base Res *
7 R113-1 R22-3 Base Res *
8 R112-2 Q7-2 Base Q7 *
9 R113-2 Q8-2 Base Q8 *
10 Q7-1 C79-2 GND Tie emitters of Q7, Q8 together *
11 Q8-1 C79-2 GND Tie emitters of Q7, Q8 together *
12 Q7-3 AR4-3 Collector Q7 *
13 Q8-3 AR4-5 Collector Q8 *
14 R114-1 PCB @R21-8** SEQ_EN5 Pull down to bias U7 & U20 *
15 R114-2 U2-7 GND Pull down to bias U7 & U20 *
16 R115-1 PCB @R21-6** SEQ_EN4 Pull down to bias U6 & U19 *
17 R115-2 U2-7 GND Pull down to bias U6 & U19 *
18 R116-1 PCB @R21-4** SEQ_EN3 Pull down to bias U5 & U18 *
19 R116-2 U2-7 GND Pull down to bias U5 & U18 *
20 R117-1 PCB @R22-7** SEQ_EN1 Pull down to bias U3 & U16 *
21 R117-2 U2-7 GND Pull down to bias U3 & U16 *
22 R118-1 PCB @R21-10** SEQ_EN2 Pull down to bias U4 & U17 *
23 R118-2 U2-7 GND Pull down to bias U4 & U17 *

Construction Notes:
1) Refer to attached drawing for exact location of all cuts and jumps.
2) Install R112, R113, Q7, Q8 on Circuit side.
* Use Comp body as jumper; extend Comp leads using 24Awg,BLU,SLD wire as needed.
**Resistors in networks (R21 & R22) have been removed. Connect new res to PCB land.
TED#: 85-0148-001-CUT REV 1
CUTS LIST PAGE 1 OF 1
TITLE: CARD, CLK, BI, FPGA, 5 POWER DRIVERS, 2 VREF ENG: L. ZIEGLER DATE: 8/21/2002

For Details See PCB Assembly Drawing

CUT # FROM TO NOTES CUT ON SIDE

1 AR4-3 U14-83 AR4 Circuit

2 AR4-5 U14-45 AR4 Circuit
 A B C D

2/2C
FB1 DIGV1_2
R97 DIG 2/2C
FERITE_BEAD DIGV3_4
7 10 +5V +8V -8V 2/2C
+5V DIGV5_6
2/2C
+5V 680 DIGV7_8
CLK R97 PS1 FLT
14 4 13
+5V
VS+ 17 18 19 1 5 9 13
C26 8 680 DFLT +5V +8V -8V V1_2 V5_6 J1
OUT 20MHZCLK R97 PS2
1000PF 5 12 V3_4 V7_8
GND U2 1/1C +5V
1/1A 25 DIG1 3 2/1C
20MHZ 680 20MHZCLK 20MHZCLK DIG1
7 R97 PS3 1/2B 27
OSC FAULT FAULT
6 11 1/2B 23 DIG2 4 2/1C
+5V DIG_FLT DIG_FLT DIG2
1
1/4C
STATUS STAT
FPGA 680
R97 PS4 RESET
1/1A
24
28
EN_DIG
RESET
DIG3 7 2/1C
DIG3
1

681
TF
EPF8282ALC84-X 3 14
+5V
FPGA DIG4 8 2/2C
DIG4
12 55 680
+5V +5V 20MHZCLK LED_DIGFLT R97 PS5
27 1 16 1/4B 26 DIG5 11 2/2C
STATUS R54 LED_FLT1 +5V A A DIG5
75 2 1/4B 29
+5V NS/P LED_FLT2 680 B B
41 R97 OC 1/4B 30 DIG6 12 2/2C
LED_FLT3 C C DIG6
R103 74 28 2 15 1/4B 32
MSEL0 LED_FLT4 +5V D D
100K 53 16 1/1A 20 DIG7 15 2/2C
RESET MSEL1 LED_FLT5 680 SPARE5 SPARE5 DIG7
32 24 R97 UV 1/1A 22
STATUS LED_OC SPARE6 SPARE6
R94 U28 U28 10 56 8 9 1/1A 31 DIG8 16 2/3C
1/1C DCLK LED_UV +5V SPARE7 SPARE7 DIG8
TF 1 2 11 10 33 1/1A 21
CONFIG 680 SPARE8 SPARE8
RST
100 1/1C 77
FAULT
40
FAULT 85-0148-002
C9
4.7UF
SN74LS14 SN74LS14 SPARE5
SPARE6
1/1C 81
SPARE5
SPARE6 EN_PS1
48
1/1C
0 0 2 10 Gnd 8 DIG DRIVERS
R6 1/1C 49 25 1 1 6 14
TA SPARE7 SPARE7 EN_PS2
681 1/1C 79 82 2 2
SPARE8 SPARE8 EN_PS3
36 22 3 3
+5V LED_EN EN_PS4
72 4 4
ENBLD TF U14 EN_PS5 +8V
0 10 VCP 11 14 83 5 5
A0 D0 DATA0 EN_VREG1
1 9 12 13 45 6 6
A1 D1 DATA1 EN_VREG2
BOOT PROM

2 8 13 9 15 7 7
A2 D2 DATA2 EN_DIG
3 7 15 8 +8V
A3 D3 DATA3
4 6 16 7 73 0
A4 D4 DATA4 OCFLT1
5 5 17 6 35 1 VREG1 2/2C
A5 D5 DATA5 OCFLT2 1.2V AV=? VREG1
6 4 18 4 42 2
2 A6 D6 DATA6 OCFLT3 EN1 2
7 3 19 3 19 3
A7 D7 DATA7 OCFLT4
8 25 20 4
A8 OCFLT5
9 24 11 EN2
A9 CONF_DONE

SEQ_EN[1:8]
10 21 37 0 VREG2 2/2C
A10 UVFLT1 1.2V AV=? VREG2
11 23 0 78 39 1
A11 BADDR0 UVFLT2
12 2 U15 1 76 23 2
A12 BADDR1 UVFLT3
13 26 2 71 34 3 DUAL VOLTAGE REF
CONF_DONE

A13 AM27256 BADDR2 UVFLT4

14 27 3 70 21 4 85-0148-001-SCH-02 GND
A14 BADDR3 UVFLT5
4 69
BADDR4 +8V
5 67 1
BADDR5 DIG_FLT DIG_FLT
OE
CE

6 66
BADDR6 1/1C
7 65 18 0
20 22 BADDR7 TIMER_EN
8 64 29 1 +8V
1/4C BADDR8 BUZZER_EN
9 63 44 2 0 2/1C

OCFLT[1:5]
BADDR9 DIGFLT_EN SEQ_EN1 VOUT1 VOUT1
10 62 43 3 1 2/1C
BADDR10 UVFLT_EN SEQ_EN2 VOUT2 VOUT2
11 61 46 4 2 2/3C
BADDR11 OCFLT_EN SEQ_EN3 VOUT3 VOUT3
12 60 50 5 3 2/3C

5 CHANNEL SHUT DOWN CIRCUIT

BADDR12 BIT_1 SEQ_EN4 VOUT4 VOUT4
13 58 54 6 4 2/3C
BADDR13 BIT_0 SEQ_EN5 VOUT5_NEG VOUT5_NEG
14 57 51 7
BADDR14 PS5_EN OC4 OC2

ADDR[0:14]
84
BUZZER OC5 OC3 OC1 PGND
50
PGND
SW1 DIP SWITCH DECODER

85-0148-001-SCH-03
30
CLK1MHZ CPCLK
31
TGL_SPLY_EN 1/3B,2/3A
0 2/1C SWITCH# FUNCTION STATE
---------------------------------------------------------------------------

UVFLT[1:5]
OCFLT1 VIN1 VIN1
1 2/1C
+5V OCFLT2 VIN2 VIN2
2 2/3C
3 +5V 3
OCFLT3 VIN3
2/3C
VIN3 1=OFF 5 MIN TIMER ENABLED 3

SWITCH[0:7]
OCFLT4 VIN4 VIN4
4 2/3C
1 R23 4.7K OCFLT5 VIN5_NEG VIN5_NEG 2=OFF BUZZER ENABLED
50MH UV4 UV2
L1 3=OFF DIGITAL FAULT ENABLED
UV5 UV3 UV1 X1V
15 2 3 4 5 6 7 8 9 10
PGND X1G 4=OFF UNDER VOLTAGE ENABLED
2N2222A BUZ BUZZER
CPCLK 0
U28 1/3B,2/3A 1
UVFLT1 X2V 5=OFF OVER CURRENT ENABLED
Q6 R26 1/4C UVFLT2 PGND X2G
TF 4 3 2
1 1 16 0 3
UVFLT3 +5V_REF +5V_REF 6=ON, 7 = ON PWR SUP 1 ENABLED
BZ1 TIMER_DIS UVFLT4 2/2B X3V
4.75K 2 2 15 1 4
BUZZER SN74LS14 BUZZER_DIS UVFLT5 PGND X3G 6=ON, 7 = OFF PWR SUP 1,2 ENABLED
3 3 14 2
DIGFLT_DIS -8V GND
4 4 13 3
UVFLT_DIS
5 5 12 4
X4V 6=OFF, 7 = ON PWR SUP 1,2,3 ENABLED
OCFLT_DIS PGND X4G
6 6 11 5
BIT1
7 7 10 6 6=OFF, 7 = OFF PWR SUP 1,2,3,4 ENABLED
BIT0 -8V X5V
8 8 9 7
+5V PS5_DIS PGND X5G 8=OFF PWR SUP 5 ENABLED
SW1
A
1/1C +5V
APPROVAL
R80 B
100K 1/1C 1 R34 4.7K
C
R18 U28 U28 1/1C
TEST ENGINEER
TF 5 6 9 8
D
4 ENA
100
C79 SN74LS14 SN74LS14
1/1C 2 103 5 6 7 8 9 4
ZIEGLER TITLE CARD, CLK, BI, FPGA 4
PRODUCT ENGINEER
4.7UF
TA
BYPASS CAPS 5 POWER CHANNELS, 2 VREF
BUZZER
ROSSELLI

DIG_FLT
STATUS
+5V +5V +5V +5V +5V +5V 1/2A CONF_DONE
REV SIZE TED NUMBER
REVISION DESC:
C32
.1UF
CC
C31
.1UF
CC
C30
.1UF
CC
C29
.1UF
CC
C28
.1UF
CC
C27
.1UF
CC
1 B 85-0148-001-SCH-01
DATE FILE //jafar/te_lib/public_html/ted/85 SHEET OF
1/1A

1/3A

1/3A 4/30/99 1 2
/85-0148/85-0148-001/sch
A B C D
 A B C D

1/3D IN1
+5V 25 1 I1 VIN1 1A
+12V VIN1 E E P1A
2 G1 GND1 1B
1/3D OUT1 PGND E E P1B
1 25 3 O1 VOUT1 2A 1
VOUT1 E E P2A
2B
1 1/3D IN2 E P2B
U21 25 6 I2 VIN2 3A
VIN2 E E P3A
+12V VIN 7 G2 GND2 3B
1/3D OUT2 PGND E E P3B
GND1 3 25 25 13 O2 VOUT2 4A
VOUT +5V VOUT2 E E P4A
4B
1/1D DIG1 E P4B
C1 GND C68 20 5 D1 DIG1 5A
DIG1 E E P5A
470UF 2 47UF 5B
1/1D DIG2 E P5B
AL 20 8 D2 DIG2 6A

85-0148-003
TA DIG2 E E P6A
6B
1/1D DIG3 E P6B
20 10 D3 DIG3 7A
DIG3 E E P7A
7B
1/1D DIG4 E P7B
20 11 D4 DIG4 8A
DIG4 E E P8A
8B
1/1D D1_2 E P8B
+5VREF 20 4 D12 D1_2 9A
+12V DIGV1_2 E E P9A
12 G3 GND3 9B

EDGE FINGER CONNECTOR

1/1D D3_4 E E P9B
20 9 D34 D3_4 10A
DIGV3_4 E E P10A
10B

HEADER CONNECTOR
3 +12V E P10B
U22 25 14 V12_1 12V_1 11A
+12V E E P11A
VIN 11B
E P11B
1 1/3C 15 G4 GND4 12A
VOUT +5V_REF E E P12A
12B
E P12B
GND 16 V12_2 12V_2 13A

Wire Programming Card

C25 E E P13A
78L05 2 47UF 13B
E P13B
17 VRG VRGND 14A
TA E E P14A
14B
1/2D VREG1 E P14B
20 18 VR1 VREG1 15A
2 VREG1 E E P15A 2
15B
1/2D VREG2 E P15B
20 19 VR2 VREG2 16A
VREG2 E E P16A
16B
+12V +12V 1/1D D5_6 E P16B
C80 +8V 20 29 D56 D5_6 17A
+12V DIGV5_6 E E P17A
TA 21 G5 GND5 17B
1 2 1/1D D7_8 E E P17B
20 26 D78 D7_8 18A
47UF BAS70-04 DIGV7_8 E E P18A
18B
U34 D3 1/1D DIG5 E P18B
C67 1 20 28 D5 DIG5 19A
DIG5 E E P19A
VIN 3 19B
1/1D DIG6 E P19B
3 20 20 27 D6 DIG6 20A
.1UF VOUT +8V DIG6 E E P20A
20B
CPCLK CC 1/1D DIG7 E P20B
6 GND C8 20 25 D7 DIG7 21A
DIG7 E E P21A
V+ 2 7808 47UF 21B
1/1D DIG8 E P21B
2 7 20 20 24 D8 DIG8 22A
TA DIG8 E E P22A
22B
GND 1/3D IN3 E P22B
U13 25 20 I3 VIN3 23A
VIN3 E E P23A
3 22 G6 GND6 23B
TSC426 1/3D OUT3 PGND E E P23B
25 23 O3 VOUT3 24A
-12V VOUT3 E E P24A
24B
1/3D IN4 E P24B
C66 D16 25 30 I4 VIN4 25A
VIN4 E E P25A
20 20 -12V -8V 31 G7 GND7 25B
CPCLK 1/3D OUT4 PGND E E P25B
25 32 O4 VOUT4 26A
1/3B, +12V .1UF 1N5820 1 2 VOUT4 E E P26A
26B
CC AL BAS70-04 1/3D IN5 E P26B
D15 25 34 I5 VIN5 27A
470UF D4 VIN5_NEG E E P27A
1N5820 35 G8 GND8 27B
C6 U1 1/3D OUT5 PGND E E P27B
6 2 3 25 33 O5 VOUT5 28A
VOUT5_NEG E E P28A
3 V+ VIN 28B 3
E P28B
4 5 3 J3 P1
VOUT -8V
20
GND TA
U13 GND
3 1 7908 47UF
TSC426 C10

APPROVAL

TEST ENGINEER

4 ZIEGLER TITLE CARD, CLK, BI, FPGA 4

U28 PRODUCT ENGINEER
13 12 5 POWER CHANNELS, 2 VREF
SN74LS14
ROSSELLI REV SIZE TED NUMBER
REVISION DESC:
1 B 85-0148-001-SCH-01
DATE FILE //jafar/te_lib/public_html/ted/85 SHEET OF

4/30/99 /85-0148/85-0148-001/sch 2 2
A B C D
 2 4
1 3

+8V +8V

C65
.1UF

+8V +8V

2 1
BAS70-04
D1
8
3 + 3
VS+
PU1 R12 F1
1 TF
AR4 VREG1
B C63 B
100 .25 AMP
R112 CC .1UF 2 VS- LT1413CN8
EN1
CC Q7 -
2N2222A 4
4.7K
TF
R19
+8V
10.0K

TF R35
CCW R52
R111 TF 25T
10.0K
4.99K 50K
TF VOLTAGE GAIN PROGRAMMABLE FROM 1.6V TO 5.6V
R109
15.0K
1
VR8
1.2V
AD589JH
2
TF
R20
10.0K
+8V +8V

2 1
BAS70-04
D2
8
5 + 3
VS+
PU2 R13 F2
7 TF
AR4 VREG2
C64
100 .25 AMP
R113 CC .1UF 6 VS- LT1413CN8
EN2
CC Q8 -
2N2222A 4
4.7K

R36
CCW R53
TF 25T
A
A 4.99K 50K
TF VOLTAGE GAIN PROGRAMMABLE FROM 1.6V TO 5.6V
R110
15.0K

FUSES ARE NANO^2 FAST ACTING FUSES W/OMNI-BLOK

APPROVAL
DIGI-KEY P/N F1219CT-ND
REPLACEMENT FUSES: DIGI-KEY F1140CT-ND TEST ENGINEER

ZIEGLER TITLE CARD, CLK, BI, FPGA

PRODUCT ENGINEER
DUAL VOLTAGE REFERENCE SUB CKT
ROSSELLI REV SIZE TED NUMBER

A 85-0148-001-SCH-02
REVISION DESC:

1
DATE FILE
//jafar/te_lib/public_html/ted/85 SHEET OF

4/30/99 /85-0148/85-0148-001/sch
1 1
1 3
2 4
 A B C D

+5V +5V

1 R21 4.7K

C33 C34
.1UF .1UF 4 2 3 6 5 7 8 9 10
3/2A
CC CC
3/3A
3/4A
F3 4/2A
1 +5V 1

PU10
PU11
PU12
PU13
PU14
PU15
PU16
PU17
PU18
VIN1 4/3A
5 AMP 4/4A
+8V +8V 5/4A
R102 C2 5/1A
C36 C35 C39 R82 1 5 100K 470UF 5/2A
.1UF .1UF .1UF U16 +5V
332 AL
CC CC CC TIL111
7 1 R22 4.7K
PGND
2 6 4
U29 2 SCH-02-1/1A
C38 C37 1 R75
1 Q1 SCH-02-1/1B
.1UF .1UF
CC CC 8 C11 IRF640 3 4 2 7 6 5 108 9
R84 R55 20 1/2A
5 1000PF 332 51.1K +5V
-8V -8V 3 1/3A
.06W 1/4A
2 VR1 2/2A
1 6

PU2

PU1
PU4
PU5
PU6
PU7
PU8
PU9
1N4745 R60 2/3A
U3 16V 10M 2/4A
DIG12-06-100 6 MOC3022
+5V_REF +5V_REF
2 4
1/3B,1/4B,2/3B,2/4B,3/3B,3/4B,4/3B,4/4B,5/1B,5/2B
R25
3W
PGND PGND VOUT1

0.1

2 R83 2
332 +8V -8V
PU4

1/2D
7 4
SEQ_EN1
V+ V-
SW2 2
10.0K R104 1 12
2 11 R37 -
1.00K R38 3 10 6
+ 3
1.00K U23
100 R7
COMP
+8V
+8V 8 5 1
INA117
N1

8
2
11 VS+ -
PU5 R39
+9 1
AR1
VS+
1/2D OCTRIP1 1.00K
7 +5V_REF VS- + 3
OCFLT1 U8 LT1413CN8
GND 1/2A C70
VS- 10 100PF 4
8 -
6 CCW R65
LM319 1K
3 3
C13 -8V
1000PF
-8V

+8V

11 R1
PU6
- 5
VS+
1/2D UVTRIP1
12 +5V_REF 90.9K
UVFLT1 U8
GND 1/2A C69
VS- 4 100PF R14
3 + R66 4.75K APPROVAL
6 CCW
LM319 1K

C12
TEST ENGINEER
-8V 1000PF
4 UNDER VOLTAGE TRIP LEVEL
(UVTRIP) = Vout/20
ZIEGLER TITLE CARD, CLK, BI, FPGA 4
PRODUCT ENGINEER
5 CHANNEL SHUTDOWN SUB CKT
ROSSELLI REV SIZE TED NUMBER
REVISION DESC:

FUSES ARE NANO^2 FAST ACTING FUSES

1 B 85-0148-001-SCH-03
REPLACEMENT FUSES: DIGI-KEY F1149CT-ND
DATE FILE //jafar/te_lib/public_html/ted/85 SHEET OF

4/30/99 /85-0148/85-0148-001/sch 1 5
A B C D
 A B C D

+5V

C43 C44
.1UF .1UF
CC CC F4
1 +5V 1
VIN2
5 AMP

R99 C3
R85 1 5 100K 470UF
+8V
332 U17 AL
C42 C41 TIL111
.1UF .1UF 7
PGND
CC CC 2 6 4
U30 2
1 R76
1 Q2
C40 C45 8 C16 IRF640
R86 R56 20
.1UF .1UF 5 1000PF 332 51.1K +5V
3
CC CC .06W
2 VR2
-8V
1 6 1N4745 R61
U4 16V 10M
DIG12-06-100 6 MOC3022
2 4
R24
3W
VOUT2

0.1

2 R87 2
332 +8V -8V
PU7

1/2D
7 4
SEQ_EN2
V+ V-
SW2 2
10.0K R105 4 9
5 8 R42 -
1.00K R40 6 7 6
+ 3
1.00K U24
100 R8
COMP
+8V
+8V 8 5 1
INA117

8
6
11 VS+ -
PU8 R41
+9 7
AR1
VS+
1/2D OCTRIP2 1.00K
7 +5V_REF VS- + 5
OCFLT2 U9 LT1413CN8
GND 1/2A C71
VS- 10 100PF 4
8 -
6 CCW R67
LM319 1K
3 3
C14 -8V
1000PF
-8V

+8V

11 R2
PU9
- 5
VS+
1/2D UVTRIP2
12 +5V_REF 90.9K
UVFLT2 U9
GND 1/2A C72
VS- 4 100PF R15
3 + R68 4.75K APPROVAL
6 CCW
LM319 1K

C15
TEST ENGINEER
-8V 1000PF
4 UNDER VOLTAGE TRIP LEVEL
(UVTRIP) = Vout/20
ZIEGLER TITLE CARD, CLK, BI, FPGA 4
PRODUCT ENGINEER
5 CHANNEL SHUTDOWN SUB CKT
ROSSELLI REV SIZE TED NUMBER
REVISION DESC:

FUSES ARE NANO^2 FAST ACTING FUSES

1 B 85-0148-001-SCH-03
REPLACEMENT FUSES: DIGI-KEY F1149CT-ND
DATE FILE //jafar/te_lib/public_html/ted/85 SHEET OF

4/30/99 /85-0148/85-0148-001/sch 2 5
A B C D
 A B C D

+5V

C49 C50
.1UF .1UF
CC CC F5
1 +5V 1
VIN3
5 AMP

R100 C4
R88 1 5 100K 470UF
+8V
332 U18 AL
C48 C47 C52 TIL111
.1UF .1UF .1UF 7
PGND
CC CC CC 2 6 4
U31 2
1 R77
1 Q3
C46 C51 8 C19 IRF640
R89 R57 20
.1UF .1UF 5 1000PF 332 51.1K +5V
3
CC CC .06W
2 VR3
-8V
1 6 1N4745 R62
U5 16V 10M
DIG12-06-100 6 MOC3022
2 4
R27
3W
VOUT3

0.1

2 R90 2
332 +8V -8V
PU10

1/1D
7 4
SEQ_EN3
V+ V-
SW3 2
10.0K R106 1 12
2 11 R45 -
1.00K R43 3 10 6
+ 3
1.00K U25
100 R9
COMP
+8V
+8V 8 5 1
INA117

8
2
11 VS+ -
PU11 R44
+9 1
AR2
VS+
1/1D OCTRIP3 1.00K
7 +5V_REF VS- + 3
OCFLT3 U10 LT1413CN8
GND 1/2A C73
VS- 10 100PF 4
8 -
6 CCW R69
LM319 1K
3 3
C17 -8V
1000PF
-8V

+8V

11 R3
PU12
- 5
VS+
1/1D UVTRIP3
12 +5V_REF 90.9K
UVFLT3 U10
GND 1/2A C74
VS- 4 100PF R16
3 + R70 4.75K APPROVAL
6 CCW
LM319 1K

C18
TEST ENGINEER
-8V 1000PF
4 UNDER VOLTAGE TRIP LEVEL
(UVTRIP) = Vout/20
ZIEGLER TITLE CARD, CLK, BI, FPGA 4
PRODUCT ENGINEER
5 CHANNEL SHUTDOWN SUB CKT
ROSSELLI REV SIZE TED NUMBER
REVISION DESC:

FUSES ARE NANO^2 FAST ACTING FUSES

1 B 85-0148-001-SCH-03
REPLACEMENT FUSES: DIGI-KEY F1149CT-ND
DATE FILE //jafar/te_lib/public_html/ted/85 SHEET OF

4/30/99 /85-0148/85-0148-001/sch 3 5
A B C D
 A B C D

+5V

C56 C57
.1UF .1UF
CC CC F6
1 +5V 1
VIN4
5 AMP

R101 C5
R91 1 5 100K 470UF
+8V
332 U19 AL
C55 C54 TIL111
.1UF .1UF 7
PGND
CC CC 2 6 4
U32 2
1 R78
1 Q4
C53 C58 8 C22 IRF640
R92 R58 20
.1UF .1UF 5 1000PF 332 51.1K +5V
3
CC CC .06W
2 VR4
-8V
1 6 1N4745 R63
U6 16V 10M
DIG12-06-100 6 MOC3022
2 4
R28
3W
VOUT4

0.1

2 R93 2
332 +8V -8V
PU13

1/1D
7 4
SEQ_EN4
V+ V-
SW3 2
10.0K R107 4 9
5 8 R48 -
1.00K R46 6 7 6
+ 3
1.00K U26
100 R10
COMP
+8V
+8V 8 5 1
INA117

8
6
11 VS+ -
PU14 R47
+9 7
AR2
VS+
1/1D OCTRIP4 1.00K
7 +5V_REF VS- + 5
OCFLT4 U11 LT1413CN8
GND 1/2A C75
VS- 10 100PF 4
8 -
6 CCW R71
LM319 1K
3 3
C20 -8V
1000PF
-8V

+8V

11 R4
PU15
- 5
VS+
1/1D UVTRIP4
12 +5V_REF 90.9K
UVFLT4 U11
GND 1/2A C76
VS- 4 100PF R17
3 + R72 4.75K APPROVAL
6 CCW
LM319 1K

C21
TEST ENGINEER
-8V 1000PF
4 UNDER VOLTAGE TRIP LEVEL
(UVTRIP) = Vout/20
ZIEGLER TITLE CARD, CLK, BI, FPGA 4
PRODUCT ENGINEER
5 CHANNEL SHUTDOWN SUB CKT
ROSSELLI REV SIZE TED NUMBER
REVISION DESC:

FUSES ARE NANO^2 FAST ACTING FUSES

1 B 85-0148-001-SCH-03
REPLACEMENT FUSES: DIGI-KEY F1149CT-ND
DATE FILE //jafar/te_lib/public_html/ted/85 SHEET OF

4/30/99 /85-0148/85-0148-001/sch 4 5
A B C D
 A B C D

+8V -8V

7 4
V+ V-
SW4 2
10.0K R108 1 1 6 +5V
2 2 5 R51 -
1.00K R49 3 3 4 6
+ 3
1.00K U27
100 R11
1 C62 C82 1
COMP .1UF .1UF
+8V
+8V 8 5 1 CC CC
INA117

8
2
11 VS+ -
PU17 R50 +8V
+9 1
AR3
VS+ C61 C60 C84
1/1D OCTRIP5 1.00K
7 +5V_REF VS- + 3 .1UF .1UF .1UF
OCFLT5 U12 LT1413CN8
GND 1/2A C77 CC CC CC
VS- 10 100PF 4
8 -
6 CCW R73 C59 C83
LM319 1K .1UF .1UF
C23 -8V CC CC
1000PF
-8V
-8V R96 R98 R5 TF
TF TF
9.53K 9.53K
90.9K
-8V TF
+8V R95
9.53K
2 2
4
LT1413CN8 VS-
-
11 R30 6
PU18
- 5 TF
AR3
VS+ 7
1/1D UVTRIP5 1.00K
12 +5V_REF VS+
UVFLT5 U12
GND 1/2A C78 + 5
VS- 4 100PF 8
3 + R74
6 CCW
LM319 1K
+8V
C24
-8V 1000PF
UNDER VOLTAGE TRIP LEVEL
(UVTRIP) = Vout/20
+5V

R79 1 5
332 U20
TIL111
7
2 6 4
U33
3 1 R29 3
3W
VOUT5_NEG
8 C81 R64 R31
5 1000PF 332 51.1K +5V 0.1
.06W
2 VR5
1 6 1N4745 R32
U7 16V 10M
DIG12-06-100 6 MOC3022
PGND
2 4
R33 3
1 Q5
IRF9540 100K C7
20 R81 470UF
2 AL
F7
VIN5_NEG
R59 5 AMP
PU16 332

1/1D APPROVAL
SEQ_EN5

TEST ENGINEER

4 ZIEGLER TITLE CARD, CLK, BI, FPGA 4

PRODUCT ENGINEER
5 CHANNEL SHUTDOWN SUB CKT
ROSSELLI REV SIZE TED NUMBER
REVISION DESC:

FUSES ARE NANO^2 FAST ACTING FUSES

1 B 85-0148-001-SCH-03
REPLACEMENT FUSES: DIGI-KEY F1149CT-ND
DATE FILE //jafar/te_lib/public_html/ted/85 SHEET OF

4/30/99 /85-0148/85-0148-001/sch 5 5
A B C D
 DESIGN COVER SHEET
TITLE: CARD,CLK,BI,FPGA, 8 DIGITAL DRIVERS, 2 DACS 85-0148-002
ENG: L. ZIEGLER

Status > PROD

Design Rev > OI

DWG/DOC No. SIZE DSK Name, Description Revisions

-002 A FINAL ASSEMBLY 1
-002-SCH-01 A SCHEMATIC 1
-002-SCH-02 A SCHEMATIC 1
-002-SCH-03 A SCHEMATIC 1
-002-BOM A BILL OF MATERIALS 1
-002-WRL A WIRELIST 1
-002-MAP A ROAD MAP OF PCB 1
-002-ART FILMS OF PCB ARTWORK 1
-002-ZIP 3.5" ZIP FILE OF PCB ARTWORK 1
 TED#: 85-0148-002-BOM REV 1
BILL OF MATERIALS PAGE 1 OF 1
TITLE: CARD, CLK, BI, FPGA, 8 DIGITAL DRIVERS 2 DACS ENG: L. ZIEGLER DATE: 8/21/2002

ITEM # QTY PART NO. DESCRIPTION NOTES REF1 REF2 REF3 REF4

1 4 101365 CAP,CC.50V,+/-10%,.01UF C1 C2 C3 C4
2 15 101366 CAP,CC.50V,+/-10%,.1UF C31 C9 C10 C11
C12 C16 C19 C20
C41 C32 C27 C28
C29 C30 C43
2A 16 NOT INSTALLED NOT INSTALLED C34 C23 C24 C13
C14 C15 C17 C18
C21 C22 C25 C26
C39 C35 C40 C33
3 6 101387 CAP,TA,50V,+/-20%,4.7UF C36 C37 C7 C5
C8 C6
4 6 101229 CONN,HEADER,MALE,SINGLE,2 PINS REQD,3M:929834-01-36 JDAC1 DAC1_1X DAC0_1X JDAC0
JDIG8 JDIG7
5 1 101229 CONN,HEADER,MALE,SINGLE,32 PINS REQD,3M:929834-01-36 (4) 8 PIN LOCATIONS P1
6 1 MAX518BCPA-ND (DIGI-KEY) DAC,MAXIM518,8BIT,SERIAL,DUAL,SINGLESUPPLY U9
7 2 BAS70-04DICT-ND (DIGI-KEY) DIODE,SCHOTTKY,SMD,IF=200MA,RRT=4NS,DUAL,BAS70-04 D10 D9
8 4 101063 DIODE,ZENER,1W,13V,1N4743 VR2 VR3 VR4 VR1
9 14 F1219CT-ND (DIGI-KEY) FUSE,SMD,HLDR & FAST ACTING FUSE,.25 A,OMNI-BLOK:F1219CT F1 F2 F3 F4
F5 F6 F7 F8
F9 F10 F11 F12
F13 F14
10 4 158-1050-ND (DIGI-KEY) IC,BUFFER/DRIVER,DUAL,1.5A,FET,TC426CPA U2 U6 U4 U8
11 4 101462 IC,COMPARATOR,DUAL, P/N:LM319M U5 U3 U7 U1
12 1 52F1921 (NEWARK) IC,FPGA,ALTERA,EPF8282ALC84-4 U11
13 1 AM27C256-120DC-ND (DIGI-KEY) IC,MEMORY,EPROM,256K,150NS,AM27256 U10
14 1 LT1413CN8-ND (DIGI-KEY) IC,OPAMP,DUAL,SINGLE SUPPLY,LINEAR TECH:LT1413CN8 AR1
15 1 67-1220-ND (DIGI-KEY) LED, RT ANGLE,GREEN,LUMEX: SSFLXH100LGD ENBLD
16 3 101632 RES,NTWRK,BUS,5/4W,2%,SIP10,4.7K R3 R10 R11
17 1 4116R-1-472-ND (DIGI-KEY) RES,NTWRK,ISO,2.25W,2%,DIP16,4.7K R12
18 8 RES,TF,1/8W,1%,2.00K R31 R13 R34 R33
R32 R35 R29 R30
19 2 RES,TF,1/8W,1%,49.9K R4 R5
20 2 RES,TF,1/8W,1%,100 R2 R1
21 2 RES,TF,1/8W,1%,100K R7 R8
22 1 RES,TF,1/8W,1%,681 R6
23 2 RES,TF,1W,5%,0 R21 R20
24 8 P51XCT-ND (DIGI-KEY) RES,TF,1W,5%,51 R25 R27 R15 R16
R23 R17 R18 R24
24A 8 NOT INSTALLED NOT INSTALLED R26 R28 R22
R14 R9 R19
25 1 CT2094MS-ND (DIGI-KEY) SWITCH,CTS,DIP-8PIN-4POS,209MS SW1
26 8 BAS70DICT-ND (DIGI-KEY) VISHAY,BAS70,DIGIKEY-BAS70DICT-ND D5 D7 D6 D8
D4 D3 D2 D1
27 1 A347-ND (DIGI-KEY) SOCKET,IC,DIP28,600MI,ARIES,ZIF,LO-PROFILE XU10
28 6 101419 SOCKET,IC,DIP8,300MIL XU9 XU2 XU4 XU6
XU8 XAR1
29 4 101420 SOCKET,IC,DIP14,300MIL XU1 XU3 XU5 XU7
30 1 A2125-ND(DIGI-KEY) SOCKET,PLCC 84, AMP:821573-1 XU11
31 1 85-0148-002 PCB,SUPPLY MON,BURN-IN,FPGA,8 CHANNEL DIGITAL DRIVER CARD
TED#: 85-0148-002-WRL REV 1
WIRE LIST PAGE 1 OF 1
TITLE: CARD,CLK,BI,FPGA, 8 DIGITAL DRIVERS, 2 DACS ENG: L. ZIEGLER DATE: 8/21/2002

For Details See PCB Assembly Drawing

WIRE # FROM TO SIGNAL NOTES WIRE TYPE

1 U11-32 R3-4 Status pull-up 24AWG,BLU,STR

 A B C D

+5V
FUSES ARE NANO^2 FAST ACTING FUSES W/OMNI-BLOK
FPGA DIG_FLT
43
DIG_FLT
85-0148-002-SCH-02
DIGI-KEY P/N F1219CT-ND
EPF8282ALC84-X DIG1 84 0
+5V
8 DIGITAL DRIVERS
REPLACEMENT FUSES: DIGI-KEY F1140CT-ND
12 44 1 F9
20MHZCLK 20MHZCLK DIG2 V1_2
22 2 1
DIG3 V1_2
75 2 3 2
+5V NS/P DIG4 .25 AMP GND1
42 4 3
DIG5 DIG1
74 25 5 4
MSEL0 DIG6 IN1 DIG2
1 53 15 6 0 DIG1 F10 1
MSEL1 DIG7
32 55 7 1 5
STATUS STATUS DIG8 IN2 V3_4
10 DIG2 6
DCLK .25 AMP GND2
33 7
RESET CONFIG DIG3
24 0 8
COMP1 COMP1 DIG4
28 35 1 0 F11
EN_DIG EN_DIG COMP2
34 2 1 CMPLVL1_2 9
COMP3 COMP2 V5_6
73 1 3 10
FAULT FAULT COMP4 .25 AMP GND3
30 4 CMPLVL1_2 11
TF COMP5 DIG5
41 56 5 12
+5V LED_ENABLED COMP6 V3_4 DIG6
20 6 F12
ENBLD R6 U11 COMP7
681 31 29 7 13
RESET COMP8 V7_8
DAC BIT 14
.25 AMP GND4
0 10 VCP 11 14 48 15
A0 D0 DATA0 DATA1 UNUSED3 IN3 DIG7
1 9 12 13 49 2 DIG3 16
A1 D1 DATA1 DATA2 UNUSED4 DIG8
BOOT PROM

2 8 13 9 51 3
A2 D2 DATA2 DATA3 UNUSED5 IN4
3 7 15 8 77 DIG4 17
A3 D3 DATA3 DATA4 UNUSED6 +5V +5V
4 6 16 7 79 VR1 VR2 VR3 VR4 18
A4 D4 DATA4 DATA5 UNUSED7 +8V +8V
5 5 17 6 82 13V 13V 13V 13V 25
A5 D5 DATA5 DATA6 UNUSED8 COMP3 20MHZCLK 20MHZCLK
6 4 18 4 2 1N4743 1N4743 1N4743 1N4743 19
A6 D6 DATA6 DATA7 -8V -8V
7 3 19 3 54 3 CMPLVL3_4
A7 D7 DATA7 DATA8 A A COMP4
8 25 72 27
A8 B B FAULT FAULT
9 24 83 CMPLVL3_4 23
A9 C C DIG_FLT DIG_FLT
10 21 27 16 24
A10 PROM_EN D D V5_6 EN_DIG EN_DIG
11 23 11 40 28
A11 CONF_DONE SPARE5 SPARE5 RESET RESET
12 2 U10 19
A12 SPARE6 SPARE6

COMP[1:8]

IN[1:8]
13 26 0 78 21 26
2 A13 AM27256 BADDR0 SPARE7 SPARE7 A A 2
14 27 1 76 37 29
A14 BADDR1 SPARE8 SPARE8 IN5 B B
2 71 4 DIG5 30
BADDR2 C C
3 70 5 32
BADDR3 D D
OE
CE

4 69 50 0 IN6 DIG6 20
PU_CONF BADDR4 DAC_SCL SPARE5 SPARE5
5 67 46 1 22
20 22 BADDR5 DAC_SDA SPARE6 SPARE6
6 66 81 2 31
BADDR6 DAC_AD0 COMP5 SPARE7 SPARE7
7 65 18 3 4 21
BADDR7 DAC_AD1 SPARE8 SPARE8
8 64 5 CMPLVL5_6 P1
BADDR8 COMP6
9 63 BADDR9
10 62 45 0 CMPLVL5_6
BADDR10 DATA_GEN_SEL
11 61 39 1
BADDR11 DIGFLT_EN V7_8
12 60 36 2
BADDR12 DAC0_EN
13 58 23 3
BADDR13 DAC1_EN
14 57 BADDR14
6 IN7 DIG7 JDIG7
ADDR[0:14]
7
IN8 DIG8 JDAC1

6 COMP7
DAC_CTL[0:3]
SWITCH[0:3]

+5V 7 CMPLVL7_8
COMP8 JDIG8
4.7K R3 1 CMPLVL7_8 GND
JDAC0

3 3
10 9 8 7 6 5 4 3 2
EN_DIG

SW1 DIP SWITCH DECODER

RESET
PU_CONF

STATUS

FAULT

+5V +8V

SWITCH# FUNCTION STATE

SW1 +5V +8V -------------------------------------------------------------------------------
8 1 1 0 0
DATA_GEN_SEL
7 2 2 1 1
SCL DUAL OUT0 1=OFF DATA_GEN_SEL UNUSED
DIGFLT_DIS SDA OUT1
6 3 3 2 2
DAC0_EN
5 4 4 3 3
AD0 DAC 2=OFF DIGFLT_EN ENABLED
DAC1_EN AD1
W/ BUFFER 3=ON DAC0 ENABLED
GND 85-0148-002-SCH-03
4=ON DAC1 ENABLED

APPROVAL

TEST ENGINEER

4 ZIEGLER TITLE CARD, CLK, BI, FPGA 4

PRODUCT ENGINEER
BYPASS CAPS 8 CHANNEL DIGITAL DRIVER CARD
+5V +5V +5V +5V +5V
ROSSELLI
REV SIZE TED NUMBER
REVISION DESC:
C32
.1UF
CC
C31
.1UF
CC
C30
.1UF
CC
C29
.1UF
CC
C9
.1UF
CC
1 B 85-0148-002-SCH-01
DATE FILE //jafar/ziegler/ted/85 SHEET OF

5/3/99 /85-0148/85-0148-002 1 1
A B C D
 A B C D

V1_2 V3_4
C5 C6
TA TA
4.7UF 4.7UF
C11 C19

6 .1UF 6 .1UF
1 CC CC 1
PU1 PU5
V+ R21 F1 V+ R17 F3
4 U2 5 TF 4 U4 5 TF
IN1 DIG1 IN3 DIG3
GND 51 .25 AMP GND 51 .25 AMP
TSC426 TSC426
3 3

R9 C13 R13 R16 C18 R30

NI NI 2.00K NI NI 2.00K
TF CC TF TF CC TF
V1_2 V1_2
V1_2 V3_4
D2 D3
C12 C20

.1UF BAS70 .1UF BAS70 3

CC 11 CC 11 R12
PU2 LM319 VS+ +4 PU6 LM319 VS+ +4 4.7K

12 12
COMP1 U1 COMP3 U3 14
GND GND
VS- 5 C14 VS- 5 C21
CMPLVL1_2 CMPLVL3_4
3 - CC NI 3 - CC NI
CMPLVL1_2
6 6
2 4 2
R12
4.7K C1
.01UF
13

V1_2 V3_4 V3_4 V3_4

6 6
PU3 PU7
V+ R15 F2 V+ R18 F4
2 U2 7 TF 2 U4 7 TF 1
IN2 DIG2 IN4 DIG4
R12
GND 51 .25 AMP GND 51 .25 AMP
4.7K
TSC426 TSC426
3 3
16

R14 R19 CMPLVL3_4

C15 R29 C23 R31
NI NI 2.00K NI NI 2.00K 2
TF CC TF TF CC TF R12
3 4.7K C2 3
.01UF
V1_2 V3_4
D1 D4 15

BAS70 BAS70
11 11
PU4 LM319 VS+ +9 PU8 LM319 VS+ +9
7 7
COMP2 U1 COMP4 U3
GND GND
VS- 10 C17 VS- 10 C22
CMPLVL1_2 CMPLVL3_4
8 - CC NI 8 - CC NI
6 6

APPROVAL
+5V

R10 4.7K TEST ENGINEER

1
4 FUSES ARE NANO^2 FAST ACTING FUSES W/OMNI-BLOK ZIEGLER TITLE CARD, CLK, BI, FPGA 4

DIGI-KEY P/N F1219CT-ND PRODUCT ENGINEER

+5V +5V
2 3 4 5 6 7 8 9 10 8 CHANNEL DIGITAL DRIVER SUB CKT
REPLACEMENT FUSES: DIGI-KEY F1140CT-ND ROSSELLI REV SIZE TED NUMBER
REVISION DESC:
1 B 85-0148-002-SCH-02
PU1
PU3
PU5
PU7
PU2
PU4
PU8
PU6

DATE FILE //jafar/ziegler/ted/85 SHEET OF

5/3/99 /85-0148/85-0148-002 1 2
A B C D
 A B C D

V5_6 V7_8
C8 C7
TA TA
4.7UF 4.7UF
C43 C27

6 .1UF 6 .1UF
1 CC CC 1
PU9 PU13
V+ R20 F5 V+ R25 F7
2 U6 7 TF 4 U8 5 TF
IN5 DIG5 IN7 DIG7
GND 51 .25 AMP GND 51 .25 AMP
TSC426 TSC426
3 3

R22 C24 R32 R26 C26 R34

NI NI 2.00K NI NI 2.00K
TF CC TF TF CC TF
V5_6 V5_6
V5_6 V7_8
D6 D8
C41 C28

.1UF BAS70 .1UF BAS70 5

CC 11 CC 11 R12
PU10 LM319 VS+ +9 PU14 LM319 VS+ +4 4.7K

7 12
COMP5 U5 COMP7 U7 12
GND GND
VS- 10 C40 VS- 5 C33
CMPLVL5_6 CMPLVL7_8
8 - CC NI 3 - CC NI
CMPLVL5_6
6 6
2 6 2
R12
4.7K C3
.01UF
11

V5_6 V7_8 V7_8 V7_8

6 6
PU11 PU15
V+ R23 F6 V+ R27 F8
4 U6 5 TF 2 U8 7 TF 8
IN6 DIG6 IN8 DIG8
R12
GND 51 .25 AMP GND 51 .25 AMP
4.7K
TSC426 TSC426
3 3
9

R24 R28 CMPLVL7_8

C25 R33 C35 R35
NI NI 2.00K NI NI 2.00K 7
TF CC TF TF CC TF R12
3 4.7K C4 3
.01UF
V5_6 V7_8
D5 D7 10

BAS70 BAS70
11 11
PU12 LM319 VS+ +4 PU16 LM319 VS+ +9
12 7
COMP6 U5 COMP8 U7
GND GND
VS- 5 C39 VS- 10 C34
CMPLVL5_6 CMPLVL7_8
3 - CC NI 8 - CC NI
6 6

APPROVAL
+5V

FUSES ARE NANO^2 FAST ACTING FUSES W/OMNI-BLOK 1 R11 4.7K TEST ENGINEER

4 DIGI-KEY P/N F1219CT-ND ZIEGLER TITLE CARD, CLK, BI, FPGA 4

REPLACEMENT FUSES: DIGI-KEY F1140CT-ND PRODUCT ENGINEER

2 3 4 5 6 7 8 9 10 8 CHANNEL DIGITAL DRIVER SUB CKT
ROSSELLI REV SIZE TED NUMBER
REVISION DESC:
1 B 85-0148-002-SCH-02
PU11
PU9
PU10
PU12
PU16
PU14
PU13
PU15

DATE FILE //jafar/ziegler/ted/85 SHEET OF

5/3/99 /85-0148/85-0148-002 2 2
A B C D
 2 4
1 3

DAC0_1X

R8 R5
TF TF
100K 49.9K

+8V

B B
8
2
- VS+
R2 F14
1 TF
AR1 OUT0
100 .25 AMP
3
+ VS- LT1413CN8 3
4
D10
BAS70-04
2 1

+5V
+8V

DAC1_1X
7
VDD
3
SCL SCL
4 1
SDA SDA OUT0
6 U9 8 R7 R4
AD0 AD0 OUT1
5 MAX518 TF TF
AD1 AD1
DUAL 8 BIT DAC
100K 49.9K
GND
2 +8V

8
6
- VS+
R1 F13
7 TF
AR1 OUT1
100 .25 AMP
5
+ VS- LT1413CN8 3
4
D9
BAS70-04
+8V +8V 2 1
A
A C10 C36 +8V
.1UF 4.7UF
CC
TA

APPROVAL

+5V +5V
TEST ENGINEER

C16
ZIEGLER TITLE
CARD, CLK, BI, FPGA
C37
.1UF PRODUCT ENGINEER

CC
4.7UF FUSES ARE NANO^2 FAST ACTING FUSES W/OMNI-BLOK ROSSELLI Dual Digital to Analog Converters
TA REV SIZE TED NUMBER
DIGI-KEY P/N F1219CT-ND REVISION DESC:

1 A 85-0148-002-SCH-03
REPLACEMENT FUSES: DIGI-KEY F1140CT-ND DATE FILE
//jafar/ziegler/ted/85 SHEET OF

5/3/99 /85-0148/85-0148-002 1 1
1 3
2 4
 DESIGN COVER SHEET
TITLE: CARD, CLK, BI, FPGA, WIRE PROGRAMMING CARD 85-0148-003
ENG: L. ZIEGLER

Status > PROD

Design Rev > OI

DWG/DOC No. SIZE DSK Name, Description Revisions

-003 A FINAL ASSEMBLY 1
-003-SCH A SCHEMATIC 1
-003-BOM A BILL OF MATERIALS 1
-003-ART FILMS OF PCB ARTWORK 1
-003-ZIP 3.5" ZIP FILE OF PCB ARTWORK 1
TED#: 85-0148-003-BOM REV 1
BILL OF MATERIALS PAGE 1 OF 1
CARD, CARD, CLK, BI, FPGA, WIRE PROGRAMMING CARD ENG: L. ZIEGLER DATE: 8/21/2002

ITEM # QTY PART NO. DESCRIPTION NOTES REF1 REF2 REF3 REF4

1 1 929647-09-36-ND (DIGI-KEY) CONN,HEADER,MALE,BAR,0.1INCH,SINGLE ROW,36PIN J3

2 1 929836-09-36-ND (DIGI-KEY) CONN,HEADER,MALE,DUAL ROW,28PIN P3
3 1 85-0148-003 PCB, SUPPLY MON, BURN-IN,FPGA,WIRE PROGRAMIING CARD
4 1 85-0148-007 WIRE PROGRAMMING CARD REINFORCING BAR
5 2 SCREW, 6-32, 1", CAP HEAD
6 2 PLASTIC CAP HEAD FOR 6-32 CAP HEAD SCREW
 2 4
1 3

1A 29
P1A 1 VIN1 VIN1
1B 30
P1B GND1 GND1
2A 31
P2A 2 VOUT1 VOUT1
2B
P2B
3A 32
P3A 3 VIN2 VIN2
3B 33
P3B GND2 GND2
4A 34
P4A 4 VOUT2 VOUT2
4B
P4B
5A 35
P5A 5 DIG1 DIG1
5B
P5B
6A 36
P6A 6 DIG2 DIG2
6B

56 PIN STRAIGHT DUAL ROW MALE HEADER

P6B

36 PIN STRAIGHT SINGLE ROW MALE HEADER

B 7A 37 B
P7A 7 DIG3 DIG3
7B
P7B
8A 38
P8A 8 DIG4 DIG4
8B
P8B
9A 39
P9A 9 D1_2 D1_2
9B 40
P9B GND3 GND3
10A 41
P10A 10 D3_4 D3_4
10B
P10B
11A 42
P11A 11 12V_1 12V_1
11B
P11B
12A 43
P12A 12 GND4 GND4
12B
P12B
13A 44
P13A 13 12V_2 12V_2
13B
P13B
14A 45
P14A 14 VRGND VRGND
14B
P14B
15A 46
P15A 15 VREG1 VREG1
15B
P15B
16A 47
P16A 16 VREG2 VREG2
16B
P16B
17A 48
P17A 17 D5_6 D5_6
17B 49
P17B GND5 GND5
18A 50
P18A 18 D7_8 D7_8
18B
P18B
19A 51
P19A 19 DIG5 DIG5
19B
P19B
20A 52
P20A 20 DIG6 DIG6
20B
P20B
21A 53
P21A 21 DIG7 DIG7
21B
P21B
22A 54
P22A 22 DIG8 DIG8
22B
P22B
23A 55
P23A 23 VIN3 VIN3
23B 56
P23B GND6 GND6
24A 57
P24A 24 VOUT3 VOUT3
24B
P24B
25A 58
P25A 25 VIN4 VIN4
25B 59
P25B GND7 GND7
26A 60
P26A 26 VOUT4 VOUT4
26B
P26B
27A 61
P27A 27 VIN5 VIN5
27B 62
P27B GND8 GND8
28A 63 A
P28A 28 VOUT5 VOUT5
A 28B
P28B
P3 P3

APPROVAL

TEST ENGINEER

ZIEGLER TITLE
CARD, CLK, BI, FPGA
PRODUCT ENGINEER
WIRE PROGRAMMING CARD
ROSSELLI REV SIZE TED NUMBER
REVISION DESC:
1 A 85-0148-003-SCH-01
DATE FILE
//jafar/ziegler/ted/85 SHEET OF

5/3/99 /85-0148/85-0148-003
1 1
1 3
2 4
TED#: 85-0148-004 REV 1
FINAL ASSEMBLY PAGE 1 OF 1
TITLE: CARD, CLK, BI, FPGA, 85-0148-001 DEBUG FIRMWARE ENG: L. ZIEGLER DATE: 8/21/2002

1) COPY 85-0148-004-BIN DEBUG CODE FROM ATTACHED 3.5" FLOPPY DISKETTE INTO EPROM BURNER AT ADDRESS #h0000

2) LOAD DEBUG CODE INTO BLANK EPROM, TYPE AM27256 28 PIN DIP, STARTING AT MEMORY ADDRESS #h0000

3) LABEL EPROM 85-0148-004-BIN REV #

4) INSTALL PROGRAMMED EPROM ONTO 85-0148-001 U15

 85-0148-004-DBG Rev 2
Debug Instructions for 5 Channel FPGA Burn-In Monitor Card
1. Perform this debug procedure prior to installation of any DUT specific firmware.
2. Refer to schematics 85-0148-001-SCH (hardware) and 85-0148-004-SCH (firmware) at all times during
debug process.
3. Remove 8 Channel Digital Driver Card 85-0148-002, if installed.
4. Remove Wire Programming Card 85-0148-003, if installed.
5. VISUALLY INSPECT ALL COMPONENTS for proper installation and seating prior to start of debug
procedure.
6. PROGRAM EPROM.
Program and install U15 EPROM with 85-0148-004-BIN debug code per instructions in 85-0148-004.
7. VERIFY DIP SWITCH OPERATION
With an Ohm meter, verify proper DIP switch operation, looking for shorts.
8. PROGRAM DIP SWITCHES. Set all 4 DIP switches as follows:
SW1
1. ON (5 Min Timer Disabled)
2. ON (Buzzer Disabled)
3. ON (Digital Faults Disabled)
4. ON (Under Voltage Faults Disabled)
5. ON (Over Current Faults Disabled)
6. ON
7. ON (6 ON & 7 ON = only Channel 1 Enabled)
8. ON (Channel 5 Disabled)
SW2
1. ON (Over Current Gain = 10, Channel 1)
2. OFF
3. OFF
4. ON (Over Current Gain = 10, Channel 2)
5. OFF
6. OFF
SW3
1. ON (Over Current Gain = 10, Channel 3)
2. OFF
3. OFF
4. ON (Over Current Gain = 10, Channel 4)
5. OFF
6. OFF
SW4
1. ON (Over Current Gain = 10, Channel 5)
2. OFF
3. OFF

Page 1 of 4
 85-0148-004-DBG cntd

9. Connect an (OFF) 12V bench supply's positive lead to the "+12V" testpoint and negative lead to the
"GND1" testpoint. Set the Current Limit of this supply to not more than 500mA.
10. POWER ON BENCH SUPPLY
Look for green "ENBLD" LED to remain lit.
Current on bench supply should measure approximately 300mA.
11. VERIFY CARD VOLTAGE REGULATORS
Refer to 85-0148-001-SCH-01 Sheet 2.
Measure "+12V", "+5V", "+5VREF", "+8V", "-12V", and "-8V" testpoints.
Note that -12V supply is generated from a charge pump running from the FPGA. If -12V is missing,
look for a 1MHZ square wave at testpoint "CPCLK". If missing, verify oscillator operation, see below.
Acceptable range for -12V is {-14V to -10.5V).
If any of the above measurements fail, debug appropriate voltage regulator and charge pump circuitry.
Also, the FPGA or EPROM may be damaged.
12. VERIFY OSCILLATOR OPERATION
Refer to 85-0148-001-SCH-01 Sheet 1.
Look for 20MHZ oscillator output waveform at testpoint "CLK".
If above measurement fails, debug appropriate oscillator and FPGA circuitry.
13. VERIFY BUTTONS OPERATION
Refer to 85-0148-001-SCH-01 Sheet 1.
Press "ENA" button.
Green "ENBLD" LED should turn off.
Press again, "ENBLD" LED should light.
Press "RST" button.
Red "STATUS" LED should flicker.
Green "ENBLD" LED should light.
If any of the above measurements fail, debug appropriate button circuitry. Also, the FPGA or EPROM
may be damaged.
14. VERIFY DUAL VOLTAGE REFERENCES
Refer to 85-0148-001-SCH-02.
Measure 1.2V at AR4-3 and AR4-5, generated by VR8.
Measure testpoints "VREG1" and "VREG2".
Adjust trimpots R52 and R53 respectively, up and down to verify full scale range of 1.6V to 5.6V.
If any of the above measurements fail, debug appropriate transistors, Zener, and op-amp circuitry.

Page 2 of 4
 85-0148-004-DBG cntd

15. VERIFY POSITIVE POWER CHANNELS

Refer to 85-0148-001-SCH-03, Sheets 1 to 4.
TURN OFF BENCH SUPPLY.
Connect the same +12V bench supply's positive lead to all of the following testpoints
"+12V", "IN1", "IN2", "IN3", & "IN4" ONLY.
CAUTION !!!!! CAUTION !!!!!
DO NOT CONNECT +12V TO TESTPOINT "IN5". THIS IS A NEGATIVE CHANNEL
AND INVERTING THIS SUPPLY WILL PERMANENTLY DAMAGE THE BOARD.
CAUTION !!!!! CAUTION !!!!!
TURN ON BENCH SUPPLY.
CHANNEL 1 IS ENABLED & CHANNELS 2, 3 & 4 ARE DISABLED
Measure 12V at testpoint "OUT1".
Measure 0V at testpoints "OUT2", "OUT3" & "OUT4".
Move SW1-7 to OFF (Enable power channels 1 to 2).
CHANNELS 1 & 2 ARE ENABLED, CHANNELS 3 & 4 ARE DISABLED
Measure 12V at testpoints "OUT1" & "OUT2".
Measure 0V at testpoints "OUT3" & "OUT4".
Move SW1-6 to OFF SW1-7 to ON (Enable power channels 1 to 3).
CHANNELS 1, 2 & 3 ARE ENABLED, CHANNEL 4 IS DISABLED
Measure 12V at testpoints "OUT1", "OUT2" & "OUT3".
Measure 0V at testpoint "OUT4".
Move SW1-7 to OFF (Enable power channels 1 to 4).
CHANNELS 1, 2, 3 & 4 ARE ENABLED
Measure 12V at testpoints "OUT1", "OUT2", "OUT3" & "OUT4".
If any of the above measurements fail, debug appropriate opto-coupled gate drive circuitry.
16. VERIFY NEGATIVE POWER CHANNEL
Refer to 85-0148-001-SCH-03, Sheet 5.
TURN OFF +12V BENCH SUPPLY.
Connect a new -12V (NEGATIVE TWELVE VOLTS) bench supply to testpoint "IN5" ONLY.
If using a true negative supply, connect the -12V lead to "IN5" and the ground lead to "GND1".
If inverting a floating positive supply, connect the Positive lead to "GND1" and the negative lead of the
supply to "IN5". Verify all voltages before connecting to board.
CAUTION !!!!! CAUTION !!!!!
DO NOT CONNECT +12V TO TESTPOINT "IN5". THIS IS A NEGATIVE CHANNEL
AND INVERTING THIS SUPPLY WILL PERMANENTLY DAMAGE THE BOARD.
CAUTION !!!!! CAUTION !!!!!
Turn on both bench supplies.
CHANNEL 5 IS DISABLED
Measure 0V at testpoint "OUT5".
Move SW1-8 to OFF (Enable power channel 5)
CHANNEL 5 IS ENABLED
Measure -12V at testpoint "OUT5".
If any of the above measurements fail, debug appropriate opto-coupled gate drive circuitry.
17. ADJUST FAULT THRESHOLDS
Refer to 85-0148-001-SCH-03, Sheets 1 to 5.
Adjust 10 trimpots R65 to R74 to set 10 testpoints "OCTRIPx" and "UVTRIPx" to 0.500V +/- 50mV.

Page 3 of 4
 85-0148-004-DBG cntd

18. VERIFY BUZZER OPERATION

Refer to 85-0148-001-SCH-01 Sheet 1
Move SW1-2 to OFF (Buzzer enabled)
Move SW1-4 to OFF (Under Voltage enabled).
Turn R66 clockwise until buzzer rings.
Turn R66 counter-clockwise 1 revolution. Buzzer should remain on.
Press RST button. Buzzer should turn off.
Move SW1-2 to ON (Buzzer disabled).
If any of the above measurements fail, debug appropriate buzzer driver circuitry.
19. VERIFY UNDER VOLTAGE OPERATION
Refer to 85-0148-001-SCH-03, Sheets 1 to 5.
Turn R66 clockwise until LED's "UV" and "PS1" turn on.
Turn R66 counter-clockwise 1 revolution. LED's should remain on.
Press RST button. LED's should turn off.
If any of the above measurements fail, move SW1-4 to ON (Under Voltage disabled) and debug
appropriate divider and comparator circuitry.
Repeat for all 5 channels, per following table.
TRIMPOT LED's
R66 UV, PS1
R68 UV, PS2
R70 UV, PS3
R72 UV, PS4
R74 UV, PS5
20. VERIFY OVER CURRENT OPERATION
Refer to 85-0148-001-SCH-03, Sheets 1 to 5.
Obtain and connect a 100 OHM, 2 Watt (or better) resistor between "OUT1" testpoint "GND1".
Move SW1-5 to OFF (Over Current enabled).
Turn R65 counter-clockwise several revolutions until LED's "OC" and "PS1" turn on.
Turn R65 clockwise 1 revolution. LED's should remain on.
Press RST button. LED's should turn off.
Disconnect the resistor.
If any of the above measurements fail, move SW1-5 to ON (Over Current disabled) and debug
appropriate gain stages and comparator circuitry.
Repeat for all 5 channels, per following table.
TRIMPOT LED's
R65 OC, PS1
R67 OC, PS2
R69 OC, PS3
R71 OC, PS4
R73 OC, PS5
21. VERIFY THE 5 MINUTE TIMER
Refer to 85-0148-001-SCH-01, Sheet 1.
Move SW1-1 to OFF (5 Minute Timer enabled).
Measure "OUT1" for at least 10 minutes. The voltage toggles between 12V and 0V every 5 minutes.
Move SW1-1 to ON (5 Minute Timer disabled).
If any of the above measurements fail, debug appropriate circuitry.
22. REMOVE AND STORE THE EPROM
If appropriate, continue debug procedure with document 85-0148-006-DBG (Digital Card Debug).
Otherwise, install a new EPROM and set DIP switches and trimpots per DUT specific burn-in
requirements.

Page 4 of 4
 VCC
TFF
NAND2
NAND3 DFF
PRN SPLY_EN
T Q OUTPUT
PRN nFAULT nLED_EN 85-0148-004-sch@36
D Q

CLRN
DFF DFF CLRN
NOT 85-0148-004-sch
INPUT PRN PRN NAND3
85-0148-004-sch@31 TGL_SPLY_EN D Q D Q NOT
85-0148-004-sch nFAULT OUTPUT
nBUZZER 85-0148-004-sch@84

CLRN CLRN VCC 85-0148-004-sch

TFF
PRN
CLK100HZ 85-0148-004-sch 85-0148-004-sch T Q
OUTPUT
CLK10KHZ CLK1MHZ 85-0148-004-sch@30

CLRN
INPUT
85-0148-004-sch@29 BUZZ_EN OR3
00
85-0148-004-sch PS2
INPUT BIT_1 01
CLK10MHZ 85-0148-004-sch@50 BIT_1
OR2
CLK1MHZ INPUT BIT_0 10
INPUT
85-0148-004-sch@54 BIT_0 PS3
85-0148-004-sch@77 SPARE5 CLK100KHZ
INPUT VCC TFF 11
85-0148-004-sch@81 SPARE6 CLK10KHZ
INPUT VCC TFF
PRN CLK250KHZ
85-0148-004-sch@49 SPARE7 CLK1KHZ T Q PS4
PRN
INPUT
85-0148-004-sch@79 SPARE8 CLK100HZ T Q
NOT WIRE
DFF CLK10HZ INPUT PS5
CLRN 85-0148-004-sch@51 PS5_EN
PRN CLK1HZ CLRN
D Q
INPUT
85-0148-004-sch
85-0148-004-sch@12 20MHZCLK
85-0148-004-sch
CLRN
OUTPUT
EN_PS1 85-0148-004-sch@48
85-0148-004-sch AND2

OUTPUT
PS2 EN_PS2 85-0148-004-sch@25

AND2
NOT
SPLY_EN OUTPUT
PS3 EN_PS3 85-0148-004-sch@82
CLK1HZ
21mux AND2
A AND2 OUTPUT
SPLY_EN PS4 EN_PS4 85-0148-004-sch@22
B Y
INPUT AND2
85-0148-004-sch@18 TIMER_EN S CLK10HZ
OUTPUT
INPUT MULTIPLEXER 85-0148-004-sch PS5 EN_PS5 85-0148-004-sch@72
85-0148-004-sch@37 UVFLT1
NOT
AND2 OUTPUT
INPUT nEN_VREG1 85-0148-004-sch@83
85-0148-004-sch@39 UVFLT2 nFAULT
PS2 NOT
OUTPUT
AND2 nEN_VREG2 85-0148-004-sch@45
INPUT
85-0148-004-sch@23 UVFLT3 NOT
PS3 OUTPUT
nEN_DIG 85-0148-004-sch@15
AND2
INPUT WIRE
85-0148-004-sch@34 UVFLT4 FAULT_EN
PS4
AND2
INPUT
85-0148-004-sch@21 UVFLT5
PS5 OUTPUT
nLED_FLT1 85-0148-004-sch@27
AND2 OUTPUT
INPUT nLED_FLT2 85-0148-004-sch@2
85-0148-004-sch@43 UVFLT_EN OUTPUT
FAULT_EN nLED_FLT3 85-0148-004-sch@41
CLK250KHZ OUTPUT
nLED_FLT4 85-0148-004-sch@28
85-0148-004-sch OUTPUT
nLED_FLT5 85-0148-004-sch@16

SW1 DIP SWITCH DECODER

INPUT SWITCH# FUNCTION STATE
85-0148-004-sch@73 OCFLT1
INPUT ---------------------- ---------------------- ----------------
85-0148-004-sch@35 OCFLT2
INPUT 1=OFF 5 MIN TIMER ENABLED
85-0148-004-sch@42 OCFLT3
INPUT 2=OFF BUZZER ENABLED
85-0148-004-sch@19 OCFLT4
INPUT OUTPUT 3=OFF DIGITAL FAULT ENABLED
85-0148-004-sch@20 OCFLT5 AND2 nLED_UV 85-0148-004-sch@56
INPUT OUTPUT 4=OFF UNDER VOLTAGE ENABLED
85-0148-004-sch@46 OCFLT_EN nLED_OC 85-0148-004-sch@24
CLK250KHZ OUTPUT 5=OFF OVER CURRENT ENABLED
FAULT_EN nLED_DIGFLT 85-0148-004-sch@55
85-0148-004-sch
6=ON, 7=ON PWR SUP 1 ENABLED
6=ON, 7=OFF PWR SUP 1,2 ENABLED
6=OFF,7=ON PWR SUP 1,2,3 ENABLED
nLED_UV
BNOR3 6=OFF,7=OFF PWR SUP 1,2,3,4 ENABLED
AND2
INPUT nLED_OC OUTPUT 8=OFF PWR SUP 5 ENABLED
85-0148-004-sch@1 DIG_FLT SRFFE nFAULT 85-0148-004-sch@40
NOT
FAULT_EN CLK250KHZ PRN nLED_DIGFLT 85-0148-004-sch
S Q
TITLE
CLK250KHZ FPGA, 5 SUPPLY MON, BURNIN
ENA COMPANY

R
Allegro MicroSystems
INPUT DESIGNER
85-0148-004-sch@44 DIGFLT_EN CLRN
Larry Ziegler
SIZE NUMBER REV
D 85-0148-004-SCH 1
GND DATE SHEET OF
1:29p 5-10-1999 1 1
 DESIGN COVER SHEET

TITLE: CARD, CLK, BI, FPGA, AUX 5 INPUT BANANA PANEL 85-0148-005
ENG: L. ZIEGLER

Status > PROD

Design Rev > OI

DWG/DOC No. SIZE DSK Name, Description Revisions

-005 A FINAL ASSEMBLY 1
-005-BOM A BILL OF MATERIALS 1
TED#: 85-0148-005-BOM REV 1
BILL OF MATERIALS PAGE 1 OF 1
TITLE: CARD, CLK, BI, FPGA, AUX 5 INPUT BANANA PANEL ENG: L. ZIEGLER DATE: 8/21/2002

ITEM # QTY PART NO. DESCRIPTION NOTES REF1 REF2 REF3 REF4

1 5 101127 CONN,BANA,FEMALE,BLK, P/N:108-0903-001 X1G X2G X3G X4G

X5G
2 5 101129 CONN,BANA,FEMALE,RED, P/N:108-0902-001 X1V X2V X3V X4V
X5V
3 10 101138 CONN,BANA,NUTS, P/N
4 1 85-0148-005 BANANA PANEL CHASSIS
 DESIGN COVER SHEET
TITLE: CARD, CLK, BI, FPGA, 85-0148-002 DEBUG FIRMWARE 85-0148-006
ENG: L. ZIEGLER

Status > PROD

Design Rev > OI

DWG/DOC No. SIZE DSK Name, Description Revisions

-006 A FINAL ASSEMBLY 1
-006-SCH A SCHEMATIC 1
-006-DBG A DEBUG INSTRUCTIONS 1
-006-BIN 3.5" BINARY CODE 1
-006-SIN 3.5" SINE WAVE DATA 1
TED#: 85-0148-006 REV 1
FINAL ASSEMBLY PAGE 1 OF 2
TITLE: CARD, CLK, BI, FPGA, 85-0148-002 DEBUG FIRMWARE ENG: L. ZIEGLER DATE: 8/21/2002

1) COPY 85-0148-006-BIN DEBUG CODE FROM ATTACHED 3.5" FLOPPY DISKETTE INTO EPROM BURNER AT ADDRESS #h0000

2) LOAD DEBUG CODE INTO BLANK EPROM, TYPE AM27256 28 PIN DIP, STARTING AT MEMORY ADDRESS #h0000

3) COPY 85-0148-006-SIN SINE WAVE DATA FROM ATTACHED 3.5" FLOPPY DISKETTE INTO EPROM BURNER AT ADDRESS #h4000

4) LOAD SINE WAVE DATA INTO SAME EPROM STARTING AT MEMORY ADDRESS #h4000

5) LABEL EPROM 85-0148-006-BIN REV #

6) INSTALL PROGRAMMED EPROM ONTO 85-0148-002 U10

TED#: 85-0148-006 REV 1
FINAL ASSEMBLY PAGE 2 OF 2
TITLE: CARD, CLK, BI, FPGA, 85-0148-002 DEBUG FIRMWARE ENG: L. ZIEGLER DATE: 8/21/2002

0
 85-0148-006-DBG Rev 2
Debug Instructions for 8 Channel FPGA Digital Driver Card
1. Perform all debug instructions in 85-0148-004-DBG prior to beginning this procedure. Use only a fully
functioning Master Controller Card 85-0148-001 to perform the debug of Digital Driver Card 85-0148-002.
2. Perform this debug procedure prior to installation of any DUT specific firmware.
3. Refer to schematics 85-0148-001-SCH and 85-0148-002-SCH (hardware) and also
85-0148-004-SCH and 85-0148-006-SCH (firmware) at all times during debug process.
4. Remove Wire Programming Card 85-0148-003 from Card 85-0148-001, if installed.
5. VISUALLY INSPECT ALL COMPONENTS for proper installation and seating prior to start of debug
procedure.
6. VERIFY DIP SWITCH OPERATION
With an Ohm meter, verify proper DIP switch operation, looking for shorts.
7. PROGRAM EPROM.
Program and install U10 EPROM with 85-0148-006-BIN Debug Code and 85-0148-006-SIN Sine Wave
Data per instructions in 85-0148-006.
8. PROGRAM DIP SWITCHES ON MOTHER BOARD prior to installing daughter board.
Set all 4 DIP switches on Master Controller Card 84-0148-001 as follows:
SW1
1. ON (5 Min Timer Disabled)
2. ON (Buzzer Disabled)
3. OFF (Digital Faults Enabled)
4. ON (Under Voltage Faults Disabled)
5. ON (Over Current Faults Disabled)
6. ON
7. ON (6 ON & 7 ON = only Channel 1 Enabled)
8. ON (Channel 5 Disabled)
SW2
1. ON (Over Current Gain = 10, Channel 1)
2. OFF
3. OFF
4. ON (Over Current Gain = 10, Channel 2)
5. OFF
6. OFF
SW3
1. ON (Over Current Gain = 10, Channel 3)
2. OFF
3. OFF
4. ON (Over Current Gain = 10, Channel 4)
5. OFF
6. OFF
SW4
1. ON (Over Current Gain = 10, Channel 5)
2. OFF
3. OFF

Page 1 of 3
 85-0148-006-DBG cntd

9. PROGRAM DIP SWITCHES ON DAUGHTER CARD.

Set DIP switch SW1 on Digital Driver Card 84-0148-002 as follows:
1. OFF (Unused)
2. ON (Digital Faults Disabled)
3. OFF (DAC0 Disabled)
4. OFF (DAC1 Disabled)
10. Connect an (OFF) +12V bench supply's positive lead to 85-0148-001 "+12V" testpoint and the negative lead
to the "GND1" testpoint. Set the current limit of this supply to not more than 500mA
11. Install 8 Channel Digital Driver Card 85-0148-002 onto Master Controller Card 85-0148-001.
You may wish to connect both an "easy clip" and a scope ground lead to the GND1 testpoint loop prior
to installation.
12. Connect an (OFF) +5V bench supply's positive lead to all 4 testpoints 85-0148-001 "D1_2", "D3_4",
"D5_6" & "D7_8" and then connect the negative lead to the "GND1" testpoint.
13. POWER ON BOTH BENCH SUPPLIES.
Look for both green "ENBLD" LED's to remain lit.
Current on +12V bench supply should measure approximately 400mA.
Current on +5V bench supply should measure approximately 10mA.
If the above measurements fail, debug appropriate daughter card circuitry. If the "DIG" LED on the
mother card remains lit at any time, move 85-0148-001 SW1-3 to ON (Digital Faults disabled). Also,
the FPGA or EPROM may be damaged.
14. VERIFY MOTHER CARD VOLTAGE REGULATORS.
Refer to 85-0148-001-SCH-01 Sheet 2 and 85-0148-002-SCH.
Measure "+12V", "+5V", "+5VREF", "+8V", "-12V", and "-8V" testpoints on 85-0148-001.
Note that -12V supply is generated from a charge pump running from the FPGA. Look for 1MHz
square wave at testpoint CPCLK. If missing, verify oscillator operation, see below. Acceptable range
for -12V is {-14V to -10.5V).
The only supplies used on the daughter card are +5V and +8V. Measure these at U9-7 and AR1-8.
If any of the above measurements fail, debug appropriate daughter card circuitry. If the "DIG" LED on
the mother card remains lit at any time, move 85-0148-001 SW1-3 to ON (Digital Faults disabled).
Also, the FPGA or EPROM may be damaged.
15. VERIFY OSCILLATOR OPERATION
Refer to 85-0148-002-SCH-01.
Look for 20MHz oscillator output waveform at testpoint U11-12.
If above measurement fails, debug FPGA circuitry.
16. VERIFY BUTTONS OPERATION
Refer to 85-0148-002-SCH-01.
Press "ENA" button.
Both green "ENBLD" LED's should turn off.
Press again, both "ENBLD" LED's should light.
Press "RST" button.
Red "STATUS" LED should flicker.
Both green "ENBLD" LED's should light.
If any of the above measurements fail, debug appropriate circuitry. If the "DIG" LED on the mother
card remains lit at any time, move 85-0148-001 SW1-3 to ON (Digital Faults disabled). Also, the FPGA
or EPROM may be damaged.

Page 2 of 3
 85-0148-006-DBG cntd

17. VERIFY DACS OPERATION

Refer to 85-0148-002-SCH-03
DAC0 & DAC1 ARE DISABLED
Measure 0V DC at jumpers "JDAC0-1" & "JDAC1-1".
Move SW1-3 to ON (Enable DAC0).
DAC0 IS ENABLED, DAC1 IS DISABLED
Measure 4Hz 0-7.5V Sine Wave at jumper "JDAC0-1".
Measure 0V DC at jumper "JDAC1-1".
Move SW1-3 to OFF & SW1-4 to ON (Disable DAC0 & Enable DAC1).
DAC0 IS DISABLED, DAC1 IS ENABLED
Measure 0V DC at jumper "JDAC0-1".
Measure 4Hz 0-7.5V Sine Wave at jumper "JDAC1-1".
Move SW1-3 to ON (Enable DAC0).
DAC0 & DAC1 ARE ENABLED
Measure 2Hz 0-7.5V Sine Wave at jumpers "JDAC0-1" & "JDAC1-1".
If any of the above measurements fail, debug appropriate DAC or op-amp circuitry. Also, the FPGA or
EPROM may be damaged.
18. VERIFY DIGITAL DRIVERS OPERATION
Refer to 85-0148-002-SCH-02 Sheets 1 & 2.
Measure 3 non-uniform pulses, repeating at 100Hz at 85-0148-001 testpoint "DIG1".
Measure 3 uniform pulses repeating at 100Hz at 85-0148-001 testpoint "DIG2".
Measure 25KHz square wave at 85-0148-001 testpoint "DIG3".
Measure 100KHz square wave at 85-0148-001 testpoint "DIG4".
Measure 100KHz square wave at 85-0148-001 testpoint "DIG5".
Measure 1KHz square wave at 85-0148-001 testpoint "DIG6".
Measure 100KHz square wave at jumper "JDIG7-1".
Measure 10KHz square wave at jumper "JDIG8-1".
If any of the above measurements fail, debug appropriate digital driver U2, U4, U6, U8. If the "DIG"
LED on the mother card remains lit at any time, move 85-0148-001 SW1-3 to ON (Digital Faults
disabled). If the "DIG" LED on the mother card remains lit at any time, move 85-0148-001 SW1-3 to
ON (Digital Faults disabled). Also, the FPGA or EPROM may be damaged.
19. VERIFY DIGITAL COMPARATORS OPERATION
Refer to 85-0148-002-SCH-02 Sheets 1 & 2.
Move SW1-2 to OFF (Enable Digital Faults)
With one end of a test prod tied to GND, briefly touch F1 with the other end of the prod. A quick "tap"
on the fuse with the prod should be sufficient to cause a fault.
The red "DIG" LED on the mother board should light and both green LED's should extinguish.
Press the "RST" button on the mother board.
Only the green LED's should light.
Repeat for F2 to F8. WARNING!!! BE CERTAIN NOT TO SHORT FUSES F9 TO F14.
If any of the above measurements fail, debug appropriate comparator U1, U3, U5, U7. If the "DIG" LED
on the mother card remains lit at any time, move 85-0148-001 SW1-3 to ON (Digital Faults disabled). If
the "DIG" LED on the mother card remains lit at any time, move 85-0148-001 SW1-3 to ON (Digital
Faults disabled) and 85-0148-002 SW1-2 to ON (Digital Faults disabled). Also, the FPGA or EPROM
may be damaged.
20. REMOVE AND STORE THE EPROM
If appropriate, install a new EPROM and set DIP switches and trimpots per DUT specific burn-in
requirements.

Page 3 of 3
 AND2 OUTPUT
CLK100HZ DIG1 85-0148-006-sch@84
INPUT
EN_DIG COMP1 85-0148-006-sch@24
CLK10MHZ OUTPUT
DIG2 85-0148-006-sch@44
CLK1MHZ CLK100KHZ INPUT
COMP2 85-0148-006-sch@35
INPUT CLK100KHZ OUTPUT
85-0148-006-sch@12 20MHZCLK DIG3 85-0148-006-sch@22
CLK10KHZ INPUT
COMP3 85-0148-006-sch@34
CLK1KHZ CLK100KHZ OUTPUT
DIG4 85-0148-006-sch@2
CLK100HZ INPUT
COMP4 85-0148-006-sch@1
CLK1MHZ
nDATA_FLT1_4

CLK100KHZ OUTPUT
DIG5 85-0148-006-sch@42
INPUT
COMP5 85-0148-006-sch@30
CLK1KHZ OUTPUT
DIG6 85-0148-006-sch@25
INPUT
COMP6 85-0148-006-sch@56
CLK100KHZ OUTPUT
DIG7 85-0148-006-sch@15
INPUT
COMP7 85-0148-006-sch@20
CLK10KHZ OUTPUT
DIG8 85-0148-006-sch@55
INPUT
NOT COMP8 85-0148-006-sch@29
EN_DIG NOR2 CLK1MHZ
DIG_FLT
nDATA_FLT5_8
INPUT
85-0148-006-sch@28 nEN_DIG

OR2

OUTPUT
nLED_ENABLED 85-0148-006-sch@41

EN_DIG
SW1 DIP SWITCH DECODER
INPUT AND3
DATA_GEN_SEL
85-0148-006-sch@45
INPUT SWITCH# FUNCTION STATE DIGFLT_EN OUTPUT
85-0148-006-sch@39 DIGFLT_EN DIG_FLT 85-0148-006-sch@43
INPUT ---------------------- ---------------------- ---------------------- NAND2
85-0148-006-sch@36 nDAC0_EN nDATA_FLT1_4
INPUT 1=OFF DATA_GEN_EN UNUSED
85-0148-006-sch@23 nDAC1_EN nDATA_FLT5_8
2=OFF DIGFLT_EN ENABLED
3=ON nDAC0_EN ENABLED
4=ON nDAC1_EN ENABLED
OUTPUT
DAC_SCL 85-0148-006-sch@50
SEND A DAC BYTE OUTPUT
DAC_SDA 85-0148-006-sch@46
EVERY 1 MS OUTPUT
NAND2 ENABLE THE DACS ONLY WHEN DAC_AD0 85-0148-006-sch@81
CLK1KHZ OUTPUT
AT LEAST ONE DAC IS SELECTED DAC_AD1 85-0148-006-sch@18
EN_DIG OR2

OUTPUT
AND2 BADDR0 85-0148-006-sch@78
nDAC0_EN OUTPUT
CLK1MHZ BADDR1 85-0148-006-sch@76
INPUT nDAC1_EN OUTPUT
85-0148-006-sch@14 DATA1 BADDR2 85-0148-006-sch@71
INPUT nDAC0_EN OUTPUT
85-0148-006-sch@13 DATA2 BADDR3 85-0148-006-sch@70
INPUT OUTPUT
85-0148-006-sch@9 DATA3 nDAC1_EN BADDR4 85-0148-006-sch@69
INPUT OUTPUT
85-0148-006-sch@8 DATA4 BADDR5 85-0148-006-sch@67
INPUT DATA[8..1] OUTPUT
85-0148-006-sch@7 DATA5 BADDR6 85-0148-006-sch@66
INPUT BADDR[14..0] OUTPUT
85-0148-006-sch@6 DATA6 BADDR7 85-0148-006-sch@65
INPUT OUTPUT
85-0148-006-sch@4 DATA7 BADDR8 85-0148-006-sch@64
INPUT OUTPUT
85-0148-006-sch@3 DATA8 BADDR9 85-0148-006-sch@63
OUTPUT
BADDR10 85-0148-006-sch@62
OUTPUT
BADDR11 85-0148-006-sch@61
OUTPUT
BADDR12 85-0148-006-sch@60
OUTPUT
BADDR13 85-0148-006-sch@58
OUTPUT
BADDR14 85-0148-006-sch@57

SPARE INPUTS RESERVED FOR FUTURE USE

OUTPUT
nPROM_EN 85-0148-006-sch@27
INPUT
85-0148-006-sch@73 nFAULT
INPUT
85-0148-006-sch@54 A
INPUT
85-0148-006-sch@72 B
INPUT
85-0148-006-sch@83 C
INPUT
85-0148-006-sch@16 D
TITLE
85-0148-006-sch@40 SPARE5 INPUT FPGA, SCHEMATIC,TOP-LEVEL,DIGITAL
INPUT COMPANY
85-0148-006-sch@19 SPARE6
INPUT
Allegro MicroSystems
85-0148-006-sch@21 SPARE7 DESIGNER
85-0148-006-sch@37 SPARE8 INPUT Larry Ziegler
SIZE NUMBER REV
D 85-0148-006-SCH 1
DATE SHEET OF
2:52p 8-30-1999 1 1
 DESIGN COVER SHEET
TITLE: CARD, CLK, BI, FPGA, WIRE CARD REINFORCING BAR 85-0148-007
ENG: L. ZIEGLER

Status > PROD

Design Rev > OI

DWG/DOC No. SIZE DSK Name, Description Revisions

-007 A FINAL ASSEMBLY 1
-007-BOM A BILL OF MATERIALS 1
 TED#: 85-0148-007-BOM REV 1
BILL OF MATERIALS PAGE 1 OF 1
ENG: L. ZIEGLER
TITLE: CARD, CLK, BI, FPGA, WRIE CARD REINFORCING BAR DATE: 8/21/2002

ITEM # QTY PART NO. DESCRIPTION NOTES REF1 REF2 REF3 REF4

1 2 S-632-3-ZI PEM SELF CLINCHING NUT, CARBON STEEL, 6/32, 0.087 SHANK, ZINC PLATED
 DESIGN COVER SHEET
TITLE: CARD, CLK, BI, FPGA, POWER CARD REINFORCING BAR 85-0148-008
ENG: L. ZIEGLER

Status > PROD

Design Rev > OI

DWG/DOC No. SIZE DSK Name, Description Revisions

-008 A FINAL ASSEMBLY 1