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    Single and Double Diffusion Breaks in 14Nm Finfet and Beyond

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    Irving

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    Single and Double Diffusion Breaks in 14Nm Finfet and Beyond

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    Irving
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    E-2-03

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    Single and Double Diffusion Breaks in 14Nm Finfet and Beyond

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    Extended Abstracts of the 2017 International Conference on Solid State Devices and Materials, Sendai, 2017, pp219-220

    E-2-03

    Single and Double Diffusion Breaks in 14nm FinFET and Beyond


    K. Miyaguchi, F. M. Bufler, T. Chiarella, P. Matagne, N. Horiguchi, A. De Keersgieter, G. Eneman, A. Spessot, *B. Parvais,
    D. Verkest and A. Mocuta
    IMEC, Kapeldreef 75, B-3001 Leuven, Belgium, Phone: +32-1628-3286, E-mail: Kenichi.Miyaguchi@imec.be

    Abstract pitch, 11nm gate spacer thickness, 110nm poly pitch and
    Layout-dependent effect (LDE) in FinFET technology DDB structure. The length-of-oxide (LOD) represents a dis-
    is investigated by means of TCAD process and Monte- tance from edge of the center channel to the STI. We fabri-
    Carlo device simulation. A good agreement is obtained cated the devices having 3 different LOD, named LODn in
    when comparing to experimental data on 14nm FinFET which LOD equals to n*CPP-Lg/2, where CPP is poly pitch
    with double diffusion break (DDB). Single diffusion break and Lg is physical gate length.
    (SDB) in 7nm FinFET is discussed. Simulation indicates The TCAD process simulations run to estimate channel
    that stress relaxation is pronounced in case of DDB and strain of the devices of LOD1, LOD2 and LOD3, considering
    self-aligned SDB, while non-self-aligned SDB preserves only S/D epi-induced stress. The integrated channel strain in
    stress at the price of high variability. the center channel is plotted in Fig. 3. The strain increases
    from LOD1 to LOD2 by 25% approximately in both n- and
    1. Introduction p-FinFET. The channel closer to the STI suffers from stress
    The layout-dependent effect (LDE) on stress and device relaxation more due to the proximity to free space at fin-cut
    performance is a big concern in scaled CMOS technologies edge at the STI oxide, that reduces stress due to small elastic
    [1]. Double diffusion break (DDB) isolates neighboring de- stiffness. A small increase of the strain from LOD2 to LOD3
    vices with fin tuck under dummy poly shown in Fig. 1 (a), is observed since LOD2 is enough far from the STI to avoid
    taking 1 poly pitch of width of shallow trench isolation (STI). the stress relaxation.
    Single diffusion break (SDB) is a promising option to reduce
    die area with STI width of 1 gate length illustrated in Fig. 1
    (b), but a heavy facet of source/drain (S/D) epi at edge of STI
    causes epi volume reduction and drive current variation.

    Fig. 3 Integrated channel strain in the center channel in 14nm FinFET.


    Taking the estimated strain value, the single-particle MC
    device simulation considering quasiballistic overshoot effects
    was performed with analytical dopant profile [2][3]. The sim-
    Fig. 1 Schematic views of DDB and SDB structures.
    ulated drain currents of the LOD1 at absolute drain voltage of
    0.05V and 0.8V have been reasonably matched with the
    To investigate impact of DDB and SDB on S/D epi-in- measured ones in the n- and p-FinFET as depicted in Fig. 4.
    duced stress and drive current, we apply TCAD process and
    Monte-Carlo (MC) device simulations. First, we demonstrate
    that the TCAD simulation results show a good agreement
    with Imec 14nm FinFET experimental data of the DDB. Us-
    ing the validated TCAD setup, the stress and device perfor-
    mance of 7nm FinFET with the SDB are evaluated.

    2. Double Diffusion Break in 14nm-node FinFET


    Fig. 2 shows schematic views of Imec 14nm FinFET with
    28nm gate length, 7nm fin width, 26nm fin height, 45nm fin
    Fig. 4 Measured and simulated drain currents of Imec 14nm FinFET
    (LOD1)
    Fig. 5 shows the LDE on the drain current in the linear
    regime extracted at 0.4V threshold voltage offset. The meas-
    ured LDE in n-FinFET is 2% increase of the drain current
    from LOD1 to LOD2, while 4% is found in the simulation.
    The p-FinFET pronounces the LDE due to silicon-germanium
    S/D epi stressor with 16% increase in the experiments and
    11% in the simulation. In spite of incomplete device inspec-
    Fig. 2 Schematic views of Imec 14nm FinFET

    - 219 -
    tion and lack of measured stress values, the same trend be- for epitaxial growth shown in Fig. 7(b) [4].
    tween the measured and simulated results are obtained. That The SA-SDB removes a risk of the epi volume reduction
    validates a reasonable accuracy of the TCAD simulation ap- thanks to alignment to dummy poly, but S/D epi-induced
    proach for device performance prediction. stress is lost during the STI formation similar to the DDB case.
    Fig 8 compares process simulation results of the LDE on the
    channel strain in the center channel of the DDB, SDB and
    SA-SDB as well as non-fin-cut as a reference. The DDB and
    SA-SDB decrease the strain by 85% at LOD1 compared to
    the non-fin-cut due to the stress relaxation during dummy
    poly removal. The SDB has benefit of retain the strain in the
    channel due to stiff environment around the S/D epi.
    Fig. 5 Measured and simulated LDE on drain current in the linear regime

    3. Single Diffusion Break in 7nm-node FinFET


    As technology scales towards 7nm node, the electrical im-
    pact of the SDB enabling die area reduction with narrowing
    STI width has to be investigated. Fig. 6 summarizes process
    flow assumption of the DDB and SDB. The DDB and non-
    self-aligned SDB can be made by the same flow, but the
    height of the oxide filled in the STI assumes to be different Fig. 8 LDE on channel strain at center channel in 7nm FinFET
    shown in Fig. 1.
    Based on the simulated stress values, MC device simu-
    lations were run to assess drain current at supply voltage of
    0.65V. The on-state drain currents with off-state current tar-
    geted to 0.1nA/µm in LOD1 are plotted in Fig. 9. Compared
    to non-fin-cut, the on-currents of the DDB and SA-SDB are
    degraded by 10% and 38% for n- and p-FinFET respectively.
    On the other hand, the SDB achieves high on-current due to
    no loss of the strain, however the on-current degradation of
    Fig. 6 Process flow of DDB, SDB and SA-SDB
    9% in n-FinFET and 25% in p-FinFET in case of 5nm misa-
    The self-aligned SDB (SA-SDB) is formed after S/D epi lignment need to be taken into account.
    growth and its width is defined by length of poly mask. On
    the other hand, the non-self-aligned SDB has a potential issue
    of misalignment between fin-cut and poly masks. Fig. 7
    shows schematic views of 7nm FinFET with 18nm gate
    length, 5nm fin width, 35nm fin height, 24nm fin pitch, 5nm
    gate spacer thickness, 42nm poly pitch and the SDB structure.
    The fin tuck exists under the dummy poly and the S/D epi Fig. 9 Comparison of simulated on-state current in 7nm FinFET
    grows towards 3 facets of top and both sides in case of no
    misalignment. If fin-cut and poly masks are misaligned 4. Conclusion
    enough to make fin tuck in the S/D contact area, the S/D epi We demonstrated that the TCAD MC device simulation
    volume is significantly reduced due to extra facet towards results have successfully agreed with the experimental data of
    edge of the fin. The epi shape is accurately predictable using the 14nm FinFET LDE on on-state current with the DDB.
    the kinetic monte-carlo option in TCAD process simulation For a further scaling node, the validated TCAD deck has
    predicted the LDE of the SDB on channel strain and drain
    current. The non-self-aligned SDB can retain S/D epi-in-
    duced stress in the channel and achieve high drain current, but
    its variability due to mask misalignment needs to be consid-
    ered. The SA-SDB has a benefit of variability and die area
    reduction in spite of lower drain current than the non-self-
    aligned SDB.

    *B. Parvais is also at Vrije Universiteit Brussel, Belgium


    References
    [1] M Garcia Bardon et al., VLSI-Technology 2013, p. 114.
    Fig. 7 Schematic views of 7nm SDB FinFET with and without [2] F. M. Bufler, F.O. Heinz and L. Smith, SISPAD 2013, p. 172.
    misalignment
    [3] F. M. Bufler and L. Smith, J. Comput. Electron. 12, p. 651, 2013.
    [4] Synopsys Inc., “Sentaurus Process User Guide,” L-2016.03, 2016.

    - 220 -

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