Introduction to Fabrication of Electronic Components/Devices:

Semiconductor wafers, Doping, Diffusion, Annealing, Metallization, Masking, Bottom-up

approach vs Top-down approach, Lithography/Screen printing.

Semiconductor Wafer:

In electronics, a wafer (also called a slice or substrate) is a thin slice of semiconductor, such as:
crystalline silicon (c-Si), used for the fabrication of integrated circuits and, in photovoltaics, to
manufacture solar cells.

The semiconductor or silicon wafer industry, the term wafer appeared in the 1950s to describe a
thin round slice of semiconductor material, typically germanium or silicon. The round shape
characteristic of these wafers comes from single-crystal ingots usually produced using
the Czochralski method. Silicon wafers were first introduced in the 1940s.

An integrated circuit is a small but sophisticated device implementing several electronic

functions. It is made up of two major parts: a tiny and very fragile silicon chip (die) and a package
which is intended to protect the internal silicon chip and to provide users with a practical way of
handling the component. This note describes the various “front-end” and “back-end”
manufacturing processes and takes the transistor as an example, because it uses the MOS
technology. This technology is used for most of the ICs manufactured at STMicroelectronics.

The five steps of wafer forming

1. Slicing

The circumference of the monocrystalline ingot is ground down to a uniform diameter. Based on
the resistivity desired by the customer, the ingot is then cut into slices of around 1mm thickness,
using an inner-diameter saw or wire saw, to form the wafers.
2. Lapping

The sliced wafers are polished by alumina abrasive in a lapping machine to the desired
thickness, while improving the surface parallelism.

3. Etching

Mechanical damage to the wafer surface resulting from the earlier steps is removed by chemical
etching.

Polishing

The wafer surfaces are made perfectly flat and given a mirror finish by means of mechano-
chemical polishing using colloidal silica.
5. Cleaning and inspection

After cleaning, stringent inspections are performed, and the SUMCO polished wafer is completed.
The exceptionally high quality of the polished wafers manufactured by SUMCO ensures they are
favoured by customers all over the world.

THE FABRICATION OF A SEMICONDUCTOR DEVICE

The manufacturing phase of an integrated circuit can be divided into two steps. The first, wafer
fabrication, is the extremely sophisticated and intricate process of manufacturing the silicon chip.
The second, assembly, is the highly precise and automated process of packaging the die. Those
two phases are commonly known as “Front-End” and “Back-End”. They include two test steps:
wafer probing and final test. The main steps for the fabrication of a die are summarized in the
following table. Some of them are repeated several times at different stages of the process. The
order given here does not reflect the real order of fabrication process.

Photo-Masking: This step shapes the different components. The principle is quite simple (see
drawing on next page). Resin is put down on the wafer which is then exposed to light through a
specific mask. The lighten part of the resin softens and is rinsed off with solvents (Developing
step). Etching This operation removes a thin film material. There are two different methods: wet
(using a liquid or soluble compound) or dry (using a gaseous compound like oxygen or chlorine).
Diffusion This step is used to introduce dopants inside the material or to grow a thin oxide layer
onto the wafer. Wafers are inserted into a high temperature furnace (up to 1200 ° C) and doping
gazes penetrate the silicon or react with it to grow a silicon oxide layer. Ionic Implantation It
allows to introduce a dopant at a given depth into the material using a high energy electron beam.
Metal Deposition It allows the realization of electrical connections between the different cells of
the integrated circuit and the outside. Two different methods are used to deposit the metal:
evaporation or sputtering.

Wafer properties

Standard wafer sizes

Silicon

Silicon wafers are available in a variety of diameters from 25.4 mm (1 inch) to 300 mm
(11.8 inches). Semiconductor fabrication plants, colloquially known as fabs, are defined by the
diameter of wafers that they are tooled to produce. The diameter has gradually increased to
improve throughput and reduce cost with the current state-of-the-art fab using 300 mm, with a
proposal to adopt 450 mm.[15][16] Intel, TSMC, and Samsung were separately conducting research
to the advent of 450 mm "prototype" (research) fabs, though serious hurdles remain.

Wafers grown using materials other than silicon will have different thicknesses than a silicon
wafer of the same diameter. Wafer thickness is determined by the mechanical strength of the
material used; the wafer must be thick enough to support its own weight without cracking during
handling. The tabulated thicknesses relate to when that process was introduced, and are not
necessarily correct currently, for example the IBM BiCMOS7WL process is on 8-inch wafers,
but these are only 200 μm thick. The weight of the wafer goes up along with its thickness and
diameter.

Photo-Masking: This step shapes the different components. The principle is quite simple (see
drawing on next page). Resin is put down on the wafer which is then exposed to light through a
specific mask. The lighten part of the resin softens and is rinsed off with solvents (developing
step).
Etching: This operation removes a thin film material. There are two different methods: wet (using
a liquid or soluble compound) or dry (using a gaseous compound like oxygen or chlorine).

Diffusion: This step is used to introduce dopants inside the material or to grow a thin oxide layer
onto the wafer. Wafers are inserted into a high temperature furnace (up to 1200° C) and doping
gazes penetrate the silicon or react with it to grow a silicon oxide layer.

Ionic Implantation: It allows to introduce a dopant at a given depth into the material using a
high energy electron beam.

Metal Deposition: It allows the realization of electrical connections between the different cells
of the integrated circuit and the outside. Two different methods are used to deposit the metal:
evaporation or sputtering.

Passivation: Wafers are sealed with a passivation layer to prevent the device from contamination
or moisture attack. This layer is usually made of silicon nitride or a silicon oxide composite.

Back-lap: It’s the last step of wafer fabrication. Wafer thickness is reduced (for microcontroller
chips, thickness is reduced from 650 to 380 microns), and sometimes a thin gold layer is deposited
on the back of the wafer.

Historical increases of wafer size

A unit of wafer fabrication step, such as an etch step, can produce more chips proportional to the
increase in wafer area, while the cost of the unit fabrication step goes up more slowly than the
wafer area. This was the cost basis for increasing wafer size. Conversion to 300 mm wafers from
200 mm wafers began in early 2000, and reduced the price per die for about 30–40%. Larger
diameter wafers allow for more die per wafer.

In order to minimize the cost per die, manufacturers wish to maximize the number of dies that
can be made from a single wafer; dies always have a square or rectangular shape due to the
constraint of wafer dicing. In general, this is a computationally complex problem with no
analytical solution, dependent on both the area of the dies as well as their aspect ratio (square or
rectangular) and other considerations such as the width of the scribe line or saw lane, and
additional space occupied by alignment and test structures. Note that gross DPW formulas
account only for wafer area that is lost because it cannot be used to make physically complete
dies; gross DPW calculations do not account for yield loss due to defects or parametric issues.
Wafer map showing fully patterned dies, and partially patterned dies which do not fully lie within
the wafer. Nevertheless, the number of gross die per wafer (DPW) can be estimated starting with
the first-order approximation or floor function of wafer-to-die area ratio, Where,

DPW = 𝐴 = 𝜋𝑟 2 /𝑆

• d is the wafer diameter (typically in mm)

• S the size of each die (mm2) including the width of the scribe line (or in the case of a
saw lane, the kerf plus a tolerance).

This formula simply states that the number of dies which can fit on the wafer cannot exceed the
area of the wafer divided by the area of each individual die. It will always overestimate the true
best-case gross DPW, since it includes the area of partially patterned dies which do not fully lie
on the wafer surface (see figure). These partially patterned dies don't represent complete ICs, so
they cannot be sold as functional parts.

Doping: n- and p-semiconductors

Doping

Doping means the introduction of impurities into a semiconductor crystal to the defined
modification of conductivity. Two of the most important materials silicon can be doped
with, are boron (3 valence electrons = 3-valent) and phosphorus (5 valence electrons = 5-valent).
Other materials are aluminum, indium (3-valent) and arsenic, antimony (5-valent).

The dopant is integrated into the lattice structure of the semiconductor crystal, the number of
outer electrons define the type of doping. Elements with 3 valence electrons are used for p-type
doping, 5-valued elements for n-doping. The conductivity of a deliberately contaminated silicon
crystal can be increased by a factor of 106.
n-doping
The 5-valent dopant has an outer electron more than the silicon atoms. Four outer electrons
combine with ever one silicon atom, while the fifth electron is free to move and serves as
charge carrier. This free electron requires much less energy to be lifted from the valence
band into the conduction band, than the electrons which cause the intrinsic conductivity of
silicon. The dopant, which emits an electron, is known as an electron donor. The dopants
are positively charged by the loss of negative charge carriers and are built into the lattice, only
the negative electrons can move. Doped semimetals whose conductivity is based on free
(negative) electrons are n-type or n-doped. Due to the higher number of free electrons those are
also named as majority charge carriers, while free mobile holes are named as the minority
charge carriers.

Si Si Si

Si P Si

Si Si Si

Fig. 1.1: n-doping with phosphorus

Arsenic is used as an alternative to phosphorus, because its diffusion coefficient is lower. This
means that the dopant diffusion during subsequent processes is less than that of phosphorus
and thus the arsenic remains at the position where it was introduced into the lattice originally.

p-doping
In contrast to the free electron due to doping with phosphorus, the 3-valent dopant ef- fect is
exactly the opposite. The 3-valent dopants can catch an additional outer electron, thus leaving
a hole in the valence band of silicon atoms. Therefore, the electrons in the valence band
become mobile. The holes move in the opposite direction to the movement of the electrons.
The necessary energy to lift an electron into the energy level of indium as a dopant, is only
1 % of the energy which is needed to raise a valence electron of silicon into the conduction
band.

With the inclusion of an electron, the dopant is negatively charged, such dopants are called
acceptors (accept are, lat. = to add). Again, the dopant is fixed in the crystal lattice, only the
positive charges can move. Due to positive holes these semiconductors are called p-
 conductive or p-doped. Analog to n-doped semiconductors, the holes are the majority charge
carriers, free electrons are the minority charge carriers.

Doped semiconductors are electrically neutral. The terms n- and p-type doped do only refer to
the majority charge carriers. Each positive or negative charge carrier belongs to a fixed
negative or positive charged dopant.

N- and p-doped semiconductors behave approximately equal in relation to the current flow.
With increasing number of dopants, the number of charge carriers increases in the
semiconductor crystal. Here it requires only a very small number of dopants. Weakly

Si Si Si
+
Si B Si

Si Si Si

Fig. 1.2: p-doping with boron

doped silicon crystals contain only 1 impurity per 1,000,000,000 silicon atoms, high doped
semiconductors for example contain 1 foreign atom per 1,000 silicon atoms.

Electronic band structure in doped semiconductors:

Through the introduction of a dopant with five outer electrons, in n-doped semiconductors
there is an electron in the crystal which is not bound and therefore can be moved with relatively
little energy into the conduction band. Thus, in n-doped semi- conductors one finds a donator
energy level near the conduction band edge, the band gap to overcome is very small.

Analog, through introduction of a 3-valent dopant in a semiconductor, a hole is avail- able,

which may be already occupied at low-energy by an electron from the valence band of the
silicon. For p-doped semiconductors one finds an acceptor energy level near the valence
band.
 CB CB
Free electron

Fixed dopant Fixed dopant

Acceptor level
Donator level

VB VB

Fixed dopant

n-semiconductor p-semiconductor

Fig. 1.3: Band model of p- and n-type doped

semiconductors

Diffusion:

Diffusion and ion implantation are the two key processes to introduce a controlled number of
dopants into semiconductors and to alter the conductivity type. Figure 8.1 compares these two
techniques and the resulting dopantprofiles. In the diffusion process, the dopant atoms are
introduced from the gas phase of by using doped-oxide sources. The doping concentration
decreases monotonically from the surface, and the in-depth distribution of the dopant is
determined mainly by the temperature and diffusion time. Figure 8.1b reveals the ion
implantation process. Diffusion and ion implantation complement each other. For instance,
diffusion is used to form a deep junction, such as an n-tub in a CMOS device, while ion
implantation is utilized to form a shallow junction, like a source / drainjunction of a MOSFET.
Boron is the most common p-type impurity in silicon, whereas arsenic and phosphorus are used
extensively as n-type dopants. These three elements are highly soluble in silicon with
solubilities exceeding 5 x 1020 atoms / cm3 in the diffusion temperature range (between 800oC
and 1200oC). These dopants can beintroduced via several means, including solid sources (BN
for B, As2O3 for As, and P2O5 for P), liquid sources (BBr3, AsCl3, and POCl3), and gaseous
sources (B2H6, AsH3, and PH3). Usually, the gaseous source is transported to thesemiconductor
surface by an inert gas (e.g., N2) and is then reduced at the surface.
 Figure 8.1: Comparison of (a) diffusion and (b) ion implantation for theselective introduction of
dopants into a semiconductor substrate.

Diffusion Theory
Diffusion in a semiconductor can be envisaged as a series of atomic movement ofthe diffusant
(dopant) in the crystal lattice. Figure 8.2 illustrates the two basic atomic diffusion mechanisms.
The open circles represent the host atoms occupying the equilibrium lattice positions. The solid
dots represent impurity atoms. At elevated temperature, the lattice atoms vibrate around the
equilibriumlattice sites. There is a finite probability that a host atom can acquire sufficient
energy to leave the lattice site and to become an interstitial atom thereby creatinga vacancy.
When a neighboring impurity migrates to the vacancy site, as shown in Figure 8.2a, the
mechanism is called vacancy diffusion. If an interstitial atommoves from one place to another
without occupying a lattice site (Figure 8.2b), the mechanism is interstitial diffusion.
Figure 8.2: Models of atomic diffusion mechanisms for a two-dimensional lattice, with a being the
lattice constant: (a) Vacancy mechanism. (b) Interstitial mechanism.
The basic diffusion process of impurity atoms is like that of charge carriers.Let F be the flux of
dopant atoms traversing through a unit area in a unit time, and
F = -c/x,

where D is the diffusion coefficient, C is the dopant concentration, and x is thedistance in one
dimension. The equation imparts that the main driving force of the diffusion concentration
gradient -c/x, in fact, the flux is proportional to the concentration gradient, and the dopant
atoms will diffuse from a high-concentration region toward a low concentration region.

Silicon wafer processing plays a significant role in semiconductor manufacturing, mainly

because a silicon wafer is one of the major components of a semiconductor. A part of
semiconductor manufacturing is diffusion and ion implant. It is through diffusion and ion
implant by which dopants are added into a semiconductor, like silicon, to create electronic
structures that make ICs useful. To help you understand more about this process, here’s what
you need to know about diffusion.

The Basics of Diffusion

Diffusion is a part of semiconductor manufacturing, which is a part of silicon wafer processing.

Diffusion is the flow or movement of a chemical variety from an area of high concentration to
an area of lower concentration. Controlled diffusion of dopants into silicon is achieved
through diffusion furnace. It is the basis for building p-n junctions and fabrication of devices
during wafer manufacturing.

Flick’s Law

The arithmetic behind diffusion is based on Fick’s law. Fick’s first law is an equation expressing
the movement of an impurity in a substance, exhibiting that the flow of materials across a given
level is equivalent to the concentration gradient across the plane. But this law isn’t an adequate
characterization of the diffusion process since the concentration gradient of a contaminant in a
fixed volume of material tends to decline over time.
How Impurities are Deposited

There are two main methods to deposit impurities or contaminants into a substance by thermal
diffusion. The first method is called as pre-deposition. Pre-deposition is the continuous flow or
movement of impurities until it reaches the surface of the substrate so that the concentration
gradient of the impurity stays steady and stable at the surface of the substrate. The second method
is called redistribution or drive-in diffusion. It is a process that involves thin layers of impurity
materials deposited on the surface of the substrate, which diminishes with time.

The main front-end processing in building a device or integrated circuit is the selective
introduction of dopant atoms into silicon wafer.
Dopant introduction by high temperature diffusion is one of the two major processes for
achieving this.
Diffusion is a key process to introduce a controlled number of dopants into semiconductors and
to alter the conductivity type.
Diffusion is carried out at high temperature (800 to 1000 °C) in a dopant-rich gaseous ambient.
Diffusion Impurities:
Boron is the most common p-type impurity in silicon, whereas arsenic and phosphorus are used
extensively as n- type dopants.
These three elements are highly soluble in silicon with solubilities exceeding 5 x 1020 atoms /
cm3 in the diffusion temperature range (between 800oC and 1200oC).
These dopants can be introduced via several means, including:
solid sources (BN for B, As2O3 for As, and P2O5 for P),
liquid sources (BBr3, AsCl3, and POCl3), and
gaseous sources (B2H6, AsH3, and PH3).
Usually, the gaseous source is transported to the semiconductor surface by an inert gas (e.g.
N2) and is then reduced at the surface.
Diffusion is a process by which impurities are introduced into selected regions of a
semiconductor, for the purpose of changing its electronic properties.
At the present time, diffusion is a basic process step used in the fabrication of both discrete
devices and microcircuits.
Both single and multiple diffusion steps can be used for this purpose.
In silicon technology, diffusion allows the formation of sources and drain for metal-oxide-
semiconductor (MOS) devices and (b) the active regions of bipolar transistors.
It is extensively used because it is ideally adapted to batch processes where many slices are
handled in a single operation.
Unlike processes such as ion implantation, it does not produce crystal damage; thus, high-
quality junctions, with a minimum leakage current, can be made easily by this method.
Diffusion of Impurities
• Impurities can be doped into a semiconductor to form a p-n junction by thermal diffusion and
ion implantation.
• Diffusion of dopant impurities in selected regions can be carried out through windows in a
SiO2 masking layer at high temperature in a furnace.
Dopant incorporation by diffusion takes place at high temperatures ~1000oC in a furnace;
usually involves two processes: pre-deposition followed by drive-in.
Pre-deposition is a process where the wafer surface is in contact with a fixed concentration of
the dopant source.
Three different ways are possible: Diffusion of Impurities • Impurities can be doped into a
semiconductor to form a p-n junction by thermal diffusion and ion implantation. • Diffusion of
dopant impurities in selected regions can be carried out through windows in a SiO2 masking
layer at high temperature in a furnace. i) passing a dopant gas through the furnace, ii) bubbling
a carrier gas through a solution containing the dopants to produce a stream saturated with the
dopant, iii) bonding a solid source of doped oxide layer onto the wafer by spin-on technique.
Fig. Concentration Profile
•During pre-deposition, the required amount of dopant diffuses into the semiconductor.

•In the drive-in process, the semiconductor is heated in an inert environment to cause a
redistribution of the pre-deposited dopant to a desired profile.

➢ Diffusion describes the process by which atoms move in a crystal lattice.

➢ This includes self-diffusion phenomena, but goal is to study the diffusion of impurity
atoms that are introduced into the lattice for the purpose of altering its electronic
properties.
➢ In addition to concentration gradient and temperature, crystal structure and defect
concentration play an important part in diffusion.
➢ The wandering of an impurity in a lattice takes place in a series of random jumps.
➢ These jumps occur in all three dimensions, and a flux of diffusing species results if there
is a concentration gradient.
 The mechanisms by which jumps can take place:
Interstitial Diffusion:
• This is illustrated in Fig. 1, where an impurity atom moves through the crystal
lattice by jumping from oneinterstitial site to the next.
• Interstitial diffusion requires that jump motion occur from one
interstitial site to another adjacentinterstitial site.
• This process is relatively fast, because of the large number of vacant sites of this type
in a semiconductor.
• Impurities such as sodium and
lithium move in silicon by this
mechanism.
• Substitutional Diffusion:
• An impurity atom wanders through the crystal by jumping from one lattice site
to the next, thus substitutingfor the original host atom (see Fig. 2).
• However, it is necessary that this adjacent site be vacant; that is,
vacancies must be present to allowsubstitutional diffusion to occur.

Diffusion Nature

• Substitutional diffusion occurs at a much slower rate than interstitial diffusion

because the equilibrium concentration of vacancies is quite low.
• Many dopants used in silicon microcircuit fabrication are substitutional diffusers.
• Divacancies are also present in the semiconductor, so that diffusion can be
accomplished by movement into these sites.

Interstitial-Substitutional Diffusion:
• In this case, impurity atoms occupy substitutional as well as interstitial sites.
• However, they only move at a significant rate when in interstitial sites (by
interstitial diffusion).
• The dissociative mechanism, by which a substitutional impurity atom can become
an interstitial,
 leaving behind a vacancy, can be the controlling factor for this process.

• As a result, the effective diffusivity is a function of the dissociation rate, and depends
on both impurity concentration and crystal quality.
• Figure 3 illustrates this mechanism in schematic form. Copper and nickel move
in silicon by thismechanism, as do zinc, cadmium, and copper in GaAs.
• An alternative pathway for interstitial diffusion is the kick-out mechanism illustrated
in Fig. 4.
• Here, a rapidly moving interstitial diffuser can move into a substitutional site by
displacing an atom which is already in place, resulting in the formation of a self-
interstitial.
• The behaviour of both gold and platinum in silicon has been described by this
•
•
•
• process.

Interstitial Diffusion:
• This is modified version of substitutional diffusion (fig.5).
• Interstitial host atoms (self-interstitials) can be removed by pushing
substitutionally located impurity atomsinto interstitial sites.
• These impurities can now diffuse to adjacent substitutional sites and create new
self-interstitials.
• Thus, the interstitial position of the diffusion impurity atom is purely a
transition state, in moving from onesubstitutional site to another.
• This increases the concentration of vacant substitutional site over its
equilibrium value, so that interstitial diffusion is somewhat faster, than
substitutional diffusion.
• All substitutional diffusers move, in part, by this mechanism.
• The diffusion of boron and phosphorus in silicon is dominated by this process.
 Interchange Diffusion:
• This occurs when two or more atoms diffuse by an interchange process.
• Such a process is known as
– a direct interchange process, when it involves an impurity and host atom,
– a cooperative interchange, when a larger number of host atoms is involved.

Furnace annealing

is a process used in semiconductor device fabrication which consist of heating

multiple semiconductor wafers in order to affect their electrical properties. Heat treatments are
designed for different effects. Wafers can be heated in order to activate dopants, change film
to film or film to wafer substrate interfaces, densify deposited films, change states of grown
films, repair damage from implants, move dopants or drive dopants from one film into another
or from a film into the wafer substrate. During ion implantation process, the crystal substrate
is damaged due to bombardment with high energy ions. The damage caused can be repaired by
subjecting the crystal to high temperature. This process is called annealing. Furnace anneals
may be integrated into other furnace processing steps, such as oxidations, or may be processed
on their own.

Furnace anneals are performed by equipment especially built to heat semiconductor wafers.
Furnaces are capable of processing many wafers at a time but each process can last between
several hours and a day. Increasingly, furnace anneals are being supplanted by Rapid Thermal
Anneal (RTA) or Rapid Thermal Processing (RTP). This is due to the relatively long thermal
cycles of furnaces that causes the dopants that are being activated, especially boron, to diffuse
farther than is intended. RTP or RTA fixes this by having thermal cycles for each wafer that is
of the order of minutes rather than hours for furnace anneals.

What are Annealed Silicon Wafers?

In the case of silicon wafers, annealing is often used to improve the surface roughness and
crystal quality of the wafer. It can also be used to remove defects and impurities from the
surface of the wafer.

There are several different methods that can be used to anneal silicon wafers, including rapid
thermal annealing (RTA), furnace annealing, and laser annealing. The specific method used
will depend on the desired properties of the annealed wafer and the equipment available.
Annealed silicon wafers are used in a variety of applications, including the production of
microelectronic devices, such as transistors and integrated circuits (ICs). They are also used as
a substrate for the growth of thin films and as a starting material for the production of other
silicon-based materials. In addition to these applications, annealed silicon wafers are also used
in research and development for a variety of other applications.

Silicon Wafer Annealing uses a high-temperature furnace to relieves stress in silicon. The
heat activates ion-implanted dopants, reduces structural defects and stress, and reduces
interface charge at the silicon-silicon dioxide interface.

Advantages of Annealed Silicon Wafer Fabrication

Several advantages can be derived from Annealed Silicon Wafer Fabrication. Firstly, the
silicon used in the process has high purity and is less prone to heavy metals. Second, it can be
processed in a short period of time. Third, the annealed silicon wafer is relatively cheaper
than its unannealed counterpart. Then, it can be fabricated into various types of electronics.

Annealing is a process of reducing the overall cost of processing silicon wafers. This process
is also more cost-effective than other methods. For example, if a company is producing silica
optical boards, it will be able to use a lower-cost fixture. This fixture is also applicable to
smaller wafers and other substrate materials. Once the process is complete, the silicon wafer
is ready for further processing.

This method involves annealing the silicon wafer at a temperature greater than 700deg C for
several seconds or even several tens of seconds. It is important to maintain the temperature at
this level for at least one second, but the amount of time varies depending on the desired
characteristics of the wafer and the atmosphere. It can be performed without damaging the
wafer, so this method is preferred for advanced semiconductor processes.

Annealing silicon wafers can be characterized by low defect density. The defects are also free
of agglomerated voids and are significantly reduced when the silicon wafer is annealed.
Furthermore, it has a strong ability to capture heavy metal pollution, enhancing the chip yield.
In order to choose the best annealing method for your needs, be sure to select a vendor that
provides a certificate of conformance.
In the process of Annealed Silicon Wafer Fabrication, a silicon wafer is exposed to a
temperature of approximately 1200deg C. It can be annealed in hydrogen environment or at
lower temperatures. In either case, the annealed wafer is subjected to various high-temperature
processes and is usually a polycrystalline one. An annealed silicon wafer can be shaped and
etched to any shape that is desirable.

The process of Annealing involves heating the silicon wafer to a defined temperature in a
conditioned atmosphere. It depends on the type of surface and the purpose for which the
annealing is needed. An annealed silicon wafer can remove oxygen from the surface layer and
cause implanted ions to diffuse further into the silicon. The annealed silicon wafer can be
polycrystalline, monocrystalline, or polycrystalline.

The annealed silicon wafer is subjected to a high temperature to increase the quality of the
finished product. The silicon wafer is also subjected to a low-temperature environment to
enhance the efficiency of the process. The low-temperature annealing can be used to produce
thin film films and improve etching and sintering. It is possible to obtain a wide range of
different features from a single silicon wafer.

In the process of Annealed Silicon Wafer Fabrication, a silicon wafer is exposed to a

temperature of approximately 1200deg C. It can be annealed in hydrogen environment or at
lower temperatures. In either case, the annealed wafer is subjected to various high-temperature
processes and is usually a polycrystalline one. An annealed silicon wafer can be shaped and
etched to any shape that is desirable.

The process of Annealing involves heating the silicon wafer to a defined temperature in a
conditioned atmosphere. It depends on the type of surface and the purpose for which the
annealing is needed. An annealed silicon wafer can remove oxygen from the surface layer and
cause implanted ions to diffuse further into the silicon. The annealed silicon wafer can be
polycrystalline, monocrystalline, or polycrystalline.

The annealed silicon wafer is subjected to a high temperature to increase the quality of the
finished product. The silicon wafer is also subjected to a low-temperature environment to
enhance the efficiency of the process. The low-temperature annealing can be used to produce
thin film films and improve etching and sintering. It is possible to obtain a wide range of
different features from a single silicon wafer.
Metallization Provides the Connections That Bring Semiconductors to Life
The process of metallization which connects semiconductor devices using metals such as
aluminium and copper. As these interconnections provide power and enable the chip’s
operation, they highlight the significance of metallization in semiconductor manufacturing.
This article will also introduce the role of contacts and barrier metals in metallization, and
provide an insight into the larger context of connections from the perspective of a
semiconductor manufacturer.

Connections: The Veins of the Semiconductor

After the processes explored in the previous episodes including :

oxidation,

photolithography,

etching,

deposition

are completed, semiconductor devices are finally formed on the wafer’s surface. For memory
chip makers like SK Hynix, they line up transistors and capacitors1 on the wafer’s surface,
while foundries or CPU manufacturers line up three-dimensional transistors such as
FinFETs2 on the wafer.
Figure 1. Layers of a semiconductor device and areas of metal wiring

However, these devices prove to be useless if they are isolated. Just as individual devices on
top of an electronic substrate cannot work unless they are soldered, transistors on a wafer
cannot function without being interconnected with each other. These transistors operate by
receiving external power so they can perform various tasks such as moving processed data to
the next area. Accordingly, a process is required to connect devices to one another, or to a
power source. As for these devices, they must interact with one another using electricity as
semiconductors are essentially electronic circuits. This is where the metallization process
comes in to enable the operation of a semiconductor. As for different types of semiconductors
like CPUs or GPUs, they are created using the same devices that are interconnected in different
ways.

Metallization is not a single process such as photolithography, etching, and deposition —

processes that make it possible to apply metal wiring on a semiconductor. Additionally, the
metallization process is distinguishable for using materials, including metals, that have
different characteristics from materials that were used in the previous process of forming
device layers.
Thus, there is no “metallization equipment” like there is etching equipment. Instead, equipment
that is used in other processes is also used to make the metal wiring in the metallization process.
When a material needs to be carved out, etching equipment is used, while deposition equipment
is generally used to fill empty spaces. All the while, photolithography is involved between
these processes.

Contacts: Linking Wires and a Device

When connecting devices on the substrate, electric wires are first connected and then soldered
on. As layers are stacked starting from the bottom on a semiconductor, a junction called a
contact—which connects metal wiring with a device—is created after the formation of the
bottom device layer. The wiring is then connected on top of it.

Figure 3. The use of tungsten in the formation of contacts, and an example of barrier metal

It might seem like metal can be connected directly to the device without a contact, but an issue
arises as semiconductors go through miniaturization. This problem is related to the gaps that
inevitably form on the semiconductors. Although the deposition process has a “gap-fill”
property that fills in these voids to prevent devices from disintegrating, metals such as
aluminum are not able to fill in deep holes even with deposition. This results in faulty wires
which are desolate in the middle. Due to this problem, the gap must be filled beforehand by
depositing a metal like tungsten (W) that has a superior gap-fill property so the deep metal
wiring can be formed. This applies when there is significant distance between the device layer
and the metal layer. Otherwise, high-temperature heat treatment is required following the
formation of metal contacts. Furthermore, even when a metal or a material that is not heat-
resistant like aluminum is used, contacts need to be formed with tungsten while aluminum
wires are placed on top.

Barrier Metals: Reducing Metal-to-Metal Resistance

Meanwhile, a metal—or metal compound—called a barrier metal is needed between the device
and the contact. In semiconductor processing, it is very difficult to precisely connect non-
metallic and metallic materials. When two materials with different characteristics are directly
connected, a high resistance caused by the difference in conduction bands3 between the metal
and silicon occurs at the boundary. This leads to an increase in the power consumption of the
semiconductor. To avoid this, it is necessary to add a barrier metal. To make a barrier metal,
materials such as titanium (Ti) or cobalt (Co) are applied on top of the silicon layer of a
semiconductor device, and the metal reacts with the silicon atoms. This process is called
‘silicidation’ while the corresponding area is known as a contact silicide.

Barrier metals are also used to prevent unwanted damage to the device during processes.
Aluminum, for example, tends to react with silicon (Si) which is the main material in wafers.
When the aluminum metal wiring closely passes by the silicon in the device layer, a barrier
metal such as a titanium compound needs to be placed between the two as a barricade.

Figure 4. The purpose of the barrier metal when using aluminum wiring

In addition, the increased use of copper conductors due to the limitations of

aluminum has resulted in further application of barrier metals. Unlike aluminum,
copper has the tendency of diffusing into silicon dioxide (SiO2) which is more stable than
silicon. If left unchecked, the oxide film that is supposed to block the current will contain
copper atoms and cause current leakage. To prevent this, a metal called tantalum (Ta) is used
to create a boundary between the copper conductor and the device layer.
Conductors: Wires Connecting Semiconductor Devices

After soldering is completed, the wires need to be connected. The process of connecting wires
in a semiconductor has similarities to the process of connecting wires in a regular circuit. For
example, both processes create a part that is the equivalent to a sheathed cable. However, while
completed wires relate to each other in a normal electronic circuit, the wires are instead
‘created’ on top of the circuit for a semiconductor.

Figure 5. Comparison of reactive ion etching (RIE) and the damascene process (Source: Hanol
Publishing [Understanding Semiconductor Manufacturing Technology
Photomask:
Introduction
Photomasks used for optical lithography contain the pattern of the integrated circuits. The
basis is a so called blank: a glass substrate which is coated with a chrome and a resist layer.
The resist is sensitive to electron beams and can be transferred into the chrome layer via etch
processes. The chrome represents opaque areas on the photomask which are responsible for
the casting of shadow during exposure of the silicon wafers.
The photomasks are directly exposed with electron beams under hard vacuum. With this
method a resolution far below 100 nm is possible.

Due to wave optics (e.g. diffraction) there can be aberration during the exposure of wafers.
Thus the optical proximity correction (OPC) has been introduced in semiconductor
manufacturing, which can eliminate or reduce image defects. OPC means to modify the
structures on the mask in such a way that the shape of the image on the wafer looks like
desired. Furthermore, there can be additional structures just for minimizing aberration which
do not have any function for the integrated device itself.

1. First step is the exposure of photoresist with electron beams (or laser).

2. Subsequent the resist is developed to form a pattern.

3. The resist acts as a masking to transfer the pattern into the chrome layer by etch
processes.

4. Subsequent the resist is removed.

 5. Finally a pellicle is montaged on top to prevent contamination of the
glass/chrome

Photomask manufacture
The manufacturing of photomasks is basically equal to the wafer fabrication. The difference is
the exposure of the resist which is done by electron beams (photomasks) or with optical
lithography (wafer).

A photomask is an opaque plate with transparent areas that allow light to shine through in a
defined pattern. Photomasks are commonly used in photolithography for the production
of integrated circuits (ICs or "chips") to produce a pattern on a thin wafer of material
(usually silicon). Several masks are used in turn, each one reproducing a layer of the completed
design, and together known as a mask set.

History

For IC production in the 1960s and early 1970s, an opaque rubylith film laminated onto a
transparent mylar sheet was used. The design of one layer was cut into the rubylith, initially by
hand on an illuminated drafting table (later by machine (plotter)) and the unwanted rubylith
was peeled off by hand, forming the master image of that layer of the chip. Increasingly
complex and thus larger chips required larger and larger rubyliths, eventually even filling the
wall of a room. (Eventually this whole process was replaced by the optical pattern generator to
produce the master image). At this point the master image could be arrayed into a multi-chip
image called a reticle. The reticle was originally a 10X image of the chip.
The reticle was by step-and-repeater photolithography and etching used to produce a
photomask with image-size the same as the final chip. The photomask might be used directly
in the fab or be used as master-photomask to produce the final actual working photomasks.

As feature size shrank, the only way to properly focus the image was to place it in direct contact
with the wafer. These contact aligners often lifted some of the photoresist off the wafer and
onto the photomask and it had to be cleaned or discarded. This drove the adoption of reverse
master photomasks (see above), which were used to produce (with contact photolithography
and etching) the needed many actual working photomasks. Later, projection photo-lithography
meant photomask lifetime was indefinite. Still later direct-step-on-wafer stepper photo-
lithography used reticles directly and ended the use of photomasks.

Photomask materials changed over time. Initially soda glass was used with silver
halide opacity. Later borosilicate and then fused silica to control expansion,
and chromium which has better opacity to ultraviolet light were introduced. The original
pattern generators have since been replaced by electron beam lithography and laser-driven
systems which generate reticles directly from the original computerized design.

Lithographic photomasks are typically transparent fused silica plates covered with a pattern
defined with a chromium (Cr) or Fe2O3 metal absorbing film.[1] Photomasks are used at
wavelengths of 365 nm, 248 nm, and 193 nm. Photomasks have also been developed for other
forms of radiation such as 157 nm, 13.5 nm (EUV), X-ray, electrons, and ions; but these
require entirely new materials for the substrate and the pattern film.[1]

A set of photomasks, each defining a pattern layer in integrated circuit fabrication, is fed into
a photolithography stepper or scanner, and individually selected for exposure. In multi-
patterning techniques, a photomask would correspond to a subset of the layer pattern.

In photolithography for the mass production of integrated circuit devices, the more correct
term is usually photoreticle or simply reticle. In the case of a photomask, there is a one-to-
one correspondence between the mask pattern and the wafer pattern. This was the standard for
the mask aligners that were succeeded by steppers and scanners with reduction optics. As used
in steppers and scanners, the reticle commonly contains only one layer of the
designed VLSI circuit. (However, some photolithography fabrications utilize reticles with
more than one layer placed side by side onto the same mask).
The pattern is projected and shrunk by four or five times onto the wafer surface. To achieve
complete wafer coverage, the wafer is repeatedly "stepped" from position to position under the
optical column until full exposure is achieved.

Features 150 nm or below in size generally require phase-shifting to enhance the image quality
to acceptable values. This can be achieved in many ways. The two most common methods are
to use an attenuated phase-shifting background film on the mask to increase the contrast of
small intensity peaks, or to etch the exposed quartz so that the edge between the etched and
unetched areas can be used to image nearly zero intensity. In the second case, unwanted edges
would need to be trimmed out with another exposure. The former method is attenuated phase-
shifting, and is often considered a weak enhancement, requiring special illumination for the
most enhancement, while the latter method is known as alternating-aperture phase-shifting,
and is the most popular strong enhancement technique.

As leading-edge semiconductor features shrink, photomask features that are 4× larger must
inevitably shrink as well. This could pose challenges since the absorber film will need to
become thinner, and hence less opaque. A 2005 study by IMEC found that thinner absorbers
degrade image contrast and therefore contribute to line-edge roughness, using state-of-the-art
photolithography tools. One possibility is to eliminate absorbers altogether and use
"chromeless" masks, relying solely on phase-shifting for imaging.

The emergence of immersion lithography has a strong impact on photomask requirements. The
commonly used attenuated phase-shifting mask is more sensitive to the higher incidence angles
applied in "hyper-NA" lithography, due to the longer optical path through the patterned film.

Photolithography
Photolithography or UV lithography is a method of fabrication of thin film patterns. An optical
mask is irradiated with UV light to transfer the existing geometric pattern over the optical mask
to a substrate via a light-sensitive chemical process. These methods include a series of chemical
procedures, which etches the pattern into electroactive material. The prime merit of this process
is good regulation over the thickness of pattern, albeit the rigorous process, time-consuming
property, and utilization of photoresists are the major bottlenecks in their wide use.
Schematic illustration of interdigital MSCs fabricated using (A) Photolithography, adapted
with permission from [43] © 2019 Author(s), Published under license by AIP Publishing., (B)
Screen printing, reproduced with permission from [44] © The Royal Society of Chemistry
2019, (C) Stamping, Adapted with permission [22] © 2020 The Authors. Published by
WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim, (D) 3D-printing, reproduced with
permission from [29] © 2020 Taylor & Francis Group, LLC, (E) Inkjet Printing, adapted
with permission [45] © The Royal Society of Chemistry 2021, and (F) Laser direct writing,
adapted with permission from [35] Copyright © 2021, The authors, Published by Springer
Nature.

In simple words, in photolithography, the substrate is coated with active material and the
system is called a wafer. Then the wafer is covered with a photoresist. Consequently,
photomasking is executed for the region to be UV light exposed. Then UV light is irradiated
over the system. After that, the photoresist irradiated with UV light is developed and removed
followed by etching of UV-exposed active material. Finally, the remaining photoresist is
removed to obtain the wafer with the desired pattern. The implementation of complex steps
and toxic etchants are less suitable for industry-level production of MSCs. Therefore, printing
methods are endorsed by research groups to fabricate MSC devices.
Photolithography
Photolithography is a standard technique and widely used in the semiconductor industry, but it
also allows the preparation of metal nanoparticles. Since photolithography is commonly used
and well known, it will only be briefly reviewed. Its principle relies on imaging a structure
written in a lithographic mask onto a light-sensitive resist that has been previously deposited
on a substrate.
Two ways can be chosen, either with positive resist or with negative resist. The standard
process using a positive resist is schematically depicted in Figure 21. At first, a metal film is
deposited on the substrate (Figure 21(a)). Afterwards, a photoresist is spin coated on the
sample and a soft bake process (up to 30 min at temperatures between 60 and 100 °C) of the
resist is accomplished (Figure 21(b)). The sample is then illuminated through a mask with
suitable light (Figure 21(c)). Thus, the structure of the mask is imaged on the resist and causes
photochemical changes therein. Afterwards, the resist is developed and hard baked for 20–
30 min at temperatures between 120 and 180 °C (Figure 21(d)). Finally, the open metal areas
are etched away (Figure 21(e)) and the photoresist is removed, leaving the metal nanoparticles
on the substrate (Figure 21(f)).
Synthesis of nanomaterials:

There are two general approaches to the synthesis of nanomaterials and the fabrication of
nanostructures. They are (1) top-down method of miniaturizing materials, (2) bottom-up
method of building molecular structures atom by atom or molecule by molecule. The top-down
approach has been advanced by Richard Feynman in 1959 lecture stating that “there is plenty
of room at the bottom” and it is ideal for obtaining structures with long-range order and for
making connections with macroscopic world. The bottom-up approach was pioneered by Jean-
Marie Lehn (revealing that “there is plenty of room at the top”) and it is best suited for assembly
and establishing short-range order at the nanoscale.

Top-down approach This approach uses larger (macroscopic) initial structures, which can be
externally controlled in the processing of nanostructures. Typical examples are
photolithography, etching through the mask, ball milling and application of severe plastic
deformation.

1. Top-Down: lithography - The most used top-down approach is photolithography. It

has been used to manufacture computer chips and produce structures smaller than 100
nm. Typically, an oxidized silicon (Si) wafer is coated with a 1μm thick photoresist
layer. After exposure to ultraviolet (UV) light, the photoresist undergoes a
photochemical reaction, which breaks down the polymer by rupturing the polymer
chains. Subsequently, when the wafer is rinsed in a developing solution, the exposed
areas are removed leading to nano-size material. The other methods are electron-beam
lithography and X – ray lithography. In a ball milling process a powder mixture placed
in the ball mill (a cylinder with steel balls which are rotating at high speeds) is subjected
to high-energy collision from the balls. At the initial stage of ball milling, the powder
particles are flattened by the compressive forces due to the collision of the balls. Micro-
forging leads to changes in the shapes of individual particles, or cluster of particles
being impacted repeatedly by the milling balls with high kinetic energy. At the
intermediate stage of the mechanical alloying process, the intimate mixture of the
powder constituents decreases the diffusion distance to the micrometre range.
Fracturing and cold welding are the dominant milling processes at this stage. At the
final stage of the mechanical alloying process, considerable refinement and reduction
in particle size is achieved.

Bottom-up approach:These approaches include the miniaturization of materials

components (up to atomic level) with further self-assembly process leading to the
formation of nanostructures. During self-assembly the physical forces operating at
nanoscale are used to combine basic units into larger stable structures.

Examples- 1. sol-gel processing, 2. chemical vapour deposition (CVD), 3. plasma

or flame spraying synthesis, 4. laser pyrolysis, 5. atomic or molecular condensation
– Inert gas condensation.

1. The sol-gel technique for synthesis of nanomaterials is a wet- chemical technique.

Such techniques are used for the fabrication of materials starting from a chemical
solution (sol, short for solution) which acts as the precursor for an integrated network
(or gel) of either discrete particles or network polymers. Precursors in the form of
acetates or carbonates or nitrates are taken and then dissolved in deionized water. This
starting material is used to produce a colloidal suspension known as gel. After that a
gelling agent for example, polyvinyl alcohol is added and this will produce a gel. A thin
film coating is made on a substrate for example, Ni or Ti sheets and glass. At last, the
film is annealed at suitable temperature and then characterized.

2. In a chemical vapour deposition process, vapour is formed in a reaction chamber

by pyrolysis reduction, oxidation or nitridation, and then deposited on the surface.
Areas of growth are controlled by patterning processes like photolithography or
photomasking (deposition patterns are etched on to the surface layers of the wafers).

3. The inert gas condensation (IGC) process is one of the most known and simplest
technique for production of nanoparticles (in particular, Me nano-powders). An
inorganic material is vaporized inside a vacuum chamber into which an inert gas
(typically argon or helium) is periodically admitted. Once the atoms boil off, they
quickly lose their energy by colliding with the inert gas. The vapour cools rapidly and
supersaturates to form nanoparticles with sizes in the range 2–100 nm that collect on a
finger cooled by liquid nitrogen.

4. The production route for 1-D rod-like nanomaterials by liquid phase methods is like
that to produce nanoparticles. CVD methods have been adapted to make 1-D nanotubes
and nanowires. Catalyst nanoparticles are used to promote nucleation. Nanowires of
other materials such as silicon (Si) or germanium (Ge) are grown by vapour liquid-solid
(VLS) methods.