The document describes designing a BCD-to-seven-segment decoder using Verilog. It includes a truth table and Karnaugh maps to minimize the number of gates needed. A Verilog module is provided to simulate the decoder. Screenshots show the simulation output verifying the design works as intended.
The document describes designing a BCD-to-seven-segment decoder using Verilog. It includes a truth table and Karnaugh maps to minimize the number of gates needed. A Verilog module is provided to simulate the decoder. Screenshots show the simulation output verifying the design works as intended.
The document describes designing a BCD-to-seven-segment decoder using Verilog. It includes a truth table and Karnaugh maps to minimize the number of gates needed. A Verilog module is provided to simulate the decoder. Screenshots show the simulation output verifying the design works as intended.
The document describes designing a BCD-to-seven-segment decoder using Verilog. It includes a truth table and Karnaugh maps to minimize the number of gates needed. A Verilog module is provided to simulate the decoder. Screenshots show the simulation output verifying the design works as intended.
Laboratory No.3 CPET7L – 2A Thursday 7:00AM to 10:00PM
Submitted By: Almarines, Jerico Cochangco, Joshua Dabon, Eugene Ferrolino, Japhet Mendoza, Aldrin Daniel G.
Submitted To: Engr. AIMEE G. ACOBA CPE Faculty Hardware Descriptive Language
Type the question then screenshot the result of your program.
Task Assessment An ABCD-to-seven-segment decoder is a combinational circuit that converts a decimal digit in BCD to an appropriate code for the selection of segments in an indicator used to display the decimal digit in a familiar form. The seven outputs of the decoder (a, b, c, d, e, f, and g) select the corresponding segments in the display, as shown on Figure 1. The numeric display chosen to represent the decimal digit is shown in Table No.1. Using a truth table and Karnaugh maps, design the BCD-to-seven-segment using a minimum number of gates (except NOT gate).
Verilog program :
module Seg (W,X,Y,Z,a,b,c,d,e,f,g);
input W,X,Y,Z; output a,b,c,d,e,f,g; assign a = ((~(W)&~(X)&~(Z))|((~(W)&Y))|(~(W)&X&Z)|(W&~(X)&~(Y))); assign b = ((~(W)&~(Y)&~(Z))|(~(W)&Y&Z)|(~(W)&~(X))|(~(X)&~(Y))); assign c = ((~(W)&~(X)&Z)|(~(W)&X&~(Z))|(~(W)&~(Y))|(~(X)&~(Y))); assign d = ((~(X)&~(Y)&~(Z))|(~(W)&X&Z)|(~(W)&Y)); assign e = ((~(W)&~(X)&~(Z))|(W&~(X)&~(Y))|(~(W)&X&Y)); assign f = ((~(X)&~(Y)&~(Z))|(~(W)&X&~(Y))|(~(W)&X&~(Z))|(W&~(X)&~(Y))); assign g = ((W&~(X)&~(Y))|(~(W)&Y)|(~(W)&X)); endmodule
