CHAPTER 8

COUNTER

Objectives

 JK Flip-flop

 Ripple Counter

 Synchronous Counter
116 Counter

8.1 JK Flip-Flop

The JK flip-flop may be considered an extension of the SR flip-flop. The JK flip-

flop operates as an SR flip-flop whose inputs are assigned J=S and K=R. However,
whereas the S=1, R=1 input combination is not allowed (invalid), the JK uses this
input as a toggle mode. The term ‘toggle’ comes from the on-off nature of a toggle
switch. When J=1, K=1, the output Q changes from 0  1 or from1  0 .

This flip-flop can be considered the universal flip-flop: other types of flip-flop can
be made from it. The four mode of operation (hold, reset, set and toggle) are
summarized in the truth table below.

Mode Input Present Next

State State
J K Q CLK Q*
Hold 0 0 0 0
0 0 1 1
Reset 0 1 0 0
0 1 1 0
Set 1 0 0 1
1 0 1 1
Toggle 1 1 0 1
1 1 1 0

By plotting the next state Q* on a Karnaugh Map, the equation of the JK flip-flop
can be derived as Q*  K.Q  J.Q

J .K J. J. J .K
K K J SET
Q
Q 1 1
0 2 6 4
K CLR Q
Q 1 1
1 3 7 5

The truth table can be summarized as shown below:

Mode J K CLK Q
Hold 0 0 Q
Reset 0 1 0
Set 1 0 1
Toggle 1 1 Q
Counter 117

Example 1:
Assume that Q=0 initially. Determine the Q waveform for the JK flip-flop.

CLK 1 2 3 4 5 6 7 8

J J SET
Q
K
Q K CLR Q

Hold Set Hold Reset Toggle Toggle Hold Toggle

This is a positive-edge triggered JK flip-flop. The output Q changes states (reacts)

when the CLK changes from 0 to 1.

Example 2:
Assume that Q=0 initially. Determine the Q waveform for the JK flip-flop.

CLK 1 2 3 4 5 6 7 8
J J SET
Q
K
Q K CLR Q

Hold Set Hold Reset Toggle Toggle Hold Toggle

This is a negative-edge triggered JK flip-flop. The small bubble on the CLK input
indicates that this flip-flop will trigger when the CLK input goes from 1 to 0. The
output Q changes states (reacts) during 1  0 clock transition.

8.2 Ripple Counter

Counter are important digital circuits. Counters are used to measure the
frequency of a signal. They are used to in digital clock – that displays the time of
the day in hours, minutes and seconds. Digital counters have the following
characteristics:
1. Modulus of counter- the maximum number of counts.
2. Up do down counter.
3. Ripple (asynchronous) or synchronous counter.
4. Free-running or self stopping.
118 Counter

A counter that counts from 00 to 11 (0 to 3) is called modulo-4 or mod-4 counter.

The modulus of a counter is the number of counts the counter goes through. A
mod-4 ripple counter using JK flip-flops is shown below. Note that each flip-flop
is in its toggle mode. Each flip-flop output drives the CLK input of the next flip-
flop.

The clock pulse is applied to the clock of flip-flop A. The output of flip-flop A is
connected to the clock of flip-flop B. Flip-flop A will toggle (change to its opposite
state) each time a clock pulse make a 1  0 transition. The output of flip-flop A
will acts as the clock for flip-flop B, and so the output B will toggle each time A
goes from 1  0 transition. The counting sequence is 00, 01, 10, 11 (0,1,2,3).

1 J SET
Q 1 J SET A B
Q

Clock pulse A B
1 K Q 1 K
CLR CLR Q

CLK 0 1 2 3 4 5 6 7 8 9

AB 00 01 10 11 00 01 10 11 00 01

Example 1.

A mod-8 ripple counter counts from 000 to 111 (0 to 7) using 3 JK flip-flops is

shown below. Draw the output waveform.

1 J SET Q 1 J SET Q 1 J SET Q A B C

1 K CLR Q 1 K CLR Q 1 K CLR Q

Counter 119

Mod-10 counter or decade counter that counts is probably the most widely used
counter. The first step in constructing a mod-10 counter is to list the counting
sequences shown below. The counting sequence for the mod-10 is from 0 to 9.
Look at the binary count immediately after 1001 (9). In this case it is 1010. Feed
the 1010 into a logic circuit that will produce a clear or a reset pulse. The clear
pulse goes back to an asynchronous clear input on each JK flip-flop, thus clearing
or resetting the counter to 0000.

A B C D
0 0 0 0
0 0 0 1 1 1
J SET Q 1 J SET 1 J SET A B C D
0 0 1 0
0 0 1 1 J SET Q Q Q
1
0 1 0 0 1
KCLR Q
0 1 0 1 Recycle 1 KCLR 1 KCLR
KCLR Q
0 1 1 0
Q Q
0 1 1 1
1 0 0 0
1 0 0 1 CLR
1 0 1 0
1 0 1 1 Logic circuit to clear or
1 1 0 0 reset the JK flip-flop when
1 1 0 1 input is 1010
1 1 1 0
1 1 1 1

To clear or the reset the JK flip-flop, the clear input CLR=0. The truth table for the
logic circuit will produce an output CLR=0 when the input ABCD is 1010.
A B C D CLR
0 0 0 0 1
A.B A.B A.B A.B
0 0 0 1 1
0 0 1 0 1 C.D 1 1 X 1
0 4 12 8
0 0 1 1 1
0 1 0 0 1 C.D 1 1 X 1
0 1 0 1 1 1 5 13 9
0 1 1 0 1
C.D 1 1 X X
0 1 1 1 1 3 7 15 11
1 0 0 0 1
1 0 0 1 1 C.D 1 1 X 0
2 6 14 10
1 0 1 0 0
1 0 1 1 X
1 1 0 0 X CLR  A  C  A.C
1 1 0 1 X
1 1 1 0 X
1 1 1 1 X

The simplified Boolean expression is CLR  A.C . A 2-input NAND gate will do
the job when the input is A=1 and C=1. The NAND gate does the job of resetting
the JK flip-flops to 0000 by activating the CLR input to 0.
120 Counter

1 SET 1 SET 1 SET 1 SET A B C D

J Q J Q J Q J Q

1
K Q 1 K Q 1 K Q 1 K Q
CLR CLR CLR CLR

8.4 Synchronous Counter Design

Synchronous counters can count up and down and can be designed to produce
special purpose count sequences of nonconsecutive numbers. A synchronous
counter has a common clock signal that controls all flip-flops. All flip-flop CLK
inputs are tied directly to the input clock. A synchronous counter shown below
has a count sequence of nonconsecutive number: 0, 2, 4, 6.

4321

A B C

5V
+V
S S S
J Q J Q J Q
CP _ CP _ CP _
K Q K Q K Q
R R R
Counter 121

Synchronous counter design follows a systematic procedure to specify the count

sequence required and to determine the input logic expressions to obtain the
desired count sequence. The JK flip-flop excitation table describes the input
conditions that produce the output state from each individual JK flip-flop. The JK
flip-flop excitation table is shown below.

Present Next Input Mode

State State JK
0 → 0 0X Hold ( 0 0 ) or Reset ( 0 1 )
1 → 1 X0 Hold ( 0 0 ) or Set ( 1 0 )
0 → 1 1X Toggle ( 1 1 ) or Set ( 1 0 )
1 → 0 X1 Toggle ( 1 1 ) or Reset ( 0 1)

0X X0
1X

0 1

X1

Example 1:
Design a synchronous counter to count the following sequence:
0, 1, 2, 3

There are four steps in designing a synchronous counter:

1. Draw the transition state diagram showing all possible states.
2. Use the transition state diagram to set up an excitable table by listing the
present state and the next state sequence.
3. Expand the excitation table by adding J and K inputs. For each present
state, indicate the input required at each J and K to produce the transition
to the next state.
4. Design the logic circuits to generate the input required at each J and K.

Step 1: Transition state diagram.

0 1 2 3
122 Counter

Step 2: Excitation Table

Present Next
State State
PS A B NS A' B' JA KA JB KB
0 0 0 1 0 1
1 0 1 2 1 0
2 1 0 3 1 1
3 1 1 0 0 0

Step 3: Input for each J and K .

Let’s look at the first line where the transition is from 00  01 . For this state, the
A flip-flop goes from 0  0 and the B flip-flop goes from 0  1.

The 0  0 transition for A flip-flop requires an input JAKA = 0 X.

The 0  1 transition for B flip-flop requires an input JBKB = 1 X.

The excitation table is shown below:

Present Next
State State
PS A B NS A' B' JA KA JB KB
0 0 0 1 0 1 0 X 1 X
1 0 1 2 1 0 1 X X 1
2 1 0 3 1 1 X 0 1 X
3 1 1 0 0 0 X 1 X 1

Step 4: Design the logic circuits JAKA and JBKB.

The excitation table lists four J and K inputs: JA, KA, JB and KB. We must consider
each of these as an output from its own logic circuit with inputs from flip-flop A
and B. Let’s design the circuit for JA.
Counter 123

To do this we need to look at the present states of AB and the output JA. The JA
expression can be simplified using Karnaugh map as shown below.

PS A B JA A A
0 0 0 0 B 0 X
0 2
1 0 1 1
B 1 X
2 1 0 X 1 3

3 1 1 X JA  B

We follow the same steps for KA, JB and KB as shown below:

A A A A A A
B X1 0 B 1 1 B X X
0 2 0 2 0 2

B X1 1 B X X B 1 1
1 3 1 3 1 3

KA  B JB  1 KB  1

Step 5: Draw the synchronous counter

A B

1
SET
J Q J SET Q

K CLR Q K CLR Q
124 Counter

Example 1:
Design a synchronous counter to count the following sequence:

1, 2, 3

Transition State Diagram

123

Excitation Table

Present Next
State State
PS A B NS A' B' JA KA JB KB
0 0 0 X X X
1 0 1 2 1 0
2 1 0 3 1 1
3 1 1 1 0 1

Input for J and K

Present Next
State State
PS A B NS A' B' JA KA JB KB
0 0 0 X X X X X X X
1 0 1 2 1 0 1 X X 1
2 1 0 3 1 1 X 0 1 X
3 1 1 1 0 1 X 1 X 0

Design the circuit.

A A A A
B A
X
A
X B A
X
A
0 B X 0 B X X
0 2 0 2 0 2 0 2

B 1 X B X 1 B X 1 B 1 0
1 3 1 3 1 3 1 3

KB  A
Counter 125

Draw the counter circuit.

A B

1 J
SET
Q 1 J
SET
Q

K CLRQ K CLR Q
126 Counter

8.5 Synchronous Counter Analysis

Analysis is the process of determining the output response of a given circuit to a

given input sequence. A synchronous counter can be analyzed to determine the
counting sequence. Given a synchronous counter circuit, we need to determine
the state diagram that defines its counting. There are three steps in analyzing a
synchronous counter:
1. Write the J and K expressions
2. Derive the excitation table
3. From the excitation table, draw the state diagram.

Example 1:
Analyze the synchronous counter circuit shown below.
A B

1 J
SET
Q 1 J
SET
Q

K CLR Q K CLR Q

1. From the given circuit, the J and K expressions are:

JA  KA  B
1 KB  A
JB 
1

2. Derive the excitation table.

PRESENT NEXT
State State
PS A B NS A' B' JA KA JB KB
0 0 0
1 0 1
2 1 0
3 1 1
Counter 127

The input J and K can be specified according to their logic expressions.

 JA =1 and JB =1.
 KA  B . The input for KA is present state of B: 0 1 0 1.
 KB  A . The input for KB is the complement of A: 1100

PS A B NS A' B' JA KA JB KB
0 0 0 1 0 1 1
1 0 1 1 1 1 1
2 1 0 1 0 1 0
3 1 1 1 1 1 0

The next state A’B’ is determined by the present state AB and the JK input. Let’s
look at the next state for A’.

PS NS
A JA KA A'
0 1 0 Set → 1
0 → 1 1 Toggle → 1
1 1 0 Set → 1
1 → 1 1 Toggle → 0

The next state for B’ is as follows:

PS NS
B JB KB B'
0 → 1 1 Toggle → 1
1 → 1 1 Toggle → 0
0 1 0 Set → 1
1 1 0 Set → 1

The completed excitation table is:

PS A B NS A' B' JA KA JB KB
0 0 0 3 1 1 1 0 1 1
1 0 1 2 1 0 1 1 1 1
2 1 0 3 1 1 1 0 1 0
3 1 1 1 0 1 1 1 1 0
128 Counter

Transition state diagram

0 3 1 2

It has a counting sequence of 1, 2, 3.

Counter 129

Exercises

1. Assume that Q=0 initially. Determine the Q waveform for the positive-edge
triggered JK flip-flop.

CLK 1 2 3 4 5 6 7 8
SET
J Q
J

K
K CLR Q

Q=0

2. Assume that Q=0 initially. Determine the Q waveform for the negative-
edge triggered JK flip-flop.

CLK 1 2 3 4 5 6 7 8

J SET
J Q

K
K CLR Q

Q=0

3. Draw the output waveform for a mode-16 ripple counter.

1 SET 1 SET 1 SET 1 SET A B C D

J Q J Q J Q J Q
1
K CLR Q 1 K Q 1 K Q 1 K Q
CLR CLR CLR

4. Draw a mod-6 ripple counter that counts from 000 to 101.

5. Draw a mod-14 ripple counter that counts from 0000 to 1101.

130 Counter

6. Design a synchronous counter using JK flip-flop.

a. Mod-16 that counts 0 to 15.
b. Mod-4 that counts 3, 2, 1, 0.
c. Mode-10 that counts 0 to 9

7. Design a synchronous counter using JK flip-flop to count the following

sequence:
a. 1, 2, 3, 4, 5, 6
b. 2, 4, 6
c. 9,8,7,6,5,4,3,2,1,0

8. Design a self stopping synchronous counter using JK flip-flop.

a. 0,1,2,3 and stop at 3.

0123

b. 9 to 0 and stop at 0.

98765 43210

9. Determine the counting sequence.

A B C

+5V
SET SET SET
J Q J Q J Q

K CLR
Q K CLR
Q K CLR
Q

10. Determine the counting sequence.

Counter 131

A B C D

SET SET SET SET

J Q J Q J Q J Q

K CLR Q K CLR Q K CLR Q K CLR

Q
132 Counter

11. Design a synchronous counter to count the following sequence:

0, 2, 1, 3

Transition State Diagram

0 2 1 3

Excitation Table

Present Next
State State
PS A B NS A' B' JA KA JB KB
0 0 0
1 0 1
2 1 0
3 1 1

Design the logic circuits for JAKA and JBKB.

A A A A A A A A

B B B B
0 2 0 2 0 2 0 2
B
B B B
1 3 1 3 1 3 1 3

JA = KA= JB = KB =

Draw the synchronous counter

A B

J SET
Q J SET
Q

K CLR
Q K CLR
Q
Counter 133

12. Design a synchronous counter to count the following sequence:

0, 1, 2, 3, 4, 5, 6, 7

Transition State Diagram

Excitation Table

Present Next
State State
PS A B C NS A' B' C' JA KA JB KB JC KC
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1

Design the logic circuits for JAKA and JBKB.

A.B A.B A.B A.B A.B A.B A.B A.B

C C
0 2 6 4 0 2 6 4

C C
1 3 7 5 1 3 7 5

JA = KA =

A.B A.B A.B A.B A.B A.B A.B A.B

C C
0 2 6 4 0 2 6 4

C C
1 3 7 5 1 3 7 5

JB = KB =

A.B A.B A.B A.B A.B A.B A.B A.B

C C
0 2 6 4 0 2 6 4

C C
1 3 7 5 1 3 7 5

KC = KC =
134 Counter

Draw the counter.

A B C

J SET Q J SET Q J SET Q

K CLR
Q K CLR
Q K CLR
Q
Counter 135

13. Design a synchronous counter to count the following sequence:

1, 2, 3

Transition State Diagram

Assume that the state 0 goes 1.

0 123

Excitation Table

Present Next
State State
PS A B NS A' B' JA KA JB KB
0 0 0
1 0 1
2 1 0
3 1 1

Design the circuit.

A A A A A A A A

B B B B
0 2 0 2 0 2 0 2
B
B B B
1 3 1 3 1 3 1 3

JA=1 KA=B JB=1 KB  A

Draw the counter circuit.

136 Counter

14. Design a synchronous counter to count the following sequence:

0, 2 , 4 , 6

Transition State Diagram

Excitation Table

Present Next
State State
PS A B C NS A' B' C' JA KA JB KB JC KC
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1

Design the logic circuits for JAKA and JBKB.

A.B A.B A.B A.B A.B A.B A.B A.B

C C
0 2 6 4 0 2 6 4

C C
1 3 7 5 1 3 7 5

JA = KA =

A.B A.B A.B A.B A.B A.B A.B A.B

C C
0 2 6 4 0 2 6 4

C C
1 3 7 5 1 3 7 5

JB = KB =

A.B A.B A.B A.B A.B A.B A.B A.B

C C
0 2 6 4 0 2 6 4

C C
1 3 7 5 1 3 7 5

KC = KC =
Counter 137

Draw the counter.

A B C

J SET Q J SET Q J SET Q

K CLR
Q K CLR
Q K CLR
Q
138 Counter

15. Design a synchronous counter to count the following sequence:

Excitation Table

3
0 2 4 6

Present Next
State State
PS A B C NS A' B' C' JA KA JB KB JC KC
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1

Design the logic circuits for JAKA and JBKB.

A.B A.B A.B A.B A.B A.B A.B A.B

C C
0 2 6 4 0 2 6 4

C C
1 3 7 5 1 3 7 5

JA = KA =

A.B A.B A.B A.B A.B A.B A.B A.B

C C
0 2 6 4 0 2 6 4

C C
1 3 7 5 1 3 7 5

JB = KB =
Counter 139

A.B A.B A.B A.B A.B A.B A.B A.B

C C
0 2 6 4 0 2 6 4

C C
1 3 7 5 1 3 7 5

KC = KC =

Draw the counter

A B C

J SET Q J SET Q J SET Q

K CLR
Q K CLR
Q K CLR
Q
140 Counter

16. The diagram shown below is a synchronous counter. Analyze the circuit.

A B C

1
SET SET SET
J Q J Q J Q

K CLR
Q K CLR
Q K CLR
Q

J and K expressions
JA = KA =
JB = KB =
JC = KC =

Excitation Table

PS A B C NS A' B' C' JA KA JB KB JC KC

0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1

Transition State Diagram

Counter 141

17. The diagram shown below is a synchronous counter. Determine the counting
sequence.

A B

5V
+V

S S
J Q J Q
CP _ CP _
K Q K Q
R R
V1
CP1
Q1
CP2

J and K expressions
JA = KA =
JB = KB =

Excitation Table

PS A B NS A' B' JA KA JB KB
0 0 0
1 0 1
2 1 0
3 1 1

Transition State Diagram