Digital System Design

- Behavioral Modeling

Prof. Dhaval shah

 Objectives of this Topic
• initial and always blocks
• The concept of multiple flows of control
• Practice simple examples
• Procedural assignment vs. Continuous assignment
• Blocking vs. non-blocking assignments
• Conditional statements
– if, case, casex, casez
• Loop statements
– while, for, repeat, forever
 Introduction
• The move toward higher abstractions
– Gate-level modeling
• Netlist of gates

– Dataflow modeling
• Boolean function assigned to a net

– Now, behavioral modeling

• A sequential algorithm (quite similar to software) that
determines the value(s) of variable(s)

2010 3
 Structured Procedures
• Two basic structured procedure statements

always
initial

– All behavioral statements appear only inside these blocks

– Each always or initial block has a separate activity flow
(multithreading, concurrency)
– Start from simulation time 0
– No nesting
 Structured Procedures:
initial statement
• Starts at time 0
• Executes only once during a simulation
• Multiple initial blocks, execute in parallel
– All start at time 0
– Each finishes independently

• Syntax:
initial
begin
// behavioral statements
end
DSD 5
 Structured Procedures:
initial statement (cont’d)
Example:
module stimulus;
reg x, y, a, b, m;
initial
#50 $finish;
initial
endmodule
m= 1’b0;

initial
begin
#5 a=1’b1;
#25 b=1’b0;
end

initial
begin
#10 x=1’b0;
#25 y=1’b1;
end

DSD 6
 Initializing variables
• Ordinary style, using initial block
reg clock;
initial clock = 0;

• Combined declaration and initialization

reg clock = 0; // RHS must be constant

module adder (
output reg [7:0] sum = 0,
output reg co = 0,
input [7:0] a, b,
input ci);
...
endmodule

DSD 7
 Structured Procedures:
always statement
• Start at time 0
• Execute the statements in a looping fashion

module clkgen ( output reg clock);

Initial
clock = 1’b0;
Always
#10 clock = ~clock;
Initial
#1000 $finish;
...
endmodule

DSD 8
 Procedural Assignments
• Assignments inside initial and always
• To update values of “register, integer, real or
time” variables.
– The value remains unchanged until another
procedural assignment updates it

DSD 9
 Procedural Assignments (cont’d)
• Syntax
<lvalue> = <expression>

– <lvalue> can be
• reg, integer, real, time
• A bit-select of the above (e.g., addr[0])
• A part-select of the above (e.g., addr[31:16])
• A concatenation of any of the above
– <expression> is the same as introduced in dataflow modeling
– What happens if the widths do not match?
• LHS wider than RHS => RHS is zero-extended
• RHS wider than LHS => RHS is truncated (Least significant part is kept)

DSD 10
 Blocking Procedural Assignments
• The two types of procedural assignments
– Blocking assignments
– Non-blocking assignments
• Blocking assignments
– are executed in order (sequentially)
– Example:
reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count; All executed at time 0
initial begin
x=0; y=1; z=1;
count=0;
reg_a= 16’b0; reg_b = reg_a;
#15 reg_a[2] = 1’b1; executed at time 15
#10 reg_b[15:13] = {x, y, z};
count = count + 1;
end DSD
All executed at time 2511
 Non-Blocking Procedural Assignments
• Non-blocking assignments
– Processing of the next statements is not blocked for this one
– Transactions created sequentially (in order), but executed after all
blocking assignments in the corresponding simulation cycle
– Syntax:
<lvalue> <= <expression>
– Example:
reg x, y, z;
reg [15:0] reg_a, reg_b;
All executed at time 0
integer count;
initial begin
x=0; y=1; z=1;
count=0;
reg_a= 16’b0; reg_b = reg_a;
reg_a[2] <= #15 1’b1; Scheduled to run at time 15
reg_b[15:13] <= #10 {x, y, z};
count <= count + 1; Scheduled to run at time 10
end
Non-Blocking Assignments (cont’d)
• Application of non-blocking assignments
– Used to model concurrent data transfers
– Example: Write behavioral statements to swap values of two
variables

always @(posedge clock)

begin
reg1 <= #1 in1;
reg2 <= @(negedge clock) in2 ^ in3;
reg3 <= #1 reg1;
end The old value of reg1 is used

DSD 13
 Cont..
• When the final result of simulating two (or more)
concurrent processes depends on their order of execution
• Example:
always @(posedge clock)
b = a;
always @(posedge clock)
a = b;
• Solution:
always @(posedge clock)
always @(posedge clock) begin
b <= a; temp_b = b;
always @(posedge clock) temp_a = a;
b = temp_a;
a <= b; a = temp_b;
end

DSD 14
Conditional Statements
Multiway Branching
 Behavioral Modeling Statements:
Conditional Statements
• Just the same as if-else in C
• Syntax:
if (<expression>) true_statement;

if (<expression>) true_statement;
else false_statement;

if (<expression>) true_statement1;
else if (<expression>) true_statement2;
else if (<expression>) true_statement3;
else default_statement;

• True is 1 or non-zero
• False is 0 or ambiguous (x or z)
• More than one statement: begin end
 Behavioral Modeling Statements:
Multiway Branching
• Similar to switch-case statement in C

• Syntax:
case (<expression>)
alternative1: statement1;
alternative2: statement2;
...
default: default_statement; // optional
endcase

• Notes:
– <expression> is compared to the alternatives in the order
specified.
– Default statement is optional

2010 DSD 18
 Multiway Branching (cont’d)
• The case statements compare <expression> and alternatives bit-for-bit
– x and z values should match

module demultiplexer1_to_4(out0, out1, out2, out3, in, s1, s0);

output out0, out1, out2, out3;
input in, s1, s0;
always @(s1 or s0 or in)
case( {s1, s0} )
2’b00: begin ... end
2’b01: begin ... end
2’b10: begin ... end
2’b11: begin ... end
2’bx0, 2’bx1, 2’bxz, 2’bxx, 2’b0x, 2’b1x, 2’bzx:
begin ... end
2’bz0, 2’bz1, 2’bzz, 2’b0z, 2’b1z:
begin ... end
default: $display(“Unspecified control signals”);
endcase
endmodule

2010 DSD 19
 Multiway Branching (cont’d)
• casex and casez keywords
– casez treats all z values as “don’t care”
– casex treats all x and z values as “don’t care”

2010 DSD 20
Behavioral Modeling Statements: Loops
• Loops in Verilog
– while, for, repeat, forever
• The while loop syntax:
while (<expression>)
statement;

2010 DSD 21
 Loops (cont’d)
• The for loop
– Similar to C
– Syntax:
for( init_expr; cond_expr; change_expr)
statement;

2010 DSD 22
 Loops (cont’d)
• The repeat loop
– Syntax:
repeat( number_of_iterations )
statement;
– The number_of_iterations expression is evaluated only
when the loop is first encountered

integer count;
initial
begin
count = 0;
repeat(128) begin
$display("Count = %d", count);
count = count + 1;
end
end
2010 23
 Loops (cont’d)
• The forever loop
– Syntax:
forever
statement;

– Equivalent to while(1)
2010 DSD 24
 Timing Controls in
Behavioral Modeling
 Introduction
• No timing controls  No advance in simulation time

• Three methods of timing control

– delay-based
– event-based
– level-sensitive

2010 DSD 26
 Delay-based Timing Controls
• Delay  Duration between encountering and
executing a statement

• Delay symbol: #

• Delay specification syntax:

#5
#(1:2:3)

2010 DSD 27
 Delay-based Timing Controls (cont’d)
• Types of delay-based timing controls
1. Regular delay control
2. Intra-assignment delay control
3. Zero-delay control

2010 DSD 28
 Regular Delay Control
• Symbol: non-zero delay before a procedural assignment

2010 DSD 29
 Intra-assignment Delay Control
• Symbol: non-zero delay to the right of the
assignment operator

• Operation sequence:
1. Compute the RHS expression at current time.
2. Defer the assignment of the above computed
value to the LHS by the specified delay.

2010 DSD 30
 Intra-assignment Delay Control

02/18/17 Vijay Savani @ 2016

 Zero-Delay Control
• Symbol: #0

• Different initial/always blocks in the same simulation

time
– Execution order non-deterministic
• #0 ensures execution after all other statements
– Eliminates race conditions (only in simulation)

• Multiple zero-delay statements

– Non-deterministic execution order

2010 DSD 32
 Zero-Delay Control

2010 DSD 33
 Event-based Timing Control
• Event
– Change in the value of a register or net
– Used to trigger execution of a statement or block
(reactive behavior/reactivity)

• Types of Event-based timing control

1. Regular event control
2. Named event control
3. Event OR control

2010 DSD 34
 Regular Event Control
• Symbol: @(<event>)
• Events to specify:
– posedge sig
• Change of sig from any value to 1
or from 0 to any value
– negedge sig
• Change of sig from any value to 0
or from 1 to any value
– sig
• Any change in sig value

2010 DSD 35
 Named Event Control
• You can declare (name) an event, and then trigger
and recognize it.

• Keyword: event
event calc_finished;

• Verilog symbol for triggering: ->

->calc_finished
• Verilog symbol for recognizing: @()
@(calc_finished)
2010 DSD 36
 Named Event Control

2010 DSD 37
 Event OR control
• Used when need to trigger a block upon occurrence
of any of a set of events.
• The list of the events: sensitivity list
• Keyword: or

• Simpler syntax
– always @( reset, clock, d)
2010 DSD 38
 Event OR control
• Simpler syntax
– @* and @(*)

• OR

2010 DSD 39
 Level-sensitive Timing Control
• Level-sensitive vs. event-based
– event-based: wait for triggering of an event
(change in signal value)
– level-sensitive: wait for a certain condition (on
values/levels of signals)

• Keyword: wait()
always
wait(count_enable) #20 count=count+1;

2010 DSD 40
 Have you learned this topic?
• Race conditions
– Blocking vs. non-blocking assignments
– Zero delay control

• Timing control in behavioral statements

– Required to advance the simulation time
– Different types
• Delay-based
• Event-based
• Level-sensitive

2010 DSD 41
 Objectives of This Topic
• Some more constructs on Behavioral
Modeling
– Parallel blocks
– Nested blocks
– disable keyword

• Verilog® Scheduling Semantics

2011 DSD 42
 Blocks, Sequential blocks
• Used to group multiple statements
• Sequential blocks
– Keywords: begin end
– Statements are processed in order.
– A statement is executed only after its preceding
one completes.
• Exceptions: non-blocking assignments and
intra-assignment delays
– A delay or event is relative to the simulation time
when the previous statement completed
execution

2011 DSD 43
 Parallel Blocks

• Parallel Blocks
– Keywords: fork, join
– Statements in the blocks are executed concurrently
– Timing controls specify the order of execution of the
statements
– All delays are relative to the time the block was entered
• The written order of statements is not important
• The join is done when all the parallel statements are finished

2011 DSD 44
 Sequential vs. Parallel Blocks

initial
begin
x=1’b0;
#5 y=1’b1;
#10 z={x,y};
#20 w={y,x};
end

initial
fork
x=1’b0;
#5 y=1’b1;
#10 z={x,y};
#20 w={y,x};
join
2011 DSD 45
 Parallel Blocks and Race

• Parallel execution  Race conditions may arise

initial
fork
x=1’b0;
y=1’b1;
z={x,y};
w={y,x};
join

• z,w can take either 2’b01, 2’b10

or 2’bxx, 2’bxx or other combinations
depending on simulator

2011 DSD 46
 Special Features of Blocks
• Contents
– Nested blocks
– Named blocks
– Disabling named blocks

2011 DSD 47
 Nested Blocks
• Sequential and parallel blocks can be mixed

initial
begin
x=1’b0;
fork
#5 y=1’b1;
#10 z={x,y};
join
#20 w={y,x};
end

2011 DSD 48
 Named blocks
• Syntax:
begin: <the_name> fork: <the_name>
… …
end join
• Advantages:
– Can have local variables (local variables are static)
– Are part of the design hierarchy.
– Their local variables can be accessed using hierarchical
names
– Can be disabled

2011 DSD 49
 Disabling Named Blocks
• Keyword: disable
• Action:
– Similar to break in C/C++, but can disable any
named block not just the inner-most block.

2011 DSD 50
 Functions and Task

2010 DSD 51
 Introduction
• Procedures/Subroutines/Functions in SW
programming languages
– The same functionality, in different places
• Verilog equivalence:
– Tasks and Functions
– Used in behavioral modeling
– Task and functions can not have wires and contain
behavioral statements only.

2010 DSD 52
 Differences between...
• Functions • Tasks
– Can enable (call) just another – Can enable other tasks and functions
function (not task) – May execute in non-zero simulation
– Execute in 0 simulation time time
– No timing control statements – May contain any timing control
allowed statements
– At least one input – May have arbitrary input,
output, or inout
– Return only a single value
– Do not return any value
– Used when Verilog code is purely – Used for Verilog code that contains
combinational, execute in zero delays, timing, event constructs,
simulation times and provides event constructs or multiple output
exactly one output arguments

2010 DSD 53
 Functions
• Keyword: function, endfunction
• Can be used if the procedure
– does not have any timing control constructs
– returns exactly one single value
– has at least one input argument

2010 DSD 54
 Function Declaration Syntax

function <range_or_type> <func_name>;

input <input argument(s)> // at least one input
<variable_declaration(s)> // optional
begin // if more than one statement needed
<statements>
end // if begin used
endfunction

2010 DSD 55
 Function Examples: Parity Generator
Function that calculates the parity of a 32-bit address and returns the value

2010 DSD 56
 Function Semantics
– much like function in Pascal
– An internal implicit reg is declared inside the
function with the same name
– The return value is specified by setting that
implicit reg
– <range_or_type> defines width and type of
the implicit reg
• <type> can be integer or real
• default bit width is 1

2010 DSD 57
 Tasks
• Keywords: task, endtask
• Must be used if the procedure has
– any timing control constructs
– zero or more than one output arguments
– no input arguments

2010 DSD 58
 Task Declaration Syntax

task <task_name>;
<I/O declarations> // optional
<variable and event declarations>
begin // if more than one statement needed
<statement(s)>
end // if begin used!
endtask

2010 DSD 59
 Task Invocation Syntax

<task_name>;
<task_name> (<arguments>);

– input and inout arguments are passed into the

task
– output and inout arguments are passed back
to the invoking statement when task is completed

2010 DSD 60
I/O declaration in modules vs. tasks

– Both use keywords: input, output, inout

– In modules, represent ports
• connect to external signals
– In tasks, represent arguments
• pass values to and from the task

2010 DSD 61
 Task Examples

2010 DSD 62
 Other way to define task

2010 DSD 63
 Automatic Tasks and Functions
• Used for re-entrant code
– Task called from multiple locations
– Recursive function calls
• Keyword
– automatic
• Example
function automatic integer factorial;
task automatic bitwise_xor;

2010 DSD 64