Course Code: Course Title: Credit Structure (L-T-P-C) :: CS403 Computer Organization and Architecture 3-1-0-4

Course Code: CS403
Course Title:
Computer Organization and
Architecture
Credit Structure (L-T-P-C): 3-1-0-4
Dr. Sidheswar Routray

Associate Professor, CSE
Indrashil University
Saturday, May 4, 2024 1

Introduction to Computer System and its sub modules
• There are two basic types of electrical signals, namely, analog and digital. The
analog signals are continuous in nature and digital signals are discrete in nature.
• The electronic device that works with continuous signals is known as analog device
and the electronic device that works with discrete signals is known as digital device.
• We use ‘0’ to represent LOW and ‘1’ to represent HIGH.

Computer Architecture
• Computer architecture refers to those parameters of a computer system that are visible to a
programmer or those parameters that have a direct impact on the logical execution of a
program.
• Examples of architectural attributes include the instruction set, the number of bits used to
represent different data types, I/O mechanisms, and techniques for addressing memory.

Computer Organization
• Computer organization refers to the operational units and their interconnections that
realize the architectural specifications.
• Examples of organizational attributes include those hardware details transparent to the

programmer, such as control signals, interfaces between the computer and peripherals,
and the memory technology used.

The Von Neumann Architecture
Model for designing and building computers, based on the following three characteristics
1) The computer consists of four main sub-systems:
• Memory
• ALU (Arithmetic/Logic Unit)
• Control Unit
• Input/Output System (I/O)
2) Program is stored in memory during execution.
3) Program instructions are executed sequentially.

The Von Neumann Architecture

Arithmetic & Logical Unit
• Consider an ALU which can perform four arithmetic operations and four logical
operations To distinguish between arithmetic and logical operation, we may use a
signal line,
• 0 - in that signal, represents an arithmetic operation and
• 1 - in that signal, represents a logical operation.

Arithmetic & Logical Unit

Block Diagram of the ALU

Design of the ALU

Functions of the ALU

Buses
Three types of bus are used.
•Address bus - carries memory addresses from the processor to other components such
as primary storage and input/output devices.
•Data bus - carries the data between the processor and other components.
•Control bus - carries control signals from the processor to other components.

Buses

Basic Computer Model and different units of Computer
• Central Processor Unit,

• Input Unit,
• Output Unit,
• Memory Unit

Programming language
A program is a set of instructions that the computer executes.
1. Machine language
2. Assembly language
3. High level language

Machine level programming
• Machine language is the language written as stings of binary 1’s & 0’s. it is the only
language which a computer can understands without a translation program.
• A machine language instruction has two parts.
1. Operation code: Which tells the computer what function to perform
2. Operand: Which tells the computer on which the function is operating & storing (Register
or memory & so on)

Machine level programming
Disadvantages of Machine level programming
1. It is machine dependent i.e., it differs from computer to computer
2. It is difficult to program & write
3. It is prone to errors
4. It is difficult to modify

Assembly level programming
• It is a low level programming language that allows the user to write a program using
alphanumeric mnemonic codes, instead of numeric codes for a set of instructions.
• It requires a translator known as Assembler to convert assembly language into machine
language.
• It assembles the machine language program in the main memory of the computer and makes
it ready for execution.

Assembly level programming
Advantages of Assembly level programming

1. It is easy to understand and use
2. It is easy to locate and correct errors
3. It is easier to modify
Disadvantages Assembly level programming

1. It is machine dependent

High level programming
• It is machine independent language. It enables the user to write programs in a language

which resembles English words and familiar mathematical symbols.
• COBOL was the first high level language developed for business.
• Each statement in a high level language is a micro instruction which is translated into several
machine language instructions.
• A Compiler is a translator program which translates a high level programming language into
its equivalent machine language programs.

• Source code : It is the input or the programming instructor of a procedural language. The
compiler translates the source code into machine level language which is known as object
code. Object code can be saved and executed as and when desired by the user.
Source Code Language translator program Object code
High level language Machine level language

Linker : A program used with a compiler to provide links to the libraries needed for an
executable program. It takes one or more object code generated by a compiler and
combines them into a single executable program.
Interpreter : It is a translator used for translating high level language into the desired
output. It takes one statement, translates it into machine language instructions and
then immediately executes the result. Its output is the result of program execution.

Advantages of High level programming
1. It is machine independent
2. It is easier to learn & use.
3. It is easier to maintain and gives few errors.
Disadvantages of High level programming

1. It lowers efficiency
2. It is less flexible

Addressing modes
The most common addressing techniques are:

• Immediate
• Direct
• Indirect
• Register
• Register Indirect
• Displacement
• Stack

Addressing modes
To explain the addressing modes, the following notations are used:
A = contents of an address field in the instruction that refers to a memory

R = contents of an address field in the instruction that refers to a register
EA = actual (effective) address of the location containing the referenced operand
(X) = contents of location X

Immediate Addressing
• The simplest form of addressing is immediate addressing, in which the operand is

actually present in the instruction:
OPERAND = A
• The advantage of immediate addressing is that no memory reference other than the
instruction fetch is required to obtain the operand. The disadvantage is that the size
of the number is restricted to the size of the address field, which, in most instruction
sets, is small compared with the world length.

Immediate Addressing

Direct Addressing
• A very simple form of addressing is direct addressing, in which the address field
contains the effective address of the operand:
EA = A
• It requires only one memory reference and no special calculation.

Indirect Addressing
• In Direct Addressing, the length of the address field is usually less than the word
length, thus limiting the address range. One solution is to have the address field refer to
the address of a word in memory, which in turn contains a full-length address of the
operand. This is known as indirect addressing.
EA = (A)

Register Addressing
• Register addressing is similar to direct addressing. The only difference is that the
address field refers to a register rather than a main memory address.
EA = R
• The advantages of register addressing are that only a small address field is needed in
the instruction and no memory reference is required. The disadvantage of register
addressing is that the address space is very limited.

Register Addressing

Register Indirect Addressing
• Register indirect addressing is similar to indirect addressing, except that the address field
refers to a register instead of a memory location.
• It requires only one memory reference and no special calculation.
EA = (R)

Instruction Set
• The operation of a CPU is determine by the instruction it executes, referred to as machine

instructions or computer instructions. The collection of different instructions is referred as
the instruction set of the CPU.
• Each instruction must contain the information required by the CPU for execution.
• Opcodes are represented by abbreviations, called mnemonics, that indicate the operations

Instruction Set
The instruction set of a CPU can be categorized as follows:

• Data Processing
• Data Storage
• Data Movement
• Control
Types of Operands
•Addresses
•Numbers
•Characters
•Logical Data

Instruction Set
Types of Operations
1. Data Transfer
2. Arithmetic
3. Logical
4. Input Output [ I/O ]
5. System Control
6. Transfer Control

Data Transfer
• Move (Transfer) :Transfer word or block from source to destination

• Store: Transfer word from processor to memory
• Load (fetch): Transfer word from memory to processor
• Exchange: Swap contents of source and destination
• Clear (reset): Transfer word of 0s to destination
• Set: Transfer word of 1s to destination
• Push: Transfer word from source to top of stack
• Pop: Transfer word from top of stack to destination

Arithmetic
•Add: Compute sum of two operands

•Subtract: Compute difference of two operands
•Multiply: Compute product of two operands
•Divide: Compute quotient of two operands
•Absolute: Replace operand by its absolute value
•Negate: Change sign of operand
•Increment : Add 1 to operand
•Decrement: Subtract 1 from operand

Logical
• AND: Performs the logical operation AND bitwise
• OR: Performs the logical operation OR bitwise
• NOT: Performs the logical operation NOT bitwise
• Exclusive OR: Performs the specified logical operation Exclusive-OR bitwise
• Test: Test specified condition; set flag(s) based on outcome
• Compare: Make logical or arithmetic comparison Set flag(s) based on outcome
• Set Control Variables: Class of instructions to set controls for protection purposes, interrupt handling, timer
control etc.
• Shift: Left (right) shift operand, introducing constant at end
• Rotate: Left (right) shift operation, with wraparound end

Input/output
• Input (Read): Transfer data from specified I/O port or device to destination (e.g., main
memory or processor register)
• Output (Write): Transfer data from specified source to I/O port or device.
• Start I/O: Transfer instructions to I/O processor to initiate I/O operation.
• Test I/O: Transfer status information from I/O system to specified destination

System Control
• System control instructions are those which are used for system setting and it can be used
only in privileged state.
• Typically, these instructions are reserved for the use of operating systems.

Transfer of Control
The most common transfer-of-control operations found in instruction set are:

1. Branch
2. Skip
3. Procedure call.
BRP X: Branch to location X if result is positive
BRN X: Branch to location X if result is negative
BRZ X: Branch to location X is result is zero
BRO X: Branch to location X if overflow occurs

Instruction Format
1. Zero Address Instruction

Op-Code
2. One Address Instruction

Op-Code Address
3. Two Address Instruction

Op-Code Address-1 Address-2
4. Three Address Instruction

Op-Code Address-1 Address-2 Address-3

Register Transfer language
• A digital computer system exhibits an interconnection of digital modules
such as registers, decoders, arithmetic elements, and Control logic.
• These digital modules are interconnected with some common data and
control paths to form a complete digital system.
• Moreover, digital modules are best defined by the registers and the
operations that are performed on the data stored in them.
• The operations performed on the data stored in registers are
called Micro-operations.

The internal hardware organization of a digital system is best defined by
specifying:
• The set of registers and the flow of data between them.
• The sequence of micro-operations performed on the data which are
stored in the registers.
• The control paths that initiates the sequence of micro-operation

The Register Transfer Language is the symbolic representation of notations
used to specify the sequence of micro-operations.
In a computer system, data transfer takes place between processor registers
and memory and between processor registers and input-output systems. These
data transfer can be represented by standard notations given below:
• Notations R0, R1, R2..., and so on represent processor registers.
• The addresses of memory locations are represented by names such as LOC,
PLACE, MEM, etc.
• Input-output registers are represented by names such as DATA IN, DATA
OUT and so on.
• The content of register or memory location is denoted by placing square
brackets around the name of the register or memory location.

Registers are designated by capital letters, sometimes followed by numbers (e.g., A, R13, IR)
Often the names indicate function:
MAR - memory address register
PC - program counter
IR - instruction register
Registers and their contents can be viewed and represented in various ways
A register can be viewed as a single entity:
MAR
Registers may also be represented showing the bits of data they contain

Designation of a register
- a register
- portion of a register
- a bit of a register
Common ways of drawing the block diagram of a register
Register Showing individual bits

R1 7 6 5 4 3 2 1 0
15 0 15 8 7 0
R2 PC(H) PC(L)
Numbering of bits Subfields

Register Transfer
• The term Register Transfer refers to the availability of hardware logic circuits that can
perform a given micro-operation and transfer the result of the operation to the same or
another register.
• Most of the standard notations used for specifying operations on various registers are stated
below.
The memory address register is designated by MAR.
Program Counter PC holds the next instruction's address.
Instruction Register IR holds the instruction being executed.
R1 (Processor Register).
We can also indicate individual bits by placing them in parenthesis. For instance, PC (8-15),
R2 (5), etc.
Data Transfer from one register to another register is represented in symbolic form by means
of replacement operator. For instance, the following statement denotes a transfer of the data
of register R1 into register R2.
R2 R1

Register Transfer
• Typically, most of the users want the transfer to occur only in a predetermined
control condition. This can be shown by following if-then statement:
If (P=1) then (R2 ← R1); Here P is a control signal generated in the control
section.
• It is more convenient to specify a control function (P) by separating the
control variables from the register transfer operation. For instance, the
following statement defines the data transfer operation under a specific
control function (P).
P: R2 ← R1

Register Transfer
• The following image shows the block diagram that depicts the transfer of data
from R1 to R2
• Here, the letter 'n' indicates the number of bits for the register. The 'n' outputs of the register
R1 are connected to the 'n' inputs of register R2. A load input is activated by the control
variable 'P' which is transferred to the register R2.

Bus and Memory Transfers
• A digital system composed of many registers, and paths must be provided to

transfer information from one register to another.
• The number of wires connecting all of the registers will be excessive if
separate lines are used between each register and all other registers in the
system.
• A bus structure, on the other hand, is more efficient for transferring
information between registers in a multi-register configuration system.
• A bus consists of a set of common lines, one for each bit of register, through
which binary information is transferred one at a time.
• Control signals determine which register is selected by the bus during a
particular register transfer.

• The following block diagram shows a Bus system for four registers. It is
constructed with the help of four 4 * 1 Multiplexers each having four data
inputs (0 through 3) and two selection inputs (S1 and S2).
• We have used labels to make it more convenient for you to understand the
input-output configuration of a Bus system for four registers. For instance,
output 1 of register A is connected to input 0 of MUX1.


• The two selection lines S1 and S2 are connected to the selection inputs of all
four multiplexers. The selection lines choose the four bits of one register and
transfer them into the four-line common bus.
• When both of the select lines are at low logic, i.e. S1S0 = 00, the 0 data inputs
of all four multiplexers are selected and applied to the outputs that forms the
bus. This, in turn, causes the bus lines to receive the content of register A since
the outputs of this register are connected to the 0 data inputs of the
multiplexers.
• Similarly, when S1S0 = 01, register B is selected, and the bus lines will receive
the content provided by register B.
• The following function table shows the register that is selected by the bus for
each of the four possible binary values of the Selection lines.

• A bus system can also be constructed using three-state gates instead of multiplexers.
• The three state gates can be considered as a digital circuit that has three gates, two of which are signals
equivalent to logic 1 and 0 as in a conventional gate. However, the third gate exhibits a high-impedance
state.
• The most commonly used three state gates in case of the bus system is a buffer gate.
• The graphical symbol of a three-state buffer gate can be represented as:

• The following diagram demonstrates the construction of a bus system with three-state buffers.
• The outputs generated by the four buffers are

connected to form a single bus line.
• Only one buffer can be in active state at a given point
of time.
• The control inputs to the buffers determine which of
the four normal inputs will communicate with the bus
line.
• A 2 * 4 decoder ensures that no more than one
control input is active at any given point of time.

Memory Transfer
Most of the standard notations used for specifying operations on memory transfer are stated
below.
• The transfer of information from a memory unit to the user end is called a Read operation.
• The transfer of new information to be stored in the memory is called a Write operation.
• A memory word is designated by the letter M.
• We must specify the address of memory word while writing the memory transfer operations.
• The address register is designated by AR and the data register by DR.
• Thus, a read operation can be stated as:
Read: DR ← M [AR]
The Read statement causes a transfer of information into the data register
(DR) from the memory word (M) selected by the address register (AR).
And the corresponding write operation can be stated as:
Write: M [AR] ← R1
The Write statement causes a transfer of information from register R1 into the memory word (M) selected
by address register (AR).

Arithmetic Micro-operations
In general, the Arithmetic Micro-operations deals with the operations performed on numeric data stored in
the registers.
The basic Arithmetic Micro-operations are classified in the following categories:
• Addition
• Subtraction
• Increment
• Decrement
• Shift
Some additional Arithmetic Micro-operations are classified as:
• Add with carry
• Subtract with borrow
• Transfer/Load, etc.
The following table shows the symbolic representation of various Arithmetic Micro-operations.

Arithmetic Micro-operations
Symbolic Representation Description

R3 ← R1 + R2 The contents of R1 plus R2 are transferred to R3.
R3 ← R1 - R2 The contents of R1 minus R2 are transferred to R3.
R2 ← R2' Complement the contents of R2 (1's complement)
R2 ← R2' + 1 2's complement the contents of R2 (negate)
R3 ← R1 + R2' + 1 R1 plus the 2's complement of R2 (subtraction)
R1 ← R1 + 1 Increment the contents of R1 by one
R1 ← R1 - 1 Decrement the contents of R1 by one

Binary Adder
• The Add micro-operation requires registers that can hold the data and the digital components that
can perform the arithmetic addition.
• A Binary Adder is a digital circuit that performs the arithmetic sum of two binary numbers provided
with any length.
• A Binary Adder is constructed using full-adder circuits connected in series, with the output carry
from one full-adder connected to the input carry of the next full-adder.
• The following block diagram shows the interconnections of four full-adder circuits to provide a 4-bit
binary adder.

Binary Adder
• The augend bits (A) and the addend bits (B) are designated by subscript numbers from right to
left, with subscript '0' denoting the low-order bit.
• The carry inputs starts from C0 to C3 connected in a chain through the full-adders. C4 is the
resultant output carry generated by the last full-adder circuit.
• The output carry from each full-adder is connected to the input carry of the next-high-order full-
adder.
• The sum outputs (S0 to S3) generates the required arithmetic sum of augend and addend bits.
• The n data bits for the A and B inputs come from different source registers. For instance, data bits
for A input comes from source register R1 and data bits for B input comes from source register
R2.
• The arithmetic sum of the data inputs of A and B can be transferred to a third register or to one of
the source registers (R1 or R2).

Binary Adder-Subtractor
• The Subtraction micro-operation can be done easily by taking the 2's compliment of addend bits
and adding it to the augend bits.
• The Arithmetic micro-operations like addition and subtraction can be combined into one common
circuit by including an exclusive-OR gate with each full adder.
• The block diagram for a 4-bit adder-subtractor circuit can be represented as:

Binary Adder-Subtractor
• When the mode input (M) is at a low logic, i.e. '0', the circuit act as an adder and when the mode
input is at a high logic, i.e. '1', the circuit act as a subtractor.
• The exclusive-OR gate connected in series receives input M and one of the inputs B.
• When M is at a low logic, we have B⊕ 0 = B.
The full-adders receive the value of B, the input carry is 0, and the circuit performs A plus B.
• When M is at a high logic, we have B⊕ 1 = B' and C0 = 1.
The B inputs are complemented, and a 1 is added through the input carry. The circuit performs the
operation A plus the 2's complement of B.

Binary Incrementer
• The increment micro-operation adds one binary value to the value of binary variables stored in a
register. For instance, a 4-bit register has a binary value 0110, when incremented by one the value
becomes 0111.
• The increment micro-operation is best implemented by a 4-bit combinational circuit incrementer. A
4-bit combinational circuit incrementer can be represented by the following block diagram.

Binary Incrementer
• A logic-1 is applied to one of the inputs of least significant half-adder, and the other input is
connected to the least significant bit of the number to be incremented.
• The output carry from one half-adder is connected to one of the inputs of the next-higher-order
half-adder.
• The binary incrementer circuit receives the four bits from A0 through A3, adds one to it, and
generates the incremented output in S0 through S3.
• The output carry C4 will be 1 only after incrementing binary 1111.

Shift Micro- Operations
• Shift micro-operations are those micro-operations that are used for serial transfer of information. These are
also used in conjunction with arithmetic micro-operation, logic micro-operation, and other data-processing
operations.
There are three types of shifts micro-operations:
1. Logical :
It transfers the 0 zero through the serial input. We use the symbols shl for logical shift-left and shr for shift-
right.
Logical Shift Left –
In this shift one position moves each bit to the left one by one. The Empty least significant bit (LSB) is
filled with zero (i.e, the serial input), and the most significant bit (MSB) is rejected.

• Right Logical Shift –
In this one position moves each bit to the right one by one and the least significant bit(LSB) is rejected and
the empty MSB is filled with zero

2. Arithmetic :
This micro-operation shifts a signed binary number to the left or to the right position. In an arithmetic shift-left, it
multiplies a signed binary number by 2 and In an arithmetic shift-right, it divides the number by 2.
Left Arithmetic Shift –
In this one position moves each bit to the left one by one. The empty least significant bit (LSB) is filled with zero
and the most significant bit (MSB) is rejected. Same as the Left Logical Shift.

Right Arithmetic Shift –
In this one position moves each bit to the right one by one and the least significant bit is rejected and the empty
MSB is filled with the value of the previous MSB.

Circular :
The circular shift circulates the bits in the sequence of the register around the both ends without any loss of
information.
Left Circular Shift –

Right Circular Shift –

Arithmetic Logic Shift Unit
• Arithmetic Logic Shift Unit (ALSU) is a member of the Arithmetic Logic Unit (ALU) in a computer system.
• It is a digital circuit that performs logical, arithmetic, and shift operations.
• Rather than having individual registers calculating the micro operations directly, the computer deploys a
number of storage registers which is connected to a common operational unit known as an arithmetic
logic unit or ALU.
• Now, to implement the micro operation, the contents of specified registers are allocated in the inputs of
the common Arithmetic Logic Unit.
• The Arithmetic Logic Unit performs an operation that leads as a result and gets transferred to a
destination register.
• Arithmetic Logic Unit may be a combinatory circuit in order that the complete register transfer operation
from the supply registers through the ALU and into the destination register is performed throughout one
clock pulse amount.
• Sometimes, the shift micro operations are performed in a separate unit, but sometimes it is made as a
part of full ALU.

One stage of ALSU

• We can combine and make one ALU with common selection variables by adding arithmetic, logic, and
shift circuits.
• We can see the, One stage of an arithmetic logic shift unit in the diagram below. Some particular micro
operations are selected through the inputs S1 and S0.
• 4 x 1 multiplexer at the output chooses between associate arithmetic output between Ei and a logic output
in Hi.
• The data in the multiplexer are selected through inputs S3 and S2 and the other two data inputs to the
multiplexer obtain the inputs Ai – 1 for the shr operation and Ai + 1 for the shl operation.
• The circuit whose one stage is given in the below diagram provides 8 arithmetic operations, 4 logic
operations, and 2 shift operations, and Each operation is selected by the 5 variables S3, S2, S1, S0, and
Cin.
• The below table shows the 14 operations perform by the Arithmetic Logic Unit:
• The first 8 are arithmetic operations which are selected by S3 S2 = 00
• The next 4 are logic operations which are selected by S3 S2 = 01
• The last two are shift operations which are selected by S3 S2 = 10 & 11


CPU structure and functions
Central Processing Unit (CPU) consists of the following features −
• CPU is considered as the brain of the computer.
• CPU performs all types of data processing operations.
• It stores data, intermediate results, and instructions (program).
• It controls the operation of all parts of the computer.
CPU itself has following three components.

• Memory or Storage Unit
• Control Unit
• ALU(Arithmetic Logic Unit)

Memory or Storage Unit
• This unit can store instructions, data, and intermediate results. This unit
supplies information to other units of the computer when needed. It is also
known as internal storage unit or the main memory or the primary storage
or Random Access Memory (RAM).
• Its size affects speed, power, and capability. Primary memory and
secondary memory are two types of memories in the computer. Functions of
the memory unit are −
1. It stores all the data and the instructions required for processing.
2. It stores intermediate results of processing.
3. It stores the final results of processing before these results are released to
an output device.
4. All inputs and outputs are transmitted through the main memory.
Control Unit
This unit controls the operations of all parts of the computer but does not carry
out any actual data processing operations.
Functions of this unit are −
1. It is responsible for controlling the transfer of data and instructions among
other units of a computer.
2. It manages and coordinates all the units of the computer.
3. It obtains the instructions from the memory, interprets them, and directs the
operation of the computer.
4. It communicates with Input/Output devices for transfer of data or results
from storage.
5. It does not process or store data.

ALU (Arithmetic Logic Unit)
This unit consists of two subsections namely,
• Arithmetic Section
• Logic Section
Arithmetic Section
• Function of arithmetic section is to perform arithmetic operations like
addition, subtraction, multiplication, and division. All complex operations are
done by making repetitive use of the above operations.
Logic Section
• Function of logic section is to perform logic operations such as comparing,
selecting, matching, and merging of data.

Introduction of ALU and Data Path
• The ALU is a digital circuit that provides arithmetic and logic operations. It is the fundamental building
block of the central processing unit of a computer.
• A modern CPU has a very powerful ALU and it is complex in design. In addition to ALU modern CPU
contains a control unit and a set of registers.
• Most of the operations are performed by one or more ALU’s, which load data from the input register.
Registers are a small amount of storage available to the CPU.
• These registers can be accessed very fast. The control unit tells ALU what operation to perform on
the available data.
• After calculation/manipulation, the ALU stores the output in an output register.

• The CPU can be divided into two sections: the data section and the control section.
• The DATA section is also known as the data path.
• BUS:In early computers “BUS” were parallel electrical wires with multiple hardware connections.
• Therefore a bus is a communication system that transfers data between components inside a
computer, or between computers.
• It includes hardware components like wires, optical fibers, etc and software, including communication
protocols.
• The Registers, ALU, and the interconnecting BUS are collectively referred to as data paths.
Types of the bus are:
Address bus: The buses which are used to carry address.
Data bus: The buses which are used to carry data.
Control bus: If the bus is carrying control signals.
Power bus: If it is carrying clock pulse, power signals it is known as a power bus, and so on.

Program Counter –
• A program counter (PC) is a CPU register in the computer processor which has the address of the
next instruction to be executed from memory.
• As each instruction gets fetched, the program counter increases its stored value by 1. It is a digital
counter needed for faster execution of tasks as well as for tracking the current execution point.
Instruction Register –
• In computing, an instruction register (IR) is the part of a CPU’s control unit that holds the instruction
currently being executed or decoded.
• An instruction register is the part of a CPU’s control unit that holds the instruction currently being
executed or decoded. The instruction register specifically holds the instruction and provides it to the
instruction decoder circuit.
Memory Address Register –
• The Memory Address Register (MAR) is the CPU register that either store the memory address from
which data will be fetched from the CPU, or the address to which data will be sent and stored.
• It is a temporary storage component in the CPU(central processing unit) that temporarily stores the
address (location) of the data sent by the memory unit until the instruction for the particular data is
executed.

Memory Data Register –
• The memory data register (MDR) is the register in a computer’s processor, or central processing unit,
CPU, that stores the data being transferred to and from the immediate access storage. Memory data
register (MDR) is also known as memory buffer register (MBR).
General Purpose Register –
• General purpose registers are used to store temporary data within the microprocessor. It is a
multipurpose register. They can be used either by a programmer or by a user.

System bus structure
• A System bus is a set of wires for moving data, instructions, and control signals from one computer
component to another component.
• It is a high-speed internal connection between the processor and other components.
• There are 3 types of the system bus, or we can say components of a system bus.
• They are Address bus, Data bus, and Control bus.
• We can think bus as a highway on which data travels in a computer and within it.
• A bus can be 8 bit, 16 bit, 32 bit, and so on. A 32-bit bus means, it can transmit 32 bits of information
at a time. A bus can be internal or external.
Functions of system bus

• Different types of buses are used in the computer bus scheme. Depending on its purpose, each of
these buses is allocated to carry a certain form of signal and data.
Some basic functions carried out by system bus are:
• Addressing the issue
• Signals of Control
• Providing Components with Power
• Scheduling System Time
• Data Sharing

Data Bus
• A data bus is a computer subsystem that carries the data between the processor and other components.
• The data bus is bidirectional that allows for the transferring of data from one component to another
within a computer system or between two computers.
• This can include transferring data to and from the memory, or from the central processing unit
(CPU) to other components.
• Each one is designed to handle so many bits of data at a time. It is the main part of a system bus that
allows the actual transmission of data.
• A typical data bus is 32-bits wide. This means that up to 32 bits of data can travel through a data bus
every second.
• Newer computers are making data buses that can handle 64-bit and even 128-bit data paths.

Address Bus
• An address bus is a computer bus architecture that carries memory addresses from the
processor to other components such as primary storage to input/output devices.
• The address bus is unidirectional. It is used to transfer data between devices that are identified by the
hardware address of the physical memory (the physical address), which is stored in the form of binary
numbers to enable the data bus to access memory storage.
• The address bus is used by the CPU or direct memory access (DMA) enabled device to locate the
physical address to communicate read/write commands. All address busses are read and written by the
CPU or DMA in the form of bits.

Control Bus
• A control bus is a computer bus that is used to carries control signals from the processor to other
components. It also carries the clock’s pulses which are used by the CPU to communicate with devices
that are contained within the computer.
• In the computer system, the CPU transmits a variety of control signals to components and devices. This
occurs through physical connections such as cables or printed circuits.
• The control bus is bidirectional and is comprised of interrupt lines, byte enables lines, read/write
signals, and status lines.
• After data being processed, the control bus carries commands from the CPU and returns status signals
from the devices. For example, if the data is being read or written to the device, the appropriate line (read
or write) will be active (i.e. logic one).

Unit 2: Computer registers
Instruction Codes
• An instruction code is a group of bits that instruct the computer to

perform a specific operation.
• The operation code of an instruction is a group of bits that define
operations such as addition, subtraction, shift, complement, etc.
• An instruction must also include one or more operands, which indicate
the registers and/or memory addresses from which data is taken or to
which data is deposited.
• The instructions are stored in computer memory in the same manner
that data is stored.
• The control unit interprets these instructions and uses the operations
code to determine the sequences of microoperations that must be
performed to execute the instruction.

Stored Program Organization
• The operands are specified by indicating the registers and/or memory

locations in which they are stored.
• k bits can be used to specify which of 2k registers (or memory
locations) are to be used.
• The simplest design is to have one processor register (called the
accumulator) and two fields in the instruction, one for the opcode and
one for the operand.
• Any operation that does not need a memory operand frees the other
bits to be used for other purposes, such as specifying different
operations.

Common Bus System

Computer Instructions

Unit 3: Instruction set

Introduction of Assembler
• Assembler is a program for converting instructions written in low-level assembly
code into relocatable machine code and generating along information for the
loader.
• It is necessary to convert user written programs into a machinery code.
• This is called as translation of the high level language to low level that is
machinery language.
• This type of translation is performed with the help of system software.
• Assembler can be defined as a program that translates an assembly language
program into a machine language program.

Introduction of Assembler
• It generates instructions by evaluating the mnemonics (symbols) in operation field
and find the value of symbol and literals to produce machine code.
• Now, if assembler do all this work in one scan then it is called single pass
assembler, otherwise if it does in multiple scans then called multiple pass
assembler. Here assembler divide these tasks in two passes:

Pass-1:
Define symbols and literals and remember them in symbol table and
literal table respectively.
Keep track of location counter
Process pseudo-operations
Defines program that assigns the memory addresses to the variables and
translates the source code into machine code
Pass-2:
Generate object code by converting symbolic op-code into respective
numeric op-code
Generate data for literals and look for values of symbols
Defines program which reads the source code two times
It reads the source code and translates the code into object code.

Firstly, We will take a small assembly language program to understand the working in their
respective passes. Assembly language statement format:
[Label] [Opcode] [operand]
Example: M ADD R1, ='3'

where, M - Label; ADD - symbolic opcode;
R1 - symbolic register operand; (='3') - Literal
Assembly Program:
Label Op-code operand LC value(Location counter)
JOHN START 200
MOVER R1, ='3' 200
MOVEM R1, X 201
L1 MOVER R2, ='2' 202
LTORG 203
X DS 1 204
END 205

Let’s take a look on how this program is working:
START: This instruction starts the execution of program from location 200
and label with START provides name for the program.(JOHN is name for
program)
MOVER: It moves the content of literal(=’3′) into register operand R1.
MOVEM: It moves the content of register into memory operand(X).
MOVER: It again moves the content of literal(=’2′) into register operand R2
and its label is specified as L1.
LTORG: It assigns address to literals(current LC value).
DS(Data Space): It assigns a data space of 1 to Symbol X.
END: It finishes the program execution.

Unit 4: Memory system & I/O organization

Memory
1. Concept of Memory.
2. Cache Memory.
3. Memory Management
4. Virtual memory
The memory of computer is broadly categories into two categories:
• Internal Memory or Primary Memory
• External Memory or Secondary Memory

Main Memory
• The main memory acts as the central storage unit in a computer
system. It is a relatively large and fast memory which is used to store
programs and data during the run time operations.
• The primary technology used for the main memory is based on

semiconductor integrated circuits. The integrated circuits for the main
memory are classified into two major units.
• RAM (Random Access Memory) integrated circuit chips

• ROM (Read Only Memory) integrated circuit chips

Primary Memory
RAM:
• The RAM integrated circuit chips are further classified into two possible
operating modes, static and dynamic.
• The primary compositions of a static RAM are flip-flops that store the
binary information. The nature of the stored information is volatile, i.e. it
remains valid as long as power is applied to the system.
• The static RAM is easy to use and takes less time performing read and
write operations as compared to dynamic RAM.

Primary Memory
The dynamic RAM

• The dynamic RAM exhibits the binary information in the form of electric
charges that are applied to capacitors. The capacitors are integrated
inside the chip by MOS transistors.
• The dynamic RAM consumes less power and provides large storage
capacity in a single memory chip.

RAM Chip
• RAM chips are available in a variety of sizes and are used as per the system requirement. The
following block diagram demonstrates the chip interconnection in a 128 * 8 RAM chip.

RAM Chip
• A 128 * 8 RAM chip has a memory capacity of 128 words of eight bits
(one byte) per word. This requires a 7-bit address and an 8-bit
bidirectional data bus.
• The 8-bit bidirectional data bus allows the transfer of data either from
memory to CPU during a read operation or from CPU to memory during
a write operation.
• The read and write inputs specify the memory operation, and the two
chip select (CS) control inputs are for enabling the chip only when the
microprocessor selects it.
• The bidirectional data bus is constructed using three-state buffers.
• The output generated by three-state buffers can be placed in one of the
three possible states which include a signal equivalent to logic 1, a
signal equal to logic 0, or a high-impedance state.

RAM Chip
• From the functional table, we can conclude that the unit is in operation only when CS1 = 1
and CS2 = 0. The bar on top of the second select variable indicates that this input is enabled when it
is equal to 0.

ROM
• The primary component of the main memory is RAM integrated circuit

chips, but a portion of memory may be constructed with ROM chips.
• A ROM memory is used for keeping programs and data that are
permanently resident in the computer.
• Apart from the permanent storage of data, the ROM portion of main
memory is needed for storing an initial program called a bootstrap loader.
The primary function of the bootstrap loader program is to start the
computer software operating when power is turned on.
• ROM chips are also available in a variety of sizes and are also used as per
the system requirement. The following block diagram demonstrates the
chip interconnection in a 512 * 8 ROM chip.

ROM
• A ROM chip has a similar organization as a RAM chip. However, a ROM can only
perform read operation; the data bus can only operate in an output mode.
• The 9-bit address lines in the ROM chip specify any one of the 512 bytes stored in it.
• The value for chip select 1 and chip select 2 must be 1 and 0 for the unit to operate.
Otherwise, the data bus is said to be in a high-impedance state.

Main Memory Organization
• 16X4 Means 16 Locations & 4 bits in each Location
• Read – Retrieve data from memory to CPU registers

• Write – Store data to memory from CPU registers
• To transfer data we require data bus
• To specify or to identify a particular memory location we
require address bus

What is Semiconductor Memory?
• A type of electronic memory known as semiconductor memory stores

digital data by making use of semiconductor materials, most commonly
silicon. Data is stored in binary format in this memory, with “1s” and “0s”
representing electrical charges.
Types of Semiconductor Memory

There are two types of semi conductor memory
• Random Access Memory(RAM)
• Read-Only Memory(ROM)

RAM
• Random write and read operation for any cell

• Volatile data
• Most of computer memory
Type: Unpredictable – information evaporates
without power.
Function: stores data for active applications on a
temporary basis.
Speed: lightning-fast access in a flash.
Capacity: Normally more modest than ROM.
Applications: Running projects, open documents,
program tabs.

ROM
• Non-volatile Data
• Method of Data Writing
• Mask ROM
• Data written during chip fabrication
• PROM
• Fuse ROM: Non-rewritable
• EPROM: Erase data by UV rays
• EEPROM: Erase and write through
electrical means
• Speed 2-3 times slower than RAM
• Upper limit on write operations
• Flash Memory – High density, Low Cost

ROM
• MROM (Masked ROM)

• The very first ROMs were hard-wired devices that contained a pre-programmed set
of data or instructions. These kind of ROMs are known as masked ROMs, which are
inexpensive.
• PROM (Programmable Read Only Memory)

• PROM is read-only memory that can be modified only once by a user. The user buys a
blank PROM and enters the desired contents using a PROM program. Inside the
PROM chip, there are small fuses which are burnt open during programming. It can
be programmed only once and is not erasable.

ROM
• EPROM (Erasable and Programmable Read Only Memory)

• EPROM can be erased by exposing it to ultra-violet light for a duration of up to 40
minutes. Usually, an EPROM eraser achieves this function. During programming, an
electrical charge is trapped in an insulated gate region. The charge is retained for
more than 10 years because the charge has no leakage path. For erasing this charge,
ultra-violet light is passed through a quartz crystal window (lid). This exposure to
ultra-violet light dissipates the charge. During normal use, the quartz lid is sealed
with a sticker.
• EEPROM (Electrically Erasable and Programmable Read Only Memory)
• EEPROM is programmed and erased electrically. It can be erased and reprogrammed
about ten thousand times. Both erasing and programming take about 4 to 10 ms
(millisecond). In EEPROM, any location can be selectively erased and programmed.
EEPROMs can be erased one byte at a time, rather than erasing the entire chip.
Hence, the process of reprogramming is flexible but slow.
What is Flash Memory?
• Flash memory is secondary memory and so it is not volatile which means it

persists the data even if there is not an electrical supply provided.
• This flash memory works on the principle of EEPROM. EEPROM stands for
Electrical Erasable Programmable Read-Only Memory.
• ROM operation can only one time write and many times read and we can’t
erase it.
• But Flash Memory can be erased multiple times and update the data or
program integrated into it.
• So it gives flexibility to the updation of the program but ROM has no such type
of feature.

Features of Flash Memory
• Non-volatile: There is no loss of data when there is no electricity supply.

• Solid-state: It is SS technology so it is faster than HDD type storage.
• Fast access times: It supports solid-state technology so it has faster access
time.
• Large storage capacity: Flash memory devices can store large amounts of data,
from a few GB (Gigabytes) to several TB(Terabytes).
• Low power consumption: It is not based on header like HDD so no mechanical
components in flash memory so it uses less amount of electricity from read the
data.
• Flexibility towards Erase and write operations: Flash memory can be erased
electrically multiple times and read multiple times so flexibility towards
read/write operation is more in flash memory.

CPU and Memory
CPU can interact with main memory in two ways:

It can write a byte/word to a given memory location.
The previous bits that were in that location are destroyed
The new bits are saved for future use.
It can read a byte/word from a given memory location.
The CPU copies the bits stored at that location and stores them in a CPU register
The contents of the memory location are NOT changed.

Main Memory Characteristics
Very closely connected to the CPU.
Contents are quickly and easily changed.
Holds the programs and data that the processor is actively working with.
Interacts with the processor millions of times per second.
Nothing permanent is kept in main memory.

Auxiliary Memory
• An Auxiliary memory is known as the lowest-cost, highest-capacity and

slowest-access storage in a computer system. It is where programs and data
are kept for long-term storage or when not in immediate use. The most
common examples of auxiliary memories are magnetic tapes and magnetic
disks.
Magnetic Disks
• A magnetic disk is a type of memory constructed using a circular plate of metal
or plastic coated with magnetized materials. Usually, both sides of the disks
are used to carry out read/write operations. However, several disks may be
stacked on one spindle with read/write head available on each surface.

Auxiliary Memory
• The following image shows the structural representation for a magnetic disk.
• The memory bits are stored in the magnetized surface in spots along the
concentric circles called tracks.
• The concentric circles (tracks) are commonly divided into sections called
sectors.

Magnetic Tape
• Magnetic tape is a storage medium that allows data archiving, collection, and
backup for different kinds of data. The magnetic tape is constructed using a
plastic strip coated with a magnetic recording medium.
• The bits are recorded as magnetic spots on the tape along several tracks.
Usually, seven or nine bits are recorded simultaneously to form a character
together with a parity bit.
• Magnetic tape units can be halted, started to move forward or in reverse, or
can be rewound. However, they cannot be started or stopped fast enough
between individual characters. For this reason, information is recorded in
blocks referred to as records.

Associative Memory
• An associative memory can be considered as a memory unit whose stored
data can be identified for access by the content of the data itself rather than by
an address or memory location.
• Associative memory is often referred to as Content Addressable Memory
(CAM).
• When a write operation is performed on associative memory, no address or
memory location is given to the word. The memory itself is capable of finding
an empty unused location to store the word.
• On the other hand, when the word is to be read from an associative memory,
the content of the word, or part of the word, is specified. The words which
match the specified content are located by the memory and are marked for
reading.

The following diagram shows the block representation of an Associative memory.

• From the block diagram, we can say that an associative memory consists
of a memory array and logic for 'm' words with 'n' bits per word.
• The functional registers like the argument register A and key
register K each have n bits, one for each bit of a word. The match
register M consists of m bits, one for each memory word.
• The words which are kept in the memory are compared in parallel with
the content of the argument register.
• The key register (K) provides a mask for choosing a particular field or key
in the argument word. If the key register contains a binary value of all 1's,
then the entire argument is compared with each memory word.
Otherwise, only those bits in the argument that have 1's in their
corresponding position of the key register are compared. Thus, the key
provides a mask for identifying a piece of information which specifies how
the reference to memory is made.
• The following diagram can represent the relation between the memory
array and the external registers in an associative memory.
• The cells present inside the memory array are marked by the letter C with two subscripts. The first
subscript gives the word number and the second specifies the bit position in the word. For instance,
the cell Cij is the cell for bit j in word i.
• A bit Aj in the argument register is compared with all the bits in column j of the array provided that
Kj = 1. This process is done for all columns j = 1, 2, 3......, n.
• If a match occurs between all the unmasked bits of the argument and the bits in word i, the
corresponding bit Mi in the match register is set to 1. If one or more unmasked bits of the argument
and the word do not match, Mi is cleared to 0.
Secondary Storage Characteristics
Connected to main memory through a bus and a device controller.

Contents are easily changed, but access is very slow compared to main
memory.
Only occasionally interacts with CPU.
Used for long-term storage of programs and data.
Much larger than main memory (GBs vs. MBs).

• CPU --- Memory Hi Lo
• 16-bit CPU Byte Organized
15-8 7-0 Lower order byte
• Data Size Hi
first or little endian
CPU
Lo
Higher order byte

first or Big endian
Lo CPU
Hi
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The data transfer between main memory and the CPU takes place through two
CPU registers.
MAR : Memory Address Register
MDR : Memory Data Register.
If the MAR is k-bit long, then the total addressable memory location will be 2k.
If the MDR is n-bit long, then the n bit of data is transferred in one memory cycle.
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Binary Storage Cell
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Binary Storage Cell
• The binary cells are kind of storage cells that are capable of storing one binary
digit or binary character. They are used to store information in digital electronics.
• When a cell is read, it saves one bit of binary data, and before it can be accessed,
it must be set to store a 1 and then reset to a 0.

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Depending on the technology used to construct a RAM, there are two
types of RAM –
SRAM: Static Random Access Memory.
DRAM: Dynamic Random Access Memory
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DRAM
SRAM & DRAM both are volatile
DRAM packing density is more & Less expensive
DRAM requires supporting refresh circuitry
SRAM is faster than DRAM
• The storage element of the DRAM memory cell is the capacitor

labeled in the diagram above.
• The charge stored in the capacitor degrades over time, so its value
must be refreshed (read and rewritten) periodically.
• The nMOS transistor acts as a gate to allow reading or writing
when open or storing when closed.

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Memory Management
Five State Process Model

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Memory Management
1. Uni- Program Memory
2. Multi –Program Operating System
Uni-Program: User Program
• Memory split into two

1. For operating system
2. For currently executing program
Uni-Program

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Memory Management
Memory
Multi-Program:
Operating System
Memory split into multiple

User Program 1
1. For operating system
User Program 2
2. User part of memory is subdivided to
accommodate multiple processes. User Program 3
Multi-Program

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Partitioning
1) Fixed size partitions
2) Variable size partitions

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Paging
The memory is partitioned into equal fixed size chunks that are relatively
small. This chunk of memory is known as frames or page frames.
Each process is also divided into small fixed chunks of same size. The
chunks of a program is known as pages.
At a given point of time some of the frames in memory are in use and
some are free. The list of free frame is maintained by the operating system.

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Cache Memory
• It is the fact that CPU is a faster device and memory is a relatively slower device.
• Memory access is the main bottleneck for the performance efficiency. If a faster memory device can be
inserted between main memory and CPU, the efficiency can be increased.
• The faster memory that is inserted between CPU and Main Memory is termed as Cache memory.
• The data or contents of the main memory that are used frequently by CPU are stored in the cache
memory so that the processor can easily access that data in a shorter time. Whenever the CPU needs
to access memory, it first checks the cache memory. If the data is not found in cache memory, then the
CPU moves into the main memory.
• Cache memory is placed between the CPU and the main memory. The block diagram for a cache
memory can be represented as:

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Cache Mapping
• There are three different types of mapping used for
the purpose of cache memory which are as follows:
Direct mapping
Associative mapping
Set-Associative mapping

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Direct Mapping
• The simplest technique, known as direct mapping, maps
each block of main memory into only one possible cache
line. or In Direct mapping, assign each memory block to a
specific line in the cache.
• If a line is previously taken up by a memory block when a
new block needs to be loaded, the old block is trashed.
• An address space is split into two parts index field and a
tag field.
• The cache is used to store the tag field whereas the rest
is stored in the main memory.
• Direct mapping`s performance is directly proportional to
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Direct Mapping
• For purposes of cache access, each main memory address can be viewed
as consisting of three fields.
• The least significant w bits identify a unique word or byte within a block of
main memory.
• In most contemporary machines, the address is at the byte level.
• The remaining s bits specify one of the 2s blocks of main memory.
• The cache logic interprets these s bits as a tag of s-r bits (most significant
portion) and a line field of r bits.
• This latter field identifies one of the m=2r lines of the cache. Line offset is
index bits in the direct mapping.

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Associative Mapping
• In this type of mapping, the associative memory is used to store content and
addresses of the memory word.
• Any block can go into any line of the cache.
• This means that the word id bits are used to identify which word in the block
is needed, but the tag becomes all of the remaining bits.
• This enables the placement of any word at any place in the cache memory.
• It is considered to be the fastest and the most flexible mapping form. In
associative mapping the index bits are zero.

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Set-associative Mapping
• This form of mapping is an enhanced form of direct mapping where the
drawbacks of direct mapping are removed.
• Set associative addresses the problem of possible thrashing in the direct
mapping method.
• It does this by saying that instead of having exactly one line that a block can
map to in the cache, we will group a few lines together creating a set.
• Then a block in memory can map to any one of the lines of a specific set.
• Set-associative mapping allows that each word that is present in the cache
can have two or more words in the main memory for the same index
address.

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Set-associative Mapping
• Set associative cache mapping combines the best of direct and associative
cache mapping techniques.
• In set associative mapping the index bits are given by the set offset bits. In
this case, the cache consists of a number of sets, each of which consists of a
number of lines. The relationships are

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Direct Mapping
• A particular block of main
memory can be brought to a
particular block of cache
memory.
• It is not flexible

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Associative Mapping
• In this mapping function, any
block of Main memory can
potentially reside in any cache
block position.
• This is much more flexible
mapping method.

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Block Set Associative Mapping
• In this method, blocks
of cache are grouped
into sets, and the
mapping allows a block
of main memory to
reside in any block of a
specific set. From the
flexibility point of view,
it is in between to the
other two methods

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Virtual Memory
What is Virtual Memory?
• Virtual memory in COA is simply a technique used to provide an impression of presence of

large main memory to the programmer, when in actual it’s not present physically.
• The size of virtual memory is equivalent to the size of secondary memory. Each virtual address
or logical address referenced by the CPU is mapped to a physical address in main memory.
• A hardware device called Memory Management Unit (MMU) performs this mapping during run
time. To perform this activity MMU actually takes help of a memory map table, which is
maintained by the operating system.
• The set of all logical address generated by CPU or program is known as logical address
space. It is also called as virtual address space.
• The set of all physical addresses corresponding to the above logical addresses is known
as physical address space.

The virtual address space is used to develop a process. The special hardware unit , called
Memory Management Unit (MMU) translates virtual address to physical address. When
the desired data is in the main memory, the CPU can work with these data. If the data are
not in the main memory, the MMU causes the operating system to bring into the memory
from the disk.

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Advantages of Virtual memory
Listed below are major advantages of using virtual
memory techniques:
• Virtual memory technique helps in efficient utilization of main
memory. As larger size programs are divided into blocks and
partially each block is loaded into main memory as per need.
This makes simultaneous execution of multiple program
possible.
• Virtual memory helps in efficient CPU utilization
• Virtual memory helps to improve overall throughput.

VIRTUAL MEMORY
Relation between memory space and address in a virtual

memory system
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Memory table for mapping a virtual address

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Address space and memory space split into groups of lK words.
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Memory Table in a paged system

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An associative memory page table.
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Input / Output
The computer system's input/output (I/O) architecture is its interface to the
outside world.
The two important modules of the computer system -
1. The processor and
2. The memory module.
The third key component of a computer system is a set of I/O modules
Each I/O module interfaces to the system bus and controls one or more
peripheral devices.
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Input / Output
There are several reasons why an I/O device or peripheral device is not
directly connected to the system bus?
1. There are a wide variety of peripherals with various methods of operation.
2. The data transfer rate of peripherals is often much slower than that of the
memory or processor.
3. Peripherals often use different data formats and word lengths than the
computer to which they are attached

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Input/output Modules
The major functions of an I/O module are categorized as follows –
1. Control and timing
2. Processor Communication
3. Device Communication
4. Data Buffering
5. Error Detection

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1. Control & timings

•The I/O function includes a control and timing requirement to co-ordinate
the flow of traffic between internal resources and external devices.

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The control of the transfer of data from an external device to the processor might
involve the following sequence of steps –
1. The processor interacts with the I/O module to check the status of the attached
device.
2. The I/O module returns the device status.
3. If the device is operational and ready to transmit, the processor requests the
transfer of data, by means of a command to the I/O module.
4. The I/O module obtains a unit of data from external device.
5. The data are transferred from the I/O module to the processor.
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2. Processor & Device Communication
During the I/O operation, the I/O module must communicate with the
processor and with the external device
Processor communication involves the following:
Command decoding
Data
Status Reporting
Address Recognition
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Processor communication involves the following:
1. Command decoding :The I/O module accepts command from the
processor, typically sent as signals on control bus.
2. Data :Data are exchanged between the processor and the I/O module
over the data bus.

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3. Status Reporting :Because peripherals are so slow, it is important to
know the status of the I/O module. For example, if an I/O module is
asked to send data to the processor(read), it may not be ready to do so
because it is still working on the previous I/O command. This fact can
be reported with a status signal. Common status signals
are BUSY and READY.
4. Address Recognition :Just as each word of memory has an address,
so thus each of the I/O devices. Thus an I/O module must recognize
one unique
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May 4, 2024 for each178peripheral it controls. 178
3. Device communication: On the other hand, the I/O must be able to perform
device communication. This communication involves command, status information
and data.
4. Data Buffering
An essential task of an I/O module is data buffering
The data buffering is required due to the mismatch of the speed of CPU, memory and
other peripheral devices.
So, the I/O modules store the data in a data buffer and regulate the transfer of data as
per the speed of the devices.
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5. Error Detection
Another task of I/O module is error detection and for subsequently
reporting error to the processor.
One class or error includes mechanical and electrical malfunctions
reported by the device (e.g. paper jam).
Another class consists of unintentional changes to the bit pattern as it is
transmitted from devices to the I/O module.
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Block diagram of I/O Module
1. Control & timings

•The I/O function includes a control and timing requirement to co-ordinate
the flow of traffic between internal resources and external devices.

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Example of I/O interface unit.

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Example of I/O interface unit.

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I/O Controller
Control/Status Registers
CPU tells device what to do --- write to control register
CPU checks whether task is done --- read status register
Data registers
CPU transfers data to/from device
Device electronics
Performs actual operation

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Input / Output Subsystem
There are three ways that computer buses can be used to communicate
with memory and I/O:
1. Use two separate buses, one for memory and the other for I/O.
2. Use one common bus for both memory and I/O but have separate
control lines for each.
3. Use one common bus for memory and I/O with common control lines.

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I/O Operations
Two types of addressing are possible
Memory-mapped I/O
Isolated or I/O mapped I/O

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Memory-mapped I/O
• There is a single address space for memory locations and I/O devices
• The processor treats the status and address register of the I/O
modules as memory location and the same machine instructions are
used to access both memory and I/O devices.
• For example, if the size of address bus of a processor is 16, then there
are 216 combinations and all together 216 address locations can be
addressed with these 16 address lines.

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Memory-mapped I/O
• Since I/O devices are included in the same memory address space, so
the status and address registers of I/O modules are treated as memory
location by the processor.
• Therefore, the same machine instructions are used to access both

memory and I/O devices.

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Isolated or I/O -mapped I/O
• In this scheme, the full range of addresses may be available for both.
• The address refers to a memory location or an I/O device is specified
with the help of a command line.
• In general command line is used to identify a memory location or an
I/O device.

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Isolated or I/O -mapped I/O
• If = 1, it indicates that the address present in address bus is the

address of an I/O device.
• If = 0, it indicates that the address present in address bus is the
address of a memory location.
• Since full range of address is available for both memory and I/O
devices, so, with 16 address lines, the system may now support both
216 memory locations and 216 I/O addresses.
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Differences between Memory Mapped I/O & I/O
Mapped I/O
S.No. Memory Mapped I/O I/O Mapped I/O
1 I/O device is treated like a memory device and hence I/O device is treated as an I/O device and hence given
given a memory address. an I/O address.
2 Both have same address space Memory and I/O have separate address space
3 Due to addition of I/O addressable memory become All address can be used by the memory
less for memory
4 Same instructions can control both I/O and Memory Separate instruction control read and write operation
in I/O and Memory
5 Normal memory address are for both In this I/O address are called ports.
6 Lesser efficient More efficient due to separate buses

7 Smaller in size Larger in size due to more buses
8 Simpler logic is used as I/O is also treated as It is complex due to separate separate logic is used to
memory only. control both.

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Direct Memory Access (DMA)
• DMA Controller is a hardware device that allows I/O devices to directly
access memory with less participation of the processor.
• DMA controller needs the same old circuits of an interface to communicate
with the CPU and Input/Output devices.
• Figure-1 below shows the block diagram of the DMA controller.
• The unit communicates with the CPU through data bus and control lines.
• Through the use of the address bus and allowing the DMA and RS register
to select inputs, the register within the DMA is chosen by the CPU.
• RD and WR are two-way inputs.
• When BG (bus grant) input is 0, the CPU can communicate with DMA
registers. When BG (bus grant) input is 1, the CPU has relinquished the
buses and DMA can communicate directly with the memory.

Direct Memory Access (DMA) contd.

DMA controller registers
The DMA controller has three registers as follows.
• Address register – It contains the address to specify the desired location in memory.
• Word count register – It contains the number of words to be transferred.
• Control register – It specifies the transfer mode.
Explanation:
• The CPU initializes the DMA by sending the given information through the data bus.
• The starting address of the memory block where the data is available (to read) or where
data are to be stored (to write).
• It also sends word count which is the number of words in the memory block to be read or
write.
• Control to define the mode of transfer such as read or write.
• A control to begin the DMA transfer.

Data Transfer
1. Synchronous : All devices derive the timing information from common clock line.
2. Asynchronous: No common clock
Require control signals
1. Strobe Pulse
2. Handshaking

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Asynchronous Data Transfer
• The internal operations in an individual unit of a digital system are synchronized using clock
pulse. It means clock pulse is given to all registers within a unit.
• And all data transfer among internal registers occurs simultaneously during the occurrence
of the clock pulse.
• Now, suppose any two units of a digital system are designed independently, such as CPU
and I/O interface.
• If the registers in the I/O interface share a common clock with CPU registers, then transfer
between the two units is said to be synchronous.
• But in most cases, the internal timing in each unit is independent of each other, so each
uses its private clock for its internal registers.
• In this case, the two units are said to be asynchronous to each other, and if data transfer
occurs between them, this data transfer is called Asynchronous Data Transfer.

• But, the Asynchronous Data Transfer between two independent units requires that control signals be
transmitted between the communicating units so that the time can be indicated at which they send
data. These two methods can achieve this asynchronous way of data transfer:
Strobe control: A strobe pulse is supplied by one unit to indicate to the other unit when the transfer
has to occur.
Handshaking: This method is commonly used to accompany each data item being transferred with a
control signal that indicates data in the bus. The unit receiving the data item responds with another
signal to acknowledge receipt of the data.
• The strobe pulse and handshaking method of asynchronous data transfer is not restricted to I/O
transfer. They are used extensively on numerous occasions requiring the transfer of data between
two independent units. So, here we consider the transmitting unit as a source and receiving unit as a
destination.
• For example, the CPU is the source during output or write transfer and the destination unit during
input or read transfer.
• Therefore, the control sequence during an asynchronous transfer depends on whether the transfer is
initiated by the source or by the destination.
• So, while discussing each data transfer method asynchronously, you can see the control sequence
in both terms when it is initiated by source or by destination. In this way, each data transfer method
can be further divided into parts, source initiated and destination initiated.

Asynchronous Data Transfer Methods
The asynchronous data transfer between two independent units requires that control signals be
transmitted between the communicating units to indicate when they send the data. Thus, the two methods
can achieve the asynchronous way of data transfer.
1. Strobe Control Method

The Strobe Control method of asynchronous data transfer employs a single control line to time each
transfer. This control line is also known as a strobe, and it may be achieved either by source or
destination, depending on which initiate the transfer.
Source initiated strobe: In the below block diagram, you can see that strobe is initiated by source, and
as shown in the timing diagram, the source unit first places the data on the data bus.

• After a brief delay to ensure that the data resolve to a stable value, the source activates a strobe pulse.
The information on the data bus and strobe control signal remains in the active state for a sufficient time
to allow the destination unit to receive the data.
• The destination unit uses a falling edge of strobe control to transfer the contents of a data bus to one of
its internal registers. The source removes the data from the data bus after it disables its strobe pulse.
• Thus, new valid data will be available only after the strobe is enabled again. In this case, the strobe may
be a memory-write control signal from the CPU to a memory unit. The CPU places the word on the data
bus and informs the memory unit, which is the destination.
Destination initiated strobe: In the below block diagram, you see that the strobe initiated by destination,
and in the timing diagram, the destination unit first activates the strobe pulse, informing the source to provide
the data.

• The source unit responds by placing the requested binary information on the data bus. The data must
be valid and remain on the bus long enough for the destination unit to accept it.
The falling edge of the strobe pulse can use again to trigger a destination register. The destination unit
then disables the strobe. Finally, and source removes the data from the data bus after a determined
time interval.
• In this case, the strobe may be a memory read control from the CPU to a memory unit. The CPU
initiates the read operation to inform the memory, which is a source unit, to place the selected word into
the data bus.

Strobe Control

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Handshaking
Source initiated transfer using handshake
Block Diagram
Timing Diagram
Sequence of events

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Handshaking
Destination initiated transfer using handshake
Block Diagram
Timing Diagram
Sequence of events

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Asynchronous data transmission
A transmitted character can be detected by the receiver from knowledge
of the transmission rules:
1. When a character is not being sent, the line is kept in the 1-state.
2. The initiation of a character transmission is detected from the start bit,
which is always 0.
3. The character bits always follow the start bit.
4. After the last bit of the character is transmitted, a stop bit is detected
when the line returns to the 1-state for at least one bit time.
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Asynchronous data transmission

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Asynchronous Communication Interface

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Asynchronous Communication Interface

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There are three basic forms of input and output systems
Programmed I/O
Interrupt driven I/O
Direct Memory Access(DMA)

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Programmed I/O: With programmed I/O, the processor executes a
program that gives its direct control of the I/O operation, including sensing
device status, sending a read or write command, and transferring the
data.
Interrupt driven I/O: With interrupt driven I/O, the processor issues an
I/O command, continues to execute other instructions, and is interrupted
by the I/O module when the I/O module completes its work.
DMA: In Direct Memory Access (DMA), the I/O module and main memory
exchange dataMaydirectly
2024 4, 2024 without processor
210 involvement. 210
I/O Commands
There are four types of I/O commands that an I/O module will receive
when it is addressed by a processor
Control : Used to activate a peripheral device and instruct it what to do.
These commands are specific to a particular type of peripheral
device.
Test : Used to test various status conditions associated with an I/O
module and its peripherals. The processor will want to know if the most
recent I/O operation is completed, or any error has occurred.
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I/O Commands
Read : Causes the I/O module to obtain an item of data from the
peripheral and place it in the internal buffer.
Write : Causes the I/O module to take an item of data ( byte or word )
from the data bus and subsequently transmit the data item to the
peripheral.

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Programmed I/O
With programmed I/O, the processor

executes a program that gives its
direct control of the I/O operation,
including sensing device status,
sending a read or write command,
and transferring the data.

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Example

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Example
The transfer of each byte requires three
instructions:
1. Read the status register.
2. Check the status of the flag bit and branch
to step 1 if not set or to step 3 if set.
3. Read the data register.
Flow chart for CPU program to input data

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Interrupt driven I/O
With interrupt driven I/O, the processor issues an

I/O command, continues to execute other
instructions, and is interrupted by the I/O module
when the I/O module completes its work.

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Unit 5: Pipelining & Multiprocessors

Introduction to pipelining
• Pipelining is a technique of decomposing a sequential process into
sub-operations, with each sub-process being executed in a special
dedicated segment that operates concurrently with all other
segments.
Conventional Sequential Execution
Pipelined Execution

Introduction to pipelining: (Cont’d…..)
Example of pipelining

Decomposition of the instruction execution:
• Fetch Instruction (FI)
• Decode Instruction (DI)
• Calculate Operand (CO)
• Fetch Operands(FO)
• Execute Instruction (EI)
• Write Operand(WO)
Timing Diagram for Instruction Pipeline Operation

Four Stage Pipeline
F: Fetch, Read the instruction from the memory
D: Decode, decode the instruction and fetch the source operand (S)
O: Operate, perform the operation
W: Write, store the result in the destination location.
Timing diagram for 4- stage instruction pipeline

Instruction Execution in a Four Stage Pipeline
Flow-chart

Design Issues of Pipeline
The cycle time of an instruction pipeline is the time needed to advance
a set of instructions one stage through the pipeline. The cycle time can
be determined as:
Where,

Design Issues of Pipeline: (Cont’d….)
• Let Tk,n be the total time required for a pipeline with k stages to
execute n instructions. Then,
• A total of k cycles are required to complete the execution of the first

instruction, and the remaining n-1 instructions require n-1 cycles.
• consider a processor with equivalent functions but no pipeline, and

assume that the instruction cycle time is

Design Issues of Pipeline: (Cont’d….)
• The speedup factor for the instruction pipeline compared to execution
without the pipeline is defined as

Introduction to Parallel processing
• Parallel processing may occur in the instruction stream, in the data
stream, or in both. Flynn's classification divides computers into four
major groups as follows:
1. Single instruction stream, single data stream (SISD)
2. Single instruction stream, multiple data stream (SIMD)
3. Multiple instruction stream, single data stream (MISD)
4. Multiple instruction stream, multiple data stream (MIMD)
Introduction to Parallel processing (Cont’d….)
• Single Instruction Stream, Single data stream(SISD)-A computer architecture in which a single uni-core processor
executes a single instruction stream, to operate on data stored in a single memory.
• Single Instruction, Multiple Data (SIMD) system: A single machine instruction controls the simultaneous execution
of a number of processing elements on a lockstep basis. Each processing element has an associated data memory,
so that each instruction is executed on a different set of data by the different processors. Vector and array
processors fall into this category
• Multiple Instruction, Single Data (MISD) system :A sequence of data is transmitted to a set of processors, each
of which executes a different instruction sequence. This structure has never been implemented.
• Multiple Instruction, Multiple Data (MIMD) system: A set of processors simultaneously execute different
instruction sequences on different data sets. SMPs, clusters, and NUMA systems fits into this category.

Attached Array Processor
• An attached array processor is an auxiliary processor attached to a
general-purpose computer. It is intended to improve the performance
of the host computer in specific task.
Attached array processor with host computer

SIMD array processor
• An Single Input Multi Data (SIMD) array processor is a computer with
multiple processing units operating in parallel.
SIMD array processor organization

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Course Code: CS403

Dr. Sidheswar Routray

Saturday, May 4, 2024 1

• We use ‘0’ to represent LOW and ‘1’ to represent HIGH.

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• Examples of organizational attributes include those hardware details transparent to the

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• Central Processor Unit,

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A program is a set of instructions that the computer executes.

3. High level language

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Disadvantages of Machine level programming

1. It is machine dependent i.e., it differs from computer to computer

2. It is difficult to program & write

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Advantages of Assembly level programming

Disadvantages Assembly level programming

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• It is machine independent language. It enables the user to write programs in a language

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Source Code Language translator program Object code

High level language Machine level language

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Disadvantages of High level programming

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The most common addressing techniques are:

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To explain the addressing modes, the following notations are used:

A = contents of an address field in the instruction that refers to a memory

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• The simplest form of addressing is immediate addressing, in which the operand is

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• The operation of a CPU is determine by the instruction it executes, referred to as machine

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The instruction set of a CPU can be categorized as follows:

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• Move (Transfer) :Transfer word or block from source to destination

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