Module3 PartC DataPath

DataPath
Module 3- Part C
1
Introduction
• Movement of data within a processor from one component to
another
• Registers, ALU, and the interconnecting bus collectively form the
datapath
• ALU
• Performs arithmetic and logical operations
• Contains control lines to select one of the possible ALU
operations
• Registers
• General purpose registers to store data, memory address
register (MAR), memory data register (MDR), program
counter (PC), instruction register (IR), temporary
registers (optional)
• Buses
• Internal (one or more) and external to carry the data
from one component to another
2
Single Bus
Organizatio
n of
Datapath
3
Basic Steps in Instruction
Execution
• Fetch the contents of the memory location pointed to by the
PC. Load these contents into the IR to be interpreted.
IR  [PC]
• Assuming that the memory is byte addressable, increment

the contents of the PC by 4.
PC  PC + 4
• Carry out the actions specified by the instruction.
4
Basic Steps in Instruction
Execution
• Most instructions involve the following
operations:
• Transfer a word of data from one processor
register to another or the ALU
• Perform an arithmetic or logical operation
and store the result in a processor register
• Fetch the contents of a memory location and
load them into a processor register
• Store a word of data from a processor
register into a memory location
5
Register Transfer
MOV R1, R4
• Enable the output of 𝑹𝟏 by

setting 𝑹𝟏𝒐𝒖𝒕 to 1. This
places the contents of 𝑹𝟏
on the processor bus.
• Enable the input of the
register 𝑹𝟒 b setting 𝑹𝟒𝒊𝒏
to 1. This loads data from
the processor bus into
register 𝑹𝟒.
6
Arithmetic and Logic
Operations
ADD R1, R2,
R3
• 𝑅1𝑜𝑢𝑡 , 𝑌𝑖𝑛
• 𝑅2𝑜𝑢𝑡 , 𝑆𝑒𝑙𝑒𝑐𝑡𝑌, 𝐴𝑑𝑑, 𝑍𝑖𝑛
• 𝑍𝑜𝑢𝑡 , 𝑅3𝑖𝑛
7
Memory Read and Write
first line paakatha
2nd line vachu
• Memory Read MOV R2 , [ R1 ] third line decide or
3rd vachu 2nd decide
MOV (R1),
R2
• 𝑅1𝑜𝑢𝑡 , 𝑀𝐴𝑅𝑖𝑛 , 𝑅𝑒𝑎𝑑
• 𝑀𝐷𝑅𝑖𝑛𝐸 , 𝑊𝑀𝐹𝐶
• 𝑀𝐷𝑅𝑜𝑢𝑡 , 𝑅2𝑖𝑛
• Memory Write
MOV [R1],R2 MOV R2,
(R1)
• 𝑅1𝑜𝑢𝑡 , 𝑀𝐴𝑅𝑖𝑛
• 𝑅2𝑜𝑢𝑡 , 𝑀𝐷𝑅𝑖𝑛 , 𝑊𝑟𝑖𝑡𝑒
• 𝑀𝐷𝑅𝑜𝑢𝑡𝐸 , 𝑊𝑀𝐹𝐶
8
Execution of a Complete
Instruction
ADD (R3),
R1
9
Multi Cycle Data Path
Architecture
10
Why Multi Cycle Data Path ?
• In a single cycle data path architecture , exclusively single data

word could be moved through the bus in a given clock cycle
• Because of this no of steps needed to execute the inst increases
• To decrease the no of steps needed to execute the inst and to

transfer more than one word in a clock cycle we go for multicycle
11
How Multi Cycle Data Path
Works
• Three buses are used to link reg and ALU of the CPU
• All GPR ,
R1, R2…Rn are presented in one block known as reg files
• Figure 2. shows the register files has three ports
12
Figure 2.
Multi Cycle
Data Path
Architecture
13
Works
• One input and two output ports
• Therefore data of three registers are possible to access in single

clk cycle
• Through Bus C, the value could be put in one reg
• Data from two regs is available through Bus A and Bus B
14
Works
• Bus A and B are used to move the source operands to i/ps of the
ALU A and B
• After ALU process is executed the resultant is moved to

destination operand through the bus C
• Separate incremental unit is provided to increment the value of

PC after every instruction is executed
15
Execution of Instruction using Multi
Cycle Data Path Add R1, R2, R3 Control
Sequence
• The inst adds the values of register R2 & R3 and stores the
resultant in R1
16
Add R1, R2, R3 Control
Sequence Explanation
• Step 1: The value of the PC are moved to MAR by means of
Bus B to begin Read operation. PCMAR
• Parallelly PC is incremented point towards the next

instruction PCPC+1
17
Multi Cycle Data Path Add R1, R2,
R3 Control Sequence Explanation
• Step 2: The processor waits for WMFC signal from the memory
• Step 3: The inst code is moved from MDR to IR MDR IR
• Step 4: The inst decoder decodes the IR contents
18
Add R1, R2, R3 Control
Sequence Explanation
• Step 4: Two values from reg R2 & R3 are made accessible at
inputs A and B of ALU by means of Bus A & B
• By activating the Add signal two inputs are added
• Through Bus C the resultant is stored in R1
19

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DataPath

• Assuming that the memory is byte addressable, increment

• Carry out the actions specified by the instruction.

• Enable the output of 𝑹𝟏 by

• In a single cycle data path architecture , exclusively single data

• Because of this no of steps needed to execute the inst increases

• To decrease the no of steps needed to execute the inst and to

• Figure 2. shows the register files has three ports

• Therefore data of three registers are possible to access in single

• Through Bus C, the value could be put in one reg

• Data from two regs is available through Bus A and Bus B

• After ALU process is executed the resultant is moved to

• Separate incremental unit is provided to increment the value of

• Parallelly PC is incremented point towards the next

• Step 3: The inst code is moved from MDR to IR MDR IR

• Step 4: The inst decoder decodes the IR contents

• By activating the Add signal two inputs are added

• Through Bus C the resultant is stored in R1

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