Semiconductor Manufacturing Technology

Semiconductor
Manufacturing Technology
Michael
Michael Quirk
Quirk &
& Julian
Julian Serda
Serda
©
© October
October 2001
2001 by
by Prentice
Prentice Hall
Hall
Chapter 1
Introduction to the
Semiconductor Industry
Semiconductor Manufacturing Technology © 2001by Prentice Hall

by Michael Quirk and Julian Serda
Microprocessor Chips Vacuum Tubes
Photo courtesy of
Advanced Micro Devices
Semiconductor Manufacturing Technology Photo 1.1 © 2001by Prentice Hall

The Semiconductor Industry
INFRASTRUCTURE PRODUCT
APPLICATIONS
Industry Standards
(SIA, SEMI, NIST, etc.)
Consumers:
Production Tools • Computers
• Automotive
Utilities • Aerospace
Materials & Chemicals Chip • Medical
Manufacturer • other industries
Metrology Tools Customer Service
Analytical Laboratories Original Equipment Manufacturers
Technical Workforce Printed Circuit Board Industry
Colleges & Universities
Semiconductor Manufacturing Technology Figure 1.1 © 2001by Prentice Hall

The First Transistor The First Planar
from Bell Labs Transistor
Photo courtesy of Lucent Technologies Bell Labs Innovations

Jack Kilby’s First Integrated Circuit
Photo courtesy of Texas Instruments, Inc.

Top View of Wafer with Chips
A single integrated
circuit, also known as a
die, chip, and microchip

Circuit Integration of Semiconductors
Number of
Semiconductor
Circuit Integration Components per
Industry Time Period
Chip
No integration (discrete components) Prior to 1960 1
Small scale integration (SSI) Early 1960s 2 to 50
Medium scale integration (MSI) 1960s to Early 1970s 50 to 5,000
Early 1970s to Late
Large scale integration (LSI) 5,000 to 100,000
1970s
Late 1970s to Late
Very large scale integration (VLSI) 100,000 to 1,000,000
1980s
Ultra large scale integration (ULSI) 1990s to present > 1,000,000
Semiconductor Manufacturing Technology Table 1.1 © 2001by Prentice Hall

IC Fabrication
• Silicon
– Wafer
– Wafer Sizes
– Devices and Layers
• Wafer Fab
• Stages of IC Fabrication
– Wafer preparation
– Wafer fabrication
– Wafer test/sort
– Assembly and packaging
– Final test
Evolution of Wafer Size
2000
1992
1987
1981
1975
1965
50 mm 100 mm 125 mm 150 mm 200 mm 300 mm

Devices and Layers from a Silicon Chip
Top protective layer Conductive layer
Metal layer
Insulation layers drain
Recessed conductive
layer
Silicon substrate
Silicon substrate

Stages of IC Fabrication
Single crystal silicon

1. Wafer Preparation 4. Assembly and Packaging:
includes crystal The wafer is cut Scribe line
growing, rounding, along scribe lines
slicing and polishing. to separate each die. A single die
Wafers sliced from ingot
Wafer Fabrication Assembly Packaging

2. Metal connections
includes cleaning, are made and the
layering, patterning, chip is encapsulated.
etching and doping.
3. Test/Sort includes Defective die 5. Final Test ensures IC

probing, testing and passes electrical and
sorting of each die on environmental
the wafer. testing.

Preparation of Silicon Wafers
Polysilicon Seed crystal
6. Edge Rounding
Crucible
1. Crystal Growth
Heater
7. Lapping
2. Single Crystal Ingot
8. Wafer Etching
3. Crystal Trimming and

Diameter Grind
Polishing
Slurry head
9. Polishong
4. Flat Grinding
Polishing table
5. Wafer Slicing 10. Wafer Inspection
(Note: Terms in Figure 1.7 are explained in Chapter 4.)

Sample of Microchip Packaging

Semiconductor Trends
• Increase in Chip Performance

– Critical Dimension (CD)
– Components per Chip
– Moore’s Law
– Power Consumption
• Increase in Chip Reliability
• Reduction in Chip Price

Critical Dimension
Common IC Features
Line Width Space
Contact Hole

Past and Future Technology Nodes for
Device Critical Dimension (CD)
1988 1992 1995 1997 1999 2001 2002 2005
CD
1.0 0.5 0.35 0.25 0.18 0.15 0.13 0.10
(µm)
Semiconductor Manufacturing Technology Table 1.2 © 2001by Prentice Hall

Moore’s Law for Microprocessors
The number of transistors on a chip double every 18 months.
100M
10M 500
Pentium Pro
Pentium
Transistors
1M 80486 25
80386
100K 80286 1.0
8086
10K .1
8080
4004 .01
1975 1980 1985 1990 1995 2000
Year
Used with permission from Proceedings of the IEEE, January, 1998, © 1998 IEEE

Size Comparison of Early and Modern
Semiconductors
1990s Microchip
(5~25 million transistors)
1960s Transistor
U.S. coin, 10 cents

Reduction in Chip Power Consumption per IC
10
Average Power in micro Watts (10-6 W)
0
1997 1999 2001 2003 2006 2009 2012
Year
Redrawn from Semiconductor Industry Association,
National Technology Roadmap, 1997
Reliability Improvement of Chips
700
600
Long-Term Failure Rate Goals
in parts per million (PPM)
500
400
300
200
100
0
1972 1976 1980 1984 1988 1992 1996 2000
Year

Price Decrease of Semiconductor Chips
104 Electron tubes Semiconductor devices
Standard tube
Device size =
102 Miniature tube Price =
Bipolar transistor
1
Integrated circuits
MSI
Relative value
10-2 LSI
VLSI
10-4
10-6 ULSI
10-8
10-10
1930 1940 1950 1960 1970 1980 1990 2000
Year
Redrawn from C. Chang & S. Sze, McGraw-Hill, ULSI Technology, (New York: McGraw-Hill, 1996), xxiii.
The Electronic Era
• 1950s: Transistor Technology

• 1960s: Process Technology
• 1970s: Competition
• 1980s: Automation
• 1990s: Volume Production

Monocrystal Silicon Growth -CZ Method
Crystal puller
and rotation
mechanism Crystal seed
Single crystal Molten

silicon polysilicon
Quartz Heat shield

crucible
Carbon heating
element Water jacket

Dopant Concentration Nomenclature
Concentration (Atoms/cm3)
Dopant
Material < 1014 1014 to 1016 1016 to 1019 >1019
Type (Very Lightly Doped) (Lightly Doped) (Doped) (Heavily Doped)
Pentavalent n n-- n- n n+
Trivalent p p-- p- p p+

Increase in Number of Chips
on Larger Wafer Diameter
88 die
200-mm wafer
232 die
300-mm wafer

Crystal Defects in Silicon
A crystal defect (microdefect) is any

interruption in the repetitive nature of the
unit cell crystal structure.
Three general types of crystal defects in silicon:

1. Point defects - Localized crystal defect at
the atomic level
2. Dislocations - Displaced unit cells
3. Gross defects - Defects in crystal structure

Yield of a Wafer
66 good die
Yield = = 75%
88 total die
Reduction in defect density is a critical aspect for increasing wafer yield.

Basic Process Steps for Wafer Preparation
Wafer
Wafer Lapping
Lapping
Crystal
Crystal Growth
Growth and
and Edge
Edge Grind
Grind Cleaning
Cleaning
Shaping
Shaping Etching
Etching Inspection
Inspection
Wafer
Wafer Slicing
Slicing Polishing
Polishing Packaging
Packaging

Ingot Diameter Grind
Preparing crystal ingot for grinding
Diameter
grind
Flat grind

Wafer Identifying Flats
P-type (111) P-type (100)
N-type (111) N-type (100)

Wafer Notch and Laser Scribe
1234567890
Notch Scribed identification number

Chemical Etch of Wafer Surface
to Remove Damage

Double-Sided Wafer Polish
Upper polishing pad
Wafer
Slurry
Lower polishing pad

Quality Measures
• Physical dimensions
• Flatness
• Microroughness
• Oxygen content
• Crystal defects
• Particles
• Bulk resistivity

Improving Silicon Wafer Requirements
Year
(Critical Dimension)
1995 1998 2000 2004
(0.35 µm) (0.25 µm) (0.18 µm) (0.13 µm)
Wafer diameter
200 200 300 300
(mm)
Site flatnessA (µm) 0.23 0.17 0.12 0.08
Site size (mm x mm) (22 x 22) (26 x 32) 26 x 32 26 x 36
MicroroughnessB of front
0.2 0.15 0.1 0.1
surface (RMS)C (nm)
Oxygen content
≤ 24 ± 2 ≤ 23 ± 2 ≤ 23 ± 1.5 ≤ 22 ± 1.5
(ppm)D
Bulk microdefectsE
≤ 5000 ≤ 1000 ≤ 500 ≤ 100
(defects/cm2)
Particles per unit area
0.17 0.13 0.075 0.055
(#/cm2)
EpilayerF thickness
(± % uniformity) (µm) 3.0 (± 5%) 2.0 (± 3%) 1.4 (± 2%) 1.0 (± 2%)

Wafer Deformation
Positive deviation Wafer Negative deviation

Reference plane
Vacuum chuck

Flatness of Wafer Front Surface
Silicon wafer surface

Formation of Epitaxial Silicon Layers
Epitaxial layer
Silicon wafer
Monocrystalline layers

CTE Mismatch of Two Materials
Deposited film
Substrate CTE of deposited material
equals CTE of substrate
(a)
Compressive High CTE material

stress Low CTE material
(b)
Tensile Low CTE material

stress High CTE material
(c)

Process Chemicals
Liquids
•Acids
•Bases
•pH
•Solvents
•Chemical Distribution

Common Acids Used in Semiconductor
Manufacturing
Acid Symbol Examples of Use*
Etching of silicon dioxide (SiO2) and to clean
Hydrofluoric acid HF
quartzware.
Wet cleaning chemical that is part of the
Hydrochloric acid HCl standard clean 2 (SC-2) solution to remove
heavy metals from wafer.
Solution known as “Piranha” (7 parts H2SO4 to
Sulfuric acid H2SO4 3 parts of 30% hydrogen peroxide (H2O2)) used
to clean wafers.
Buffered oxide etch
(BOE): Solution of
HF and NH4F Etching of silicon dioxide (SiO2) film.
hydrofluoric acid and
ammonium fluoride
Etching of silicon nitride (Si3N4)
Phosphoric acid H3PO4
Used in mixture of HF and HNO3 to etch
Nitric acid HNO3
phosphosilicate glass (PSG).
Boron Tribromide BBr3 Liquid source of boron dopant.
Phosphorus
POCl3 Liquid source of phosphorus dopant.
Oxychloride

Common Bases Used in Semiconductor
Manufacturing
B ase S ym b o l E xam ple o f U se

H ydrogen pero xide H 2O 2 C atalyst in etch solution
Am m onium hydroxide N H 4O H C leaning solution
P otassium hydroxide P ositive photoresist
KOH
developer
T etram ethyl am m onium P ositive photoresist
TMAH
H ydro xide developer

Common Solvents Used in
Semiconductor Manufacturing
Common
Solvent Example of Use
Name
Deionized Water DI Water Widely used to rinse wafers.
Isopropyl alcohol IPA General purpose cleaning solvent.
Solvent used for wafer and general
Trichloroethylene TCE
cleaning.
General purpose cleaning solvent
Acetone Acetone
(stronger than IPA).
Strong cleaning solvent, may also be
Xylene Xylene used for photoresist edge bead
removal.

Bulk Chemical Distribution
Photo courtesy of Advanced Micro Devices

Wafer Fab Cleanroom
Photograph courtesy of Advanced Micro Devices, main fab corridor

Wafer Contaminants
Surface contaminant
Embedded particle

Relative Size of Particles
Cloud particles
Atoms Haze
Fog particles
Atmospheric dust
Sand
Size of single
molecules
of matter Thin smoke Pebbles
Dust
10-7 10-6 10-5 10-4 10-3 10-2 10-1 1 10

Millimeters

Defect from Particles
Micrograph courtesy of AMD, particle underneath photoresist pattern

Relative Size of Human Hair to 0.18 µm Feature
Size
The relative size of the human hair

is approximately 500 times the
size of the smallest feature size on
an integrated circuit.
Minimum IC feature size = 0.18 µm

Line
~90 µm Contact hole
width Space
90 µm
= 500
0.18 µm
A small example of a
Cross section of human hair segment from a larger
integrated circuit.

Particles Per Wafer Per Pass on a Wafer
Process
Tool
Initial particle count Initial particle count after

before the wafer is the wafer passes through
Particles are added to the
inserted in process tool. the process tool.
wafer by the process tool.

Typical Metal Impurities
Heavy Metals Alkali Metals
Iron (Fe) Sodium (Na)
Copper (Cu) Potassium (K)
Aluminum (Al) Lithium (Li)
Chromium (Cr)
Tungsten (W)
Titanium (Ti)

Particles Attracted to a Charged Wafer
- - - - - - - - -
- - - - - - - - - - - - - -
- - - - - - - - - - - - - - -
- - - - - - - - - - - - - -
- - - - - - - - - - -

Sources and Control of Contamination
Seven Sources of Contamination

in a Wafer Fab:
• Air
• Humans
• Facility
• Water
• Process Chemicals
• Process Gases
• Production Equipment

Definition of Airborne Particulate Cleanliness
Classes Per Federal Standard 209E
Particles/ft3
Class 0.1 µm 0.2 µm 0.3 µm 0.5 µm 5 µm
1 3.50 x 10 7.70 3.00 1.00
10 3.50 x 102 7.50 x 10 3.00 x 10 1.00 x 101
100 7.50 x 102 3.00 x 102 1.00 x 102
1,000 1.00 x 103 7.00
10,000 1.00 x 104 7.00 x 10
100,000 1.00 x 105 7.00 x 102

Particles Emitted by Human Activities
Average Number of Particles

Source of Particles
per Minute > 0.3 µm
Motionless (sitting or standing) 100,000
Moving hands, arms, trunk, neck and head 500,000
Walking at 2 miles per hour 5,000,000
Walking at 3.5 miles per hour 7,500,000
Cleanest Skin (per square foot) 10,000,000

Technician in Cleanroom Garment
The goal of the cleanroom garment

system is to meet these functional
criteria:
• Total containment of body-
generated particles and aerosols.
• Zero particle release from the
garment system.
• Zero electrical charge buildup for
ESD.
• No release of chemical or biological
residues.

Proper Cleanroom Protocol
Should Do: Should Not Do: Why?
Entry into cleanroom by only Keep out unauthorized personnel. Cleanroom's impose strict and
authorized personnel. demanding restrictions.
Take only what is necessary into Keep out all contaminants listed To prevent entry of unwanted
the cleanroom. in the company's cleanroom contamination sources.
policies and procedures.
Gown according to the company's No bare street clothes allowed To keep cleanroom apparel free
cleanroom policies and within the cleanroom. Do not of contaminants that could be
procedures. From head to feet. touch garments with bare skin. carried into the cleanroom.
Always make sure that all head Do not expose any facial or head Hair is a source of unwanted
and facial hare is covered. hair. contaminants.
Follow procedures for entering Do not open any door into the Air showers may assist in
the cleanroom, such as shoe cleanroom until all procedures are removing contaminants from
cleaner, air shower (if required). complete. garments. Some companies have
discontinued the use of air
showers.
Keep cleanroom garment closed Do not expose any street clothing. Sources of unwanted
at all times while in the Do not touch anything in the contamination.
cleanroom. cleanroom with bare skin.
Move slowly. Do not congregate or move This disrupts the airflow pattern.
quickly.

Cleanroom Facility Topics
• Cleanroom Layout
• Airflow Principles
• Air Filtering
• Temperature and Humidity
• Electrostatic Discharge

Bay and Chase Concept for Cleanroom
Service access corridor
Class 10,000
Service Chase
Service chase
Class 1,000
Class 1,000
Production bay Service chase Production bay Service chase Production bay
Class 1 Class 1,000 Class 1 Class 1,000 Class 1
Main manufacturing access corridor

Class 1
Service Chase
Service chase
Class 1,000
Class 1,000
Production bay Service chase Production bay Service chase Production bay
Class 1 Class 1,000 Class 1 Class 1,000 Class 1
Service access corridor

Class 10,000

Laminar Air Flow
HEPA filters
Air turbulence
SMT
Objects interfere with

normal laminar air
flow and create air
turbulence which can
Laminar air flows dislodge and carry
through perforated small particles.
floor.

HEPA Filter

Water in the Wafer Fab
• DI Water Installation
• Deionization
• DI Water Filtration
• Zeta Potential
• Bacterial Control

Unacceptable Contaminants in DI Water
• Dissolved Ions
• Organic Materials
• Particulates
• Bacteria
• Silica
• Dissolved Oxygen

Size of Particles in Water
Ion particles Colloids Suspended solids
Virus Bacteria
Pyrogen
Colloidal silica Yeast
Clay, silt
0.0001 0.001 0.01 0.1 1 10 100

Microns

Wafer Cassette

Minienvironment Concept
HEPA filters
Minienvironment
chamber Class 1
Production Bay
Class 1,000
Process
equipment
SMIF
load/unload SMIF pod (Class 1 or better)
interface
SMIF Pod Interface
Photograph courtesy of Applied Materials, Centura 5300 SMIF pod interface


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Semiconductor

Semiconductor Manufacturing Technology © 2001by Prentice Hall

Semiconductor Manufacturing Technology Photo 1.1 © 2001by Prentice Hall

Semiconductor Manufacturing Technology Figure 1.1 © 2001by Prentice Hall

Photo courtesy of Lucent Technologies Bell Labs Innovations

Semiconductor Manufacturing Technology Photo 1.3 © 2001by Prentice Hall

Photo courtesy of Texas Instruments, Inc.

Semiconductor Manufacturing Technology Photo 1.4 © 2001by Prentice Hall

Semiconductor Manufacturing Technology Figure 1.3 © 2001by Prentice Hall

Semiconductor Manufacturing Technology Table 1.1 © 2001by Prentice Hall

50 mm 100 mm 125 mm 150 mm 200 mm 300 mm

Semiconductor Manufacturing Technology Figure 1.4 © 2001by Prentice Hall

Top protective layer Conductive layer

Insulation layers drain

Semiconductor Manufacturing Technology Figure 1.5 © 2001by Prentice Hall

Single crystal silicon

Wafer Fabrication Assembly Packaging

3. Test/Sort includes Defective die 5. Final Test ensures IC

Semiconductor Manufacturing Technology Figure 1.6 © 2001by Prentice Hall

2. Single Crystal Ingot

3. Crystal Trimming and

5. Wafer Slicing 10. Wafer Inspection

(Note: Terms in Figure 1.7 are explained in Chapter 4.)

Semiconductor Manufacturing Technology Figure 1.8 © 2001by Prentice Hall

• Increase in Chip Performance

Semiconductor Manufacturing Technology © 2001by Prentice Hall

Line Width Space

Semiconductor Manufacturing Technology Figure 1.9 © 2001by Prentice Hall

1988 1992 1995 1997 1999 2001 2002 2005

Semiconductor Manufacturing Technology Table 1.2 © 2001by Prentice Hall

100K 80286 1.0

Semiconductor Manufacturing Technology Figure 1.11 © 2001by Prentice Hall

U.S. coin, 10 cents

Semiconductor Manufacturing Technology Figure 1.12 © 2001by Prentice Hall

Semiconductor Manufacturing Technology Figure 1.14 © 2001by Prentice Hall

• 1950s: Transistor Technology

Semiconductor Manufacturing Technology © 2001by Prentice Hall

Single crystal Molten

Quartz Heat shield

Semiconductor Manufacturing Technology © 2001by Prentice Hall

Semiconductor Manufacturing Technology © 2001by Prentice Hall

Semiconductor Manufacturing Technology © 2001by Prentice Hall

A crystal defect (microdefect) is any

Three general types of crystal defects in silicon:

Semiconductor Manufacturing Technology © 2001by Prentice Hall

Reduction in defect density is a critical aspect for increasing wafer yield.

Semiconductor Manufacturing Technology © 2001by Prentice Hall

Semiconductor Manufacturing Technology © 2001by Prentice Hall

Preparing crystal ingot for grinding

Semiconductor Manufacturing Technology © 2001by Prentice Hall

P-type (111) P-type (100)

N-type (111) N-type (100)

Semiconductor Manufacturing Technology © 2001by Prentice Hall

Notch Scribed identification number

Semiconductor Manufacturing Technology © 2001by Prentice Hall

Semiconductor Manufacturing Technology © 2001by Prentice Hall

Upper polishing pad

Lower polishing pad

Semiconductor Manufacturing Technology © 2001by Prentice Hall