Analog Design Journal Power

How to parallel two DC/DC converters with

digital controllers
By Bosheng Sun, Application Engineer, High Voltage
Ian Bower, Firmware Engineer, High Voltage

Introduction converter with the higher voltage will provide most of

In high-power applications or N+1 redundant power the current to the load. This will cause two side effects.
systems, two or more power converters are connected in First, the converter with the high output current suffers
parallel to provide power to the load, thus increasing the high stress and thus reduced reliability. Second, over-
amount of current available. current protection may be triggered and shut down the
However, parallel operation is not as simple as just converter.
connecting the outputs together; it brings new challenges. • Simultaneous startup: If a heavy load is already
A properly operating parallel system should meet these applied during startup and one converter starts up ear-
criteria: lier than the other, it has to provide all of the load cur-
• Interleaving: Interleaving means that the switching rent. Overcurrent protection may be triggered and shut
frequency of the second power converter should be down the converter, causing startup to fail.
phase-shifted relative to the first converter in order to Not every controller has integrated these functions,
evenly space the power pulses. Proper interleaving especially digital controllers. On the other hand, digital
reduces the voltage ripple of the combined converters, controllers dominate systems where parallel operation is
resulting in potential output-capacitance reduction and mandatory. Although most digital controllers have a
cost savings. Different topologies require different synchronize pin and some digital controllers even have a
degrees of shift. For two buck converters, the phase current-sharing pin, they won’t do proper interleaving and
should shift by 180 degrees. For two full-bridge convert- current sharing if the pins are simply connected together.
ers, because the frequency of output pulses is twice the Because of component tolerance, they will most likely not
switching frequency, a phase shift of 90 degrees is start up simultaneously either.
appropriate. It is important to define and implement a proper parallel-
• Current sharing: Due to the component tolerance, the operation algorithm. This article uses two UCD3138-
output voltages of the power converters will not be controlled, phase-shift full-bridge DC/DC converters to
exactly the same. A slight difference in output voltage implement these functions. Figure 1 shows the hardware
will cause a huge difference in output current; thus the connections.

Figure 1. Parallel operation of two phase-shift

full-bridge DC/DC converters

Phase-Shift Full Bridge

+ (Master) +
VOUT
–
VIN DPWM0A
UCD3138 PWM0
GPIO
– Load
+
DC
–

Phase-Shift Full Bridge

+ (Slave) +
VOUT
–
VIN GPIO
UCD3138 TCAP

– SYNC

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Analog Design Journal Power

Interleaving • The master should keep sending SYNC and PWM0

Like most digital controllers, the UCD3138 has a SYNC pin ­signals even if it shuts down due to fault protection.
that can synchronize pulse-width modulation (PWM) • During normal operation, the master continues sending
outputs to an external signal. One power converter, desig- out the PWM0 signal; the slave continues measuring this
nated as the master, can generate a synchronize signal signal and adjusting its switching frequency to match
(DPWM0A in this example) that equals its switching the master. This way, the slave will track the master’s
frequency but is phase-shifted 90 degrees. Connecting this switching frequency as temperature and clock frequen-
signal to the SYNC pin of the other power converter cies change.
(designated as slave) and configuring the slave to synchro- Figures 2 and 3 show test results. Figure 2 is the fixed-
nize to it will shift the slave’s switching frequency by leg PWM waveform after interleaving. Note that the
90 degrees. master and slave channels are phase-shifted by 90 degrees.
However, there’s a problem: because of component Figure 3 is the output voltage before the output inductor.
tolerances, no two controllers have exactly the same inter- Its frequency is twice the switching frequency and the
nal clock frequency. Moreover, the clock frequency master and slave signals are well interleaved. The inductor-
changes with temperature; even if the two clock frequen- current pulses are 180 degrees out of phase.
cies are close at room temperature, they can be different
when the temperature changes. If the master and slave
clock frequencies are significantly different, forcing them Figure 2. Master and slave PWM signals
to synchronize may cause PWM pulse stretching or
missing pulses, resulting in power-stage damage.
Therefore, the first thing to do is to match the switching
frequencies. To do that, the slave converter needs to know Master PWM
the master’s switching frequency. One option is to (2 V/div)
measure the frequency of the SYNC signal because it
matches the master’s switching frequency. However, the
SYNC signal is high frequency and the capture function of
the UCD3138 has limited resolution. The frequency
measurement may not be accurate enough.
For a more accurate measurement, let the master
converter generate another PWM signal (PWM0 in this Slave PWM
(2 V/div)
example) with a much lower frequency and send this
signal to the timer-capture (TCAP) pin of the slave Time (4 µs/div)
converter. The slave converter captures this signal and
determines the switching frequency of the master, and
then adjusts its switching frequency to match. Once this
Figure 3. Master and slave secondary
process is complete, it is safe to enable the synchroniza- switch-node voltage
tion function. The two converters will now be interleaved.
There is a general-purpose input/output (GPIO) signal
from slave to master in this configuration used for simulta-
neous startup, which will be discussed later.
Here are some things to note about Figure 1: Master Switch Node
(10 V/div)
• The SYNC signal is rising-edge-triggered in this example.
• The phase-shift full-bridge topology has two legs: a fixed
leg where the PWM waveform is fixed and a shifted leg
where the PWM is phase-shifted to the fixed leg. The
SYNC signal should be 90 degrees phase-delayed to the
PWM waveform of the master’s fixed leg.
• It is the slave’s fixed leg that synchronizes to this SYNC Slave Switch Node
(10 V/div)
signal.
• The slave should not turn on until it receives the first Time (2 µs/div)
SYNC signal.
• If the SYNC signal stops, the slave can shut down or
continue running at its own switching frequency,
depending on the system requirements.

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Analog Design Journal Power

Current sharing The bigger the k, the more accurate the current sharing,
There are two popular current-sharing methods: active but the more deviation of output voltage versus load.
current sharing and passive-droop current sharing. Each Simultaneous startup
has its own pros and cons. In active current sharing, a
A power-converter startup sequence usually goes like this:
current-share bus connects the paralleled power convert-
ers. The signal on the share bus represents the average 1. Turn on VIN.
current of all modules; each power supply attempts to 2. The bias starts up and provides VCC to the controller.
adjust its output current in order to match its output 3. The controller initializes.
current with the average current. 4. The controller checks that VIN is correct and that
In this article, passive-droop current sharing is used as there are no other faults.
the example. There is no current-share bus required, so 5. The converter turns on.
droop current sharing is also called zero-wire current
sharing. Compared to active current sharing, passive- With the addition of interleaving function, the master
droop current sharing is a simple but reliable current- and slave converters have different firmware. This causes
sharing method. In this method, the power-supply the controllers to have different initialization times. Also,
circuitry measures its output current and adjusts its given the component tolerance of the two converters,
voltage either up or down. If the load current increases, even without the interleaving function, they won’t turn on
the voltage decreases linearly. simultaneously.
Figure 4 shows the characteristics of output-voltage Thus, a “handshaking” mechanism is required. A simple
versus output-current for two power converters. The extra way to achieve this is to use both the SYNC signal and the
voltage drop or “droop” is proportional to the load current. connection between a GPIO pin on both the master and
If one of the paralleled power converters tries to provide slave converters. The master does not send a SYNC signal
more current, its output will droop slightly, resulting in a until it has finished the initialization and is ready to turn
reduced current. The other converter will provide more on. Once the slave receives the SYNC signal and is ready
current to the load; thus, the power supplies will share the to turn on, it sends a “SLAVE_READY” signal back to the
output load between them. master and turns on. The master will turn on immediately
With digital-controller firmware, the implementation is once it receives this SLAVE_READY signal. This way,
easy. The firmware monitors its output current through an master and slave will turn on at the same time, as shown
analog-to-digital converter (ADC) and adjusts the voltage- in Figure 5. Now the SYNC signal is not only used as a
loop reference accordingly. Equation 1 shows how the synchronization signal but also as a handshaking signal.
voltage-loop reference is calculated: The GPIO and SYNC connections are the same as shown
in Figure 1.
Voltage-loop reference =
 I  Figure 5. Handshaking during startup
Nominal reference − k ×  IOUT - OUT_max  (1)
 2 
where k is the slope of the curve in Figure 4. Power up
Equation 2 calculates k as:
Maximum allowed voltagedroop
( no load to full load )
k= (2) Master Initialization Slave Initialization
IOUT _ max

Figure 4. Characteristics of output-voltage Master ready

vs. output-current in droop-current sharing

Master starts
sending SYNC Slave detects SYNC

Hand
VOUT (V)

Slave ready
shaking
Nominal Voltage
Master receives Slave sends out
"SLAVE_READY" signal "SLAVE_READY" signal

0 50 100 Master turns on Slave turns on

IOUT (%)

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Analog Design Journal Power

If the extra GPIO pin is not available, a delay in the Conclusion

master code can be added right before it starts sending High-power applications or N+1 redundant power systems
out the SYNC signal. The delay should be long enough to require two or more power converters running in parallel.
guarantee that when the slave receives the first SYNC The power supplies in a properly paralleled operating
signal, its initialization is complete and it is ready to turn system should start up simultaneously, be interleaved and
on. This way, the master does not need to wait for share the load current.
SLAVE_READY; it can turn on immediately after it starts This article presented an example of how to implement
sending the SYNC signal. The slave will turn on immedi- such functions in a digital controller that does not already
ately after it receives the first SYNC signal and both the have these capabilities built-in. Although two converters
master and slave will turn on at the same time. This were used in the example, the same concepts can be
method saves the extra GPIO pin, but at the cost of extra extended to three or more converters running in parallel.
startup delay time.
Related Web sites
Product information:
UCD3138

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Analog Design Journal

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