A G R E AT E R M E AS U R E O F CO N F I D E N C E may be used in actual circuits, they are typi-

cally integrated into fabrication processes as

a test structure. Since they are simple struc-
tures and their fabrication is easy to control,
they are a convenient way to evaluate the
underlying processes.
The metal/polysilicon layer shown in
Figure 1 is one plate of the capacitor, and
silicon dioxide is the insulator. Since the
substrate below the insulating layer is a
semiconducting material, it is not by itself
the other plate of the capacitor. In effect, the
majority charge carriers become the other
plate. Physically, capacitance, C, is deter-

Fundamentals of
mined from the variables in the following
equation:
C = A (κ/d), where

Semiconductor C-V
A is the area of the capacitor,
κ is the dielectric constant of the insulator,
and

Measurements d is the separation of the two plates.

Therefore, the larger A and κ are, and
the thinner the insulator is, the higher the
capacitance will be. Typically, semiconduc-
tor capacitance values range from nanofar-
Lee Stauffer, Keithley Instruments, Inc. ads to picofarads, or smaller.
The procedure for taking C-V measure-
C-V measurements provide a wealth of process parameters, and analyze failure ments involves the application of DC bias
infor­mation about device and material mechanisms. voltages across the capacitor while mak-
characteristics. With appropriate methodologies, instru- ing the measurements with an AC signal
mentation, and software, a multitude of (Figure 1). Commonly, AC frequencies from
A Universal Test semiconductor device and material parame- about 10kHz to 10MHz are used for these
Capacitance-voltage (C-V) testing is ters can be derived. This information is used measurements. The bias is applied as a DC
widely used to determine semiconductor all along the production chain beginning voltage sweep that drives the MOSCAP
parameters, particularly in MOSCAP and with evaluation of epitaxially grown crys- structure from its accumulation region into
MOSFET structures. However, other types tals, including parameters such as average the depletion region, and then into inversion
of semiconductor devices and technologies doping concentration, doping profiles, and (Figure 2).
can also be characterized with C-V measure- carrier lifetimes. In wafer processes, C-V A strong DC bias causes majority car-
ments, including bipolar junction transistors measurements can reveal oxide thickness, riers in the substrate to accumulate near
(BJTs), JFETs, III-V compound devices, oxide charges, mobile ions (contamination), the insulator interface. Since they can’t get
photovoltaic cells, MEMs devices, organic and interface trap density. These measure- through the insulating layer, capacitance is
TFT displays, photodiodes, carbon nano- ments continue to be used after other process at a maximum in the accumulation region as
tubes (CNTs), and many others. steps, such as lithography, etching, cleaning,
The fundamental nature of these meas- dielectric and polysilicon depositions, and
urements makes them useful in a wide metallization. After devices are fully fabri-
range of applications and disciplines. They cated on the wafer, C-V is used to character- Metal
–
are used in the research labs of universities ize threshold voltages and other parameters Silicon Dioxide C-Meter
and semiconductor manufacturers to evalu- during reliability and basic device testing and + + + + + + + + (AC signal)
+
ate new materials, processes, devices, and to model the performance of these devices.
circuits. C-V measurements are extremely p-type

important to product and yield enhancement The Physics of Semiconductor

engineers, who are responsible for improv- Capacitance
ing processes and device performance. A MOSCAP structure is a fundamental Figure 1. C-V measurement circuit for a
Reliability engineers use these measure- device formed during semiconductor fabri- MOSCAP structure formed on a P-type
ments to qualify material suppliers, monitor cation (see Figure 1). Although these devices substrate.

Fundamentals of Semiconductor C-V Measurements February 2009 1

 HCUR

10mV–100mV AC
Source
HPOT

±30VDC
AC ZX
Voltmeter

LPOT

AC DUT
Ammeter Current
LCUR

Figure 3. Basic test setup for C-V measurements.

Figure 2. DC bias sweep of MOSCAP structure obtained during
C-V testing. Challenges to Successful C-V Measurements
The block diagram of a C-V test setup (Figure 3) is deceptively
the charges stack up near that interface (i.e., d is at a minimum). See simple. However, certain challenges are associated with this testing.
Figure 1. One of the fundamental parameters that can be derived Typically, test personnel have problems in the following areas:
from C-V accumulation measurements is the silicon dioxide thick- • Low capacitance measurements (picofarads and smaller values)
ness, tox. • C-V instrument connections (through a prober) to the
As bias voltage is decreased, majority carriers get pushed away wafer device
from the oxide interface and the depletion region forms. When the • Leaky (high D) capacitance measure­ments
bias voltage is reversed, charge carriers move the greatest distance • Using hardware and software to acquire the data
from the oxide layer, and capacitance is at a minimum (i.e., d is at a • Parameter extractions
maximum). From this inversion region capacitance, the number of Overcoming these challenges requires careful attention to the
majority carriers can be derived. The same basic concepts apply to techniques used along with appropriate hardware and software.
MOSFET transistors, even though their physical structure and dop- Low Capacitance Measurements. If C is small, the DUT’s AC
ing is more complex. response current is small and hard to measure. However, at higher
Many other parameters can be derived from the three regions frequencies, the DUT impedance is reduced, so the current increases
shown in Figure 2 as the bias voltage is swept through them. Different and is easier to measure. Often semiconductor capacitance is very
AC signal frequencies can reveal additional details. Low frequen- low (less than 1pF), which is below the capabilities of many LCR
cies reveal what are called quasistatic characteristics, whereas high meters. Even those claiming to measure these small capacitance val-
frequency testing is more indicative of dynamic performance. Both ues may have confusing specifications that make it difficult to deter-
types of C-V testing are often required. mine the final accuracy in the measurement. If accuracy over the
instrument’s full measurement range is not explicitly stated, the user
Basic Test Setup needs to clarify this with the manufacturer.
Figure 3 is the block diagram of a basic C-V measurement setup. High D (Leaky) Capacitors. In addition to having a low C value,
Because C-V measurements are actually made at AC frequencies, a semiconductor capacitor may also be leaky. That is the case when
the capacitance for the device under test (DUT) is calculated with the equivalent R in parallel with C is too low. This results in resis-
the following: tive impedance overwhelming the capacitive impedance, and the C
CDUT = IDUT / 2πfVAC, where value gets lost in the noise. For devices with ultra-thin oxide layers, D
IDUT is the magnitude of the AC current through the DUT, values can be greater than five. In general, as D increases, the accu-
f is the test frequency, and racy of a C measurement is rapidly degraded, so high D is a limiting
VAC is the magnitude and phase angle of the measured AC voltage factor in the practical use of a C meter. Again, higher frequencies
In other words, the test measures the AC impedance of the DUT can help solve the problem. At higher frequencies the capacitive
by applying an AC voltage and measuring the resulting AC current, impedance is lower, resulting in a C current that is higher and more
AC voltage, and impedance phase angle between them. easily measured.
These measurements take into account series and parallel resist- C-V Measurement Connections. In most test environments, the
ance associated with the capacitance, as well as the dissipation factor DUT is a test structure on a wafer: It is connected to the C-V instru-
(leakage). Figure 4 illustrates the basic circuit variables that can be ment through a prober, a probe card adapter, and a switch matrix.
derived from the measurements. Even if no switch is involved, there is still a prober and significant

2 February 2009 Fundamentals of Semiconductor C-V Measurements

 Z, Theta: Impedance and Phase Angle interested in less common tests, such as
R + jX: Resistance and Reactance performing both a C‑V and C‑f sweep on
Cp–Gp: Parallel Capacitance and Conductance
a Metal‑Insulator‑Metal (MIM) capacitor,
measuring small interconnect capacitance
Cs–Rs: Series Capacitance and Resistance
on a wafer, or doing a C‑V sweep on a two-
Cs–Rs Cp–Gp terminal nanowire device. The parameter
extractions should be easily obtained, with
|Z| = R2 + X2 where: Z = impedance automated curve plotting. (See, for example,
Z = R + jX D = dissipation factor Figure 5.)
Z
Often, engineers and researchers are
Xs D = Rs/jXs θ = phase angle
expected to perform C-V measurements
θ R = Zcos θ R = resistance
with little experience and training on the
X = Zsin θ X = reactance instrumentation. A test system with an intui-
Rs tive user interface and easy-to-use features
Cs = 1/(2πfXs) G = conductance
Cp = Cs/(1+D ) 2 makes this practical. That includes simple
test setup, sequence control, and data analy-
Gp = Rs/(Rs 2 + Xs 2)
sis. Otherwise, the user spends more time
learning the system than collecting and
Figure 4. Basic electrical variables available from C-V measurements.
using the data. Other considerations are a
cabling. At high frequencies, special cor- MEMs devices, organic TFT displays, and test system with:
rections and compensation must be applied. photodiodes, require tests at higher voltage • Tightly integrated source-measure units,
Usually, this is achieved with some combina- or current. For these applications, a separate digital oscilloscope and C-V meter
tion of an open, short, or calibration device. high voltage DC power supply and C meter • Easy integration with other external
Because of the complexity of the hardware, are required; DC bias up to 400V differen- instruments
cabling, and compensation techniques, it is a tial (0 to ±400V) and a current output up to • High resolution and precise measure-
good idea to confer with C-V test application 300mA are very useful. Being able to apply ments at the probe tips (DC biasing down
engineers. They are skilled at working with differential DC bias on both the HI and LO to millivolts and capacitance measure-
various probe systems to overcome many terminals of the C-V instrument offers more ments down to femtofarads)
types of interconnection problems. flexible control over electric fields within the • Test setups and libraries that can be eas-
Obtaining Useful Data. In addition to the DUT, which is very helpful in the research ily modified
accuracy issues mentioned earlier, practical and modeling of novel devices, such as nano- • Diagnostic/troubleshooting tools that let
considerations in C-V data collection include scale components. users know whether or not the system is
the instrumentation’s range of test variables, The instrumentation software should performing correctly.
versatility of parameter extraction software, include ready-to-run test routines that do not
and ease of hardware usage. Traditionally, require user programming. These should be
C-V testing has been limited to about 30V available for the most widely used device
and 10mA DC bias. However, many appli- technologies and test regimens, which were
cations, such as characterizing LD MOS mentioned in the first three paragraphs of
structures, low-k interlayer dielectrics, this article. Some researchers may also be

About the Author

Lee Stauffer is a Senior Marketer
with Keithley Instruments in Cleveland,
Ohio, USA, where he is responsible for
developing and supporting products for
the semiconductor manufacturing and
research markets. His formal education
in electrical engineering and semicon-
ductor device physics is complemented
by 20 years experience in semiconductor
process and product engineering, device
characterization, and instrumentation
Figure 5. Example of parameter extractions from a Keithley Model 4200-SCS showing doping design. He can be reached at 440-248-
characteristics (blue curve on left), which is related to the reciprocal of 1/C2 vs. Vg (red curve). The 0400, or by e-mail at lstauffer@keithley.
right graph shows the doping profile as the number of carriers per cubic centimeter as a function of
substrate depth. com.

Fundamentals of Semiconductor C-V Measurements February 2009 3

 Specifications are subject to change without notice.
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4 February 2009 Fundamentals of Semiconductor C-V Measurements