Compal Pal60 La-6562p PDF

A B C D E
COMPAL CONFIDENTIAL
MODEL NAME : PAL60
1 1
PCB NO : LA-6562P (DA80000JP00)

BOM P/N : 43193031L01
GPIO MAP: E3 Master GPIO Map10102010.xlsx
2
E3 MACALLAN 15" UMA 2
rPGA Sandy Bridge +

FCBGA PCH Cougar Point-M
2010-10-27
REV : 0.3(X02)
3 @ : Nopop Component 3
CONN@ : Connector Component
MB Type BOM P/N
TPM EN/ TCM DIS 43193031L01 (R1) 1@ 3@
TPM DIS/ TCM EN 43193031L02 (R1) 2@ 4@
TPM DIS/ TCM DIS 43193031L03 (R1) 2@ 3@
4 4
MB PCB
Part Number Description
DELL CONFIDENTIAL/PROPRIETARY
DA80000I700 PCB 0FH LA-6562P REV0 M/B UMA
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Cover Sheet
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.3
LA-6562P
Date: Wednesday, October 27, 2010 Sheet 1 of 66
A B C D E
A B C D E
Block Diagram Compal confidential Model: PAL60 Support Frequence 1066/1333

Memory BUS
(DDR3) DDRIII-DIMM X2
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
Sandy Bridge page 12,13
LVDS CONN LVDS 4MB (Socket G1)

1
rPGA /BGA CPU 1
page 24
USB 13 TS
988 pins page 24
CRT CONN For MB/Dock USB 11
Video Switch BT page 42
IO/B page 6~11
VGA PI3V712-AZLEX
page 25 USB 12
FDI DMI Camera Trough LVDS Cable
page 24
Lane x 8 Lane x 4
HDMI CONN VGA
SATA Repeater
DOCKING page 26 DPB INTEL USB MAX4951BECTP E-SATA
DPC SATA 4
PORT page 45
page 39 DPD
COUGAR POINT-M USB 1 USB Port page 45
DAI
USB BGA USB 0
USB Port page 45
SATA
DOCK LAN
1394 page 36 USB 2
2 2
2. IEEE1394+Card reader page 14~21 USB Port
OZ600RJ1LN IO/B
USB 1
SDXC page 36 USB Port
PCIE 6 Intel Lewisville
PCIE 7 82579LM
page 36
HD Audio I/F
PCI Express BUS DOCK LAN
page 32
SPI
PCIE 3 PCIE 5 PCIE 2 PCIE 1 Option S-ATA 0/1 6GB/s, S-ATA 2/3/4/5 3GB/s
LAN SWITCH
EXPRESS 1/2 Mini Card 1/2 Mini Card Full Mini Card China TPM1.2 LPC BUS PI3L720
Card Pink Panther WLAN WWAN/UWB SSX35BCB HDA Codec INT.Speaker
W25X64ZE page 32
92HD90B2 page 30
page 38 page 37 page 37 page 37 page 36
page 14
USB 10 USB 6 USB 4 USB 5 64M 4K sector page 30 HeadPhone & Transformer
SATA 0
TDA8034HN USH TPM1.2 MIC Jack
3 Smart Card
page 34 W25Q16BV page 33 3
Stick page 34 BCM5882 page 46
page 14 HDD MDC
IO/B
page 35,36 16M 4K sector
CPU XDP Port RFID page 28 page 45 RJ45
page 34 Fingerprint DAI
page 7 FP_USB USB 7 SATA 1
CONN To Docking side page 33
page 23
PCH XDP Port PCIE 4 E-Module
page 14 RJ11 Dig.
SMSC SIO
BC BUS page 29
MIC
Thermal ECE5028 Trough Cable
GUARDIAN III page 40 Trough LVDS Cable
EMC4002 SMSC KBC
page 22
MEC5055
WiFi ON/OFF page 41
page 31
SNIFFER/B
4 4
DC/DC Interface
page 43 TP CONN KB CONN
page 42 page 42 DELL CONFIDENTIAL/PROPRIETARY
Power On/Off Compal Electronics, Inc.
SW & LED page 31 Title
UMA Block Diagram
Size Document Number Rev
0.3
LA-6562P
Date: Tuesday, October 12, 2010 Sheet 2 of 66
A B C D E
5 4 3 2 1
POWER STATES
Signal SLP SLP SLP S4 SLP ALWAYS M SUS RUN CLOCKS USB PORT# DESTINATION
State S3# S4# S5# STATE# M# PLANE PLANE PLANE PLANE
0 JUSB1 (Ext Right Side)
S0 (Full ON) / M0 HIGH HIGH HIGH HIGH HIGH ON ON ON ON ON
1 JESA1 (Ext Right Side)
D
S3 (Suspend to RAM) / M1 LOW HIGH HIGH HIGH HIGH ON ON ON OFF OFF D
2 IO Board- JUSB1 (Ext Left Side)
S4 (Suspend to DISK) / M1 LOW LOW HIGH LOW HIGH ON ON OFF OFF OFF
3 IO Board- JUSB2 (Ext Left Side)
S5 (SOFT OFF) / M1 LOW LOW LOW LOW HIGH ON ON OFF OFF OFF
4 WLAN
S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH HIGH LOW ON OFF ON OFF OFF
5 WWAN
S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW LOW ON OFF OFF OFF OFF PCH
6 JMINI3(Pink Panther)
S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW LOW ON OFF OFF OFF OFF
7 USH->BIO
PM TABLE 8 DOCKING
+15V_ALW +3.3V_SUS +5V_RUN +3.3V_M +3.3V_M
+5V_ALW +1.5V_MEM +3.3V_RUN +1.05V_M +1.05V_M 9 DOCKING
C
+3.3V_ALW_PCH +1.8V_RUN (M-OFF) SATA DESTINATION C
power
plane +3.3V_RTC_LDO +1.5V_RUN 10 Express card
+0.75V_DDR_VTT SATA 0 HDD
+VCC_CORE 11 Bluetooth
+1.05V_RUN_VTT SATA 1 ODD/ E3 Module Bay
+1.05V_RUN 12 Camera
State
SATA 2 NA
13 LCD Touch
SATA 3 NA
S0 ON ON ON ON ON
SATA 4 ESATA 0 BIO

S3 ON ON OFF ON OFF
USH
SATA 5 Dock 1 NA
S5 S4/AC ON OFF OFF ON OFF
S5 S4/AC don't exist OFF OFF OFF OFF OFF
B
PCI EXPRESS DESTINATION B
UMA DP/HDMI Port Connetion
Lane 1 MINI CARD-1 WWAN
Port B MB HDMI Conn
Lane 2 MINI CARD-2 WLAN
Port C Dock DP port 2
Lane 3 Express card
Port D Dock DP port 1
Lane 4 E3 Module Bay (USB3)
Lane 5 MINI CARD-3 (Pink Panther)
Lane 6 MMI
Lane 7 10/100/1G LOM
A Lane 8 None A
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Index and Config.
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 0.3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-6562P
5 4 3 2 1
5 4 3 2 1
MODC_EN
HDDC_EN
EN_INVPWR FDC654P
+BL_PWR_SRC
Q21
D D
ADAPTER
SI3456BDV SI3456BDV
(Q27) (Q30)
+PWR_SRC 1.05V_VTTPWRGD
BATTERY ISL95870AH +0.8V_VCC_SA +5V_HDD +5V_MOD
(PU13)
ALWON
+15V_ALW
C ISL6236IRZA C
CHARGER +5V_ALW RUN_ON
(PU2)
SI4164DY
+3.3V_ALW (Q50)
AUX_EN_WOWL
PCH_ALW_ON
+5V_RUN
AUX_ON
SUS_ON
RUN_ON
M_ON
SN1003055 RT8209BGQW
MAX17411 RT8209BGQW RT9026GFP TPS51311
(PU9) (PU3) (PU5) (PU4) (PU7) (PU16) SI3456BDV SI3456BDV S13456 SI3456 NTMS4107 SI3456
B (Q38) (Q49) (Q54) (Q34) (Q55) (Q58) B
1.05V_0.8V_PWROK
CPU_VTT_ON
0.75V_VR_EN
M_ON
DDR_ON
RUN_ON
+3.3V_WLAN +3.3V_ALW_PCH +3.3V_SUS +3.3V_LAN +3.3V_RUN +3.3V_M
+VCC_CORE +1.5V_MEM +0.75V_DDR_VTT +1.8V_RUN +1.05V_RUN_VTT +1.05V_M
Pop option
RUN_ON
CPU1.5V_S3_GATE RUN_ON
Pop option
+1.0V_LAN +3.3V_M
AO4728 SI3456 SI4164

A (QC3) (Q59) A
+1.05V_RUN BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Power Rail
+1.5V_CPU_VDDQ +1.5V_RUN NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
LA-6562P
5 4 3 2 1
5 4 3 2 1
2.2K
SMBUS Address [0x9a]
2.2K
+3.3V_ALW_PCH
H14 MEM_SMBCLK 202
2N7002 SMBUS Address [A0h]
C9 MEM_SMBDATA 200 DIMMA A0h --> 1010 0000
2N7002
2.2K
202
PCH SMBUS Address [A4h]
2.2K
+3.3V_LAN 200 DIMMB A4h --> 1010 0100
D D
C6 LAN_SMBCLK 28
G8 LAN_SMBDATA 31 LOM SMBUS Address [C8]

M16 E14 53
XDP1 SMBUS Address [TBD]
2.2K 51
SML1_SMBDATA
SML1_SMBCLK
+3.3V_ALW_PCH
2.2K 53
51 XDP2
A5 B6 2.2K SMBUS Address [TBD]
3A 3A
2.2K +3.3V_ALW SMBUS Address
APR_EC: 0x48
B4 DOCK_SMB_CLK 127
SPR_EC: 0x70 2.2K
1A
DOCK_SMB_DAT
129 DOCKING MSLICE_EC: 0x72
1A A3 USB: 0x59 +3.3V_RUN
2.2K
AUDIO: 0x34
SLICE_BATTERY: 0x17 14
2.2K SLICE_CHARGER: 0x13
13 G Sensor
SMBUS Address [TBD]
C
2.2K +3.3V_ALW C
B5 LCD_SMBCLK
1B 30
A4 LCD_SMDATA WWAN
1B 32 SMBUS Address [TBD]
2.2K
KBC 2.2K
+3.3V_ALW
SMBUS Address
100 ohm 7
1C A56 PBAT_SMBCLK SMB_ADM1032: 0x98
6 BATTERY SMBUS Address [0x16] SMB_DIAG_DUMP: 0x04
1C B59 PBAT_SMBDAT 100 ohm
CONN SMB_DIAG_DUMP2: 0x05
2.2K SMB_BLACKTOP: 0x60
+3.3V_ALW
2.2K
A50 USH_SMBCLK M9
1E
B53 USH_SMBDAT L9 USH SMBUS Address [0xa4]
1E
B
2.2K B
+3.3V_ALW
2.2K
MEC 5055 7
2B A49 CARD_SMBCLK
8 Express card SMBUS Address [TBD]
2B B52 CARD_SMBDAT
2.2K
+3.3V_ALW
2.2K
B50 CHARGER_SMBCLK 10
1G
A47 CHARGER_SMBDAT 9 Charger
1G SMBUS Address [0x12]
2.2K
+3.3V_RUN
2.2K
B7 BAY_SMBDAT 31
2D
A7 BAY_SMBCLK 32 E3 Module Bay SMBUS Address [TBD]
2D
A A
2.2K
2.2K
B49 DAI_GPU_R3P_SMBCLK
2A 8
B48 DAI_GPU_R3P_SMBDAT A/D,D/A SMBUS Address [0x30]
2A 9 Title
converter
SMBUS TOPOLOGY
0.3
LA-6562P
5 4 3 2 1
5 4 3 2 1
(1)PEG_RCOMPO (H22) use 4mil connect to PEG_ICOMPI, then use 4mil connect to RC2. JCPU1I
(2)PEG_ICOMPO use 12mil connect to RC2

JCPU1A T35 F22
PEG_COMP VSS161 VSS234
PEG_ICOMPI J22 T34 VSS162 VSS235 F19
J21 T33 E30
DMI_CRX_PTX_N0 PEG_ICOMPO VSS163 VSS236
<16> DMI_CRX_PTX_N0 B27 DMI_RX#[0] PEG_RCOMPO H22 T32 VSS164 VSS237 E27
DMI_CRX_PTX_N1 B25 T31 E24
<16> DMI_CRX_PTX_N1 DMI_RX#[1] VSS165 VSS238
DMI_CRX_PTX_N2 A25 T30 E21
D <16> DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 DMI_RX#[2] VSS166 VSS239 D
<16> DMI_CRX_PTX_N3 B24 DMI_RX#[3] PEG_RX#[0] K33 T29 VSS167 VSS240 E18
PEG_RX#[1] M35 T28 VSS168 VSS241 E15
DMI_CRX_PTX_P0 B28 L34 T27 E13
<16> DMI_CRX_PTX_P0 DMI_RX[0] PEG_RX#[2] VSS169 VSS242
DMI_CRX_PTX_P1 B26 J35 T26 E10
DMI
DMI_CRX_PTX_P2 A24 J32 P9 E9
DMI_CRX_PTX_P3 B23 H34 P8 E8
H31 P6 E7
DMI_CTX_PRX_N0 PEG_RX#[6] VSS173 VSS246
<16> DMI_CTX_PRX_N0 G21 DMI_TX#[0] PEG_RX#[7] G33 P5 VSS174 VSS247 E6
<16> DMI_CTX_PRX_N1 DMI_CTX_PRX_N1 E22 G30 P3 E5
DMI_CTX_PRX_N2 DMI_TX#[1] PEG_RX#[8] VSS175 VSS248
<16> DMI_CTX_PRX_N2 F21 F35 P2 E4
DMI_CTX_PRX_N3 DMI_TX#[2] PEG_RX#[9] VSS176 VSS249
<16> DMI_CTX_PRX_N3 D21 DMI_TX#[3] PEG_RX#[10] E34 N35 VSS177 VSS250 E3
E32 N34 E2
DMI_CTX_PRX_P0 PEG_RX#[11] VSS178 VSS251
<16> DMI_CTX_PRX_P0 G22 DMI_TX[0] PEG_RX#[12] D33 N33 VSS179 VSS252 E1
<16> DMI_CTX_PRX_P1 DMI_CTX_PRX_P1 D22 D31 N32 D35
DMI_CTX_PRX_P2 DMI_TX[1] PEG_RX#[13] VSS180 VSS253
PCI EXPRESS* - GRAPHICS

<16> DMI_CTX_PRX_P2 F20 B33 N31 D32
DMI_CTX_PRX_P3 DMI_TX[2] PEG_RX#[14] VSS181 VSS254
<16> DMI_CTX_PRX_P3 C21 C32 N30 D29
DMI_TX[3] PEG_RX#[15] VSS182 VSS255
N29 VSS183 VSS256 D26
J33 N28 D20
PEG_RX[0] VSS184 VSS257
PEG_RX[1] L35 N27 VSS185 VSS258 D17
K34 N26 C34
FDI_CTX_PRX_N0 PEG_RX[2] VSS186 VSS259
<16> FDI_CTX_PRX_N0 A21 H35 M34 C31
FDI_CTX_PRX_N1 FDI0_TX#[0] PEG_RX[3] VSS187 VSS260
<16> FDI_CTX_PRX_N1 H19 H32 L33 C28
<16> FDI_CTX_PRX_N2 E19 FDI0_TX#[2] PEG_RX[5] G34 L30 VSS189 VSS262 C27
FDI_CTX_PRX_N3 F18 G31 L27 C25
Intel(R) FDI
<16> FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6] VSS190 VSS263
<16> FDI_CTX_PRX_N4 FDI_CTX_PRX_N4 B21 F33 L9 C23
<16> FDI_CTX_PRX_N5 C20 FDI1_TX#[1] PEG_RX[8] F30 L8 VSS192 VSS265 C10
<16> FDI_CTX_PRX_N6 FDI_CTX_PRX_N6 D18 E35 L6 C1
<16> FDI_CTX_PRX_N7 E17 E33 L5 B22
FDI1_TX#[3] PEG_RX[10] VSS194 VSS267
F32 L4 B19
<16> FDI_CTX_PRX_P0 FDI_CTX_PRX_P0 A22

FDI0_TX[0]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
D34
E31
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
<16> FDI_CTX_PRX_P1 FDI_CTX_PRX_P1 G19 C33 L1 B13
C FDI_CTX_PRX_P2 FDI0_TX[1] PEG_RX[14] VSS198 VSS271 C
<16> FDI_CTX_PRX_P2 E20 FDI0_TX[2] PEG_RX[15] B32 K35 VSS199 VSS272 B11
<16> FDI_CTX_PRX_P3 FDI_CTX_PRX_P3 G18 K32 B9
FDI_CTX_PRX_P4 FDI0_TX[3] VSS200 VSS273
<16> FDI_CTX_PRX_P4 B20 M29 K29 B8
FDI_CTX_PRX_P5 FDI1_TX[0] PEG_TX#[0] VSS201 VSS274
<16> FDI_CTX_PRX_P5 C19 FDI1_TX[1] PEG_TX#[1] M32 K26 VSS202 VSS275 B7
<16> FDI_CTX_PRX_P6 FDI_CTX_PRX_P6 D19 M31 J34 B5
FDI_CTX_PRX_P7 FDI1_TX[2] PEG_TX#[2] VSS203 VSS276
<16> FDI_CTX_PRX_P7 F17 L32 J31 B3
FDI1_TX[3] PEG_TX#[3] VSS204 VSS277
PEG_TX#[4] L29 H33 VSS205 VSS278 B2
FDI_FSYNC0 J18 K31 H30 A35
<16> FDI_FSYNC0 FDI_FSYNC1 FDI0_FSYNC PEG_TX#[5] VSS206 VSS279
<16> FDI_FSYNC1 J17 FDI1_FSYNC PEG_TX#[6] K28 H27 VSS207 VSS280 A32
J30 H24 A29
FDI_INT PEG_TX#[7] VSS208 VSS281
<16> FDI_INT H20 FDI_INT PEG_TX#[8] J28 H21 VSS209 VSS282 A26
H29 H18 A23
FDI_LSYNC0 PEG_TX#[9] VSS210 VSS283
<16> FDI_LSYNC0 J19 FDI0_LSYNC PEG_TX#[10] G27 H15 VSS211 VSS284 A20
FDI_LSYNC1 H17 E29 H13 A3
<16> FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11] VSS212 VSS285
F27 H10
PEG_TX#[12] VSS213
(1) EDP_COMPIO use 4mil trace to RC1 PEG_TX#[13]
D28 H9
VSS214
F26 H8
(2) EDP_ICOMPO use 12mil to RC1 PEG_TX#[14] VSS215
E25 H7
EDP_COMP PEG_TX#[15] VSS216
A18 H6
eDP_COMPIO VSS217
A17 eDP_ICOMPO PEG_TX[0] M28 H5 VSS218
B16 M33 H4
eDP_HPD PEG_TX[1] VSS219
M30 H3
PEG_TX[2] VSS220
L31 H2
PEG_TX[3] VSS221
C15 L28 H1
eDP_AUX PEG_TX[4] VSS222
D15 K30 G35
eDP_AUX# PEG_TX[5] VSS223
eDP
K27 G32
PEG_TX[6] VSS224
PEG_TX[7] J29 G29 VSS225
C17 J27 G26
eDP_TX[0] PEG_TX[8] VSS226
F16 H28 G23
C16 G28 G20
G15 E28 G17
F28 G11
B PEG_TX[12] VSS230 B
C18 eDP_TX#[0] PEG_TX[13] D27 F34 VSS231
E16 eDP_TX#[1] PEG_TX[14] E26 F31 VSS232
D16 D25 F29
eDP_TX#[2] PEG_TX[15] VSS233
F15 eDP_TX#[3]
Sandy Bridge_rPGA_Rev1p0
CONN@
DP Compensation Sandy Bridge_rPGA_Rev1p0

PEG Compensation CONN@
+1.05V_RUN_VTT
+1.05V_RUN_VTT
1
1
RC2
RC1 24.9_0402_1%~D
24.9_0402_1%~D
2
2
PEG_COMP
EDP_COMP
eDP_COMPIO and ICOMPO signals should be shorted near PEG_ICOMPI and RCOMPO signals should be shorted and routed
A
balls and routed with typical impedance <25 mohms with - max length = 500 mils - typical impedance = 43 mohms A
PEG_ICOMPO signals should be routed with - max length = 500 mils
Title
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Sandy Bridge (1/6)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
0.3
5 4 3 2 1
5 4 3 2 1
Follow DG Rev0.71 SM_DRAMPWROK topology +1.05V_RUN_VTT

+1.5V_CPU_VDDQ +3.3V_ALW_PCH
+1.05V_RUN_VTT +1.05V_RUN_VTT
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
+3.3V_ALW_PCH
1
0.1U_0402_16V4Z~D 1 1
1
CC1561 2
CC65
CC66
RC12 @ RC124 JXDP1
5
UC2 200_0402_5%~D 1K_0402_5%~D 1 2
2 2 XDP_PREQ# GND0 GND1 CFG16
1 3 4 CFG16 <9>
P
<40,41> RUNPWROK
2
B RUNPWROK_AND OBSFN_A0 OBSFN_C0
4 1 2 PM_DRAM_PWRGD_CPU XDP_PRDY# 5 6 CFG17 CFG17 <9>
2
O RC28 130_0402_5%~D OBSFN_A1 OBSFN_C1
+3.3V_ALW_PCH 1 2 2 7 8
A GND2 GND3
2
RC18 200_0402_5%~D SYS_PWROK_XDP XDP_OBS0 9 10 CFG0 CFG0 <9>
74AHC1G09GW_TSSOP5~D RC64 XDP_OBS1 OBSDATA_A0 OBSDATA_C0 CFG1
<16> PM_DRAM_PWRGD Place near JXDP1 11 12 CFG1 <9>
3
39_0402_5%~D OBSDATA_A1 OBSDATA_C1
13 GND4 GND5 14
D XDP_OBS2 CFG2 D
15 OBSDATA_A2 OBSDATA_C2 16 CFG2 <9>
XDP_OBS3 17 18 CFG3 CFG3 <9>
1 1
OBSDATA_A3 OBSDATA_C3
19 GND6 GND7 20
D CFG10 CFG8
<9> CFG10 21 22 CFG8 <9>
QC1 CFG11 OBSFN_B0 OBSFN_D0 CFG9
<11,43> RUN_ON_CPU1.5VS3# 2 <9> CFG11 23 24 CFG9 <9>
G SSM3K7002FU_SC70-3~D OBSFN_B1 OBSFN_D1
25 GND8 GND9 26
S XDP_OBS4 27 28 CFG4 CFG4 <9>
3
XDP_OBS5 OBSDATA_B0 OBSDATA_D0 CFG5
29 OBSDATA_B1 OBSDATA_D1 30 CFG5 <9>
The resistor for HOOK2 should beplaced 31 32
XDP_OBS6 GND10 GND11 CFG6
such that the stub is very small on CFG0 net 33
OBSDATA_B2 OBSDATA_D2
34 CFG6 <9>
XDP_OBS7 35 36 CFG7 CFG7 <9>
OBSDATA_B3 OBSDATA_D3
37 38
H_CPUPWRGD H_CPUPWRGD_XDP GND12 GND13 CLK_XDP
1 2 39 PWRGOOD/HOOK0 ITPCLK/HOOK4 40
RC51 2 1K_0402_5%~D CFD_PWRBTN#_XDP 41 42 CLK_XDP#
<14,16> SIO_PWRBTN#_R HOOK1 ITPCLK#/HOOK5
RC6 0_0402_5%~D 43 44
CFG0 XDP_HOOK2 VCC_OBS_AB VCC_OBS_CD XDP_RST#_R
1 2 45 46
+1.05V_RUN_VTT RC71 SYS_PWROK_XDP HOOK2 RESET#/HOOK6 XDP_DBRESET#
<16,40> SYS_PWROK 2 1K_0402_5%~D 47 HOOK3 DBR#/HOOK7 48
@RC9
@ RC9 0_0402_5%~D 49 50
DDR_XDP_SMBDAT_R1 GND14 GND15 XDP_TDO
<12,13,14,15,28,37> DDR_XDP_WAN_SMBDAT 1 2 51 SDA TD0 52
1 2 H_THERMTRIP# RC125
1 2 0_0402_5%~D DDR_XDP_SMBCLK_R1 53 54 XDP_TRST#
<12,13,14,15,28,37> DDR_XDP_WAN_SMBCLK SCL TRST#
@ RC126 56_0402_5%~D RC127 0_0402_5%~D 55 56 XDP_TDI
H_CATERR# XDP_TCLK TCK1 TDI XDP_TMS
1 2 57 58
@ RC128 49.9_0402_1%~D TCK0 TMS
59 GND16 GND17 60
1 2 H_PROCHOT#
RC44 62_0402_5%~D JCPU1B SAMTE_BSH-030-01-L-D-A
CONN@
A28 CPU_DMI 1 2
BCLK CLK_CPU_DMI <15>
MISC
CLOCKS
C26 A27 CPU_DMI# RC13 1 2 0_0402_5%~D
PROC_SELECT# BCLK# CLK_CPU_DMI# <15> XDP_RST#_R
RC15 0_0402_5%~D 2 1 PLTRST_XDP# <17>
RC8 1K_0402_5%~D
C C
<40> CPU_DETECT# AN34 SKTOCC#
A16 CPU_DPLL 1 2
DPLL_REF_CLK CPU_DPLL# CLK_CPU_DPLL <15>
A15 RC16 1 2 0_0402_5%~D
DPLL_REF_CLK# CLK_CPU_DPLL# <15>
RC17 0_0402_5%~D
1 2 CLK_XDP 1 2
H_CATERR# CLK_CPU_ITP <15>
AL33 @ RC48
@RC48 0_0402_5%~D RH107 0_0402_5%~D
CATERR# CLK_XDP# 1 2 CLK_CPU_ITP# <15>
RH106 0_0402_5%~D
THERMAL
D
AN33 R8 DDR3_DRAMRST#_CPU 3 1
<41> PECI_EC PECI SM_DRAMRST# DDR3_DRAMRST# <12>
DDR3
MISC
QC2
Max 500mils BSS138W-7-F_SOT323-3~D
G
<9> CLK_XDP_ITP 1 2
2
1
<41,53> H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP0 @ RH109 0_0402_5%~D
RC57 56_0402_5%~D PROCHOT# SM_RCOMP[0] SM_RCOMP1 RC50
A5 <9> CLK_XDP_ITP# 1 2
SM_RCOMP[1] SM_RCOMP2 DDR_HVREF_RST
Close to JCBU1 A4 4.99K_0402_1%~D @ RH108 0_0402_5%~D
SM_RCOMP[2]
<22> H_THERMTRIP# 1 2 H_THERMTRIP#_R AN32 SM_RCOMP2 --> 15mil 1
2
RC129 0_0402_5%~D THERMTRIP#
SM_RCOMP1/0 --> 20mil CC177
0.047U_0402_16V4Z~D
place RC129 near CPU 2
AP29 XDP_PRDY#
PRDY# XDP_PREQ#
AP27
PREQ#
AR26 XDP_TCLK 1 2
TCK <15> DDR_HVREF_RST_PCH
PWR MANAGEMENT
AR27 XDP_TMS RC46 0_0402_5%~D

JTAG & BPM
H_PM_SYNC TMS XDP_TRST#

<16> H_PM_SYNC AM34
PM_SYNC TRST#
AP30 <41> DDR_HVREF_RST_GATE 1 2 PU/PD for JTAG signals
@RC47
@ RC47 0_0402_5%~D
AR28 XDP_TDI_R +3.3V_RUN
TDI XDP_TDO_R
AP26
TDO
<18> H_CPUPWRGD 1 2 VCCPWRGOOD_0_R AP33
B RC25 0_0402_5%~D UNCOREPWRGOOD XDP_DBRESET# B
2 1
RC19 1K_0402_5%~D
AL35 XDP_DBRESET#_R 2 1 XDP_DBRESET# XDP_DBRESET# <14,16>
PM_DRAM_PWRGD_CPU DBR# RC26 0_0402_5%~D +1.05V_RUN_VTT
V8 SM_DRAMPWROK
AT28 XDP_OBS0_R 1 2 XDP_OBS0 XDP_TMS RC27 2 1 51_0402_1%~D
BPM#[0] XDP_OBS1_R RC30 0_0402_5%~D XDP_OBS1 XDP_TDI_R XDP_TDI
AR29 1 2 1 2
BPM#[1] XDP_OBS2_R RC31 0_0402_5%~D XDP_OBS2 RC23 0_0402_5%~D XDP_TDI_R RC29 2
AR30 1 2 1 51_0402_1%~D
PCH_PLTRST#_R BPM#[2] XDP_OBS3_R RC33 0_0402_5%~D XDP_OBS3
AR33 AT30 1 2
RESET# BPM#[3] XDP_OBS4_R RC34 0_0402_5%~D XDP_OBS4 XDP_PREQ# @ RC32 2
BPM#[4] AP32 1 2 1 51_0402_1%~D
AR31 XDP_OBS5_R RC36 1 2 0_0402_5%~D XDP_OBS5 XDP_TDO_R 1 2 XDP_TDO
BPM#[5] XDP_OBS6_R RC37 0_0402_5%~D XDP_OBS6 RC24 0_0402_5%~D XDP_TDO RC35 2
AT31 1 2 1 51_0402_1%~D
BPM#[6] XDP_OBS7_R RC38 0_0402_5%~D XDP_OBS7
BPM#[7] AR32 1 2
RC39 0_0402_5%~D
For ESD concern, please put near CPU XDP_TCLK RC40 2 1
51_0402_1%~D
Sandy Bridge_rPGA_Rev1p0 XDP_TRST# RC41 2 1
CONN@ 51_0402_1%~D
Buffered reset to CPU +3.3V_RUN VCCPWRGOOD_0_R

+1.05V_RUN_VTT SM_RCOMP2
SM_RCOMP1
1
0.1U_0402_16V4Z~D
SM_RCOMP0
1 RC130
1
140_0402_1%~D
200_0402_1%~D
75_0402_1%~D
RC4
25.5_0402_1%~D
10K_0402_5%~D
1
CC140
RC42
RC43
RC45
2
2
UC1
2
1 5
2
A NC VCC A
<14,17> PCH_PLTRST# 2
A PCH_PLTRST#_BUF
3 GND Y 4 1 2 PCH_PLTRST#_R
RC10 43_0402_5%~D Avoid stub in the PWRGD path
SN74LVC1G07DCKR_SC70-5~D
& RC130
Open drain buffer
Title
Sandy Bridge (2/6)
0.3
5 4 3 2 1
5 4 3 2 1
JCPU1D
JCPU1C
AE2 M_CLK_DDR2
D M_CLK_DDR0 <13> DDR_B_D[0..63] SB_CLK[0] M_CLK_DDR#2 M_CLK_DDR2 <13> D
<12> DDR_A_D[0..63] SA_CLK[0] AB6 M_CLK_DDR0 <12> SB_CLK#[0] AD2 M_CLK_DDR#2 <13>
AA6 M_CLK_DDR#0 DDR_B_D0 C9 R9 DDR_CKE2_DIMMB
DDR_A_D0 SA_CLK#[0] DDR_CKE0_DIMMA M_CLK_DDR#0 <12> DDR_B_D1 SB_DQ[0] SB_CKE[0] DDR_CKE2_DIMMB <13>
C5 SA_DQ[0] SA_CKE[0] V9 DDR_CKE0_DIMMA <12> A7 SB_DQ[1]
DDR_A_D1 D5 DDR_B_D2 D10
DDR_A_D2 SA_DQ[1] DDR_B_D3 SB_DQ[2]
D3 C8
DDR_A_D3 SA_DQ[2] DDR_B_D4 SB_DQ[3] M_CLK_DDR3
D2 SA_DQ[3] A9 SB_DQ[4] SB_CLK[1] AE1 M_CLK_DDR3 <13>
DDR_A_D4 D6 AA5 M_CLK_DDR1 DDR_B_D5 A8 AD1 M_CLK_DDR#3
DDR_A_D5 SA_DQ[4] SA_CLK[1] M_CLK_DDR#1 M_CLK_DDR1 <12> DDR_B_D6 SB_DQ[5] SB_CLK#[1] DDR_CKE3_DIMMB M_CLK_DDR#3 <13>
C6 SA_DQ[5] SA_CLK#[1] AB5 M_CLK_DDR#1 <12> D9 SB_DQ[6] SB_CKE[1] R10 DDR_CKE3_DIMMB <13>
DDR_A_D6 C2 V10 DDR_CKE1_DIMMA DDR_B_D7 D8
SA_DQ[6] SA_CKE[1] DDR_CKE1_DIMMA <12> SB_DQ[7]
DDR_A_D7 C3 DDR_B_D8 G4
F10 SA_DQ[8] F4 SB_DQ[9]
DDR_A_D9 F8 DDR_B_D10 F1 AB2
DDR_A_D10 SA_DQ[9] DDR_B_D11 SB_DQ[10] RSVD_TP[11]
G10 SA_DQ[10] RSVD_TP[1] AB4 G1 SB_DQ[11] RSVD_TP[12] AA2
DDR_A_D11 G9 AA4 DDR_B_D12 G5 T9
DDR_A_D12 SA_DQ[11] RSVD_TP[2] DDR_B_D13 SB_DQ[12] RSVD_TP[13]
F9 W9 F5
DDR_A_D13 SA_DQ[12] RSVD_TP[3] DDR_B_D14 SB_DQ[13]
F7 F2
G8 SA_DQ[14] G2 SB_DQ[15]
DDR_A_D15 G7 DDR_B_D16 J7 AA1
DDR_A_D16 SA_DQ[15] DDR_B_D17 SB_DQ[16] RSVD_TP[14]
K4 SA_DQ[16] RSVD_TP[4] AB3 J8 SB_DQ[17] RSVD_TP[15] AB1
DDR_A_D17 K5 AA3 DDR_B_D18 K10 T10
K1 W10 K9
J1 J9
J5 SA_DQ[20] J10 SB_DQ[21]
DDR_A_D21 J4 DDR_B_D22 K8 AD3 DDR_CS2_DIMMB#
DDR_A_D22 SA_DQ[21] DDR_CS0_DIMMA# DDR_B_D23 SB_DQ[22] SB_CS#[0] DDR_CS3_DIMMB# DDR_CS2_DIMMB# <13>
J2 AK3 DDR_CS0_DIMMA# <12> K7 AE3 DDR_CS3_DIMMB# <13>
DDR_A_D23 SA_DQ[22] SA_CS#[0] DDR_CS1_DIMMA# DDR_B_D24 SB_DQ[23] SB_CS#[1]
K2 SA_DQ[23] SA_CS#[1] AL3 DDR_CS1_DIMMA# <12> M5 SB_DQ[24] RSVD_TP[17] AD6
DDR_A_D24 M8 AG1 DDR_B_D25 N4 AE6
N10 AH1 N2
N8 SA_DQ[26] N1 SB_DQ[27]
DDR_A_D27 N7 DDR_B_D28 M4
DDR_A_D28 SA_DQ[27] DDR_B_D29 SB_DQ[28] M_ODT2
M10 N5 AE4 M_ODT2 <13>
SA_DQ[28] SB_DQ[29] SB_ODT[0]
DDR SYSTEM MEMORY B

DDR_A_D29 M9 AH3 M_ODT0 DDR_B_D30 M2 AD4 M_ODT3
C DDR_A_D30 SA_DQ[29] SA_ODT[0] M_ODT1 M_ODT0 <12> DDR_B_D31 SB_DQ[30] SB_ODT[1] M_ODT3 <13> C
N9 AG3 M1 AD5
DDR SYSTEM MEMORY A
DDR_A_D31 SA_DQ[30] SA_ODT[1] M_ODT1 <12> DDR_B_D32 SB_DQ[31] RSVD_TP[19]
M7 AG2 AM5 AE5
AG6 AH2 AM6
AG5 SA_DQ[33] AR3 SB_DQ[34]
DDR_A_D34 AK6 DDR_B_D35 AP3
AK5 AN3 DDR_B_DQS#[0..7] <13>
DDR_A_D36 SA_DQ[35] DDR_B_D37 SB_DQ[36] DDR_B_DQS#0
AH5 SA_DQ[36] DDR_A_DQS#[0..7] <12> AN2 SB_DQ[37] SB_DQS#[0] D7
DDR_A_D37 AH6 C4 DDR_A_DQS#0 DDR_B_D38 AN1 F3 DDR_B_DQS#1
DDR_A_D38 SA_DQ[37] SA_DQS#[0] DDR_A_DQS#1 DDR_B_D39 SB_DQ[38] SB_DQS#[1] DDR_B_DQS#2
AJ5 SA_DQ[38] SA_DQS#[1] G6 AP2 SB_DQ[39] SB_DQS#[2] K6
DDR_A_D39 AJ6 J3 DDR_A_DQS#2 DDR_B_D40 AP5 N3 DDR_B_DQS#3
AJ8 SA_DQ[40] SA_DQS#[3] M6 AN9 SB_DQ[41] SB_DQS#[4] AN5
DDR_A_D41 AK8 AL6 DDR_A_DQS#4 DDR_B_D42 AT5 AP9 DDR_B_DQS#5
AJ9 SA_DQ[42] SA_DQS#[5] AM8 AT6 SB_DQ[43] SB_DQS#[6] AK12
DDR_A_D43 AK9 AR12 DDR_A_DQS#6 DDR_B_D44 AP6 AP15 DDR_B_DQS#7
DDR_A_D44 SA_DQ[43] SA_DQS#[6] DDR_A_DQS#7 DDR_B_D45 SB_DQ[44] SB_DQS#[7]
AH8 AM15 AN8
DDR_A_D45 SA_DQ[44] SA_DQS#[7] DDR_B_D46 SB_DQ[45]
AH9 AR6
AL9 AR5
AL8 AR9 DDR_B_DQS[0..7] <13>
DDR_A_D48 SA_DQ[47] DDR_B_D49 SB_DQ[48] DDR_B_DQS0
AP11 DDR_A_DQS[0..7] <12> AJ11 C7
DDR_A_D49 SA_DQ[48] DDR_A_DQS0 DDR_B_D50 SB_DQ[49] SB_DQS[0] DDR_B_DQS1
AN11 SA_DQ[49] SA_DQS[0] D4 AT8 SB_DQ[50] SB_DQS[1] G3
DDR_A_D50 AL12 F6 DDR_A_DQS1 DDR_B_D51 AT9 J6 DDR_B_DQS2
DDR_A_D51 SA_DQ[50] SA_DQS[1] DDR_A_DQS2 DDR_B_D52 SB_DQ[51] SB_DQS[2] DDR_B_DQS3
AM12 K3 AH11 M3
AM11 N6 AR8 AN6
AL11 AL5 AJ12 AP8
AP12 AM9 AH12 AK11
AN12 AR11 AT11 AP14
DDR_A_D56 SA_DQ[55] SA_DQS[6] DDR_A_DQS7 DDR_B_D57 SB_DQ[56] SB_DQS[7]
AJ14 SA_DQ[56] SA_DQS[7] AM14 AN14 SB_DQ[57]
DDR_A_D57 AH14 DDR_B_D58 AR14
AL15 AT14 DDR_B_MA[0..15] <13>
AK15 DDR_A_MA[0..15] <12> AT12
DDR_A_D60 SA_DQ[59] DDR_B_D61 SB_DQ[60] DDR_B_MA0
AL14 AN15 AA8
DDR_A_D61 SA_DQ[60] DDR_A_MA0 DDR_B_D62 SB_DQ[61] SB_MA[0] DDR_B_MA1
AK14 AD10 AR15 T7
B DDR_A_D62 SA_DQ[61] SA_MA[0] DDR_A_MA1 DDR_B_D63 SB_DQ[62] SB_MA[1] DDR_B_MA2 B
AJ15 SA_DQ[62] SA_MA[1] W1 AT15 SB_DQ[63] SB_MA[2] R7
DDR_A_D63 AH15 W2 DDR_A_MA2 T6 DDR_B_MA3
SA_DQ[63] SA_MA[2] DDR_A_MA3 SB_MA[3] DDR_B_MA4
W7 T2
SA_MA[3] DDR_A_MA4 SB_MA[4] DDR_B_MA5
SA_MA[4] V3 SB_MA[5] T4
V2 DDR_A_MA5 T3 DDR_B_MA6
SA_MA[5] DDR_A_MA6 DDR_B_BS0 SB_MA[6] DDR_B_MA7
W3 <13> DDR_B_BS0 AA9 R2
DDR_A_BS0 SA_MA[6] DDR_A_MA7 DDR_B_BS1 SB_BS[0] SB_MA[7] DDR_B_MA8
<12> DDR_A_BS0 AE10 W6 <13> DDR_B_BS1 AA7 T5
DDR_A_BS1 SA_BS[0] SA_MA[7] DDR_A_MA8 DDR_B_BS2 SB_BS[1] SB_MA[8] DDR_B_MA9
<12> DDR_A_BS1 AF10 V1 <13> DDR_B_BS2 R6 R3
DDR_A_BS2 SA_BS[1] SA_MA[8] DDR_A_MA9 SB_BS[2] SB_MA[9] DDR_B_MA10
<12> DDR_A_BS2 V6 W5 AB7
SA_BS[2] SA_MA[9] DDR_A_MA10 SB_MA[10] DDR_B_MA11
SA_MA[10] AD8 SB_MA[11] R1
V4 DDR_A_MA11 T1 DDR_B_MA12
SA_MA[11] DDR_A_MA12 DDR_B_CAS# SB_MA[12] DDR_B_MA13
W4 <13> DDR_B_CAS# AA10 AB10
DDR_A_CAS# SA_MA[12] DDR_A_MA13 DDR_B_RAS# SB_CAS# SB_MA[13] DDR_B_MA14
<12> DDR_A_CAS# AE8 SA_CAS# SA_MA[13] AF8 <13> DDR_B_RAS# AB8 SB_RAS# SB_MA[14] R5
DDR_A_RAS# AD9 V5 DDR_A_MA14 DDR_B_WE# AB9 R4 DDR_B_MA15
<12> DDR_A_RAS# SA_RAS# SA_MA[14] <13> DDR_B_WE# SB_WE# SB_MA[15]
DDR_A_WE# AF9 V7 DDR_A_MA15
<12> DDR_A_WE# SA_WE# SA_MA[15]
Sandy Bridge_rPGA_Rev1p0 CONN@
CONN@
A A
Title
Sandy Bridge (3/6)
0.3
5 4 3 2 1
5 4 3 2 1
CFG Straps for Processor
CFG2
1
@RC51
@ RC51
1K_0402_5%~D
2
D JCPU1E D
L7 @ T1 PAD~D
RSVD28 @ T2 PAD~D
AG7
CFG0 RSVD29 @ T3 PAD~D
<7> CFG0 AK28 CFG[0] RSVD30 AE7
CFG1 AK29 AK2 @ T4 PAD~D PEG Static Lane Reversal - CFG2 is for the 16x
<7> CFG1 CFG2 CFG[1] RSVD31
AL26 W8 @ T5 PAD~D
<7> CFG3 AL27 CFG[3]
CFG4 AK26 1:(Default) Normal Operation; Lane #
<7> CFG4 CFG5 CFG[4]
<7> CFG5 AL29 CFG[5] RSVD33 AT26 @ T6 PAD~D CFG2 definition matches socket pin map definition
CFG6 AL30 AM33 @ T7 PAD~D
<7> CFG7 AM31 CFG[7] RSVD35 AJ27 @ T8 PAD~D 0:Lane Reversed
CFG8 AM32
<7> CFG8 CFG9 CFG[8]
<7> CFG9 AM30
CFG10 CFG[9]
<7> CFG10 AM28
CFG11 CFG[10] CFG4
<7> CFG11 AM26 CFG[11]
@ T9 PAD~D CFG12 AN28
CFG[12]
1
@ T10 PAD~D CFG13 AN31 T8 @ T11 PAD~D
@ T12 PAD~D CFG14 CFG[13] RSVD37 @ T13 PAD~D @ RC52
AN26 J16
@ T14 PAD~D CFG15 CFG[14] RSVD38 @ T15 PAD~D 1K_0402_5%~D
AM27 H16
+VCC_GFXCORE CFG16 CFG[15] RSVD39 @ T16 PAD~D
<7> CFG16 AK31 G16
CFG17 CFG[16] RSVD40
<7> CFG17 AN29
2
CFG[17]
1 2 RSVD1
@RC122
@ RC122 49.9_0402_1%~D
AR35 @ T17 PAD~D

+VCC_CORE RSVD1 RSVD41 @ T18 PAD~D
AJ31 AT34
RSVD2 VAXG_VAL_SENSE RSVD42 @ T19 PAD~D
AH31 VSSAXG_VAL_SENSE RSVD43 AT33
1 2 RSVD3 RSVD3 AJ33 VCC_VAL_SENSE RSVD44 AP35 @ T20 PAD~D Display Port Presence Strap
@RC120
@ RC120 49.9_0402_1%~D RSVD4 AH33 AR34 @ T21 PAD~D
VSS_VAL_SENSE RSVD45
C C
1 : Disabled; No Physical Display Port
1 2 RSVD2 PAD~D T22 @ AJ26 CFG4 attached to Embedded Display Port
RSVD5
RESERVED
@RC123
@ RC123 49.9_0402_1%~D
1 2 RSVD4
@RC121
@ RC121 49.9_0402_1%~D
RSVD46 B34 @ T23 PAD~D 0 : Enabled; An external Display Port device is
1 2 +DIMM0_1_VREF_CPU +DIMM0_1_VREF_CPU
+DIMM0_1_VREF_CPU B4 A33 @ T24 PAD~D
connected to the Embedded Display Port
@RC96
@ RC96 1K_0402_5%~D +DIMM0_1_CA_CPU D1 RSVD6 RSVD47 @ T25 PAD~D
+DIMM0_1_CA_CPU RSVD7 RSVD48 A34
1 2 +DIMM0_1_CA_CPU B35 @ T26 PAD~D
@RC97
@ RC97 1K_0402_5%~D RSVD49 @ T27 PAD~D
RSVD50 C35
PAD~D T28 @ F25 CFG6

PAD~D T29 @ RSVD8
F24
PAD~D T30 @ RSVD9 CFG5
F23 RSVD10
PAD~D T31 @ D24 AJ32 @ T32 PAD~D
RSVD11 RSVD51
1
PAD~D T33 @ G25 AK32 @ T34 PAD~D
PAD~D T35 @ RSVD12 RSVD52 @ RC54 @ RC53
G24
PAD~D T36 @ RSVD13 1K_0402_5%~D 1K_0402_5%~D
E23
PAD~D T37 @ RSVD14
D23
PAD~D T38 @ RSVD15 @ T39 PAD~D
C30 AH27
2
PAD~D T40 @ RSVD16 VCC_DIE_SENSE
A31 RSVD17
PAD~D T41 @ B30
PAD~D T42 @ RSVD18
B29
PAD~D T43 @ RSVD19
D30 AN35 CLK_XDP_ITP <7>
PAD~D T44 @ RSVD20 RSVD54
B31 AM35 CLK_XDP_ITP# <7>
PAD~D T45 @ RSVD21 RSVD55
A30
PAD~D T46 @ RSVD22
C29
RSVD23
PCIE Port Bifurcation Straps
PAD~D T47 @ J20
PAD~D T48 @ RSVD24 @ T49 PAD~D
B18 AT2
RSVD25 RSVD56
PAD~D T155 @ A19
VCCIO_SEL RSVD57
AT1 @ T50 PAD~D 11: (Default) x16 - Device 1 functions 1 and 2 disabled
AR1 @ T51 PAD~D
B RSVD58 B
CFG[6:5] 10: x8, x8 - Device 1 function 1 enabled ; function 2
PAD~D T52 @ J15 RSVD27 disabled
01: Reserved - (Device 1 function 1 disabled ; function
B1 @ T53 PAD~D
KEY 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
Sandy Bridge_rPGA_Rev1p0 CFG7

CONN@
1
@ RC56
1K_0402_5%~D
2
PEG DEFER TRAINING
1: (Default) PEG Train immediately

CFG7 following xxRESETB de assertion
0: PEG Wait for BIOS for training
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Sandy Bridge (4/6)
LA-6562P
5 4 3 2 1
5 4 3 2 1
JCPU1F POWER
+1.05V_RUN_VTT
+VCC_CORE +VCC_CORE
53AAG35 8.5A 22uF X 12.

VCC1
AG34 AH13
VCC2 VCCIO1
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1 1 1 1 1 AG33 VCC3 VCCIO2 AH10
AG32 AG10
CC67 CC75 CC76 CC77 VCC4 VCCIO3
CC68 AG31 AC10 1 1 1 1 1 1 1 1 1 1 1
D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D VCC5 VCCIO4 D
AG30 VCC6 VCCIO5 Y10
2 2 2 2 2
CC78
CC69
CC79
CC80
CC81
CC82
CC83
CC84
CC85
CC70
CC86
AG29 VCC7 VCCIO6 U10
AG28 VCC8 VCCIO7 P10
AG27 L10 2 2 2 2 2 2 2 2 2 2 2
VCC9 VCCIO8
AG26 J14
VCC10 VCCIO9
AF35 VCC11 VCCIO10 J13
AF34 J12
VCC12 VCCIO11
1 1 1 1 1 1 AF33 VCC13 VCCIO12 J11
@ AF32 H14
CC87 CC71 CC72 CC88 CC73 VCC14 VCCIO13
CC74 AF31 H12
VCC15 VCCIO14
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M~D
10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D AF30 H11
2 2 2 2 2 2 VCC16 VCCIO15
AF29 G14 1 1 1
VCC17 VCCIO16
AF28 VCC18 VCCIO17 G13 1 1 1 1 1
PEG AND DDR
CC107
CC108
CC109
AF27 G12 + + +
VCC19 VCCIO18
CC89
CC90
CC91
CC92
CC93
AF26 F14
VCC20 VCCIO19
AD35 F13
VCC21 VCCIO20 2 2 2 2 2 2 2 2
AD34 VCC22 VCCIO21 F12
AD33 F11 @ @ @ @ @
VCC23 VCCIO22
AD32 VCC24 VCCIO23 E14
AD31 E12
VCC25 VCCIO24
AD30
VCC26
AD29 E11
VCC27 VCCIO25
AD28 VCC28 VCCIO26 D14
AD27 VCC29 VCCIO27 D13
AD26 D12
VCC30 VCCIO28
AC35 VCC31 VCCIO29 D11
+VCC_CORE AC34 C14
VCC32 VCCIO30
AC33 C13
VCC33 VCCIO31
AC32 VCC34 VCCIO32 C12
AC31 VCC35 VCCIO33 C11
1 1 1 1 1 AC30 B14
VCC36 VCCIO34
AC29 B12
C CC110 CC111 CC112 CC113 CC114 VCC37 VCCIO35 C
AC28 VCC38 VCCIO36 A14
22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D AC27 A13
2 2 2 2 2 VCC39 VCCIO37
AC26 A12
VCC40 VCCIO38 +1.05V_RUN_VTT
AA35 VCC41 VCCIO39 A11
AA34 VCC42
AA33 J23
VCC43 VCCIO40
1
AA32 VCC44
AA31 Note: Place the PU resistors close to CPU RC60
VCC45 75_0402_1%~D
1 1 1 1 1 AA30 VCC46 RC61 close to CPU 300 - 1500mils
AA29
CC115 CC116 CC117 CC118 VCC47
CC119 AA28
2
22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D VCC48
AA27
2 2 2 2 2 VCC49 H_CPU_SVIDALRT#
AA26 VCC50 1 2 VIDALERT_N <53>
CORE SUPPLY
Y35 RC61 43_0402_5%~D
VCC51
Y34
VCC52
Y33
VCC53
Y32
VCC54
Y31
VCC55 +1.05V_RUN_VTT
1 1 1 1 1 Y30
VCC56
Y29 VCC57
CC120 CC121 CC122 CC123 CC124 Y28 CAD Note: Place the PU
VCC58
1
22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D Y27 resistors close to CPU
2 2 2 2 2 VCC59 RC63
Y26 RC63 close to CPU 300 - 1500mils
VCC60 130_0402_1%~D
V35
VCC61 H_CPU_SVIDALRT#
V34 AJ29
VCC62 VIDALERT# VIDSCLK
V33 AJ30 VIDSCLK <53>
2
VCC63 VIDSCLK VIDSOUT Iccmax current changed for PDDG Rev0.7
V32 VCC64 VIDSOUT AJ28 VIDSOUT <53>
V31
VCC65
1
@
1
@
1
@
1 V30
V29
VCC66 CPU Power Rail Table
VCC67
CC125 CC126 CC127 CC128 V28
VCC68
S0 Iccmax
22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D V27 Voltage Rail Voltage Current (A)
B 2 2 2 2 VCC69 B
V26 VCC70
U35 VCC71
U34
VCC72
VCC 0.65-1.3 53
U33 VCC73
U32
VCC74
U31
VCC75
VCCIO 1.05 8.5
U30
VCC76
U29
VCC77
U28
VCC78
VAXG 0.0-1.1 26
U27 VCC79
U26 VCC80
R35 +VCC_CORE VCCPLL 1.8 3
VCC81
R34 VCC82
+VCC_CORE R33
VCC83
1
R32 VCC84
VDDQ 1.5 5
R31 Place RC66, RC70near CPU RC66
VCC85
R30 100_0402_1%~D
VCC86
R29
VCC87
VCCSA 0.65-0.9 6
1 1 1 1 R28
2
@ VCC88 VCCSENSE_R
R27 AJ35 1 2 VCCSENSE <53>
+ + + + VCC89 VCC_SENSE VSSSENSE_R
CC129 CC130 CC131 CC132 R26
VCC90 VSS_SENSE
AJ34 RC67 1 2 0_0402_5%~D VSSSENSE <53> +1.5V_MEM 1.5 12-16 *
470U_D2T_2VM~D 470U_D2T_2VM~D 470U_D2T_2VM~D 470U_D2T_2VM~D P35 RC68 0_0402_5%~D
VCC91
P34
VCC92
1
2 3 2 3 2 3 2 3 P33 VCC93 VTT_SENSE_R RC70
P32 B10 1 2 VTT_SENSE <52>
VCC94 VCCIO_SENSE VSSIO_SENSE_R RC1321
P31
VCC95 VSSIO_SENSE
A10 2 0_0402_5%~D VTT_GND <52> 100_0402_1%~D * Description
P30 RC133 0_0402_5%~D
VCC96
P29 5A to Mem controller(+1.5V_CPU_VDDQ)
2
VCC97
P28 5-6A to 2 DIMMs/channel
VCC98
P27
VCC99 2-5A to +1.5V_RUN & +0.75V_DDR_VTT
P26
VCC100
A
1 1 A
+ @CC133 + CC134
470U_D2T_2VM~D 470U_D2T_2VM~D
2 3 2 3
CONN@ Compal Electronics, Inc.
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Sandy Bridge (5/6)
5 4 3 2 1
5 4 3 2 1
+1.5V_CPU_VDDQ Source
+1.5V_MEM QC3 +1.5V_CPU_VDDQ
+3.3V_ALW2 +15V_ALW AO4728L_SO8~D
8 1
7 2
1
@
10U_0805_6.3V6M~D
20K_0402_5%~D
6 3 1
CC135
RC73
RC72 5
1
100K_0402_5%~D JCPU1H
RC74
4
100K_0402_5%~D 2 AT35 AJ22
2
VSS1 VSS81
AT32 VSS2 VSS82 AJ19
D RUN_ON_CPU1.5VS3 D
AT29 AJ16
2
VSS3 VSS83
3
QC4B 1 AT22 AJ7
RUN_ON_CPU1.5VS3# DMN66D0LDW-7_SOT363-6~D VSS6 VSS86
5 AT19 AJ4
CC136 VSS7 VSS87
AT16 VSS8 VSS88 AJ3
4700P_0402_25V7K~D +V_DDR_REF QC5 +V_SM_VREF_CNT AT13 AJ2
4
2 NTR4503NT1G_SOT23-3~D VSS9 VSS89
6
AT7 VSS11 VSS91 AH35
1 3 AT4 AH34
QC4A VSS12 VSS92
AT3 VSS13 VSS93 AH32
1 2 2 DMN66D0LDW-7_SOT363-6~D AR25 AH30
<38,40,43,50> RUN_ON VSS14 VSS94
1
@ RC77 0_0402_5%~D AR22 AH29
RC78 VSS15 VSS95
AR19 AH28
1
2 100K_0402_5%~D VSS16 VSS96
<41> CPU1.5V_S3_GATE 1 2 RUN_ON_CPU1.5VS3# <7,43> AR16 AH26
RC79 0_0402_5%~D VSS17 VSS97
AR13 AH25
VSS18 VSS98
1 2 AR10 AH22
2
@ RC134 0_0402_5%~D VSS19 VSS99
AR7 AH19
VSS20 VSS100
AR4 VSS21 VSS101 AH16
AR2 AH7
RUN_ON_CPU1.5VS3 VSS22 VSS102
AP34 AH4
+VCC_GFXCORE
JCPU1G
POWER AP31
AP28
AP25
VSS23
VSS24
VSS25
VSS103
VSS104
VSS105
AG9
AG8
AG4
VSS26 VSS106
AP22 AF6
VSS27 VSS107
26A AP19 VSS28 VSS108 AF5
SENSE
LINES
+VCC_GFXCORE AT24 AK35 VCC_AXG_SENSE <53> AP16 AF3
VAXG1 VAXG_SENSE VSS29 VSS109
AT23 AK34 VSS_AXG_SENSE <53> AP13 AF2
VAXG2 VSSAXG_SENSE VSS30 VSS110
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1 1 1 1 1 1 1 1 AT21 VAXG3 AP10 VSS31 VSS111 AE35

CC137
CC138
CC144
CC145
CC146
CC147
CC139
CC148
AT20 VAXG4 AP7 VSS32 VSS112 AE34

AT18 AP4 AE33
VAXG5 VSS33 VSS113
AT17 AP1 AE32
C 2 2 2 2 2 2 2 2 VAXG6 VSS34 VSS114 C
AR24 VAXG7 AN30 VSS35 VSS115 AE31
AR23 CC1782 1 0.1U_0402_10V7K~D AN27 AE30
VAXG8 VSS36 VSS116
AR21 AN25 AE29
AR20
VAXG9
VAXG10
+V_SM_VREF_CNT AN22
VSS37
VSS38 VSS VSS117
VSS118 AE28
VREF
AR18 CC1792 1 0.1U_0402_10V7K~D AN19 AE27
VAXG11 VSS39 VSS119
AR17 AN16 AE26
VAXG12 VSS40 VSS120
AP24 VAXG13 SM_VREF AL1 AN13 VSS41 VSS121 AE9
AP23 CC1492 1 0.1U_0402_10V7K~D AN10 AD7
VAXG14 VSS42 VSS122
AP21 VAXG15 AN7 VSS43 VSS123 AC9
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1 1 1 1 AP20
VAXG16
+V_SM_VREF should AN4
VSS44 VSS124
AC8
CC151
CC141
CC152
CC153
AP18 have 10 mil trace width CC1502 1 0.1U_0402_10V7K~D AM29 AC6

VAXG17 VSS45 VSS125
AP17 AM25 AC5
VAXG18 VSS46 VSS126
AN24 VAXG19 AM22 VSS47 VSS127 AC3
2 2 2 2 AN23 +1.5V_CPU_VDDQ AM19 AC2
VAXG20 @ PJP1 VSS48 VSS128
AN21 AM16 AB35
VAXG21 VSS49 VSS129
AN20 1 2 AM13 AB34
VAXG22 DDR3 -1.5V RAILS VSS50 VSS130
AN18 AM10 AB33
VAXG23 PAD-OPEN 4x4m VSS51 VSS131
AN17
VAXG24 5A AM7
VSS52 VSS132
AB32
GRAPHICS
AM24 AF7 +1.5V_MEM AM4 AB31

VAXG25 VDDQ1 @ PJP2 VSS53 VSS133
AM23 VAXG26 VDDQ2 AF4 AM3 VSS54 VSS134 AB30
AM21 AF1 1 2 AM2 AB29
VAXG27 VDDQ3 VSS55 VSS135
470U_D2T_2VM~D
470U_D2T_2VM~D
10U_0805_4VAM~D
10U_0805_4VAM~D
10U_0805_4VAM~D
10U_0805_4VAM~D
10U_0805_4VAM~D
10U_0805_4VAM~D
330U_D2_2VM_R6M~D
1 1 AM20 AC7 1 1 1 1 1 1 1 AM1 AB28
@ @ VAXG28 VDDQ4 PAD-OPEN 4x4m VSS56 VSS136
AM18 AC4 AL34 AB27
CC159
CC158
CC161
CC162
CC163
CC164
CC165
CC166
CC167
+ + AM17 AC1 + AL31 AB26
AL24 Y7 AL28 Y9
VAXG31 VDDQ7 2 2 2 2 2 2 VSS59 VSS139
AL23 Y4 AL25 Y8
2 3 2 3 VAXG32 VDDQ8 2 VSS60 VSS140
AL21 VAXG33 VDDQ9 Y1 AL22 VSS61 VSS141 Y6
AL20 U7 AL19 Y5
AL18 U4 AL16 Y3
AL17 U1 AL13 Y2
AK24 P7 AL10 W35
AK23 P4 AL7 W34
B VAXG38 VDDQ14 VSS66 VSS146 B
AK21 VAXG39 VDDQ15 P1 AL4 VSS67 VSS147 W33
AK20 VAXG40 AL2 VSS68 VSS148 W32
AK18 AK33 W31
VAXG41 VSS69 VSS149
AK17 VAXG42 AK30 VSS70 VSS150 W30
AJ24 AK27 W29
VAXG43 VSS71 VSS151
AJ23 AK25 W28
VAXG44 VSS72 VSS152
AJ21 AK22 W27
VAXG45 VSS73 VSS153
AJ20 AK19 W26
VAXG46 VSS74 VSS154
AJ18 AK16 U9
VAXG47 VSS75 VSS155
AJ17 VAXG48 AK13 VSS76 VSS156 U8
AH24
6A AK10 U6
SA RAIL
VAXG49 VSS77 VSS157

AH23 AK7 U5
VAXG50 VSS78 VSS158
AH21 VAXG51 VCCSA1 M27 +VCC_SA AK4 VSS79 VSS159 U3
10U_0805_4VAM~D
10U_0805_4VAM~D
10U_0805_4VAM~D
10U_0603_6.3V6M~D
AH20 M26 AJ25 U2
VAXG52 VCCSA2 VSS80 VSS160
AH18 VAXG53 VCCSA3 L26
AH17 J26 1 1 1 1 1
VAXG54 VCCSA4
@ CC171
J25
VCCSA5
CC168
CC169
CC170
J24 + CC172
VCCSA6 330U_D2_2VM_R6M~D Sandy Bridge_rPGA_Rev1p0
H26
VCCSA7 2 2 2 2
H25
VCCSA8 2
CONN@
1.8V RAIL
3A 1
RC137
2
0_0402_5%~D
+GND_VCC_SA <56>
+1.8V_RUN B6 H23 VCCSA_SENSE <56>

VCCPLL1 VCCSA_SENSE
MISC
330U_D2_2.5VM_R6M~D
A6 VCCPLL2
10U_0805_4VAM~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1 1 1 1 A2
VCCPLL3
CC176
CC173
CC174
CC175
+ C22 H_FC_C22
FC_C22
C24 1 2 VCCSA_VID_1 <56>
2 2 2 VCCSA_VID1
10K_0402_5%~D
RC138 0_0402_5%~D
1
A 2 A
RC83
Bridge_rPGA_Rev1p0
CONN@
2

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Sandy Bridge (6/6)
LA-6562P
5 4 3 2 1
5 4 3 2 1
+V_DDR_REF 1
RD1
2
0_0402_5%~D +DIMM0_1_VREF_DQ JDIMM1 H=5.2
+DIMM0_1_VREF_CPU 1 2 +1.5V_MEM +1.5V_MEM 2-3A to 1 DIMMs/channel
<8> DDR_A_DQS#[0..7]
All VREF traces should @ RD7 0_0402_5%~D JDIMM1 CONN@
<8> DDR_A_D[0..63] have 10 mil trace width 1 VREF_DQ VSS 2
3 4 DDR_A_D4
VSS DQ4
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
DDR_A_D0 5 6 DDR_A_D5
<8> DDR_A_DQS[0..7] DQ0 DQ5 +1.5V_MEM
DDR_A_D1 7 8
DQ1 VSS DDR_A_DQS#0
<8> DDR_A_MA[0..15] 1 1 9 VSS DQS0# 10
Populate RD1 for Intel DDR3 11 12 DDR_A_DQS0
DM0 DQS0
CD1
CD2
VREFDQ multiple methods M1 13 VSS VSS 14
1
2 2 DDR_A_D3 DQ2 DQ6 DDR_A_D7 RD27
17 DQ3 DQ7 18
D 1K_0402_1%~D D
19 VSS VSS 20
DDR_A_D9 DQ8 DQ12 DDR_A_D13
23 24
2
DQ9 DQ13
25 26
DDR_A_DQS#1 VSS VSS DDR3_DRAMRST#_R 1
Layout Note: 27
DQS1# DM1
28 <13> DDR3_DRAMRST#_R 2 DDR3_DRAMRST# <7>
Note: DDR_A_DQS1 29 30 DDR3_DRAMRST#_R RD28 1K_0402_1%~D
Place near JDIMM1 31
DQS1 RESET#
32
Check voltage tolerance of DDR_A_D10 33
VSS VSS
34 DDR_A_D14
DQ10 DQ14
VREF_DQ at the DIMM socket DDR_A_D11 35 DQ11 DQ15 36 DDR_A_D15
37 38
DDR_A_D16 VSS VSS DDR_A_D20
39 DQ16 DQ20 40
+1.5V_MEM DQ17 DQ21
43 VSS VSS 44
DDR_A_DQS#2 45 46
DDR_A_DQS2 DQS2# DM2
47 48
DQS2 VSS DDR_A_D22
49 50
VSS DQ22
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
DDR_A_D19 DQ18 DQ23
1 1 1 1 53 54
DQ19 VSS DDR_A_D28
55 VSS DQ28 56
CD3
CD4
CD5
CD6
DDR_A_D25 DQ24 DQ29
59 60
2 2 2 2 DQ25 VSS DDR_A_DQS#3
61 62
VSS DQS3# DDR_A_DQS3
63 DM3 DQS3 64
65 VSS VSS 66
69 DQ27 DQ31 70
71 72
VSS VSS
DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA
+1.5V_MEM <8> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <8>
75 76
VDD VDD DDR_A_MA15
77 78
C DDR_A_BS2 NC A15 DDR_A_MA14 C
<8> DDR_A_BS2 79 BA2 A14 80
81 82
VDD VDD
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
DDR_A_MA12 83 84 DDR_A_MA11
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
85 A9 A7 86
330U_SX_2VY~D
1 87 VDD VDD 88
@ CD13
1 1 1 1 1 1 1 DDR_A_MA8 89 90 DDR_A_MA6
A8 A6
CD7
CD8
CD9
CD10
CD11
CD51
CD14
+ DDR_A_MA5 91 92 DDR_A_MA4
A5 A4
93 94
DDR_A_MA3 VDD VDD DDR_A_MA2
95 A3 A2 96
2 2 2 2 2 2 2 2 DDR_A_MA1 97 98 DDR_A_MA0
A1 A0
99 VDD VDD 100
M_CLK_DDR0 101 102 M_CLK_DDR1
<8> M_CLK_DDR0 CK0 CK1 M_CLK_DDR1 <8>
M_CLK_DDR#0 103 104 M_CLK_DDR#1
<8> M_CLK_DDR#0 CK0# CK1# M_CLK_DDR#1 <8>
105 106
DDR_A_MA10 VDD VDD DDR_A_BS1
107 108 DDR_A_BS1 <8>
DDR_A_BS0 A10/AP BA1 DDR_A_RAS#
<8> DDR_A_BS0 109 110
BA0 RAS# DDR_A_RAS# <8>
111 112
DDR_A_WE# VDD VDD DDR_CS0_DIMMA#
<8> DDR_A_WE# 113 114 DDR_CS0_DIMMA# <8>
DDR_A_CAS# WE# S0# M_ODT0
<8> DDR_A_CAS# 115 116 M_ODT0 <8>
CAS# ODT0
Layout Note: 117 VDD VDD 118
+DIMM0_1_VREF_CA
DDR_A_MA13 119 120 M_ODT1
Place near JDIMM1.203,204 DDR_CS1_DIMMA# 121
A13 ODT1
122
M_ODT1 <8>
<8> DDR_CS1_DIMMA# S1# NC
123 124
VDD VDD
125 126 1 2 +V_DDR_REF
TEST VREF_CA RD29 0_0402_5%~D
127 128
VSS VSS
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
DDR_A_D32 129 130 DDR_A_D36
131 DQ33 DQ37 132 1 2 +DIMM0_1_CA_CPU
133 134 1 1 @ RD31 0_0402_5%~D
VSS VSS
CD15
CD16
DDR_A_DQS#4 135 136
+0.75V_DDR_VTT DDR_A_DQS4 DQS4# DM4
137 138
DQS4 VSS DDR_A_D38
139 140
DDR_A_D34 VSS DQ38 DDR_A_D39 2 2
141 142
B DDR_A_D35 DQ34 DQ39 B
143 DQ35 VSS 144
145 146 DDR_A_D44
VSS DQ44
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
DDR_A_D40 147 148 DDR_A_D45

DDR_A_D41 DQ40 DQ45
1 1 1 1 149 DQ41 VSS 150
151 152 DDR_A_DQS#5
VSS DQS5#
CD17
CD18
CD19
CD20
153 154 DDR_A_DQS5

DM5 DQS5
155 156
2 2 2 2 DDR_A_D42 VSS VSS DDR_A_D46
157 158
159 160
DQ43 DQ47
161 VSS VSS 162
DDR_A_D48 163 164 DDR_A_D52
165 166
DQ49 DQ53
167 VSS VSS 168
DDR_A_DQS#6 169 170
DDR_A_DQS6 DQS6# DM6
171 DQS6 VSS 172
173 174 DDR_A_D54
DDR_A_D50 VSS DQ54 DDR_A_D55
175 176
DDR_A_D51 DQ50 DQ55
177 178
DQ51 VSS DDR_A_D60
179 180
DDR_A_D56 VSS DQ60 DDR_A_D61
181 182
DDR_A_D57 DQ56 DQ61
183 184
DQ57 VSS DDR_A_DQS#7
185 VSS DQS7# 186
187 188 DDR_A_DQS7
DM7 DQS7
189 VSS VSS 190
DDR_A_D58 191 192 DDR_A_D62
193 194
DQ59 DQ63
195 VSS VSS 196
RD21 2 10K_0402_5%~D 197 198
SA0 EVENT#
+3.3V_RUN 199 200 DDR_XDP_WAN_SMBDAT <7,13,14,15,28,37>
VDDSPD SDA
1 2 201 202 DDR_XDP_WAN_SMBCLK <7,13,14,15,28,37>
RD3 10K_0402_5%~D SA1 SCL
1 1 203 204 +0.75V_DDR_VTT
VTT VTT
0.1U_0402_16V4Z~D
2.2U_0603_6.3V6K~D
+0.75V_DDR_VTT
CD21
CD22
A A
205 GND1 GND2 206
2 2
2~D TYCO_2-2013289-2~D
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DDRIII-SODIMM SLOT1
LA-6562P
Date: Monday, October 18, 2010 Sheet 12 of 66
5 4 3 2 1
5 4 3 2 1
2-3A to 1 DIMMs/channel
All VREF traces should +DIMM0_1_VREF_DQ +1.5V_MEM +1.5V_MEM
have 10 mil trace width JDIMM2 CONN@
1 2
VREF_DQ VSS DDR_B_D4
3 4
VSS DQ4
JDIMMB H=9.2
2.2U_0603_6.3V6K~D
DDR_B_D0 5 6 DDR_B_D5
DQ0 DQ5
0.1U_0402_16V4Z~D
DDR_B_D1 7 8
DQ1 VSS DDR_B_DQS#0
<8> DDR_B_DQS#[0..7] 1 1 9 VSS DQS0# 10
11 12 DDR_B_DQS0
DM0 DQS0
CD23
CD24
<8> DDR_B_D[0..63] Populate R88 for Intel DDR3 13 VSS VSS 14
VREFDQ multiple methods M1 2 2 DDR_B_D3 17
DQ2 DQ6
18 DDR_B_D7
<8> DDR_B_DQS[0..7] DQ3 DQ7
19 20
DDR_B_D8 VSS VSS DDR_B_D12
<8> DDR_B_MA[0..15] 21 DQ8 DQ12 22
D DDR_B_D9 DDR_B_D13 D
23 DQ9 DQ13 24
25 VSS VSS 26
DDR_B_DQS#1 27 28
DDR_B_DQS1 DQS1# DM1 DDR3_DRAMRST#_R
29 30 DDR3_DRAMRST#_R <12>
DQS1 RESET#
Note: 31
VSS VSS
32
Check voltage tolerance of DDR_B_D11 35
DQ10 DQ14
36 DDR_B_D15
DQ11 DQ15
VREF_DQ at the DIMM socket 37 VSS VSS 38
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 42
DQ17 DQ21
43 VSS VSS 44
DDR_B_DQS#2 45 46
DDR_B_DQS2 DQS2# DM2
47 DQS2 VSS 48
49 50 DDR_B_D22
DDR_B_D18 VSS DQ22 DDR_B_D23
51 52
DDR_B_D19 DQ18 DQ23
53 54
DQ19 VSS DDR_B_D28
Layout Note: 55 VSS DQ28 56
Place near JDIMM2 DDR_B_D25 59
DQ24 DQ29
60
DQ25 VSS DDR_B_DQS#3
61 62
VSS DQS3# DDR_B_DQS3
63 64
DM3 DQS3
65 66
67 DQ26 DQ30 68
DQ27 DQ31
71 72
VSS VSS
+1.5V_MEM
DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB
<8> DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB <8>
75 VDD VDD 76
77 78 DDR_B_MA15
NC A15
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
DDR_B_BS2 79 80 DDR_B_MA14
<8> DDR_B_BS2 BA2 A14
1 1 1 1 81 82
C DDR_B_MA12 VDD VDD DDR_B_MA11 C
83 A12/BC# A11 84
CD25
CD26
CD27
CD28
DDR_B_MA9 85 86 DDR_B_MA7
A9 A7
87 88
2 2 2 2 DDR_B_MA8 VDD VDD DDR_B_MA6
89 A8 A6 90
A5 A4
93 94
DDR_B_MA3 VDD VDD DDR_B_MA2
95 A3 A2 96
A1 A0
99 VDD VDD 100
M_CLK_DDR2 101 102 M_CLK_DDR3
<8> M_CLK_DDR2 M_CLK_DDR#2 CK0 CK1 M_CLK_DDR#3 M_CLK_DDR3 <8>
<8> M_CLK_DDR#2 103 CK0# CK1# 104 M_CLK_DDR#3 <8>
+1.5V_MEM 105 106
DDR_B_MA10 VDD VDD DDR_B_BS1
107 A10/AP BA1 108 DDR_B_BS1 <8>
DDR_B_BS0 109 110 DDR_B_RAS#
<8> DDR_B_BS0 BA0 RAS# DDR_B_RAS# <8>
111 112
VDD VDD
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
330U_SX_2VY~D
DDR_B_WE# 113 114 DDR_CS2_DIMMB#

<8> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <8>
DDR_B_CAS# 115 116 M_ODT2
<8> DDR_B_CAS# CAS# ODT0 M_ODT2 <8>
1 117 118
VDD VDD +DIMM0_1_VREF_CA
@ CD35
1 1 1 1 1 1 1 DDR_B_MA13 119 120 M_ODT3

A13 ODT1 M_ODT3 <8>
CD29
CD30
CD31
CD32
CD33
CD34
CD36
+ DDR_CS3_DIMMB# 121 122

<8> DDR_CS3_DIMMB# S1# NC
123 124
VDD VDD
125 126
2 2 2 2 2 2 2 2 TEST VREF_CA
127 128
VSS VSS
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
DDR_B_D32 129 130 DDR_B_D36
131 132
DQ33 DQ37
133 134 1 1
DDR_B_DQS#4 VSS VSS
135 DQS4# DM4 136
CD37
CD38
DDR_B_DQS4 137 138
DQS4 VSS DDR_B_D38
139 140
DDR_B_D34 VSS DQ38 DDR_B_D39 2 2
141 142
DDR_B_D35 DQ34 DQ39
143 144
DQ35 VSS DDR_B_D44
145 146
B DDR_B_D40 VSS DQ44 DDR_B_D45 B
147 DQ40 DQ45 148
Layout Note: DDR_B_D41 149 150
DQ41 VSS DDR_B_DQS#5
151 152
Place near JDIMM2.203,204 153
VSS DQS5#
154 DDR_B_DQS5
DM5 DQS5
155 156
157 158
159 160
DQ43 DQ47
161 162
163 164
165 DQ49 DQ53 166
167 VSS VSS 168
+0.75V_DDR_VTT DDR_B_DQS#6 169 170
DDR_B_DQS6 DQS6# DM6
171 DQS6 VSS 172
173 174 DDR_B_D54
175 DQ50 DQ55 176
DDR_B_D51 177 178
DQ51 VSS
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
179 180 DDR_B_D60

1 1 1 1 181 182
DDR_B_D57 DQ56 DQ61
183 184
DQ57 VSS
CD39
CD40
CD41
CD42
185 186 DDR_B_DQS#7

VSS DQS7# DDR_B_DQS7
187 188
2 2 2 2 DM7 DQS7
189 VSS VSS 190
DDR_B_D58 191 192 DDR_B_D62
193 DQ59 DQ63 194
195 196
+3.3V_RUN VSS VSS
197 198
SA0 EVENT#
+3.3V_RUN 199 VDDSPD SDA 200 DDR_XDP_WAN_SMBDAT <7,12,14,15,28,37>
2 1 201 202 DDR_XDP_WAN_SMBCLK <7,12,14,15,28,37>
RD5 10K_0402_5%~D SA1 SCL
+0.75V_DDR_VTT 203 204 +0.75V_DDR_VTT
VTT VTT
1
10K_0402_5%~D
RD6
0.1U_0402_16V4Z~D
2.2U_0603_6.3V6K~D
1 1 205 GND1 GND2 206

A A
CD43
CD44
TYCO_2-2013310-2~D
2
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DDRIII-SODIMM SLOT2
LA-6562P
5 4 3 2 1
5 4 3 2 1
CMOS_CLR1 CMOS setting PCH_AZ_SYNC is sampled

at the rising edge of RSMRST# pin. +3.3V_ALW_PCH JXDP2
So signal should be PU to the ALWAYS rail. USB_OC0#_R XDP_FN0
Shunt Clear CMOS <17> USB_OC0#_R USB_OC1#_R
1 2
XDP_FN1 +3.3V_ALW_PCH
1
GND0 GND1
2
XDP_FN16
@RH1
@ RH1 1 2 33_0402_5%~D 3 4
<17> USB_OC1#_R USB_OC2# @RH3
@ RH3 33_0402_5%~D XDP_FN2 OBSFN_A0 OBSFN_C0 XDP_FN17
Open Keep CMOS +3.3V_ALW_PCH <17> USB_OC2# USB_OC3#
1 2
XDP_FN3
5
OBSFN_A1 OBSFN_C1
6
@RH4
@ RH4 1 2 33_0402_5%~D 1 7 8
<17> USB_OC3# USB_OC4# @RH5
@ RH5 33_0402_5%~D XDP_FN4 @ XDP_FN0 GND2 GND3 XDP_FN8
1 2 9 10
<17> USB_OC4# USB_OC5# @RH6
@ RH6 33_0402_5%~D XDP_FN5 CH1 XDP_FN1 OBSDATA_A0 OBSDATA_C0 XDP_FN9
ME_CLR1 TPM setting <17> USB_OC5#
1 2 11
12
1
USB_OC6# @RH7
@ RH7 1 2 33_0402_5%~D XDP_FN6 0.1U_0402_16V4Z~D 13 14
RH66 <17> USB_OC6# SIO_EXT_SMI# @RH8
@ RH8 33_0402_5%~D XDP_FN7 2 XDP_FN2 GND4 GND5 XDP_FN10
Shunt Clear ME RTC Registers <17,41> SIO_EXT_SMI# SLP_ME_CSW_DEV#@
1 2
XDP_FN8 XDP_FN3
15
16
XDP_FN11
1K_0402_5%~D @RH9
RH9 1 2 33_0402_5%~D 17 18
<18,40> SLP_ME_CSW_DEV# USB_MCARD1_DET#@
@RH10
RH10 33_0402_5%~D XDP_FN9 OBSDATA_A3 OBSDATA_C3
Open Keep ME RTC Registers <18,37> USB_MCARD1_DET# HDD_DET#_R
1 2
XDP_FN10
19
GND6 GND7
20
@RH12
@ RH12 1 2 33_0402_5%~D 21 22
2
BBS_BIT0_R @RH13
@ RH13 33_0402_5%~D XDP_FN11 OBSFN_B0 OBSFN_D0
1 2 23 OBSFN_B1 OBSFN_D1 24
GPIO36 @RH14
@ RH14 1 2 33_0402_5%~D XDP_FN12 25 26
+RTC_CELL PCH_AZ_SYNC <18> GPIO36 GPIO37 @RH15
@ RH15 33_0402_5%~D XDP_FN13 XDP_FN4 GND8 GND9 XDP_FN12
1 2 27 OBSDATA_B0 OBSDATA_D0 28
<18> GPIO37 EN_ESATA_RPTR# @
@RH16
RH16 33_0402_5%~D XDP_FN14 XDP_FN5 XDP_FN13
1 2 29 OBSDATA_B1 OBSDATA_D1 30
1
<18> EN_ESATA_RPTR# TEMP_ALERT# @RH17
@ RH17 33_0402_5%~D XDP_FN15
1 2 31 32
<18,40> TEMP_ALERT# GND10 GND11
1
RH282 @ PCH_GPIO15 @RH18

@ RH18 1 2 33_0402_5%~D XDP_FN16 XDP_FN6 33 34 XDP_FN14
D
RH38 100K_0402_5%~D <18> PCH_GPIO15 SIO_EXT_SCI#_R @RH19
@ RH19 33_0402_5%~D XDP_FN17 XDP_FN7 OBSDATA_B2 OBSDATA_D2 XDP_FN15
D
1 2 35 36
330K_0402_5%~D <18> SIO_EXT_SCI#_R @RH20
@ RH20 33_0402_5%~D @ RH283 1K_0402_5%~D OBSDATA_B3 OBSDATA_D3
37 38
GND12 GND13 +3.3V_ALW_PCH
2 1 RSMRST#_XDP 1 2 1.05V_0.8V_PWROK_R 39 40
2
<16,41> PCH_RSMRST# <41,53> 1.05V_0.8V_PWROK PCH_PWRBTN#_XDP PWRGOOD/HOOK0 ITPCLK/HOOK4
@RH24
@ RH24 1K_0402_5%~D 1 2 41 42
2
<7,16> SIO_PWRBTN#_R HOOK1 ITPCLK#/HOOK5

PCH_INTVRMEN @ RH21 0_0402_5%~D 43 44
VCC_OBS_AB VCC_OBS_CD RSMRST#_XDP
45 46
HOOK2 RESET#/HOOK6
1
47 48 XDP_DBRESET#
RH39 @ @ RH284 0_0402_5%~D HOOK3 DBR#/HOOK7 XDP_DBRESET# <7,16>
On Die PLL VR is supplied by 49 GND14 GND15 50
330K_0402_5%~D CH2
<7,12,13,15,28,37> DDR_XDP_WAN_SMBDAT 1 2 DDR_XDP_WAN_SMBDAT_R2 51 52 PCH_JTAG_TDO
1.5V when sampled high, 1.8 V 15P_0402_50V8J~D 1 2 DDR_XDP_WAN_SMBCLK_R2 53
SDA TD0
54
<7,12,13,15,28,37> DDR_XDP_WAN_SMBCLK SCL TRST#
when sampled low 2 1 PCH_RTCX1 @ RH285 0_0402_5%~D 55 56 PCH_JTAG_TDI
2
PCH_JTAG_TCK TCK1 TDI PCH_JTAG_TMS

57 58
YH1 TCK0 TMS
59 GND16 GND17 60
1
1 G 2
INTVRMEN- Integrated SUS RH2 SAMTE_BSH-030-01-L-D-A CONN@
10M_0402_5%~D UH4A
1.1V VRM Enable 4 3
G
* High - Enable Internal VRs CH3 A20 C38 LPC_LAD0
2
RTCX1 FWH0 / LAD0 LPC_LAD1 LPC_LAD0 <34,35,40,41>
15P_0402_50V8J~D 32.768KHZ_12.5PF_Q13MC1461000~D A38
LPC
Low - Enable External VRs FWH1 / LAD1 LPC_LAD1 <34,35,40,41> +3.3V_RUN
2 1 PCH_RTCX2_R 1 2 PCH_RTCX2 C20 B37 LPC_LAD2
RTCX2 FWH2 / LAD2 LPC_LAD2 <34,35,40,41>
RH286 0_0402_5%~D C37 LPC_LAD3
FWH3 / LAD3 LPC_LAD3 <34,35,40,41>
1 2 PCH_RTCRST# D20
+RTC_CELL RTCRST#
RH22 20K_0402_5%~D D36 LPC_LFRAME# PCH_GPIO33 2 1
SRTCRST# FWH4 / LFRAME# LPC_LFRAME# <34,35,40,41>
1 2 G22 RH355 100K_0402_5%~D
RH23 20K_0402_5%~D SRTCRST# LPC_LDRQ0#
E36
RTC
LDRQ0# LPC_LDRQ0# <40>
1 2 INTRUDER# K22 K36 LPC_LDRQ1# IRQ_SERIRQ 2 1
INTRUDER# LDRQ1# / GPIO23 LPC_LDRQ1# <40>
RH11 1M_0402_5%~D RH28 8.2K_0402_5%~D
2 1 PCH_INTVRMEN C17 V5 IRQ_SERIRQ
INTVRMEN SERIRQ IRQ_SERIRQ <34,35,40,41> PCH_AZ_SYNC_Q 2
@CH100
@ CH100 1
27P_0402_50V8J~D RH41 10K_0402_5%~D
1 1 2 2 1 1 2 2 SATA0RXN AM3 PSATA_PRX_DTX_N0_C <28>
1 2 PCH_AZ_BITCLK N34 AM1 BBS_BIT0_R 1 2
<45> PCH_AZ_MDC_BITCLK HDA_BCLK SATA0RXP PSATA_PRX_DTX_P0_C <28>
SATA 6G
RH32 33_0402_5%~D AP7 HDD RH52 4.7K_0402_5%~D
SATA0TXN PSATA_PTX_DRX_N0_C <28>
<45> PCH_AZ_MDC_SYNC 1 2PCH_AZ_SYNC_Q PCH_AZ_SYNC L34 AP5
@ @ RH33 33_0402_5%~D HDA_SYNC SATA0TXP PSATA_PTX_DRX_P0_C <28>
ME1 SHORT PADS~D CMOS1 SHORT PADS~D T10 AM10
<30> SPKR SPKR SATA1RXN SATA_ODD_PRX_DTX_N1_C <29>
1 2 1 2 SATA1RXP AM8 SATA_ODD_PRX_DTX_P1_C <29>
CH5 1U_0402_6.3V6K~D CH4 1U_0402_6.3V6K~D 1 2 PCH_AZ_RST# K34 AP11 ODD/ E Module Bay
<45> PCH_AZ_MDC_RST# HDA_RST# SATA1TXN SATA_ODD_PTX_DRX_N1_C <29>
CMOS place near DIMM RH34 33_0402_5%~D AP10
C
SATA1TXP SATA_ODD_PTX_DRX_P1_C <29> C
PCH_AZ_CODEC_SDIN0 E34 AD7 +3.3V_RUN
<30> PCH_AZ_CODEC_SDIN0 HDA_SDIN0 SATA2RXN
AD5
SATA2RXP
<30> PCH_AZ_CODEC_SDOUT 1 2 PCH_AZ_SDOUT <45> PCH_AZ_MDC_SDIN1
PCH_AZ_MDC_SDIN1 G34 HDA_SDIN1 SATA2TXN AH5
RH29 33_0402_5%~D AH4 SPKR 2 1
SATA2TXP
<30> PCH_AZ_CODEC_SYNC 1 2 PCH_AZ_SYNC_Q C34 @ RH35 10K_0402_5%~D
IHDA
RH26 33_0402_5%~D +3.3V_ALW_PCH HDA_SDIN2
AB8
SATA3RXN
<30> PCH_AZ_CODEC_RST# 1 2 PCH_AZ_RST# 1 2 A34 HDA_SDIN3 SATA3RXP AB10 No Reboot Strap
RH27 33_0402_5%~D @RH287
@ RH287 1K_0402_5%~D AF3
SATA3TXN
<30> PCH_AZ_CODEC_BITCLK 1 2 PCH_AZ_BITCLK <45> PCH_AZ_MDC_SDOUT 1 2 AF1 Low = Default
PCH_AZ_SDOUT SATA3TXP
1 RH25 33_0402_5%~D RH36 33_0402_5%~D A36 SPKR
SATA
HDA_SDO
<40> ME_FWP 1 2 Y7 ESATA_PRX_DTX_N4_C <45>
High = No Reboot
@CH101
@ CH101 +3.3V_ALW_PCH RH50 1K_0402_5%~D SATA4RXN
Y5 ESATA_PRX_DTX_P4_C <45>
27P_0402_50V8J~D PCH_GPIO33 SATA4RXP
2
C36
HDA_DOCK_EN# / GPIO33 SATA4TXN
AD3
ESATA_PTX_DRX_N4_C <45> E-SATA
AD1
SATA4TXP ESATA_PTX_DRX_P4_C <45>
1
USB30_SMI# N32
<29> USB30_SMI# HDA_DOCK_RST# / GPIO13
RH288 Y3
SATA5RXN SATA_PRX_DKTX_N5_C <39>
0_0603_5%~D Y1
SATA5RXP SATA_PRX_DKTX_P5_C <39>
SATA5TXN AB3
SATA_PTX_DKRX_N5_C <39> DOCK
RH59 2 1 51_0402_1%~D PCH_JTAG_TCK J3 AB1
2
JTAG_TCK SATA5TXP SATA_PTX_DKRX_P5_C <39>

+3.3V_ALW_PCH_JTAG RH44 2 1 200_0402_1%~D PCH_JTAG_TMS H7 Y11 +1.05V_RUN
JTAG
JTAG_TMS SATAICOMPO
RH45 2 1 200_0402_1%~D PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2
JTAG_TDI SATAICOMPI RH40 37.4_0402_1%~D
RH43 2 1 200_0402_1%~D PCH_JTAG_TDO H1
+3.3V_RUN JTAG_TDO +1.05V_RUN
AB12
SATA3RCOMPO
100_0402_1%~D
100_0402_1%~D
100_0402_1%~D
AB13 SATA3_COMP 1 2
SATA3COMPI
1
RH42 49.9_0402_1%~D
1
+3.3V_RUN
RH48
RH49
RH47
@RH295
@ RH295 SPI_MOSI (PCH_SPI_DO) PCH_SPI_CLK RBIAS_SATA3

T3 SPI_CLK SATA3RBIAS AH1 1 2
8.2K_0402_5%~D RH46 750_0402_1%~D
1
High: Enable Intel Anti-Theft Technology PCH_SPI_CS0# Y14
2
SPI_CS0# RH30
Left floating: Disable Intel Anti-Theft Technology
2
PCH_SPI_CS1# T1 10K_0402_5%~D
SPI
PCH_SPI_DO SPI_CS1# SATA_ACT#_R
P3
SATALED# SATA_ACT#_R <44>
2
1 2 PCH_SPI_DO V4 V14 HDD_DET#_R 1 2
SPI_MOSI SATA0GP / GPIO21 HDD_DET# <28>
@ R933 0_0402_5%~D RH290 0_0402_5%~D
B B
PCH_SPI_DIN U3 P1 BBS_BIT0_R 1 3
S
SPI_MISO SATA1GP / GPIO19 PCH_SATA_MOD_EN# <41>
S
PCH_AZ_SYNC_Q 3 1 PCH_AZ_SYNC
1 2 QH7 CougarPoint_Rev_1p0 QH1 BSS138W-7-F_SOT323-3~D
G
2
RH31 1M_0402_5%~D SSM3K7002FU_SC70-3~D
G
2
<7,17> PCH_PLTRST#
PCH_PLTRST#_EC BBS_BIT0 - BIOS BOOT STRAP BIT 0
<17,35,37,38,40,41> PCH_PLTRST#_EC
+3.3V_SPI C746 +3.3V_SPI C745

0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D
1 2 1 2
1
200 MIL SO8 200 MIL SO8

1
R890 R888 1
3.3K_0402_5%~D R891 3.3K_0402_5%~D JSPI1
64Mb Flash ROM 3.3K_0402_5%~D 16Mb Flash ROM R892 1 SPI_PCH_CS1# 1 2
U52 U53 3.3K_0402_5%~D 1 PCH_SPI_CS1# RH345 0_0402_5%~D
2
2
SPI_PCH_CS0# 2
1 2 SPI_PCH_CS0#_R 1 8 SPI_PCH_CS1# 1 2 SPI_PCH_CS1#_R 1 8 3 SPI_PCH_DO 1 2
2
R935 47_0402_5%~D /CS VCC R936 22_0402_5%~D /CS VCC 3 PCH_SPI_DO RH346 0_0402_5%~D
4
2
SPI_PCH_DIN 4
1 2 SPI_DIN64 2 7 SPI_PCH_DIN 1 2 SPI_DIN32 2 7 5 SPI_PCH_DIN 1 2
R894 33_0402_5%~D DO /HOLD R895 33_0402_5%~D DO /HOLD 5 PCH_SPI_DIN RH347 0_0402_5%~D
6
SPI_WP#_SEL SPI_CLK64 6
<40> SPI_WP#_SEL 1 2 3 /WP CLK 6 1 2 SPI_PCH_CLK SPI_WP#_SEL 1 2 3 /WP CLK 6 SPI_CLK32 1 2 SPI_PCH_CLK 7 7 SPI_PCH_CLK 1 2
@R898
@ R898 0_0402_5%~D R899 33_0402_5%~D @ R896 0_0402_5%~D R897 33_0402_5%~D 8 PCH_SPI_CLK RH348 0_0402_5%~D
SPI_DO64 8
4 5 1 2 SPI_PCH_DO 4 5 SPI_DO32 1 2 SPI_PCH_DO 9 SPI_PCH_CS0# 1 2
GND DIO R901 33_0402_5%~D GND DIO R900 33_0402_5%~D 9 PCH_SPI_CS0# RH349 0_0402_5%~D
10 10
11 11 +3.3V_SPI
W25Q64BVSSIG_SO8~D W25Q16BVSSIG_SO8~D 12 +3.3V_M
12
13
13
14 1 2
14 RH350 0_0402_5%~D
15
15
16 16
SPI_CLK32
SPI_CLK64
1
G1 17
1
@ 18
A @ RE2 G2 A
RE1 33_0402_5%~D
33_0402_5%~D
2
2
1 HRS_FH12-16S-0P5SH(55)~D
CONN@ 1 @ CONN@
@ CE1
CE2 27P_0402_50V8J~D
27P_0402_50V8J~D 2
2 DELL CONFIDENTIAL/PROPRIETARY
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, PCH (1/8)
LA-6562P
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
@ QH5A
2
DMN66D0LDW-7_SOT363-6~D
MEM_SMBCLK 6 1 DDR_XDP_WAN_SMBCLK <7,12,13,14,28,37>
5
MEM_SMBDATA 3 4 DDR_XDP_WAN_SMBDAT <7,12,13,14,28,37>
@ QH5B
D Follow DG0.9 Device down UH4B DMN66D0LDW-7_SOT363-6~D D
& Express/Mini card 1 2

PCIE_PRX_WANTX_N1 RH296 0_0402_5%~D
topology <37> PCIE_PRX_WANTX_N1 PCIE_PRX_WANTX_P1
BG34
BJ34
PERN1
E12 PCH_SMB_ALERT#
<37> PCIE_PRX_WANTX_P1 PERP1 SMBALERT# / GPIO11 +3.3V_ALW_PCH
MiniWWAN (Mini Card 1)---> PCIE_PTX_WANRX_N1 AV32 1 2
<37> PCIE_PTX_WANRX_N1 PCIE_PTX_WANRX_P1 PETN1 MEM_SMBCLK RH297 0_0402_5%~D
AU32 H14
<37> PCIE_PTX_WANRX_P1 PETP1 SMBCLK
PCIE_PRX_WLANTX_N2 BE34 C9 MEM_SMBDATA SML1_SMBCLK 1 2
<37> PCIE_PRX_WLANTX_N2 PERN2 SMBDATA
PCIE_PRX_WLANTX_P2 BF34 RH298 2.2K_0402_5%~D
<37> PCIE_PRX_WLANTX_P2 PCIE_PTX_WLANRX_N2 PERP2 SML1_SMBDATA
MiniWLAN (Mini Card 2)---> <37> PCIE_PTX_WLANRX_N2 BB32 PETN2 1 2
PCIE_PTX_WLANRX_P2 AY32 RH299 2.2K_0402_5%~D
SMBUS
<37> PCIE_PTX_WLANRX_P2 PETP2 DDR_HVREF_RST_PCH
SML0ALERT# / GPIO60 A12
PCIE_PRX_EXPTX_N3 DDR_HVREF_RST_PCH <7> +3.3V_ALW_PCH
<38> PCIE_PRX_EXPTX_N3 BG36
PCIE_PRX_EXPTX_P3 PERN3 LAN_SMBCLK
<38> PCIE_PRX_EXPTX_P3 BJ36 C8
PCIE_PTX_EXPRX_N3 PERP3 SML0CLK LAN_SMBCLK <32>
EXPRESS Card---> <38> PCIE_PTX_EXPRX_N3
AV34
PETN3
PCIE_PTX_EXPRX_P3 AU34 G12 LAN_SMBDATA DDR_HVREF_RST_PCH 2 1
<38> PCIE_PTX_EXPRX_P3 PETP3 SML0DATA LAN_SMBDATA <32>
RH300 1K_0402_5%~D
PCIE_PRX_EMBTX_N4 BF36 GPIO74 2 1
<29> PCIE_PRX_EMBTX_N4 PCIE_PRX_EMBTX_P4 PERN4
BE36 RH301 10K_0402_5%~D
<29> PCIE_PRX_EMBTX_P4 PERP4
E3 Module Bay---> PCIE_PTX_EMBRX_N4 AY34 C13 GPIO74 MEM_SMBCLK 2 1
<29> PCIE_PTX_EMBRX_N4 PCIE_PTX_EMBRX_P4 PETN4 SML1ALERT# / PCHHOT# / GPIO74 @ RH302 2.2K_0402_5%~D
BB34
<29> PCIE_PTX_EMBRX_P4 PETP4 SML1_SMBCLK MEM_SMBDATA
E14 2 1
PCI-E*
PCIE_PRX_WPANTX_N5 SML1CLK / GPIO58 SML1_SMBCLK <41> @ RH303 2.2K_0402_5%~D
<37> PCIE_PRX_WPANTX_N5 BG37 PERN5
1/2vMINI CARD-3 PCIE PCIE_PRX_WPANTX_P5 BH37 M16 SML1_SMBDATA PCH_SMB_ALERT# 2 1
<37> PCIE_PRX_WPANTX_P5 PERP5 SML1DATA / GPIO75 SML1_SMBDATA <41>
PCIE_PTX_WPANRX_N5 AY36 RH304 10K_0402_5%~D
(Mini Card 3)---> <37> PCIE_PTX_WPANRX_N5 PCIE_PTX_WPANRX_P5 BB36
PETN5 PEG_A_CLKRQ# 2 1
<37> PCIE_PTX_WPANRX_P5 PETP5 RH80 10K_0402_5%~D
PCIE_PRX_MMITX_N6 BJ38
<36> PCIE_PRX_MMITX_N6 PERN6
PCIE_PRX_MMITX_P6 BG38
<36> PCIE_PRX_MMITX_P6
Controller
PCIE_PTX_MMIRX_N6 PERP6 PCH_CL_CLK1 +3.3V_LAN
MMI ---> <36> PCIE_PTX_MMIRX_N6
AU36
PETN6 CL_CLK1
M7 PCH_CL_CLK1 <37>
PCIE_PTX_MMIRX_P6 AV36
C <36> PCIE_PTX_MMIRX_P6 PETP6 C
Link
PCIE_PRX_GLANTX_N7 BG40 T11 PCH_CL_DATA1 LAN_SMBCLK 2 1
<32> PCIE_PRX_GLANTX_N7 PCIE_PRX_GLANTX_P7 PERN7 CL_DATA1 PCH_CL_DATA1 <37>
BJ40 RH305 2.2K_0402_5%~D
<32> PCIE_PRX_GLANTX_P7 PERP7
10/100/1G LAN ---> PCIE_PTX_GLANRX_N7 AY40 LAN_SMBDATA 2 1
<32> PCIE_PTX_GLANRX_N7 PCIE_PTX_GLANRX_P7 PETN7 PCH_CL_RST1# RH306 2.2K_0402_5%~D
BB40 PETP7 CL_RST1# P10
<32> PCIE_PTX_GLANRX_P7 PCH_CL_RST1# <37>
BE38 PERN8
BC38
PERP8
AW38 PETN8
AY38
PETP8
M10 PEG_A_CLKRQ#
PCIE_MINI1# PEG_A_CLKRQ# / GPIO47
2 1 Y40 CLKOUT_PCIE0N
<37> CLK_PCIE_MINI1# RH3072 PCIE_MINI1
1 0_0402_5%~D Y39
<37> CLK_PCIE_MINI1 CLKOUT_PCIE0P
MiniWWAN (Mini Card 1)---> +3.3V_ALW_PCH RH3082 1 0_0402_5%~D
CLKOUT_PEG_A_N
AB37
CLOCKS
RH81 10K_0402_5%~D MINI1CLK_REQ# J2 AB38
<37> MINI1CLK_REQ# PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P
2 1 PCIE_LAN# AB49 AV22 CLK_CPU_DMI#

<32> CLK_PCIE_LAN# RH82 2 PCIE_LAN CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI CLK_CPU_DMI# <7>
1 0_0402_5%~D AB47 CLKOUT_PCIE1P CLKOUT_DMI_P AU22
<32> CLK_PCIE_LAN CLK_CPU_DMI <7>
10/100/1G LAN ---> RH83 0_0402_5%~D
LANCLK_REQ# M1 CLK_BUF_DMI# 1 2
<32> LANCLK_REQ# PCIECLKRQ1# / GPIO18 CLK_CPU_DPLL# CLK_BUF_DMI
AM12 RH74 1 2 10K_0402_5%~D
CLKOUT_DP_N CLK_CPU_DPLL CLK_CPU_DPLL# <7> RH75 10K_0402_5%~D
AM13
PCIE_MMI# CLKOUT_DP_P CLK_CPU_DPLL <7>
2 1 AA48
<36> CLK_PCIE_MMI# PCIE_MMI CLKOUT_PCIE2N CLK_BUF_BCLK
MMI Card---> <36> CLK_PCIE_MMI
RH85 2 1 0_0402_5%~D AA47
CLKOUT_PCIE2P
1 2
RH86 1 2 0_0402_5%~D BF18 CLK_BUF_DMI# RH91 10K_0402_5%~D
+3.3V_RUN CLKIN_DMI_N
RH87 10K_0402_5%~D MMICLK_REQ# V10 BE18 CLK_BUF_DMI
<36> MMICLK_REQ# PCIECLKRQ2# / GPIO20 CLKIN_DMI_P
CLK_BUF_DOT96# 1 2
2 1 PCIE_MINI3# Y37 BJ30 CLK_BUF_BCLK CLK_BUF_DOT96 RH76 1 2 10K_0402_5%~D
<37> CLK_PCIE_MINI3# PCIE_MINI3 CLKOUT_PCIE3N CLKIN_GND1_N CLK_BUF_BCLK
B
MiniWPAN (Mini Card 3)---> <37> CLK_PCIE_MINI3
RH88 2 1 0_0402_5%~D Y36
CLKOUT_PCIE3P CLKIN_GND1_P
BG30 RH77 10K_0402_5%~D
B
+3.3V_ALW_PCH RH90 2 1 0_0402_5%~D
RH152 10K_0402_5%~D MINI3CLK_REQ# A8 CLK_BUF_CKSSCD# 1 2
<37> MINI3CLK_REQ# PCIECLKRQ3# / GPIO25 CLK_BUF_DOT96# CLK_BUF_CKSSCD
G24 RH78 1 2 10K_0402_5%~D
CLKIN_DOT_96N CLK_BUF_DOT96 RH79 10K_0402_5%~D
CLKIN_DOT_96P E24
2 1 PCIE_EXP# Y43
<38> CLK_PCIE_EXP# PCIE_EXP CLKOUT_PCIE4N CLK_PCH_14M
Express card---> <38> CLK_PCIE_EXP
RH92 2 1 0_0402_5%~D Y45
CLKOUT_PCIE4P
1 2
RH93 2 1 0_0402_5%~D AK7 CLK_BUF_CKSSCD# RH183 10K_0402_5%~D
+3.3V_ALW_PCH CLKIN_SATA_N
RH94 10K_0402_5%~D EXPCLK_REQ# L12 AK5 CLK_BUF_CKSSCD
<38> EXPCLK_REQ# PCIECLKRQ4# / GPIO26 CLKIN_SATA_P
2 1 PCIE_MINI2# V45 K45 CLK_PCH_14M

<37> CLK_PCIE_MINI2# CLKOUT_PCIE5N REFCLK14IN
RH95 2 1 0_0402_5%~D PCIE_MINI2 V46 CLOCK TERMINATION for FCIM and need close to PCH
<37> CLK_PCIE_MINI2 CLKOUT_PCIE5P
MiniWLAN (Mini Card 2)---> +3.3V_ALW_PCH RH96 2 1 0_0402_5%~D
RH97 10K_0402_5%~D MINI2CLK_REQ# L14 H45 CLK_PCI_LOOPBACK
<37> MINI2CLK_REQ# PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LOOPBACK <17>
AB42 V47 XTAL25_IN 2 1

CLKOUT_PEG_B_N XTAL25_IN XTAL25_OUT RH309 0_0402_5%~D
AB40 V49
CLKOUT_PEG_B_P XTAL25_OUT
1
1 2 PEG_B_CLKRQ# E6 RH99
+3.3V_ALW_PCH PEG_B_CLKRQ# / GPIO56
RH98 10K_0402_5%~D 1M_0402_5%~D
Y47 XCLK_RCOMP 1 2 YH2
XCLK_RCOMP +1.05V_RUN
V40 RH100 90.9_0402_1%~D 25MHZ_12PF_X5H025000DC1H-H
2
CLKOUT_PCIE6N
V42 CLKOUT_PCIE6P 2 1
12P_0402_50V8J~D
12P_0402_50V8J~D
T13
PCIECLKRQ6# / GPIO45
2 2
2 1 PCIE_EMB# V38 K43 PCI_TCM 4@ RH311 2 1 22_0402_5%~D
CH18
CH19
<29> CLK_PCIE_EMB# PCIE_EMB CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 CLK_PCI_TPM_CHA <35>
eModule Bay---> <29> CLK_PCIE_EMB
RH3102 1 0_0402_5%~D V37
CLKOUT_PCIE7P
RH3122 1 0_0402_5%~D F47 SIO_14M RH313 2 1 22_0402_5%~D
+3.3V_ALW_PCH CLKOUTFLEX1 / GPIO65 CLK_SIO_14M <40> 1 1
RH104 10K_0402_5%~D EMBCLK_REQ# K12
<29> EMBCLK_REQ# PCIECLKRQ7# / GPIO46 PCI_TPM
H47 RH314 2 1 22_0402_5%~D
A CLK_BCLK_ITP# AK14 CLKOUTFLEX2 / GPIO66 CLK_PCI_TPM <34> A
<7> CLK_CPU_ITP# 2 1
RH2802 CLK_BCLK_ITP AK13 CLKOUT_ITPXDP_N JETWAY_14M @ RH315
<7> CLK_CPU_ITP 1 0_0402_5%~D CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 K49 2 1 22_0402_5%~D JETWAY_CLK14M <35>
RH281 0_0402_5%~D
CougarPoint_Rev_1p0
PCIE REQ power rail:
suspend: 0 3 4 5 6 7 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
core: 1 2 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, PCH (2/8)
LA-6562P
Date: Friday, October 15, 2010 Sheet 15 of 66
5 4 3 2 1
5 4 3 2 1
1 2 PCH_CRT_BLU
+3.3V_ALW_PCH RH131 150_0402_1%~D +3.3V_RUN
1 2 PCH_CRT_GRN
RH132 150_0402_1%~D
2.2K_0402_5%~D
2.2K_0402_5%~D
1 2 PCH_CRT_RED
1
RH133 150_0402_1%~D
RH316
RH317
1 2 SUS_STAT#/LPCPD# 1 2 ENVDD_PCH
@ RH318 10K_0402_5%~D RH134 100K_0402_5%~D
1 2 ME_SUS_PWR_ACK
2
RH144 10K_0402_5%~D PCH_DPWROK 1 2 PCH_RSMRST#_R
RH113 0_0402_5%~D
1 2 PCH_PCIE_WAKE# G_CLK_DDC2 1 6 PCH_CRT_DDC_CLK
D PCH_CRT_DDC_CLK <25> D
RH142 10K_0402_5%~D DSWODVREN - On Die DSW VR Enable
QH6A
1 2 SIO_SLP_LAN# RESET_OUT# 1 2 SYS_PWROK Enabled (DEFAULT) DMN66D0LDW-7_SOT363-6~D
2
@ RH319 10K_0402_5%~D @ RH321 0_0402_5%~D +3.3V_RUN
HIGH: RH127 STUFFED,
5
1 2 PCH_RI# RH129 UNSTUFFED QH6B
RH140 10K_0402_5%~D DMN66D0LDW-7_SOT363-6~D
G_DAT_DDC2 4 3 PCH_CRT_DDC_DAT
PCH_CRT_DDC_DAT <25>
1 2 SIO_PWRBTN#_R ME_SUS_PWR_ACK_R 1 2 SUSACK#_R Disabled
@ RH356 10K_0402_5%~D RH323 0_0402_5%~D
LOW: RH129 STUFFED,
RH127 UNSTUFFED
+3.3V_RUN
+3.3V_RUN
PCH_RSMRST# 1 2
1 2 CLKRUN# RH322 10K_0402_5%~D PCH_SDVO_CTRLCLK 2 1
RH137 8.2K_0402_5%~D RH351 2.2K_0402_5%~D
PCH_SDVO_CTRLDATA 2 1
RH352 2.2K_0402_5%~D
UH4C Intel request DDPB can not support eDP

UH4D
DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0
<6> DMI_CTX_PRX_N0 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N0 <6>
DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1 PANEL_BKEN_PCH J47 AP43
<6> DMI_CTX_PRX_N1 DMI1RXN FDI_RXN1 FDI_CTX_PRX_N1 <6> <24> PANEL_BKEN_PCH L_BKLTEN SDVO_TVCLKINN
DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2 ENVDD_PCH M45 AP45
<6> DMI_CTX_PRX_N2 DMI2RXN FDI_RXN2 FDI_CTX_PRX_N2 <6> <24,40> ENVDD_PCH L_VDD_EN SDVO_TVCLKINP
DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3
<6> DMI_CTX_PRX_N3 DMI3RXN FDI_RXN3 FDI_CTX_PRX_N3 <6>
BC12 FDI_CTX_PRX_N4 BIA_PWM_PCH P45 AM42
FDI_RXN4 FDI_CTX_PRX_N4 <6> <24> BIA_PWM_PCH L_BKLTCTL SDVO_STALLN
DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5 AM40
<6> DMI_CTX_PRX_P0 DMI0RXP FDI_RXN5 FDI_CTX_PRX_N5 <6> SDVO_STALLP
DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6 LDDC_CLK_PCH T40
C <6> DMI_CTX_PRX_P1 DMI1RXP FDI_RXN6 FDI_CTX_PRX_N6 <6> <24> LDDC_CLK_PCH L_DDC_CLK C
DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7 LDDC_DATA_PCH K47 AP39
<6> DMI_CTX_PRX_P2 DMI2RXP FDI_RXN7 FDI_CTX_PRX_N7 <6> <24> LDDC_DATA_PCH L_DDC_DATA SDVO_INTN
DMI_CTX_PRX_P3 BJ20 AP40
<6> DMI_CTX_PRX_P3 DMI3RXP SDVO_INTP
BG14 FDI_CTX_PRX_P0 T45
FDI_RXP0 FDI_CTX_PRX_P0 <6> L_CTRL_CLK
DMI_CRX_PTX_N0 AW24 BB14 FDI_CTX_PRX_P1 P39
<6> DMI_CRX_PTX_N0 DMI0TXN FDI_RXP1 FDI_CTX_PRX_P1 <6> L_CTRL_DATA
DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2
<6> DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2 FDI_CTX_PRX_P2 <6>
DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3 1 2 LVD_IBG AF37 P38 PCH_SDVO_CTRLCLK PCH_SDVO_CTRLCLK <26>
<6> DMI_CRX_PTX_N2 DMI2TXN FDI_RXP3 FDI_CTX_PRX_P3 <6> LVD_IBG SDVO_CTRLCLK
DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4 RH344 2.37K_0402_1%~D AF36 M39 PCH_SDVO_CTRLDATA
DMI
FDI
<6> DMI_CRX_PTX_N3 DMI3TXN FDI_RXP4 FDI_CTX_PRX_P4 <6> LVD_VBG SDVO_CTRLDATA PCH_SDVO_CTRLDATA <26>
FDI_RXP5
BG12 FDI_CTX_PRX_P5
FDI_CTX_PRX_P5 <6> Minimum speacing of 20mils for LVD_IBG
DMI_CRX_PTX_P0 AY24 BJ10 FDI_CTX_PRX_P6 AE48
<6> DMI_CRX_PTX_P0 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P6 <6> LVD_VREFH
DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7 AE47 AT49
<6> DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7 FDI_CTX_PRX_P7 <6> LVD_VREFL DDPB_AUXN
DMI_CRX_PTX_P2 AY18 AT47
<6> DMI_CRX_PTX_P2 DMI2TXP DDPB_AUXP
DMI_CRX_PTX_P3 AU18 AT40
<6> DMI_CRX_PTX_P3 DMI3TXP DDPB_HPD HDMIB_PCH_HPD <26>
AW16 FDI_INT LCD_ACLK-_PCH AK39
LVDS
+1.05V_RUN FDI_INT FDI_INT <6> <24> LCD_ACLK-_PCH LVDSA_CLK#
LCD_ACLK+_PCH AK40 AV42
<24> LCD_ACLK+_PCH LVDSA_CLK DDPB_0N TMDSB_PCH_N2 <26>
BJ24 AV12 FDI_FSYNC0 AV40
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 <6> DDPB_0P TMDSB_PCH_P2 <26>
LCD_A0-_PCH AN48 AV45
<24> LCD_A0-_PCH LVDSA_DATA#0 DDPB_1N TMDSB_PCH_N1 <26>
1 2 DMI_COMP_R BG25 BC10 FDI_FSYNC1 LCD_A1-_PCH AM47 AV46
Digital Display Interface

DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 <6> <24> LCD_A1-_PCH LVDSA_DATA#1 DDPB_1P TMDSB_PCH_P1 <26>
RH111 49.9_0402_1%~D LCD_A2-_PCH AK47 AU48
<24> LCD_A2-_PCH LVDSA_DATA#2 DDPB_2N TMDSB_PCH_N0 <26>
1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0 AJ48 AU47
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 <6> LVDSA_DATA#3 DDPB_2P TMDSB_PCH_P0 <26>
RH112 750_0402_1%~D AV47
FDI_LSYNC1 LCD_A0+_PCH DDPB_3N TMDSB_PCH_CLK# <26>
BB10 FDI_LSYNC1 <6> <24> LCD_A0+_PCH AN47 AV49 TMDSB_PCH_CLK <26>
FDI_LSYNC1 LCD_A1+_PCH LVDSA_DATA0 DDPB_3P
<24> LCD_A1+_PCH AM49
+RTC_CELL LCD_A2+_PCH LVDSA_DATA1
<24> LCD_A2+_PCH AK49
LVDSA_DATA2
AJ47 P46 PCH_DDPC_CTRLCLK <27>
RH127 1 LVDSA_DATA3 DDPC_CTRLCLK
A18 DSWODVREN 2 330K_0402_1%~D P42 PCH_DDPC_CTRLDATA <27>
DSWVRMEN DDPC_CTRLDATA
System Power Management
@ RH129 1 2 330K_0402_1%~D LCD_BCLK-_PCH AF40

<24> LCD_BCLK-_PCH LVDSB_CLK#
1 2 SUSACK#_R C12 E22 PCH_DPWROK LCD_BCLK+_PCH AF39 AP47
<40> SUSACK# SUSACK# DPWROK PCH_DPWROK <40> <24> LCD_BCLK+_PCH LVDSB_CLK DDPC_AUXN DPC_PCH_DOCK_AUX# <27>
@ RH114 0_0402_5%~D AP49
LCD_B0-_PCH DDPC_AUXP DPC_PCH_DOCK_AUX <27>
<24> LCD_B0-_PCH AH45 AT38 DPC_PCH_DOCK_HPD <39>
XDP_DBRESET# PCH_PCIE_WAKE# LCD_B1-_PCH LVDSB_DATA#0 DDPC_HPD
<7,14> XDP_DBRESET# K3 B9 PCH_PCIE_WAKE# <40> <24> LCD_B1-_PCH AH47
SYS_RESET# WAKE# LCD_B2-_PCH LVDSB_DATA#1
<24> LCD_B2-_PCH AF49 AY47 DPC_PCH_LANE_N0 <39>
B LVDSB_DATA#2 DDPC_0N B
AF45 AY49 DPC_PCH_LANE_P0 <39>
SYS_PWROK_R CLKRUN# LVDSB_DATA#3 DDPC_0P
<7,40> SYS_PWROK 1 2 P12 N3 CLKRUN# <35,40,41> AY43 DPC_PCH_LANE_N1 <39>
RH116 0_0402_5%~D SYS_PWROK CLKRUN# / GPIO32 LCD_B0+_PCH DDPC_1N
<24> LCD_B0+_PCH AH43 AY45 DPC_PCH_LANE_P1 <39>
LCD_B1+_PCH LVDSB_DATA0 DDPC_1P
<24> LCD_B1+_PCH AH49 BA47 DPC_PCH_LANE_N2 <39>
PCH_PWROK SUS_STAT#/LPCPD# T56 PAD~D LCD_B2+_PCH LVDSB_DATA1 DDPC_2N
<41> RESET_OUT# 1 2 L22 G8 <24> LCD_B2+_PCH AF47 BA48 DPC_PCH_LANE_P2 <39>
RH117 0_0402_5%~D PWROK SUS_STAT# / GPIO61 LVDSB_DATA2 DDPC_2P
AF43 BB47 DPC_PCH_LANE_N3 <39>
LVDSB_DATA3 DDPC_3N
BB49 DPC_PCH_LANE_P3 <39>
PM_APWROK_R SUSCLK T57 PAD~D DDPC_3P
<41> PM_APWROK 1 2 L10 N14
RH118 0_0402_5%~D APWROK SUSCLK / GPIO62
T58 PAD~D PCH_CRT_BLU N48 M43 PCH_DDPD_CTRLCLK <27>
<25> PCH_CRT_BLU CRT_BLUE DDPD_CTRLCLK
1 2 PM_DRAM_PWRGD_R B13 D10 SIO_SLP_S5# PCH_CRT_GRN P49 M36
<7> PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 SIO_SLP_S5# <41> <25> PCH_CRT_GRN CRT_GREEN DDPD_CTRLDATA PCH_DDPD_CTRLDATA <27>
RH320 0_0402_5%~D PCH_CRT_RED T49
<25> PCH_CRT_RED CRT_RED
T59 PAD~D
1 2 PCH_RSMRST#_R C21 H4 SIO_SLP_S4# AT45
CRT
<14,41> PCH_RSMRST# RSMRST# SLP_S4# SIO_SLP_S4# <40> DDPD_AUXN DPD_PCH_DOCK_AUX# <27>
RH120 0_0402_5%~D G_CLK_DDC2 T39 AT43
T60 PAD~D G_DAT_DDC2 CRT_DDC_CLK DDPD_AUXP DPD_PCH_DOCK_AUX <27>
M40 BH41 DPD_PCH_DOCK_HPD <39>
ME_SUS_PWR_ACK_R SIO_SLP_S3# CRT_DDC_DATA DDPD_HPD
<41> ME_SUS_PWR_ACK 1 2 K16 F4 SIO_SLP_S3# <40>
RH121 0_0402_5%~D SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# RH123 20_0402_1%~D BB43 DPD_PCH_LANE_N0 <39>
T61 PAD~D DDPD_0N
<7,14> SIO_PWRBTN#_R <25> PCH_CRT_HSYNC 1 2 HSYNC M47 BB45 DPD_PCH_LANE_P0 <39>
SIO_PWRBTN#_R SIO_SLP_A# CRT_HSYNC DDPD_0P
<41> SIO_PWRBTN# 1 2 E20 G10 SIO_SLP_A# <40,51> <25> PCH_CRT_VSYNC 1 2 VSYNC M49 BF44 DPD_PCH_LANE_N1 <39>
RH122 0_0402_5%~D PWRBTN# SLP_A# RH124 20_0402_1%~D CRT_VSYNC DDPD_1N
BE44 DPD_PCH_LANE_P1 <39>
T62 PAD~D DDPD_1P
BF42 DPD_PCH_LANE_N2 <39>
AC_PRESENT SIO_SLP_SUS# CRT_IREF DDPD_2N
<41> AC_PRESENT H20 G16 SIO_SLP_SUS# <40> T43 BE42 DPD_PCH_LANE_P2 <39>
ACPRESENT / GPIO31 SLP_SUS# DAC_IREF DDPD_2P
T42 BJ42 DPD_PCH_LANE_N3 <39>
T63 PAD~D CRT_IRTN DDPD_3N
BG42 DPD_PCH_LANE_P3 <39>
DDPD_3P
1
+3.3V_ALW_PCH 1 2 PCH_BATLOW# E10 AP14 H_PM_SYNC
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC <7>
RH139 8.2K_0402_5%~D CougarPoint_Rev_1p0
RH126
PCH_RI# A10 K14 SIO_SLP_LAN# 1K_0402_0.5%~D
RI# SLP_LAN# / GPIO29 SIO_SLP_LAN# <32,40>
2
CougarPoint_Rev_1p0
A A
Compal Electronics, Inc. Compal Electronics, Inc.
LA-6562P
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
1 2 PCI_PIRQA#
RH324 8.2K_0402_5%~D
UH4E
D PCI_PIRQB# D
1 2 RSVD1 AY7
RH325 8.2K_0402_5%~D AV7
PAD~D T72 @ RSVD2
BG26 TP1 RSVD3 AU3
1 2 PCI_PIRQC# PAD~D T64 @ BJ26 BG4
RH326 8.2K_0402_5%~D PAD~D T73 @ TP2 RSVD4
BH25
PAD~D T65 @ TP3
BJ16 TP4 RSVD5 AT10
1 2 PCI_PIRQD# PAD~D T74 @ BG16 BC8
RH329 8.2K_0402_5%~D PAD~D T66 @ TP5 RSVD6
AH38 TP6
PAD~D T67 @ AH37 AU2
PCI_REQ1# PAD~D T75 @ TP7 RSVD7
1 2 AK43 AT4
RH327 10K_0402_5%~D PAD~D T76 @ TP8 RSVD8
AK45 TP9 RSVD9 AT3
PAD~D T77 @ C18 AT1
LVDS_CBL_DET# PAD~D T68 @ TP10 RSVD10
1 2 N30 TP11 RSVD11 AY3
RH330 10K_0402_5%~D PAD~D T69 @ H3 AT5
PAD~D T78 @ TP12 RSVD12
AH12 AV3
CAM_MIC_CBL_DET# PAD~D T79 @ TP13 RSVD13
1 2 AM4 AV1
RH331 10K_0402_5%~D PAD~D T80 @ TP14 RSVD14
AM5 TP15 RSVD15 BB1
PAD~D T70 @ Y13 BA3
BT_DET# PAD~D T81 @ TP16 RSVD16
1 2 K24 TP17 RSVD17 BB5
RH328 10K_0402_5%~D PAD~D T71 @ L24 BB3
AB46 BB7
PCH_GPIO3 PAD~D T83 @ TP19 RSVD19
1 2 AB45 BE8
RSVD
@ RH332 10K_0402_5%~D TP20 RSVD20
RSVD21 BD4
RSVD22 BF6
PAD~D T84 @ B21 AV5

M20 AV10
AY16
PAD~D T87 @ TP23
BG46 TP24 RSVD25 AT8
AY5
RSVD26
BA2
C PAD~D T88 @ RSVD27 C
BE28 TP25
PAD~D T89 @ BC30 AT12
BE32 BF3
BJ32 TP28
PAD~D T92 @ BC28
PAD~D T93 @ TP29
BE30
PAD~D T94 @ TP30
BF32 TP31
PAD~D T95 @ BG32 C24 USBP0-
TP32 USBP0N USBP0- <45>
PCI_GNT3# PAD~D T96 @ AV26 TP33 USBP0P A24 USBP0+
USBP0+ <45>
----->Right Side Top
PAD~D T97 @ BB26 C25 USBP1-
PAD~D T98 @ AU28 TP35 USBP1P B25 USBP1+
USBP1+ <45> ----->Right Side Bottom
1
PAD~D T99 @ AY30 C26 USBP2-

@ RH333 PAD~D T100 @ AU26 TP37 USBP2P A26 USBP2+
USBP2+ <46>
----->left Side Top
1K_0402_5%~D PAD~D T101 @ AY26 K28 USBP3-
PAD~D T102 @ AV28
TP39 USBP3P
H28 USBP3+
USBP3+ <46>
----->Left Side Bottom
PAD~D T103 @ AW30 E28 USBP4-
USBP4- <37>
2
TP40 USBP4N
USBP4P
D28 USBP4+
USBP4+ <37>
----->WLAN/WIMAX
C28 USBP5-
USBP5N USBP5- <37>
USBP5P
A28 USBP5+
USBP5+ <37>
----->WWAN/UWB
C29 USBP6-
USBP6N USBP6- <37>
USBP6P
B29 USBP6+
USBP6+ <37> ----->Flash
PCI_PIRQA# K40 N28 USBP7-
PIRQA# USBP7N USBP7- <34>
PCI_PIRQB# K38 M28 USBP7+ ----->USH
PCI
PIRQB# USBP7P USBP7+ <34>
A16 swap override Strap/Top-Block PCI_PIRQC# H38 L30 USBP8-
PIRQC# USBP8N USBP8- <39>
PCI_PIRQD# G38
PIRQD# USBP8P
K30 USBP8+
USBP8+ <39>
----->DOCK
Swap Override jumper G30 USBP9-
USBP9N USBP9- <39>
PCI_REQ1# C46 E30 USBP9+ ----->DOCK
USB
REQ1# / GPIO50 USBP9P USBP9+ <39>
C44 C30 USBP10-
<37> PCIE_MCARD2_DET#_R REQ2# / GPIO52 USBP10N USBP10- <38>
Low = A16 swap <42> BT_DET#
BT_DET# E40
REQ3# / GPIO54 USBP10P
A30 USBP10+
USBP10+ <38>
----->Express Card +3.3V_ALW_PCH
PCI_GNT#3 L32 USBP11-
USBP11N USBP11- <42>
High = Default BBS_BIT1 D47
GNT1# / GPIO51 USBP11P
K32 USBP11+
USBP11+ <42> ----->Blue Tooth RPH1
E42 G32 USBP12- USB_OC0# 4 5
GNT2# / GPIO53 USBP12N USBP12- <24>
B PCI_GNT3# F46 GNT3# / GPIO55 USBP12P E32 USBP12+
USBP12+ <24>
----->Camera USB_OC1# 3 6 B
C32 USBP13- USB_OC3# 2 7
USBP13N USBP13- <24>
USBP13P
A32 USBP13+
USBP13+ <24>
----->LCD Touch USB_OC4# 1 8
LVDS_CBL_DET# G42
<24> LVDS_CBL_DET# PIRQE# / GPIO2
PCH_GPIO3 G40 Within 500 mils 10K_1206_8P4R_5%~D
CAM_MIC_CBL_DET# PIRQF# / GPIO3 USBRBIAS RPH2
<24> CAM_MIC_CBL_DET# C42 C33 1 2
FFS_PCH_INT PIRQG# / GPIO4 USBRBIAS# RH151 USB_OC5#
<28> HDD_FALL_INT 1 2 D44 4 5
RH334 0_0402_5%~D PIRQH# / GPIO5 22.6_0402_1%~D USB_OC6# 3 6
<34> PLTRST_USH# 1 2 B33 2 7
RH3351 0_0402_5%~D PAD~D T104 @ USBRBIAS USB_OC2#
<36> PLTRST_MMI# 2 K10 PME# 1 8
RH3361 2 0_0402_5%~D
<7> PLTRST_XDP#
RH3371 2 0_0402_5%~D PCH_PLTRST# C6 A14 USB_OC0#_R 1 2 10K_1206_8P4R_5%~D
<32> PLTRST_LAN# PLTRST# OC0# / GPIO59 USB_OC1#_R USB_OC0# <45>
RH3381 2 0_0402_5%~D K20 RH3391 2 0_0402_5%~D
<29> PLTRST_EMB# OC1# / GPIO40 USB_OC2# USB_OC1# <46>
RH340 0_0402_5%~D B17 RH341 0_0402_5%~D
OC2# / GPIO41 USB_OC2# <14>
2 1 PCI_5048 H49 C16 USB_OC3# SIO_EXT_SMI# 2 1
<40> CLK_PCI_5048 PCI_MEC CLKOUT_PCI0 OC3# / GPIO42 USB_OC4# USB_OC3# <14>
RH160 2 1 22_0402_5%~D H43 L16 RH51 10K_0402_5%~D
<41> CLK_PCI_MEC CLKOUT_PCI1 OC4# / GPIO43 USB_OC4# <14>
RH102 1 2 22_0402_5%~D PCI_DOCK J48 A16 USB_OC5#
<39> CLK_PCI_DOCK CLKOUT_PCI2 OC5# / GPIO9 USB_OC6# USB_OC5# <14>
RH103 33_0402_5%~D K42 D14
PCI_LOOPBACKOUT CLKOUT_PCI3 OC6# / GPIO10 SIO_EXT_SMI# USB_OC6# <14>
<15> CLK_PCI_LOOPBACK 2 1 H40 C14 SIO_EXT_SMI# <14,41>
RH105 22_0402_5%~D CLKOUT_PCI4 OC7# / GPIO14
USB_OC0#_R <14>
CougarPoint_Rev_1p0
USB_OC1#_R <14>
+3.3V_RUN CH102
0.1U_0402_16V4Z~D
1 2
Boot BIOS Strap

5
A A
UH3 SATA_SLPD
PCH_PLTRST# 1 BBS_BIT1 (BBS_BIT0) Boot BIOS Location
P
<7,14> PCH_PLTRST# B PCH_PLTRST#_EC BBS_BIT1

O 4 PCH_PLTRST#_EC <14,35,37,38,40,41>
2
A
G
0 0 LPC
1
TC7SH08FU_SSOP5~D
3
@ RH342
0 1 Reserved (NAND) 1K_0402_5%~D
Title
2
1 0 PCI PCH (4/8)

1 1 SPI 0.3
* LA-6562P
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW_PCH +3.3V_RUN
2
RH53 CONTACTLESS_DET# 1 2
4.7K_0402_5%~D RH256 10K_0402_1%~D
D D
1
SLP_ME_CSW_DEV# UH4F
<14> SIO_EXT_SCI#_R
1
SIO_EXT_SCI# 1 2 T7 C40 CONTACTLESS_DET#

<41> SIO_EXT_SCI# BMBUSY# / GPIO0 TACH4 / GPIO68 CONTACTLESS_DET# <34>
RH353 RH259 0_0402_5%~D
1K_0402_5%~D PCH_GPIO1 A42 B41 GPIO69
TACH1 / GPIO1 TACH5 / GPIO69
@
IO_LOOP# H36 C41 PCIE_MCARD3_DET# GPIO69 1 2
<46> IO_LOOP# PCIE_MCARD3_DET# <37>
2
TACH2 / GPIO6 TACH6 / GPIO70 RH260 1.5K_0402_1%~D

IO1_LOOP# E38 A40
<46> IO1_LOOP# TACH3 / GPIO7 TACH7 / GPIO71 USB_MCARD2_DET# <37>
<14,40> SIO_EXT_WAKE# C10

GPIO8
Note: PCH has internal pull up 20k ohm on PM_LANPHY_ENABLE C4
<32> PM_LANPHY_ENABLE LAN_PHY_PWR_CTRL / GPIO12
E3_PAID_TS_DET# (GPIO27) <14> PCH_GPIO15
PCH_GPIO15 G2 P4 SIO_A20GATE
SIO_A20GATE <41>
GPIO15 A20GATE
AU16
EN_ESATA_RPTR# PECI
<14> EN_ESATA_RPTR# U2 SATA4GP / GPIO16
SLP_ME_CSW_DEV# PLL ON DIE VR ENABLE P5 SIO_RCIN#
RCIN# SIO_RCIN# <41>
+3.3V_RUN
GPIO
GPIO17 D40 AY11 H_CPUPWRGD +1.05V_RUN_VTT
CPU/MISC
TACH0 / GPIO17 PROCPWRGD H_CPUPWRGD <7>
ENABLED - HIGH DEFAULT
DISABLED - LOW MEDIA_DET# T5 AY10 PCH_THRMTRIP#_R 2 1 SIO_A20GATE 2 1
<46> MEDIA_DET# SCLOCK / GPIO22 THRMTRIP# RH262 56_0402_5%~D RH158 10K_0402_5%~D
E8 T14 INIT3_3V# PAD~D T106 1 SIO_RCIN# 2 1
<37> PCIE_MCARD1_DET# GPIO24 / MEM_LED INIT3_3V# @ RH203 10K_0402_5%~D
E3_PAID_TS_DET# E16 AY1 DF_TVS CH97
+3.3V_ALW_PCH <24> E3_PAID_TS_DET# GPIO27 DF_TVS 0.1U_0402_16V4Z~D
SLP_ME_CSW_DEV# P8 2 SIO_EXT_SCI# 1 2
<14,40> SLP_ME_CSW_DEV# GPIO28
AH8 RH263 10K_0402_5%~D
SIO_EXT_WAKE# TS_VSS1 PCH_GPIO1
1 2 K1 1 2
C RH177 1K_0402_5%~D STP_PCI# / GPIO34 RH164 10K_0402_5%~D C
TS_VSS2 AK11
1 2 PCH_GPIO15 USB_MCARD1_DET# K4
<14,37> USB_MCARD1_DET# GPIO35
RH354 1K_0402_5%~D AH10
GPIO36 TS_VSS3
<14> GPIO36 V8 SATA2GP / GPIO36
TS_VSS4 AK10
GPIO37 M5
<14> GPIO37 SATA3GP / GPIO37
TPM_ID0 N2 P37 NC_1 PAD~D T108 @
SLOAD / GPIO38 NC_1
TPM_ID1 M3
SDATAOUT0 / GPIO39
FFS_INT2 V13 BG2 VSS_NCTF_15
<28> FFS_INT2 SDATAOUT1 / GPIO48 VSS_NCTF_15
TEMP_ALERT# V3 BG48 VSS_NCTF_16
<14,40> TEMP_ALERT# SATA5GP / GPIO49 VSS_NCTF_16
KB_DET# D6 BH3 VSS_NCTF_17
<42> KB_DET# GPIO57 VSS_NCTF_17
BH47 VSS_NCTF_18
VSS_NCTF_18
VSS_NCTF_1 A4 BJ4 VSS_NCTF_19
VSS_NCTF_1 VSS_NCTF_19
NCTF
VSS_NCTF_7 B3 C2 VSS_NCTF_25
B VSS_NCTF_7 VSS_NCTF_25 B
VSS_NCTF_8 B47 C48 VSS_NCTF_26
Layout note: VSS_NCTF_9 BD1 D1 VSS_NCTF_27
Trace wide 10mil & length 30mil VSS_NCTF_10 VSS_NCTF_28
Layout note:
BD49 D49 PLACE RH150 CLOSE TO THE BRANCHING POINT
VSS_NCTF_10 VSS_NCTF_28 Trace wide 10mil & length 30mil
All NCTF pins should have thick VSS_NCTF_11 VSS_NCTF_29
( TO CPU and NVRAM CONNECTOR)
BE1 E1 All NCTF pins should have thick
traces at 45°from the pad. VSS_NCTF_11 VSS_NCTF_29
VSS_NCTF_12 BE49 VSS_NCTF_12 VSS_NCTF_30 E49 VSS_NCTF_30 traces at 45°from the pad.
+VCCDFTERM
VSS_NCTF_13 BF1 F1 VSS_NCTF_31
RH149 need to close to CPU
VSS_NCTF_14 BF49 F49 VSS_NCTF_32
1
+3.3V_ALW_PCH
RH149
2 1 KB_DET# CougarPoint_Rev_1p0 2.2K_0402_5%~D
RH170 10K_0402_5%~D
2
DF_TVS_R 1 2 DF_TVS
RH150 0_0402_5%~D
+3.3V_RUN
2 1 GPIO36
@ RH171 10K_0402_5%~D
2 1 GPIO37 +3.3V_RUN +3.3V_RUN
@ RH173 1K_0402_1%~D
2 1 EN_ESATA_RPTR# DMI & FDI Termination Voltage
RH265 10K_0402_5%~D
2
2 1 TEMP_ALERT#
RH266 10K_0402_5%~D 1@ RH267 3@ RH268 Set to Vss when LOW
2 1 MEDIA_DET# 10K_0402_5%~D 20K_0402_5%~D TPM_ID0 TPM_ID1 DF_TVS
A A
RH181 10K_0402_5%~D Set to Vcc when HIGH
China TPM 0 0
1
1 2 GPIO17 TPM_ID0 TPM_ID1

1 RH269 8.2K_0402_5%~D
2
2@ RH270 4@ RH271
USH1.0 (For SSI) 1 0
IO_LOOP#
1
RH163
2
10K_0402_5%~D
10K_0402_5%~D 2.2K_0402_5%~D USH2.0 1 1 Compal Electronics, Inc.
1 2 IO1_LOOP# Title
1
RH272 10K_0402_5%~D
PCH (5/8)
0.3
LA-6562P
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
LH1
PCH Power Rail Table
+1.05V_RUN UH4G POWER +VCCADAC 2 1 S0 Iccmax
BLM18PG181SN1_0603~D Voltage Rail Voltage Current (A)
0.01U_0402_16V7K~D
0.1U_0402_10V7K~D
10U_0805_4VAM~D
AA23 U48 1 1 1
VCCCORE[1] VCCADAC
AC23 VCCCORE[2]
V_PROC_IO 1.05 0.001
10U_0805_4VAM~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CH34
CH35
CH36
CRT
1 1 1 1 AD21
VCCCORE[3]
AD23 VCCCORE[4] VSSADAC U47
2 2 2
CH30
CH32
CH33
CH31
V5REF 5 0.001
VCC CORE
AF21
VCCCORE[5] +3.3V_RUN
AF23 VCCCORE[6]
D 2 2 2 2 AG21 D
VCCCORE[7]
AG23 VCCCORE[8]
V5REF_Sus 5 0.001
AG24 VCCCORE[9] VCCALVDS AK36
AG26
VCCCORE[10] +1.8V_RUN
AG27
VCCCORE[11] VSSALVDS
AK37 Vcc3_3 3.3 0.266
AG29 LH8
VCCCORE[12] HK1608R10J-T_0603~D
AJ23
LVDS
VCCCORE[13] +1.8V_RUN_LVDS
AJ26 VCCCORE[14] VCCTX_LVDS[1] AM37 2 1 VccADAC3 3.3 0.001
22U_0805_6.3VAM~D
AJ27 1 1 1 0.1uH inductor, 200mA
VCCCORE[15]
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
CH105
AJ29 AM38
VCCCORE[16] VCCTX_LVDS[2]
CH103
CH104
AJ31 CPN: SHI0110BJ0L VccADPLLA 1.05 0.08
+1.05V_RUN VCCCORE[17]
AP36
VCCTX_LVDS[3] 2 2 2
VCCTX_LVDS[4]
AP37 VccADPLLB 1.05 0.08
AN19
+1.05V_RUN VCCIO[28]
VccCore 1.05 1.3
1 2 +VCCAPLLEXP BJ22
@ RH247 VCCAPLLEXP
1UH_LB2012T1R0M_20%~D
10U_0805_4VAM~D
1 V33 +3.3V_RUN VccDMI 1.05 0.042
HVCMOS
VCC3_3[6]
AN16
VCCIO[15]
CH40
1
AN17 VCCIO[16]
VccIO 1.05 2.925
2 @ CH43
VCC3_3[7] V34
0.1U_0402_10V7K~D
2 VccASW 1.05 1.01
AN21 VCCIO[17]
AN26 +1.05V_+1.5V_1.8V_RUN
VCCIO[18]
VccSPI 3.3 0.020
AN27 VCCIO[19] VCCVRM[3] AT16
+1.05V_RUN
AP21
VCCIO[20]
VccDSW3_3 3.3 0.003
C C
AP23 AT20 +1.05V_RUN_VTT
VCCIO[21] VCCDMI[1]
VCCDFTERM 1.8 0.19
DMI
10U_0805_4VAM~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1 1 1 1 1 AP24 1 2 CH49
VCCIO
VCCIO[22] 1U_0402_6.3V6K~D
CH44
CH45
CH46
CH47
CH48
AP26 AB36 +1.05V_RUN_VCCCLKDMI 2 1 VccRTC 3.3 2 (mA)

VCCIO[23] VCCCLKDMI +1.05V_RUN
1 1 LH9
2 2 2 2 2 AT24 @ HK1608R10J-T_0603~D
VCCIO[24] CH50 CH106 VccSus3_3 3.3 0.119
1U_0402_6.3V6K~D 10U_0805_4VAM~D
AN33 2 2
VCCIO[25]
VccSusHDA 3.3 0.01
AN34 VCCIO[26] VCCDFTERM[1] AG16
+3.3V_RUN +VCCDFTERM
VccVRM 1.8 / 1.5 0.16
BH29 AG17 1 2 +3.3V_RUN
DFT / SPI
VCC3_3[3] VCCDFTERM[2] @ RH276 0_0805_5%~D
0.1U_0402_10V7K~D
1 @PJP66
@ PJP66 VccClkDMI 1.05 0.02
+1.05V_+1.5V_1.8V_RUN AJ16 1 1 2 +1.8V_RUN
VCCDFTERM[3]
CH51
AP16
VCCVRM[2]
CH52 PAD-OPEN1x1m VccSSC 1.05 0.095
2 0.1U_0402_10V7K~D
AJ17
VCCDFTERM[4] 2
+VCCAPLL_FDI BG6 VccDIFFCLKN 1.05 0.055
VccAFDIPLL
+1.05V_RUN AP17 VCCIO[27]

VccALVDS 3.3 0.001
FDI
V1 +3.3V_M
VCCSPI
+1.05V_RUN_VTT AU20
VCCDMI[2] 1 VccTX_LVDS 1.8 0.06
CH54
B CougarPoint_Rev_1p0 1U_0402_6.3V6K~D VccAPLLEXP 1.05 0.05 B
2
+1.05V_RUN
+1.05V_RUN
1 2 +VCCAPLL_FDI
@ RH195 0.022_0805_1%
+1.5V_RUN +1.05V_+1.5V_1.8V_RUN
1 1
+ @ CH41 + @ CH42
2 1 330U_D2_2VM_R6M~D 330U_D2_2VM_R6M~D
RH197 0_0603_5%~D
+1.8V_RUN 2 2
2 1
@ RH198 0_0603_5%~D
+1.05V_RUN
2 1
@ RH199 0_0603_5%~D
A A
LA-6562P
5 4 3 2 1
5 4 3 2 1
+5V_ALW +5V_ALW_PCH
+1.05V_RUN @ PJP68 PAD-OPEN1x1m

1 2
1 2 +VCCACLK
+3.3V_ALW_PCH @ RH200 0.022_0805_1%
+3.3V_ALW2
UH4J POWER
1 2 1 3
20K_0402_5%~D
0.1U_0402_10V7K~D
RH201 0_0402_5%~D 1 AD49 N26 +1.05V_RUN
VCCACLK VCCIO[29] @ QH4
1 2
1
@ RH253 0_0402_5%~D CH55 P26 1 SSM3K7002FU_SC70-3~D 1
G
2
0.1U_0402_10V7K~D VCCIO[30]
RH278
+VCCDSW3_3 T16
D 2 VCCDSW3_3 D
CH98
P28 CH56
VCCIO[31] 1U_0402_6.3V6K~D
+PCH_VCCDSW 2 <43> ALW_ENABLE 2
V12 T27 @
2
+1.05V_RUN @ LH3 DCPSUSBYP VCCIO[32] @
1
10UH_LBR2012T100M_20%~D T29
VCCIO[33]
@
1 2 CH57 +3.3V_RUN_VCC_CLKF33 T38
0.1U_0402_10V7K~D VCC3_3[5]
2 +3.3V_ALW_PCH
10U_0805_6.3V6M~D
0.1U_0402_10V7K~D
1 VCCSUS3_3[7] T23
+1.05V_RUN
@ CH58
+VCCAPLL_CPY_PCH BH23 1
VCCAPLLDMI2
T24 +3.3V_ALW_PCH
VCCSUS3_3[8] +5V_ALW_PCH +3.3V_ALW_PCH
0.1U_0402_10V7K~D
CH59
AL29 VCCIO[14]
2 V23 1
USB
VCCSUS3_3[9] 2
2
CH60
+VCCSUS1 AL24 V24
DCPSUS[3] VCCSUS3_3[10] DH2
1 RH208
2 10_0402_5%~D
P24 RB751S40T1_SOD523-2~D
VCCSUS3_3[6]
@
CH61
1U_0402_6.3V6K~D AA19
1
2 VCCASW[1] +PCH_V5REF_SUS
VCCIO[34] T26 +1.05V_RUN
AA21 1
VCCASW[2]
AA24 M26 +PCH_V5REF_SUS CH63
VCCASW[3] V5REF_SUS
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1 1 +3.3V_ALW_PCH 0.1U_0402_10V7K~D
2
0.1U_0402_10V7K~D
Clock and Miscellaneous
AA26 VCCASW[4]
CH64
CH65
AN23 +VCCA_USBSUS 1
DCPSUS[4] CRB 0.7 RH208,RH213 trace width 20mil.
AA27 VCCASW[5]
2 2
CH66
AN24
VCCSUS3_3[1]
AA29
VCCASW[6] 2
+1.05V_M AA31 +5V_RUN +3.3V_RUN
VCCASW[7]
AC26 P34 +PCH_V5REF_RUN
VCCASW[8] V5REF
2
C C
1 1U_0402_6.3V6K~D 1 1
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
AC27 RH213 DH3
CH67 VCCASW[9]
CH68
CH69
N20 +3.3V_ALW_PCH 10_0402_5%~D RB751S40T1_SOD523-2~D
VCCSUS3_3[2]
PCI/GPIO/LPC
AC29 VCCASW[10] 1
2 2 2 N22
1
VCCSUS3_3[3] CH70 +PCH_V5REF_RUN
AC31
VCCASW[11] 1U_0603_10V6K~D +3.3V_RUN
VCCSUS3_3[4] P20
AD29 2
VCCASW[12] 1
VCCSUS3_3[5] P22
+3.3V_RUN AD31 CH71
VCCASW[13] 1
1U_0603_10V6K~D
CH72 2
1 2 W21 AA16
@RH215
@ RH215 0.022_0805_1% VCCASW[14] VCC3_3[1] 0.1U_0402_10V7K~D
LH4 W23 W16 2 +3.3V_RUN
10UH_LBR2012T100M_20%~D VCCASW[15] VCC3_3[8]
1 2 +3.3V_RUN_VCC_CLKF33 W24 T34
VCCASW[16] VCC3_3[4]
10U_0805_6.3V6M~D
1U_0402_6.3V6K~D
1 1 1
@ CH73
W26 +VCCA_USBSUS
VCCASW[17]
CH74
CH75
W29 +3.3V_RUN 0.1U_0402_10V7K~D
2 2 VCCASW[18] 2 1
W31 AJ2 @CH62

@CH62
VCCASW[19] VCC3_3[2] 1U_0402_6.3V6K~D
1 2
W33
VCCASW[20] CH76
AF13 +1.05V_RUN
VCCIO[5] 0.1U_0402_10V7K~D
2 1
+VCCRTCEXT N16 DCPRTC CH77
1 AH13
+1.05V_+1.5V_1.8V_RUN VCCIO[12] 1U_0402_6.3V6K~D
CH78 Y49 AH14 2
0.1U_0402_10V7K~D VCCVRM[4] VCCIO[13]
2
B +1.05V_RUN AF14 LH5 @ B
+1.05V_RUN_VCCA_A_DPL VCCIO[6] 10UH_LBR2012T100M_20%~D
BD47
SATA
VCCADPLLA +VCCSATAPLL
AK1 1 2 +1.05V_RUN
+1.05V_RUN_VCCA_B_DPL VCCAPLLSATA +1.05V_+1.5V_1.8V_RUN
1 BF47 VCCADPLLB 1
@
CH79 AF11 CH80
1U_0402_6.3V6K~D VCCVRM[1] 10U_0805_6.3V6M~D
AF17
2 VCCIO[7] 2
AF33
VCCDIFFCLKN[1]
AF34 AC16 +1.05V_RUN
VCCDIFFCLKN[2] VCCIO[2]
1 2 CH81 AG34 VCCDIFFCLKN[3]
1U_0402_6.3V6K~D AC17 1
VCCIO[3]
1 AG33 AD17 CH82
VCCSSC VCCIO[4] 1U_0402_6.3V6K~D
+1.05V_M CH96 2
1U_0402_6.3V6K~D +VCCSST V16 +1.05V_M
2 DCPSST
1 2 +1.05V_M_VCCSUS
@ RH248 0.022_0805_1% 1 +1.05V_M_VCCSUS
1 T17 T21
CH84 DCPSUS[1] VCCASW[22]
V19
DCPSUS[2]
MISC
0.1U_0402_10V7K~D CH83 @
+1.05V_RUN_VTT 2 1U_0402_6.3V6K~D
VCCASW[23] V21
2
CPU
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
BJ8 V_PROC_IO
1 1 1 T19
VCCASW[21]
+RTC_CELL
CH86
CH87
CH85
4.7U_0603_6.3V6K~D
2 2 2
RTC
A22 P32
HDA
VCCRTC VCCSUSHDA +3.3V_ALW_PCH

0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1 1 1 1
LH6 CougarPoint_Rev_1p0
A A
CH88
CH89
10UH_LBR2012T100M_20%~D CH90 CH91

1 2 +1.05V_RUN_VCCA_A_DPL 1U_0402_6.3V6K~D 0.1U_0402_10V7K~D
+1.05V_RUN 2 2 2 2
1 2 +1.05V_RUN_VCCA_B_DPL
220U_B2_2.5VM_R35M~D
220U_B2_2.5VM_R35M~D
LH7
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
10UH_LBR2012T100M_20%~D 1 1
1 1 Compal Electronics, Inc.
CH94
CH92
CH95
CH93
+ +
Title
+1.05V_RUN_VCCA_A_DPL 1 2 +1.05V_RUN_VCCA_B_DPL
2 2 2 2 @RH279
@ RH279 0_0805_5%~D
PCH (7/8)
0.3
LA-6562P
5 4 3 2 1
5 4 3 2 1
UH4I
AY4 H46
VSS[159] VSS[259]
AY42 VSS[160] VSS[260] K18
AY46 K26
VSS[161] VSS[261]
AY8 VSS[162] VSS[262] K39
D D
B11 VSS[163] VSS[263] K46
UH4H B15 K7
VSS[164] VSS[264]
H5 VSS[0] B19 VSS[165] VSS[265] L18
B23 L2
VSS[166] VSS[266]
AA17 AK38 B27 L20
VSS[1] VSS[80] VSS[167] VSS[267]
AA2 VSS[2] VSS[81] AK4 B31 VSS[168] VSS[268] L26
AA3 AK42 B35 L28
VSS[3] VSS[82] VSS[169] VSS[269]
AB11 AL16 F45 M12
VSS[6] VSS[85] VSS[172] VSS[272]
AB14 VSS[7] VSS[86] AL17 BB12 VSS[173] VSS[273] P16
AB39 AL19 BB16 M18
VSS[8] VSS[87] VSS[174] VSS[274]
AB4 VSS[9] VSS[88] AL2 BB20 VSS[175] VSS[275] M22
AB43 AL21 BB22 M24
VSS[10] VSS[89] VSS[176] VSS[276]
AB5 AL23 BB24 M30
VSS[11] VSS[90] VSS[177] VSS[277]
AB7 AL26 BB28 M32
VSS[12] VSS[91] VSS[178] VSS[278]
AC19 VSS[13] VSS[92] AL27 BB30 VSS[179] VSS[279] M34
AC2 AL31 BB38 M38
VSS[14] VSS[93] VSS[180] VSS[280]
AC21 VSS[15] VSS[94] AL33 BB4 VSS[181] VSS[281] M4
AC24 AL34 BB46 M42
VSS[16] VSS[95] VSS[182] VSS[282]
AC33 AL48 BC14 M46
VSS[17] VSS[96] VSS[183] VSS[283]
AC34 AM11 BC18 M8
VSS[18] VSS[97] VSS[184] VSS[284]
AC48 VSS[19] VSS[98] AM14 BC2 VSS[185] VSS[285] N18
AD10 VSS[20] VSS[99] AM36 BC22 VSS[186] VSS[286] P30
AD11 AM39 BC26 N47
VSS[21] VSS[100] VSS[187] VSS[287]
AD13 AM45 BC34 P18
VSS[23] VSS[102] VSS[189] VSS[289]
AD19 AM46 BC36 T33
VSS[24] VSS[103] VSS[190] VSS[290]
AD26 VSS[26] VSS[105] AN2 BC42 VSS[192] VSS[292] P43
AD27 AN29 BC48 P47
VSS[27] VSS[106] VSS[193] VSS[293]
AD33 AN3 BD46 P7
C VSS[28] VSS[107] VSS[194] VSS[294] C
AD34 VSS[29] VSS[108] AN31 BD5 VSS[195] VSS[295] R2
AD36 AP12 BE22 R48
VSS[30] VSS[109] VSS[196] VSS[296]
AD37 AP19 BE26 T12
VSS[31] VSS[110] VSS[197] VSS[297]
AD38 VSS[32] VSS[111] AP28 BE40 VSS[198] VSS[298] T31
AD39 VSS[33] VSS[112] AP30 BF10 VSS[199] VSS[299] T37
AD4 AP32 BF12 T4
VSS[34] VSS[113] VSS[200] VSS[300]
AD40 VSS[35] VSS[114] AP38 BF16 VSS[201] VSS[301] W34
AD42 AP4 BF20 T46
VSS[36] VSS[115] VSS[202] VSS[302]
AD43 VSS[37] VSS[116] AP42 BF22 VSS[203] VSS[303] T47
AD45 AP46 BF24 T8
VSS[38] VSS[117] VSS[204] VSS[304]
AD46 VSS[39] VSS[118] AP8 BF26 VSS[205] VSS[305] V11
AD8 AR2 BF28 V17
VSS[40] VSS[119] VSS[206] VSS[306]
AE2 VSS[41] VSS[120] AR48 BD3 VSS[207] VSS[307] V26
AE3 AT11 BF30 V27
VSS[42] VSS[121] VSS[208] VSS[308]
AF10 AT13 BF38 V29
VSS[43] VSS[122] VSS[209] VSS[309]
AF12 AT18 BF40 V31
VSS[44] VSS[123] VSS[210] VSS[310]
AD14 AT22 BF8 V36
VSS[45] VSS[124] VSS[211] VSS[311]
AD16 AT26 BG17 V39
VSS[46] VSS[125] VSS[212] VSS[312]
AF16 AT28 BG21 V43
VSS[47] VSS[126] VSS[213] VSS[313]
AF19 VSS[48] VSS[127] AT30 BG33 VSS[214] VSS[314] V7
AF24 AT32 BG44 W17
VSS[49] VSS[128] VSS[215] VSS[315]
AF26 AT34 BG8 W19
VSS[50] VSS[129] VSS[216] VSS[316]
AF27 AT39 BH11 W2
VSS[51] VSS[130] VSS[217] VSS[317]
AF29 AT42 BH15 W27
VSS[52] VSS[131] VSS[218] VSS[318]
AF31 AT46 BH17 W48
VSS[53] VSS[132] VSS[219] VSS[319]
AF38 AT7 BH19 Y12
VSS[54] VSS[133] VSS[220] VSS[320]
AF4 VSS[55] VSS[134] AU24 H10 VSS[221] VSS[321] Y38
AF42 AU30 BH27 Y4
VSS[56] VSS[135] VSS[222] VSS[322]
AF46 AV16 BH31 Y42
VSS[57] VSS[136] VSS[223] VSS[323]
AF5 AV20 BH33 Y46
VSS[58] VSS[137] VSS[224] VSS[324]
AF7 AV24 BH35 Y8
VSS[59] VSS[138] VSS[225] VSS[325]
AF8 AV30 BH39 BG29
B VSS[60] VSS[139] VSS[226] VSS[328] B
AG19 VSS[61] VSS[140] AV38 BH43 VSS[227] VSS[329] N24
AG2 VSS[62] VSS[141] AV4 BH7 VSS[228] VSS[330] AJ3
AG31 AV43 D3 AD47
VSS[63] VSS[142] VSS[229] VSS[331]
AG48 VSS[64] VSS[143] AV8 D12 VSS[230] VSS[333] B43
AH11 AW14 D16 BE10
VSS[65] VSS[144] VSS[231] VSS[334]
AH3 AW18 D18 BG41
VSS[66] VSS[145] VSS[232] VSS[335]
AH36 AW2 D22 G14
VSS[67] VSS[146] VSS[233] VSS[337]
AH39 AW22 D24 H16
VSS[68] VSS[147] VSS[234] VSS[338]
AH40 AW26 D26 T36
VSS[69] VSS[148] VSS[235] VSS[340]
AH42 VSS[70] VSS[149] AW28 D30 VSS[236] VSS[342] BG22
AH46 VSS[71] VSS[150] AW32 D32 VSS[237] VSS[343] BG24
AH7 AW34 D34 C22
VSS[72] VSS[151] VSS[238] VSS[344]
AJ19 VSS[73] VSS[152] AW36 D38 VSS[239] VSS[345] AP13
AJ21 AW40 D42 M14
VSS[74] VSS[153] VSS[240] VSS[346]
AJ24 VSS[75] VSS[154] AW48 D8 VSS[241] VSS[347] AP3
AJ33 AV11 E18 AP1
VSS[76] VSS[155] VSS[242] VSS[348]
AJ34 AY12 E26 BE16
VSS[77] VSS[156] VSS[243] VSS[349]
AK12 AY22 G18 BC16
VSS[78] VSS[157] VSS[244] VSS[350]
AK3 AY28 G20 BG28
VSS[79] VSS[158] VSS[245] VSS[351]
G26 BJ28
CougarPoint_Rev_1p0 VSS[246] VSS[352]
G28
VSS[247]
G36 VSS[248]
G48
VSS[249]
H12 VSS[250]
H18
VSS[251]
H22
VSS[252]
H24 VSS[253]
H26
VSS[254]
H30
VSS[255]
H32
VSS[256]
H34
VSS[257]
F3 VSS[258]
A A
CougarPoint_Rev_1p0 CougarPoint_Rev_1p0
LA-6562P
5 4 3 2 1
5 4 3 2 1
+FAN1_VOUT
JFAN1 CONN@
FAN1_DET# 1
1
2 2
RB751S40T1_SOD523-2~D
FAN1_TACH_FB 3 5
3 G1
22U_0805_6.3VAM~D
4 4 G2 6
1
Place under CPU 1
C219
MOLEX_53398-0471~D
Place C266 close to the Q12 as possible
D2
D D
REM_DIODE1_P_4022 2
2
1
@ 2 C
C266 2 +5V_RUN +3.3V_M
100P_0402_50V8J~D B
3 E Q12
1 MMBT3904WT1G_SC70-3~D REM_DIODE1_N_4022 BC_INT#_EMC4022 2 1
+3.3V_RUN R385 10K_0402_5%~D
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
FAN1_TACH_FB 2 1
1 1 R426 10K_0402_5%~D
10U_0805_6.3V6M~D
0.1U_0402_16V4Z~D
FAN1_DET# 2 1
C276
C275
1 1 R402 10K_0402_5%~D
2 2
C305
C1171
U9
2 2
2
+3.3V_M VDDH
3
VDDH THERMATRIP2#
6 17
VDD_PWRGD VDDL THERMTRIP2#
1 2 13 VDD_PWRGD
R389 10K_0402_5%~D 18 THERMATRIP3#
THERMTRIP3#
1 2 REM_DIODE1_N_4022 23
C270 2200P_0402_50V7K~D REM_DIODE1_P_4022 DN1/THERM
Q14, C272 Place near DIMM 24 19 THERM_STP# <48>
DP1/VREF_T SYS_SHDN#
1 2 +RTC_CELL
Q13, C277 Place near WWAN 26 DN2/DP4 POWER_SW# 20 POWER_SW# @ R390 47K_0402_1%~D
27 DP2/DN4
REM_DIODE3_P_4022
2 1 REM_DIODE3_P_4022 30 21 ACAV_IN
C DP3/DN5 ACAVAIL_CLR ACAV_IN <41,55,57> C
1 1 C271 2200P_0402_50V7K~D REM_DIODE3_N_4022 29 9 BC_INT#_EMC4022
DN3/DP5 ATF_INT#/BC_IRQ# BC_INT#_EMC4022 <41>
1
E
C Q13
B
@ C272 2 @C277
@ C277 2 MMBT3904WT1G_SC70-3~D
100P_0402_50V8J~D B 100P_0402_50V8J~D <55> MAX8731_IINP 2 1 VCP2 31
2 E Q14 2 C
R387 4.7K_0402_5%~D VCP
25
3
MMBT3904WT1G_SC70-3~D REM_DIODE3_N_4022 VIN

5 +FAN1_VOUT
VSET_4022 FAN_OUT
28 VSET FAN_OUT 4
SMCLK/BC_CLK 8 BC_CLK_EMC4022 <41>

FAN1_TACH_FB 10 7
TACH/GPIO1 SMDATA/BC_DATA BC_DAT_EMC4022 <41>
FAN1_DET# 11
GPIO2
2 1 PWM 15 +3.3V_M
+3.3V_M GPIO3/PWM/THERMTRIP_SIO
R1178 10K_0402_5%~D
+3.3V_M
1
R388
1
<41> PCH_PWRGD# 1 2 3V_PWROK# 12 22_0402_5%~D

R395 R391 1K_0402_5%~D 3V_PWROK#
8.2K_0402_5%~D
2
1 +VCC_4022
VDD ADDR_XEN 1
32 2 +VCC_4022
2
+1.05V_RUN_VTT ADDR_MODE/XEN
0.1U_0402_16V4Z~D
1U_0402_6.3V6K~D
THERMATRIP2# R393 4.7K_0402_5%~D 1 1
R398 14
TEST1
1
C273
C1179
2.2K_0402_5%~D C 1 22
TEST2
1
1 2 2 +RTC_CELL 16 33
B C278 RTC_PWR3V VSS R403 2 2
1U_0402_6.3V6K~D
Q15 E 0.1U_0402_16V4Z~D 10K_0402_5%~D
3
PMST3904_SOT323-3~D 2 EMC4022-1-EZK-TR_QFN32_5X5~D
B
1 B
<7> H_THERMTRIP#
2
C274
2
+3.3V_M
1
R405
8.2K_0402_5%~D
2
THERMATRIP3#
+RTC_CELL C281
1 VSET_4022 0.1U_0402_16V4Z~D
1 2
C280 1
5
0.1U_0402_16V4Z~D 1 U10
2 C282 R406 TC7SH08FU_SSOP5~D 1
P
B DOCK_PWR_SW# <41>
0.1U_0402_16V4Z~D 953_0402_1%~D POWER_SW# 4 O
2 POWER_SW_IN# <41>
A
G
2
2
3
Rest=953, Tp=88degree
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, FAN & Thermal Sensor
LA-6562P
5 4 3 2 1
5 4 3 2 1
D D
Fingerprint CONN.
CONN@ +3.3V_FP
JFP1 @ L8
1 1 2 +3.3V_RUN U12 DLW21SN121SQ2L_4P~D
1 R1135 0_0402_5%~D FP_USB_D+
2 1 4 1
2 FP_USB_D- GND VCC +3.3V_RUN <34> FP_USBD+ 1 2 2
3 1 2 +3.3V_ALW
C 3 FP_USB_D+ @ R1136 0_0402_5%~D C
4 4
7 5 FP_RESET# <34> 1 FP_USB_D- 2 3 FP_USB_D+ 4 3 FP_USB_D-
G1 5 IO1 IO2 <34> FP_USBD- 4 3
8 6
G2 6 C285 PRTR5V0U2X_SOT143-4~D 1 2
TYCO_2041084-6~D 0.1U_0402_16V4Z~D R409 0_0402_5%~D
2 1 2
R410 0_0402_5%~D
B B
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, FP Conn.
LA-6562P
5 4 3 2 1
5 4 3 2 1
Q18
SI3456DDV-T1-GE3_TSOP6~D
LCD Power +15V_ALW +LCDVDD +3.3V_ALW
D
6
S
ACES_59003-0400C-001 +LCDVDD +15V_ALW 4 5
1
2
1 R412 1
GND
1
220_0402_5%~D
100K_0402_5%~D
2 100K_0402_5%~D
G
BATT_WHITE_LED BATT_WHITE_LED <44> 1
1
R413
3 BATT_YELLOW_LED <44>
3
BATT_YELLOW_LED
R414
4 C292
BREATH_WHITE_LED <44>
2
BREATH_WHITE_LED 0.1U_0402_16V4Z~D
VR_SRC 5 +BL_PWR_SRC 2
6
6 2
VR_SRC
0.1U_0402_25V4Z~D
7 1 2
2
VR_SRC
3
8 C246 1
NC
Q19A
9 DISP_ON 0.1U_0603_50V4Z~D
DISP_ON/OFF#
Q19B
C293
D BIA_PWM_LVDS D
PWM 10
CONNTST_GND 11 2 5
12 2
VR_GND
1
13
4
VR_GND D6
14
VR_GND
LCD_B_CLK+ 15 LCD_BCLK+_PCH <16>
16 LCD_BCLK-_PCH <16> <40> LCD_VCC_TEST_EN 2
LCD_B_CLK- EN_LCDPWR
GND 17 1 2
LVDS_B2+ 18 LCD_B2+_PCH <16>
19 LCD_B2-_PCH <16> 3 Q20
LVDS_B2- <16,40> ENVDD_PCH
20 LCD_B1+_PCH <16> PDTC124EU_SC70-3~D
LVDS_B1+
21 LCD_B1-_PCH <16>
3
LVDS_B1- BAT54CW_SOT323-3~D
LVDS_B0+ 22 LCD_B0+_PCH <16>
23 LCD_B0-_PCH <16>
LVDS_B0-
24
GND
25 LCD_ACLK+_PCH <16>
LVDS_A_CLK+
LVDS_A_CLK- 26 LCD_ACLK-_PCH <16>
27
GND Q21
LVDS_A2+ 28 LCD_A2+_PCH <16>
+PWR_SRC FDC654P-G_SSOT-6~D
LVDS_A2-
29 LCD_A2-_PCH <16> 40mil
LVDS_A1+
30
31
LCD_A1+_PCH <16> 40mil 6
D
LVDS_A1- LCD_A1-_PCH <16> +BL_PWR_SRC
BIA_PWM_LVDS 2 BIA_PWM_LVDS_L D63 2 RB751V-40GTE-17_SOD323-2~D
S
LVDS_A0+ 32 LCD_A0+_PCH <16> 1 1 BIA_PWM_PCH <16> 4 5
33 LCD_A0-_PCH <16> LE2 BLM18BB221SN1D_2P~D 2
LVDS_A0-
10K_0402_5%~D
1000P_0402_50V7K~D
34 LDDC_DATA_PCH 1
EDID_DATA LDDC_DATA_PCH <16>
R1137
G
46 35 LDDC_CLK_PCH 1
MGND6 EDID_CLK LDDC_CLK_PCH <16>
1
45 36 LCD_TST D68 1 2 RB751V-40GTE-17_SOD323-2~D 1
LCD_TST <40> BIA_PWM_EC <41>
3
MGND5 BIST R422 C296
44 37 +3.3V_RUN
MGND4 V_EDID
C297
43 38 +LCDVDD 100K_0402_5%~D 0.1U_0603_50V4Z~D
MGND3 LCD_VDD 2
42 39
2
MGND2 LCD_VDD LVDS_CBL_DET# 2
41 40 LVDS_CBL_DET# <17>
2
MGND1 CONNTST
C PWR_SRC_ON C
JLVDS1 CONN@
Q22
SSM3K7002FU_SC70-3~D
DISP_ON D64 1 2 RB751V-40GTE-17_SOD323-2~D PANEL_BKEN_PCH <16>
1 2 1 3
S
100K_0402_5%~D
R423 47K_0402_5%~D
1
+3.3V_RUN
R1138
D69 1 2 RB751V-40GTE-17_SOD323-2~D
G
PANEL_BKEN_EC <40>
2
1 2 LDDC_CLK_PCH
R159 2.2K_0402_5%~D
1 2 LDDC_DATA_PCH EN_INVPWR
<41> EN_INVPWR
2
R160 2.2K_0402_5%~D FDC654P: P CHANNAL
Panel backlight power control by EC
Place near to JLVDS1
+5V_TSP
+5V_TSP +5V_RUN
+15V_ALW
0.1U_0402_10V7K~D
1 2
@ R1001 0_0603_5%~D
1
1
+LCDVDD +3.3V_RUN CONN@ PMV45EN_SOT23-3~D
0.1U_0402_16V4Z~D
C302
JCAM1
0.1U_0402_16V4Z~D
0.1U_0402_25V4Z~D
S
D
1 R430 3 1 CONN@
<17> CAM_MIC_CBL_DET# USBP12_D+ 1 2
2 100K_0402_5%~D JTCH1
USBP12_D- 2 +3.3V_ALW Q32
1 1 3 1 1
2
3 1
C306
B B
G
+CAMERA_VDD 4 2
2
4 2
C243
<30> DMIC_CLK 5 5 <18> E3_PAID_TS_DET# 3 3
1
C298
6 USBP13_D- 4
2 2 6 R431 2 USBP13_D+ 4
<30> DMIC0 7 7 5 5
8 100K_0402_5%~D 1 6
8 6
SD05.TCT_SOD323-2~D
SD05.TCT_SOD323-2~D
9 7
G1 Shield
1
Close to JLVDS1 of 42,43 pins Close to JLVDS1.41 10 C304 8
2
G2 Shield
3
0.1U_0402_25V4Z~D
2
D8
D7
JST_BM08B-SRSS-TB1-LF-SN~D MOLEX_48226-0611
Q125B
@ @
5
2
@ D74
6
USBP13_D- 2
4
1
+CAMERA_VDD
Q125A
USBP13_D+
For Webcam <41> TOUCH_SCREEN_PD# 2
3
PESD5V0U2BT_SOT23-3~D
S
3 1 +3.3V_RUN
1
0.1U_0402_16V4Z~D
@ L10
10U_0805_10V4Z~D
Q23 DLW21SN121SQ2L_4P~D
PMV45EN_SOT23-3~D USBP12+ USBP12_D+
Place close JTCH1
G
1
1 1 <17> USBP12+ 2 2
2
1
C299
C300
USBP12- 4 3 USBP12_D- @ LE1

2 2 <17> USBP12- 4 3 USBP13_D+
<17> USBP13+ 1 2
1 2
+15V_ALW 1 2
1
R427 0_0402_5%~D 4 USBP13_D-
C301
<17> USBP13- 4 3 3
DLW21SN121SQ2L_4P~D
1
0.1U_0402_16V4Z~D 1 2
R429 2 R428 0_0402_5%~D 1 2
A
100K_0402_5%~D Touch Screen Connector RE3 0_0402_5%~D
A
1 2
2
@ D75 RE4 0_0402_5%~D

USBP12_D-
Webcam PWR CTRL
1
1
D USBP12_D+ 3
CCD_OFF 2 1
<40> CCD_OFF
Q24
G
S C303
3
0.1U_0402_25V4Z~D Title
2
eDP & CAM &TS Conn
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, 0.3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
LA-6562P
5 4 3 2 1
2 1
+3.3V_RUN +3.3V_RUN_CRTSW_DOCK
@PJP58
@ PJP58
1 2
PAD-OPEN1x1m
SW for MB/DOCK
+3.3V_RUN_CRTSW_DOCK
B U18 B
PCH_CRT_VSYNC 1 4
<16> PCH_CRT_VSYNC A0 VDD
PCH_CRT_HSYNC 2 16
<16> PCH_CRT_HSYNC PCH_CRT_RED A1 VDD
<16> PCH_CRT_RED 5 23
PCH_CRT_GRN A2 VDD
<16> PCH_CRT_GRN 6 29
PCH_CRT_BLU A3 VDD
<16> PCH_CRT_BLU 7 32
A4 VDD
CRT_SWITCH 8 27 VSYNC_BUF
SEL1 0B1 HSYNC_BUF VSYNC_BUF <46>
25
1B1 RED_CRT HSYNC_BUF <46>
2B1 22 RED_CRT <46>
PCH_CRT_DDC_DAT 9 20 GREEN_CRT
<16> PCH_CRT_DDC_DAT PCH_CRT_DDC_CLK 10 A5 3B1 BLUE_CRT GREEN_CRT <46>
<16> PCH_CRT_DDC_CLK 18
A6 4B1 DAT_DDC2_CRT BLUE_CRT <46>
5B1 12
CRT_SWITCH CLK_DDC2_CRT DAT_DDC2_CRT <46>
<40> CRT_SWITCH 30 SEL2 6B1 14
CLK_DDC2_CRT <46>
26 VSYNC_DOCK
0B2 HSYNC_DOCK VSYNC_DOCK <39>
24
1B2 RED_DOCK HSYNC_DOCK <39>
3 21
GND 2B2 GREEN_DOCK RED_DOCK <39>
11 GND 3B2 19 GREEN_DOCK <39>
28 17 BLUE_DOCK
GND 4B2 DAT_DDC2_DOCK BLUE_DOCK <39>
31 13
GND 5B2 CLK_DDC2_DOCK DAT_DDC2_DOCK <39>
33 GPAD 6B2 15
CLK_DDC2_DOCK <39>
PI3V712-AZLEX_TQFN32_6X3~D +3.3V_RUN_CRTSW_DOCK
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
SEL1/SEL2 Chanel Source
1 1 1 1 1 1
0 A=B1 MB
C331
C332
C333
C334
C335
C336
1 A=B2 APR/SPR 2 2 2 2 2 2
A A
Title
CRT/Video switch
0.3
LA-6562P
2 1
2 1
+5V_RUN
BAT1000-7-F_SOT23-3~D
2
3
D4
NC
1 2
@R451
@ R451 0_0402_5%~D
1
L19 +VDISPLAY_VCC
2 1 TMDSB_PCH_CLK_C 1 2 TMDSB_CON_CLK
<16> TMDSB_PCH_CLK 1 2
C352 0.1U_0402_10V7K~D
2 1 TMDSB_PCH_CLK#_C 4 3 TMDSB_CON_CLK# +5V_RUN_HDMI

<16> TMDSB_PCH_CLK# 4 3
C353 0.1U_0402_10V7K~D
2A_8VDC_SMD1812P200TF
0.1U_0402_10V7K~D
10U_0805_10V4Z~D
DLW21SN900HQ2L_0805_4P~D 1 1
1 2
2
0_1206_5%~D
C337
C338
@R459
@ R459 0_0402_5%~D @
2 2
F2
R5
1 2
TMDSB_PCH_P2_C R449 1 2 680_0402_5%~D @R462
@ R462 0_0402_5%~D
TMDSB_PCH_N2_C R448 1 2 680_0402_5%~D L20
1
TMDSB_PCH_P1_C R450 1 2 680_0402_5%~D 2 1 TMDSB_PCH_P0_C 1 1 2 TMDSB_CON_P0
TMDSB_PCH_N1_C R452 <16> TMDSB_PCH_P0 2
1 2 680_0402_5%~D C350 0.1U_0402_10V7K~D
TMDSB_PCH_P0_C R453 1 2 680_0402_5%~D
B TMDSB_PCH_N0_C R454 680_0402_5%~D TMDSB_PCH_N0_C TMDSB_CON_N0 JHDMI1 CONN@ B
1 2 <16> TMDSB_PCH_N0 2 1 4 4 3 3
TMDSB_PCH_CLK_C R455 1 2 680_0402_5%~D C351 0.1U_0402_10V7K~D HDMIB_PCH_HPD_R 19
TMDSB_PCH_CLK#_C R456 680_0402_5%~D DLW21SN900HQ2L_0805_4P~D HP_DET
1 2 18 +5V
1 2 17
@R466
@ R466 0_0402_5%~D PCH_SDVO_CTRLDATA_R DDC/CEC_GND
16
SDA
1
D PCH_SDVO_CTRLCLK_R 15
R458 SCL
+3.3V_RUN 1 2 10K_0402_5%~D 2 1 2 14 Reserved
G @R468
@ R468 0_0402_5%~D HDMI_CEC 13
Q26 L21 TMDSB_CON_CLK# CEC
S 12
3
SSM3K7002FU_SC70-3~D TMDSB_PCH_P1_C TMDSB_CON_P1 CK-
<16> TMDSB_PCH_P1 2 1 1 1 2 2 11 CK_shield
C348 0.1U_0402_10V7K~D TMDSB_CON_CLK 10
TMDSB_CON_N0 CK+
9
TMDSB_PCH_N1_C TMDSB_CON_N1 D0-
<16> TMDSB_PCH_N1 2 1 4 4 3 3 8 D0_shield
C349 0.1U_0402_10V7K~D TMDSB_CON_P0 7
DLW21SN900HQ2L_0805_4P~D TMDSB_CON_N1 D0+
6
D1-
1 2 5
@R469
@ R469 0_0402_5%~D TMDSB_CON_P1 D1_shield
4 D1+ GND 23
TMDSB_CON_N2 3 22
D2- GND
1 2 2 21
@R470
@ R470 0_0402_5%~D TMDSB_CON_P2 D2_shield GND
1 D2+ GND 20
L22
2 1 TMDSB_PCH_P2_C 1 1 2 TMDSB_CON_P2 SUYIN_100042GR019M23MZR
<16> TMDSB_PCH_P2 2
C346 0.1U_0402_10V7K~D
2 1 TMDSB_PCH_N2_C 4 3 TMDSB_CON_N2
<16> TMDSB_PCH_N2 4 3
C347 0.1U_0402_10V7K~D
DLW21SN900HQ2L_0805_4P~D
1 2
@R471
@ R471 0_0402_5%~D
+5V_RUN
+3.3V_RUN
1
0_0402_5%~D
R1163
@ D65
RB751V-40GTE-17_SOD323-2~D
Q120A
2
2
1
1 6 PCH_SDVO_CTRLCLK_R 1 2 +5V_HDMI_DDC
<16> PCH_SDVO_CTRLCLK
R1153 2.2K_0402_5%~D
+3.3V_RUN
5
4 3 PCH_SDVO_CTRLDATA_R 1 2
<16> PCH_SDVO_CTRLDATA
HDMI_CEC 2 1 R1152 2.2K_0402_5%~D
R1165 10K_0402_5%~D Q120B
+3.3V_RUN
1M_0402_5%~D
2
A A
R1168
2
G
1
3 1 HDMIB_PCH_HPD_R 1 2
<16> HDMIB_PCH_HPD R1128 20K_0402_5%~D
S
Q121
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, HDMI port
LA-6562P
2 1
5 4 3 2 1
+3.3V_RUN +3.3V_RUN
D
AUX/DDC GPU for DPC to E-DOCK 2 1 C366
0.1U_0402_16V4Z~D
AUX/DDC GPU for DPD to E-DOCK 2 1
D
C371
0.1U_0402_16V4Z~D
C367 U23 C372 U29

0.1U_0402_10V7K~D 1 14 0.1U_0402_10V7K~D 1 14
DPC_AUX_C BE0 VCC BE0 VCC
<16> DPC_PCH_DOCK_AUX 2 1 2 A0 BE3 13 <16> DPD_PCH_DOCK_AUX 2 1 DPD_AUX_C 2 A0 BE3 13
DPC_DOCK_AUX 3 12 PCH_DDPC_CTRLCLK DPD_DOCK_AUX 3 12

<39> DPC_DOCK_AUX B0 A3 PCH_DDPC_CTRLCLK <16> <39> DPD_DOCK_AUX B0 A3 PCH_DDPD_CTRLCLK <16>
4 BE1 B3 11 4 BE1 B3 11
2 1 DPC_AUX#_C 5 10 2 1 DPD_AUX#_C 5 10
<16> DPC_PCH_DOCK_AUX# A1 BE2 <16> DPD_PCH_DOCK_AUX# A1 BE2
C368 0.1U_0402_10V7K~D C373 0.1U_0402_10V7K~D
DPC_DOCK_AUX# 6 9 PCH_DDPC_CTRLDATA DPD_DOCK_AUX# 6 9
<39> DPC_DOCK_AUX# B1 A2 PCH_DDPC_CTRLDATA <16> <39> DPD_DOCK_AUX# B1 A2 PCH_DDPD_CTRLDATA <16>
7 8 7 8
GND B2 GND B2
PI3C3125LEX_TSSOP14~D PI3C3125LEX_TSSOP14~D
+5V_RUN +5V_RUN
2 1 2 1
C369 0.1U_0402_16V4Z~D C370 0.1U_0402_16V4Z~D
1
C C
P
P
NC
NC
DPC_CA_DET 2 4 DPC_CA_DET# DPD_CA_DET 2 4 DPD_CA_DET#
<39> DPC_CA_DET A Y <39> DPD_CA_DET A Y
G
G
U24 U25
NC7SZ04P5X_NL_SC70-5~D NC7SZ04P5X_NL_SC70-5~D
3
3
+3.3V_RUN
1 2 DPD_CA_DET
R491 1M_0402_5%~D
1 2 PCH_DDPC_CTRLCLK
1 2 DPC_CA_DET R487 2.2K_0402_5%~D Intel WW18 Strapping option
R492 1M_0402_5%~D 1 2 PCH_DDPC_CTRLDATA
R488 2.2K_0402_5%~D
B PCH_DDPD_CTRLCLK B
1 2
R489 2.2K_0402_5%~D Intel WW18 Strapping option
1 2 PCH_DDPD_CTRLDATA
R490 2.2K_0402_5%~D
A A

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DP AUX SW
LA-6562P
5 4 3 2 1
5 4 3 2 1
Free Fall Sensor

+3.3V_RUN
D D
@ PJP53
+3.3V_RUN 2 1 +3.3V_RUN_FFS
10U_0805_6.3V6M~D
PAD-OPEN1x1m
1 2 DDR_XDP_WAN_SMBDAT 1 1
R501 2.2K_0402_5%~D U26
C387
1 2 DDR_XDP_WAN_SMBCLK C388 DE351DLTR
R502 2.2K_0402_5%~D 0.1U_0402_16V4Z~D
HDD_FALL_INT 2 2
1 2 1
R503 100K_0402_5%~D VDD_IO
6 VDD GND 2
4
HDD_FALL_INT GND
8 INT 1 GND 5
<17> HDD_FALL_INT FFS_INT2 9 10
INT 2 GND
12
DDR_XDP_WAN_SMBDAT SDO
<7,12,13,14,15,37> DDR_XDP_WAN_SMBDAT 13 SDA / SDI / SDO
14
DDR_XDP_WAN_SMBCLK SCL / SPC
<7,12,13,14,15,37> DDR_XDP_WAN_SMBCLK RSVD 3 +3.3V_RUN
7 11
+3.3V_RUN +5V_HDD CS RSVD
DE351DLTR8_LGA14_3X5~D
1
@R506
@ R506
100K_0402_5%~D
2
G
D16
2
FFS_INT2 3 1 1 2 FFS_INT2_Q
<18> FFS_INT2
S
C C
RB751S40T1_SOD523-2~D
Q29
HDD PWR
+5V_ALW
+15V_ALW
+3.3V_ALW2
For HDD Temp.
1
@ R499
1
2
5
6
100K_0402_5%~D
1
JSATA1 CONN@ D @ Q27
1 @ R500 G
2
PSATA_PTX_DRX_P0_C C389 2 GND
<14> PSATA_PTX_DRX_P0_C 1 0.01U_0402_16V7K~D SATA_PTX_DRX_P0 2 100K_0402_5%~D HDD_EN_5V 3 SI3456DDV-T1-GE3_TSOP6~D
PSATA_PTX_DRX_N0_C C390 2 RX+
<14> PSATA_PTX_DRX_N0_C 1 0.01U_0402_16V7K~D SATA_PTX_DRX_N0 3 S
RX-
4 +5V_HDD @ +5V_RUN
4
GND
3
PSATA_PRX_DTX_N0_C 2 1 SATA_PRX_DTX_N0 5 PJP3
<14> PSATA_PRX_DTX_N0_C TX-
0.1U_0603_50V4Z~D
PSATA_PRX_DTX_P0_C C391 2 1 0.01U_0402_16V7K~D SATA_PRX_DTX_P0 6 @ 1 2
<14> PSATA_PRX_DTX_P0_C TX+
Q28B
10U_0805_10V4Z~D
C392 0.01U_0402_16V7K~D 7
@PJP69
@ PJP69 GND JUMP_43X79
5 1 1
1
1 2 +3.3V_RUN_HDD 8 @
+3.3V_RUN 3.3V
6
C393
C394
B R504 B
9
4
3.3V @ 100K_0402_5%~D
10
PAD-OPEN1x1m 3.3V 2 2
Q28A
11
GND
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 1 HDD_DET# 12 2
<41> HDDC_EN
2
<14> HDD_DET# GND
@ C1187
@ C1186
13
GND
+5V_HDD 14
1
5V
1
15
2 2 5V R505
16
17
5V
GND
100K_0402_5%~D +5V_HDD Source
FFS_INT2_Q 18 23
Reserved GND1
19 24
2
GND GND2
20
12V
21 12V
22
12V
JAE_SP100421-HDD
+5V_HDD
Main SATA +5V Default
1000P_0402_50V7K~D
1 1
C395
C396
0.1U_0402_16V4Z~D
2 2
A A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT HDD CONNECTOR
5 4 3 2 1
5 4 3 2 1
+5VMOD Source
+15V_ALW +5V_ALW
1
+3.3V_ALW2
D R507 D
100K_0402_5%~D
1
2
5
6
+3.3V_ALW R509 D Q30
2
100K_0402_5%~D G
1 2 ZODD_WAKE# 2 MOD_EN 3 SI3456DDV-T1-GE3_TSOP6~D
R510 10K_0402_5%~D S
3
1 2 MOD_MD +5V_MOD @ +5V_RUN
4
0.1U_0603_50V4Z~D
R516 10K_0402_5%~D PJP4
Q31B
1 2
10U_0805_10V4Z~D
MODC_EN# 5 1
1
1 JUMP_43X79
6
C400
R511
4
+3.3V_ALW_PCH
C401
100K_0402_5%~D
2
Q31A
MODC_EC 2
<40> MODC_EN 2
2
1
1 2 USB30_SMI#
1
R514 100K_0402_5%~D R512
100K_0402_5%~D
2
For ODD JSATA2 CONN@
<14> SATA_ODD_PTX_DRX_P1_C 2 1 1
C407 SATA_ODD_PTX_DRX_P1 GND
0.01U_0402_16V7K~D 2
SATA_ODD_PTX_DRX_N1 A+
<14> SATA_ODD_PTX_DRX_N1_C 2 1 3 A-
0.01U_0402_16V7K~D C406 4
SATA_ODD_PRX_DTX_N1 GND
2 1 5
C <14> SATA_ODD_PRX_DTX_N1_C 0.01U_0402_16V7K~D C405 SATA_ODD_PRX_DTX_P1 B- C
6 B+
2 1 7
+5V_MOD <14> SATA_ODD_PRX_DTX_P1_C 0.01U_0402_16V7K~D C404 GND
DEVICE_DET# 8
<41> DEVICE_DET# DP
1 2 +5V_MOD 9 +5V
1000P_0402_50V7K~D
@ CE7 150P_0402_50V8J~D 10
+5V
0.1U_0402_16V4Z~D
1 1 MOD_MD 11 MD
12
GND
C397
C398
13 GND
2 2 14 GND
<15> CLK_PCIE_EMB 15
REFCLK+
<15> CLK_PCIE_EMB# 16 REFCLK-
17
GND
18
<15> PCIE_PRX_EMBTX_P4 PETX+
19
<15> PCIE_PRX_EMBTX_N4 PETX-
20
GND
21
PCIE_PTX_EMBRX_P4_C GND
Pleace near ODD CONN <15> PCIE_PTX_EMBRX_P4
0.1U_0402_10V7K~D 2 1 C409 22
PERX+
0.1U_0402_10V7K~D 2 1 C408 PCIE_PTX_EMBRX_N4_C 23
<15> PCIE_PTX_EMBRX_N4 PERX-
24
GND
+5V_MOD 25
+5V
<15> EMBCLK_REQ# 26
CLKREQ#
<37,38,40> PCIE_WAKE# 27
WAKE#
<17> PLTRST_EMB# 28
PERST#
<41,47> BAY_SMBDAT 29 SMB_DATA GND1 32
<41,47> BAY_SMBCLK 30 33
MOD_SATA_PCIE#_DET SMB_CLK GND2
<40> MOD_SATA_PCIE#_DET 31
HPD
+3.3V_ALW 1 2
R1177 100K_0402_5%~D TYCO_2-2129116-1
B B
+3.3V_ALW
Q76
1
S
MOD_MD 3 1 ZODD_WAKE# R515

ZODD_WAKE# <40>
100K_0402_5%~D
G
2
2
MODC_EN#
USB30_EN
Q123B Q123A
6
DMN66D0LDW-7_SOT363-6~D DMN66D0LDW-7_SOT363-6~D
4 3 USB30_SMI#
USB30_SMI# <14>
MOD_SATA_PCIE#_DET 2
5
USB30_EN
1
A A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT ODD CONNECTOR
5 4 3 2 1
2 1
place close to pin27 place close to pin38 L77 +5V_RUN

DVDD_IO should match
Internal Speakers Header with HDA Bus level +VDDA_AVDD
BLM21PG600SN1D_0805~D
1 2 +5V_RUN
+VREFOUT
2
10U_0805_10V6K~D
1U_0603_10V6K~D
0.1U_0402_16V4Z~D
1U_0603_10V6K~D
0.1U_0402_16V4Z~D
0_0805_5%~D
+3.3V_RUN_DVDD
R1095
1 1 1 1 1
1U_0603_10V6K~D
15 mils trace 1
C955
C956
C957
C1172
C1173
C1180
JSPK1 CONN@
1
2 2 2 2 2
0.1U_0402_16V4Z~D
1U_0603_10V6K~D
0.1U_0402_16V4Z~D
10U_0805_10V6K~D
INT_SPK_L+ L91 1 2 BLM18BD121SN1D_2P~D INT_SPKL_L+ 1
2
1 1 1 1 1 Place C994, C952~C957 close to Codec 2
2
C994
C953
INT_SPK_L- L92 1 2 BLM18BD121SN1D_2P~D INT_SPKR_L- 3 3
C952
C954
10U_0805_10V6K~D
0.1U_0402_16V4Z~D
10U_0805_10V6K~D
0.1U_0402_16V4Z~D
4 4 1 1 1 1
INT_SPK_R+ L93 1 2 2 2 2
2 BLM18BD121SN1D_2P~D INT_SPKR_R+ U72
C958
C959
C960
C961
5 GND 1 DVDD_CORE AVDD1 27
INT_SPK_R- L94 1 2 BLM18BD121SN1D_2P~D INT_SPKR_R- 6 38 Place C1180 close to codec pin23
GND AVDD2 2 2 2 2
TYCO_2-1775765-4 3 45 +VDDA_PVDD
DVDD_IO PVDD
PVDD 39
9 13 AUD_SENSE_A
DVDD SENSE_A AUD_SENSE_B
SENSE_B 14
MIC_IN_L and MIC_IN_RR R161 pop 0-ohm for Combo Jack,
28 MIC_IN_L 1 2
PORTA_L MIC_IN_R <46> must symmetric in layout pop 1UF for E2 backup circuit
2
PCH_AZ_CODEC_BITCLK 6 29 MIC_IN_RR C1163 1U_0402_6.3V6K~D
<14> PCH_AZ_CODEC_BITCLK BITCLK PORTA_R
@ DE2
@ DE1
23 +VREFOUT MIC_IN_RR 1 2
PCH_AZ_CODEC_SDOUT VrefOut_A
<14> PCH_AZ_CODEC_SDOUT 5 SDATA_OUT 1 2 +VREFOUT_R C1165 1U_0402_6.3V6K~D
31 AUD_HP_OUT_L R1143 2.2K_0402_5%~D +VREFOUT_R 2 1 MIC_IN_R
PORTB_L AUD_HP_OUT_R AUD_HP_OUT_L <46> D70 RB751V-40GTE-17_SOD323-2~D
<14> PCH_AZ_CODEC_SYNC 10 SYNC PORTB_R 32 AUD_HP_OUT_R <46>
Place R1096 close to codec
1 2 PCH_AZ_SDIN0_R 8 40 INT_SPK_L+
B <14> PCH_AZ_CODEC_SDIN0 33_0402_5%~D SDATA_IN PORTD_+L INT_SPK_L- B
PORTD_-L 41
R1096 PCH_AZ_CODEC_RST# 11
<14> PCH_AZ_CODEC_RST#
1
RESET# INT_SPK_R+
PORTD_+R 44
43 INT_SPK_R-
PORTD_-R
I2S_MCLK 1 2 I2S_MCLK_R 15 25
RE9 0_0402_5%~D I2S_MCLK MONO_OUT AUD_PC_BEEP 2 1 1 2 SPKR <14>
I2S_BCLK 1 2 I2S_BCLK_R 16 12 C1105 0.1U_0402_16V4Z~D R1119 100K_0402_5%~D
RE10 0_0402_5%~D I2S_SCLK PC_BEEP
2 1 1 2 BEEP <41>
I2S_DO 1 2 17 C1106 0.1U_0402_16V4Z~D R1120 100K_0402_5%~D
R1097 33_0402_5%~D I2S_DOUT DMIC_CLK_L
DMIC_CLK/GPIO 1 2 1 2 DMIC_CLK <24>
+3.3V_RUN +3.3V_RUN_DVDD I2S_LRCLK 18 4 LE3 BLM18BB221SN1D_2P~D
I2S_LRCLK DMIC_0/GPIO 2 DMIC0 <24>
@ PJP60 46
DMIC1/GPIO0/SPDIFOUT1
680P_0402_50V7K~D
680P_0402_50V7K~D
680P_0402_50V7K~D
680P_0402_50V7K~D
1 2 I2S_DI# Place R1097 close to codec 24 48 Place LE2 close to codec 1 2 1 1 1 1
I2S_DIN SPDIFOUT0//GPIO3/Aux_Out
@ C973
@ C974
@ C975
@ C976
Close to U72 pin5 Close to U72 pin6 @ R1141 10K_0402_5%~D
CAP+ 36 1 2
PAD-OPEN1x1m 1 @ R1142 10K_0402_5%~D
PCH_AZ_CODEC_SDOUT PCH_AZ_CODEC_BITCLK C962 2 2 2 2
19 No Connect 4.7U_0603_10V6K~D
20 No Connect Place C962 close to Codec
1
2
CAP- 35
@ R1077 @ R1076 Place C963~C966 close to Codec
47_0402_5%~D 10_0402_5%~D 47 21
<40> AUD_NB_MUTE# EAPD VREFFILT
CAP2 22
+3.3V_RUN 34
2
V-
1 1 7 DVSS Vreg 37
4.7U_0603_10V6K~D
4.7U_0603_10V6K~D
1U_0603_10V6K~D
10U_0805_10V6K~D
1 1 1 1
@ C978
@C978 @ C977 1 2 42 26
PVSS AVSS1
C963
C964
C965
C966
0.1U_0402_10V7K~D 10P_0402_50V8J~D R1099 10K_0402_5%~D 30
2 2 AVSS
BCLK: Audio serial data bus bit clock input/output 49 GND AVSS 33
2 2 2 2
LRCK: Audio serial data bus word clock input/output
92HD90B2X5NLGXYAX8_QFN48_7X7~D
+VDDA_AVDD place at AGND and DGND plane

Notes:
Place closely to Pin 13. R1083
2.49K_0402_1%~D
1 2 Keep PVDD supply and speaker traces routed on the DGND plane.
@
AUD_SENSE_A 2 1 C981
100P_0402_50V8J~D
Keep away from AGND and other analog signals +3.3V_RUN +3.3V_RUN
1000P_0402_50V7K~D
1 2 place at Codec bottom side

+3.3V_RUN +3.3V_RUN @ PJP62
1
39.2K_0402_1%~D
1
0.1U_0402_10V7K~D
C982 1 2
100P_0402_50V8J~D
C980
R1086
R352
20K_0402_1%~D 1 2
1
2
2
DA204U_SOT323-3~D
DA204U_SOT323-3~D
DA204U_SOT323-3~D
DA204U_SOT323-3~D
PAD-OPEN1x1m 2
@
C1103
@ D54
@ D55
@ D56
@ D57
R1088 R1087 C983
2
100K_0402_5%~D 100K_0402_5%~D 100P_0402_50V8J~D

6
1 U73
2
16
1
VCC
2 5 I2S_BCLK 2 3
<46> AUD_MIC_SWITCH AUD_HP_NB_SENSE <40,46> 1A 1Y# DAI_BCLK# <39>
1
Q107A Q107B I2S_LRCLK 4 5
1
DMN66D0LDW-7_SOT363-6~D DMN66D0LDW-7_SOT363-6~D C967 2A 2Y# DAI_LRCK# <39>

0.1U_0402_16V4Z~D Resistor SENSE_A SENSE_B I2S_DO 6 7
2 3A 3Y# DAI_DO# <39>
I2S_MCLK 10 9
4A 4Y# DAI_12MHZ# <39>
39.2K PORT A PORT E
Add for solve pop noise and detect issue 12 5A 5Y# 11
+3.3V_RUN
20K PORT B PORT F 14 13 I2S_DI#
6A 6Y#
A 1 A
<40> EN_I2S_NB_CODEC# OE1#
2
10K NA DMIC0 2 1 15 OE2# GND 8
Place closely to Pin 14 @ D58
+VDDA_AVDD R1540 DA204U_SOT323-3~D
R1078 5.11K SPDIFOUT0 SPDIFOUT1 (DMIC1) 1K_0402_5%~D CD74HC366M96_SO16~D
2.49K_0402_1%~D
AUD_SENSE_B 2 1
1
2.49K Pull-up to AVDD
1000P_0402_50V7K~D
1 DAI_DI <39>
1
+3.3V_RUN
C979
R1079 R1080 +3.3V_RUN

2 PORT A External MIC
39.2K_0402_1%~D 20K_0402_1%~D
1
R1081 PORT B HeadPhone Out

2
100K_0402_5%~D R1082
100K_0402_5%~D
PORT C Dock Audio
2
PORT D Internal SPK

<40> DOCK_HP_DET 2 5 DOCK_MIC_DET <40>
Q106A Q106B
1
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Azalia (HD) Codec
LA-6562P LA-6562P
2 1
5 4 3 2 1
D D
SW1
POWER_SW#_MB 2 1
<41,42> POWER_SW#_MB
4 3
SKRBAAE010_4P~D
@ D23
3
1 PESD24VS2UT_SOT23-3~D
2
@SW2
@ SW2
LAT_ON_SW_BTN# 2 1
<41> LAT_ON_SW_BTN#
4 3
SKRBAAE010_4P~D
C C
POWER & INSTANT ON SWITCH
B B
A A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT PWR SW/Sniffer/1394/Audio Jack
5 4 3 2 1
5 4 3 2 1
+3.3V_LAN
+3.3V_RUN
1 2 TP_LAN_JTAG_TMS
@ R545 10K_0402_5%~D
1
1 2 TP_LAN_JTAG_TCK
@ R546 10K_0402_5%~D R547
10K_0402_5%~D
U31
2
Default solution:
1 2 LANCLK_REQ#_R 48 13 LAN_TX0+ PCH +1.05V_M SVR - stuff R548, unstuff L29
<15> LANCLK_REQ# R1187 0_0402_5%~D CLK_REQ_N MDI_PLUS0 LAN_TX0-
<17> PLTRST_LAN# 36 PE_RST_N MDI_MINUS0 14 Also, option to use iSVR - stuff L29, unstuff R548
D D
CLK_PCIE_LAN 44 17 LAN_TX1+
<15> CLK_PCIE_LAN CLK_PCIE_LAN# PE_CLKP MDI_PLUS1 LAN_TX1-
<15> CLK_PCIE_LAN# 45 18
PCIE
PE_CLKN MDI_MINUS1
MDI
<15> PCIE_PRX_GLANTX_P7 2 1 PCIE_PRX_GLANTX_P7_C
C458 0.1U_0402_10V7K~D 38 20 LAN_TX2+
PETp MDI_PLUS2 +1.0V_LAN +1.05V_M
<15> PCIE_PRX_GLANTX_N7 2 1 PCIE_PRX_GLANTX_N7_C 39 PETn MDI_MINUS2 21 LAN_TX2-
C459 0.1U_0402_10V7K~D @R548
@ R548
+3.3V_LAN 1 2 PCIE_PTX_GLANRX_P7_C 41 23 LAN_TX3+ L29 0_0805_5%~D
<15> PCIE_PTX_GLANRX_P7 PERp MDI_PLUS3 LAN_TX3- REGCTL_PNP10
C460 0.1U_0402_10V7K~D 42 24 1 2 1 2
PERn MDI_MINUS3 +3.3V_LAN
10U_0805_6.3V6M~D
0.1U_0402_10V7K~D
<15> PCIE_PTX_GLANRX_N7 1 2 PCIE_PTX_GLANRX_N7_C
1
C461 0.1U_0402_10V7K~D 4.7UH_CBC2012T4R7M_20%~D 1 1
C463
R549 R551 0_0402_5%~D 28 6 VCT_LAN_R1 2 1 Idc max=330mA
SMBUS
SMB_CLK RSVD_NC
C462
10K_0402_5%~D
<15> LAN_SMBCLK 1 2 LAN_SMBCLK_R 31 SMB_DATA
@ R550 0_0603_5%~D
<15> LAN_SMBDATA 1 2 LAN_SMBDATA_R 1 +RSVD_VCC3P3_1 2 1 +3.3V_LAN
R552 0_0402_5%~D RSVD_VCC3P3_1 +RSVD_VCC3P3_2 R553 2 2 2
2 1 4.7K_0402_1%~D
2
RSVD_VCC3P3_2
SMBus Device Address 0xC8 VDD3P3_IN
5 R554 4.7K_0402_1%~D
1 2 LAN_DISABLE#_R 3
<18> PM_LANPHY_ENABLE LAN_DISABLE_N +3.3V_LAN_OUT
R555 0_0402_5%~D 4
VDD3P3_OUT
<40> LAN_DISABLE#_R 1
15 Place R548, C462, C463 and L29 close to U31
VDD3P3_15
1
LOM_ACTLED_YEL# 26 19 C464
@ R557 LOM_SPD100LED_ORG# LED0 VDD3P3_19 1U_0603_10V6K~D
27 29
LED1 VDD3P3_29
LED
10K_0402_5%~D LOM_SPD10LED_GRN# 25 +1.0V_LAN 2
LED2
47 +1.0V_LAN +3.3V_LAN
2
VDD1P0_47
VDD1P0_46 46
T142 PAD~D TP_LAN_JTAG_TDI 32 37
T143 PAD~D TP_LAN_JTAG_TDO JTAG_TDI VDD1P0_37
34
JTAG_TDO
JTAG
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
TP_LAN_JTAG_TMS 33 43
TP_LAN_JTAG_TCK JTAG_TMS VDD1P0_43
35 JTAG_TCK 1 1 1 1 1 1
C1177
C1178
11
VDD1P0_11
C466
C467
C468
C469
C XTALO C
1 2 9 XTAL_OUT VDD1P0_40 40
R1144 0_0402_5%~D XTALI 10 22 2 2 2 2 2 2
Y3 XTAL_IN VDD1P0_22
16
25MHZ_12PF_X5H025000DC1H-H VDD1P0_16
VDD1P0_8 8
2 1 LAN_TEST_EN 30 TEST_EN
RES_BIAS 12 7 REGCTL_PNP10
RBIAS CTRL_1P0
18P_0402_50V8J~D
18P_0402_50V8J~D
2 2 Place C1178 close to pin5

VSS_EPAD 49
1
1
1K_0402_5%~D
3.01K_0402_1%~D
C470
C471
Note:
+3.3V_M
R561
R562
82579_QFN48_6X6~D +1.0V_LAN will work at 0.95V to 1.15V

1 1
+1.0V_LAN POWER OPTIONS

2
2
Shared with PCH @ R563
R562 Resistor Value: 1.05V SVR * Internal SRV 0_1206_5%~D
3.01 kohm for Hanksville-M LOM
1
2.37 kohm for Hanksville-D LOM STUFF: R548 STUFF: L29 Q34
NO STUFF: L29 NO STUFF: R548 +3.3V_ALW +3.3V_LAN
+15V_ALW
D
6
S
+3.3V_ALW2 5 4
1
+3.3V_LAN 2
10U_0805_6.3V6M~D
10U_0603_6.3V6M~D
0.1U_0402_10V7K~D
R564 1 1 1 1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
100K_0402_5%~D
C1164
C475
C476
2 2 2
3
1
2
2 2 2
C472
C473
C474
R565 ENAB_3VLAN
LAN ANALOG 100K_0402_5%~D
3
1 1 1
2200P_0402_50V7K~D
B B
SWITCH
Q35B
39
30
21
14
1
8
4
1
U32 5
C477
VDD
VDD
VDD
VDD
VDD
VDD
VDD
6
38 SW_LAN_TX0+
SW_LAN_TX0+ <33>
4
B0+ SW_LAN_TX0- 2
37 SW_LAN_TX0- <33>
B0-
Q35A
LAN_TX0+ 1 2 LAN_TX0+R 2
L30 5.6NH_0603CS-5N6EJTS_5%~D A0+ SW_LAN_TX1+
34 SW_LAN_TX1+ <33> <41> AUX_ON 1 2 2
LAN_TX0- LAN_TX0-R B1+ SW_LAN_TX1- R566 0_0402_5%~D
1 2 3 A0- B1- 33 SW_LAN_TX1- <33>
L31 5.6NH_0603CS-5N6EJTS_5%~D
1
29 SW_LAN_TX2+ 1 2
LAN_TX1+ 1 LAN_TX1+R B2+ SW_LAN_TX2- SW_LAN_TX2+ <33> <16,40> SIO_SLP_LAN#
2 6 28 @ R567 0_0402_5%~D
L33 5.6NH_0603CS-5N6EJTS_5%~D A1+ B2- SW_LAN_TX2- <33>
LAN_TX1- 1 2 LAN_TX1-R 7 25 SW_LAN_TX3+
A1- B3+ SW_LAN_TX3- SW_LAN_TX3+ <33>
L32 5.6NH_0603CS-5N6EJTS_5%~D 24
B3- SW_LAN_TX3- <33>
LAN_TX2+ 1 2 LAN_TX2+R 9 17 LAN_ACTLED_YEL#
A2+ LEDB0 LED_100_ORG# LAN_ACTLED_YEL# <33>
L34 5.6NH_0603CS-5N6EJTS_5%~D 18
LAN_TX2- LAN_TX2-R LEDB1 LED_10_GRN# LED_100_ORG# <33>
1 2 10 41 LED_10_GRN# <33>
L35 5.6NH_0603CS-5N6EJTS_5%~D A2- LEDB2
36 DOCK_LOM_TRD0+ +3.3V_LAN C478
LAN_TX3+ 1 LAN_TX3+R C0+ DOCK_LOM_TRD0- DOCK_LOM_TRD0+ <39>
2 11 35 0.1U_0402_10V7K~D
A3+ C0- DOCK_LOM_TRD0- <39>
L36 5.6NH_0603CS-5N6EJTS_5%~D 1 2
LAN_TX3- 1 2 LAN_TX3-R 12 32 DOCK_LOM_TRD1+
A3- C1+ DOCK_LOM_TRD1+ <39>
L37 5.6NH_0603CS-5N6EJTS_5%~D 31 DOCK_LOM_TRD1-
C1- DOCK_LOM_TRD1- <39>
5
DOCKED 13 27 DOCK_LOM_TRD2+ LOM_SPD100LED_ORG# 1
P
<40> DOCKED SEL C2+ DOCK_LOM_TRD2- DOCK_LOM_TRD2+ <39> B
26 4
C2- DOCK_LOM_TRD2- <39> LOM_SPD10LED_GRN# O WLAN_LAN_DISB# <40>
2
A
G
LOM_ACTLED_YEL# 15 23 DOCK_LOM_TRD3+
LOM_SPD100LED_ORG# LEDA0 C3+ DOCK_LOM_TRD3- DOCK_LOM_TRD3+ <39>
16 22 TC7SH08FU_SSOP5~D
DOCK_LOM_TRD3- <39>
3
A LOM_SPD10LED_GRN# LEDA1 C3- U15 A
Layout Notice : Place bead as 42
LEDA2
19 DOCK_LOM_ACTLED_YEL#
close PI3L500 as possible LEDC0 DOCK_LOM_SPD100LED_ORG# DOCK_LOM_ACTLED_YEL# <39>
5 PD LEDC1 20 DOCK_LOM_SPD100LED_ORG# <39>
40 DOCK_LOM_SPD10LED_GRN#
_GRN# <39> 43 PAD_GND DELL CONFIDENTIAL/PROPRIETARY
1: TO DOCK
FROM NIC DOCKED
0: TO RJ45 TO
PI3L720ZHEX_TQFN42_9X3P5~D Title
DOCK
Intel 82579 (Lewisville) / LAN SW
0.3
LA-6562P
5 4 3 2 1
5 4 3 2 1
D D
T156
SW_LAN_TX0+ 1 1:1 24 NB_LAN_TX0+

<32> SW_LAN_TX0+ TD1+ TX1+
+3.3V_LAN
SW_LAN_TX0- 2
<32> SW_LAN_TX0- TD1- NB_LAN_TX0-
23
TX1-
1U_0603_10V6K~D
0.1U_0402_10V7K~D
470P_0402_50V7K~D
+TRM_CT1 3 22 Z2805 1 1 1
TDCT1 TXCT1
C481
C482
C1167
+TRM_CT2 4 21 Z2807
SW_LAN_TX1+ TDCT2 TXCT2 NB_LAN_TX1+ 2 2 2
<32> SW_LAN_TX1+ 5 1:1 20
C TD2+ TX2+ C
0.47U_0603_10V7K~D
0.47U_0603_10V7K~D
1 1 +3.3V_LAN:20mils
SW_LAN_TX1- NB_LAN_TX1- +3.3V_LAN
C480
6 19
C479
<32> SW_LAN_TX1- TD2- TX2-

2 2
JLOM1 CONN@
<32> LAN_ACTLED_YEL# 1 2 10
SW_LAN_TX2+ 1:1 NB_LAN_TX2+ R1166 150_0402_5%~D Yellow LED-
<32> SW_LAN_TX2+ 7 TD3+ TX3+ 18
9
Yellow LED+
NB_LAN_TX3- 8
SW_LAN_TX2- PR4-
<32> SW_LAN_TX2- 8
TD3- NB_LAN_TX2- NB_LAN_TX3+
17 7
TX3- PR4+
NB_LAN_TX1- 6
+TRM_CT3 Z2806 PR2-
9 16
TDCT3 TXCT3 NB_LAN_TX2- 5 PR3-
+TRM_CT4 10 15 Z2808 NB_LAN_TX2+ 4
TDCT4 TXCT4 PR3+
75_0402_1%~D
75_0402_1%~D
75_0402_1%~D
75_0402_1%~D
SW_LAN_TX3+ 11 1:1 14 NB_LAN_TX3+
<32> SW_LAN_TX3+ TD4+ TX4+
0.47U_0603_10V7K~D
0.47U_0603_10V7K~D
NB_LAN_TX1+ 3
PR2+
1 1
NB_LAN_TX0- 2
PR1-
C483
C484
GND 14
SW_LAN_TX3- 12 13 NB_LAN_TX3- NB_LAN_TX0+ 1
2 2 <32> SW_LAN_TX3- TD4- TX4- PR1+
15
GND
<32> LED_10_GRN# 1 2 11
Green LED-
1
R1164 150_0402_5%~D
350uH_IH-115-F~D <32> LED_100_ORG# 1 2 13
B R1167 150_0402_5%~D Orange LED- B
12 Green-Orange LED+
GND
R571 2
R572 2
R573 2
R574 2
TYCO_2010019-3
CHASSIS
1 2 GND_CHASSIS
C485 1000P_1808_3KV7K~D
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, RJ45 Conn
LA-6562P
5 4 3 2 1
5 4 3 2 1
Q36 +3.3V_ALW_PCH
USB_GPIO27 1 2 SI2301CDS-T1-GE3_SOT23-3~D +3.3V_ALW_USH
@ R575 0_0402_5%~D
USBP7+ 1 2 1 3 1 2 RST_N +3.3V_ALW +3.3V_ALW_USH
S
D
R576 1.5K_0402_5%~D R577 4.7K_0402_5%~D U33D
2
+3.3V_ALW_USH 1 2 OVSTB @ PJP56
R580 R578 4.7K_0402_5%~D 2 1 BCM5882
G
2
1 2 PLTRST1#_USH 4.7K_0402_5%~D 1 2 FP_RESET# REF_XIN G14 D4 UART_TX/GPIO1
@ R579 10K_0402_5%~D R582 4.7K_0402_5%~D PAD-OPEN 2x2m~D REF_XOUT F14 REFCLK_XTALIN UART_TX_GPIO_1 UART_RX/GPIO0
C4
REFCLK_XTALOUT UART_RX_GPIO_0
1 2 USH_LPCEN 1 2 SPI_RST B3
UART
1
1@ R583 4.7K_0402_5%~D Q37 U33A R645 4.7K_0402_5%~D UART_CTS_GPIO_2 BT_COEX_STATUS2 FP_RESET# <23>
A3
UART_RTS_GPIO_3 BT_COEX_STATUS2 <42>
2 LPD# RST_N
CLK
1 SSM3K7002FU_SC70-3~D G1
BCM5882 RST_N
1
@ R584 4.7K_0402_5%~D D R587 0_0402_5%~D
1 2 IRQ_SERIRQ_R 2USB_GPIO27 <17> USBP7- 1 2 USBP7-_R P5 P7 FP_USBD-
FP_USBD- <23>
R581 4.7K_0402_5%~D G USBP7+_R USBD_DN USBH_DN_0 FP_USBD+
<17> USBP7+ 1 2 P6 P8 FP_USBD+ <23> L14
D USH_SMBCLK USB_GPIO27 USBD_UP USBH_UP_0 USBH_OC0# NC D
1 2 S N7 P9 2 1 +3.3V_ALW_USH
3
R589 2.2K_0402_5%~D R588 0_0402_5%~D USBD_ATTACH_GPIO_27 USBH_OC_0 R590 4.7K_0402_5%~D JTAG_CLK_USH L1
USH_SMBDAT JTAG_TDI_USH JTAG_TCK CONTACTLESS_DET#
1 2 P11 M1 J1
R585 2.2K_0402_5%~D USBH_DN_1 JTAG_TDO_USH JTAG_TDI GPIO_4 SCC_CMDVCC_N_R
P12 N1 D2
JTAG
USBH_UP_1 JTAG_TDO GPIO_14
1 2 BCM5882_ALERT# <15> CLK_PCI_TPM
CLK_PCI_TPM P2 LCLK USBH_OC_1 P10 USBH_OC1 JTAG_CLK_USH JTAG_TMS_USH N2 JTAG_TMS GPIO_15 C2 BCM5882_GPIO15
R592 2.2K_0402_5%~D LPC_LAD0 R593 1 2 0_0402_5%~D N3 @ R591 JTAG_RST#_USH L3 B1 BT_PRI_STATUS
<14,35,40,41> LPC_LAD0 LAD0_GPIO_20 JTAG_TRSTN GPIO_16 BT_PRI_STATUS <42>
1 2 USH_PWR_STATE# <14,35,40,41> LPC_LAD1
LPC_LAD1 R594 1 2 0_0402_5%~D M4 0_0402_5%~D JTCE_USH L2
R586 4.7K_0402_5%~D LPC_LAD2 R595 1 0_0402_5%~D LAD1_GPIO_21 JTCE
<14,35,40,41> LPC_LAD2 2 K5 1 2
LAD2_GPIO_22
1 2 USBH_OC1 LPC_LAD3 R597 1 2 0_0402_5%~D N4 G3 SPI_CLK D3 CLKOUT
@
<14,35,40,41> LPC_LAD3 LAD3_GPIO_23 SSP_CLK0_GPIO_6 CLKOUT T144PAD~D
2
R596 4.7K_0402_5%~D LPC_LFRAME# R598 1 2 0_0402_5%~D K4 G2 SPI_CS JTAG_TDI_USH OVSTB E1
<14,35,40,41> LPC_LFRAME# IRQ_SERIRQ_R LFRAME_N_GPIO_18 SSP_FSS0_GPIO_7 SPI_RXD @ R601 OVSTB
<14,35,40,41> IRQ_SERIRQ
1 2 L4 LSERIRQ_GPIO_19 SSP_RXD0_GPIO_8 H1
@ R600 0_0402_5%~D H2 SPI_TXD 0_0402_5%~D C1 SPI_RST
CLK_PCI_TPM PLTRST1#_USH SSP_TXD0_GPIO_9 JTAG_TDO_USH SCANACCMODE RSTOUT_N
1 2 M3 E3
@
<17> PLTRST_USH# LRESET_N_GPIO_17 PAD~D T145 SCANACCMODE
USH_LPCEN BCMGPIO_10
SPI
R602 0_0402_5%~D M5 C3 @ R599
@@@@
T146PAD~D
LPC
1
LPCEN SSP_CLK1_GPIO_10
1
1 2 LPD# N6 B2 BCMGPIO_11 T147PAD~D 0_0402_5%~D

<35,40> SP_TPM_LPC_EN LPCPD_N_GPIO_24 SSP_FSS1_GPIO_11
@ R603 R604 0_0402_5%~D A2 BCMGPIO_12 1 2 SBOOT E2 J13 POR_MONITOR
@
SSP_RXD1_GPIO_12 T148PAD~D SECURE_BOOT POR_MONITOR T149PAD~D
10_0402_5%~D A1 BCMGPIO_13 T150PAD~D
USH_SMBCLK SSP_TXD1_GPIO_13 JTAG_TMS_USH
<41> USH_SMBCLK M9 SMBCLK
USH_SMBDAT L9 USH_TESTMODE D1 K11 SWV
@
<41> USH_SMBDAT T151PAD~D
PCI_TPM_TERM 2
BCM5882_ALERT# SMBDAT TESTMODE SWV

<40> BCM5882_ALERT#
K9 SMBALERT_N
Smard Card
SC_DET R606 1 2 150_0402_5%~D M7 M11 R607 2 1 0_0402_5%~D BCM5882_SCCLK JTAG_RST#_USH
SMB_GPIO_0 SC_CLK
2
BT_COEX_STATUS2 1 2 SMB_GPIO1 N8 M12 R608 2 1 0_0402_5%~D AUX1UC @ R605 POR_EXTR J14 C13 PLL_TESTOUT
@
SMB_GPIO_1 SC_FCB POR_EXTR PLL_TESTOUT T153PAD~D
R1581 0_0402_5%~D F2 R609 2 1 0_0402_5%~D BCM5882_GPIO25 0_0402_5%~D @ R626
SC_SEL5V_GPIO_25
4.7P_0402_50V8C~D
1 2JTAG_RST#_USH F1 R611 2 1 0_0402_5%~D BCM5882_GPIO26 1 2 1K_0402_5%~D HF_RX_TEST0

SC_SEL18V_GPIO_26
R610 1K_0402_5%~D 2 USH_PWR_STATE#_R R614 1 0_0402_5%~D BCM5882_SCDET @ R621 HF_RX_TEST2
SM BUS
<40> USH_PWR_STATE# 1 L7 M2 2
WAKEUP_N SC_DET
1 2 USH_LPCEN R613 0_0402_5%~D L11 R616 2 1 0_0402_5%~D BCM5882_IO JTCE_USH 0_0402_5%~D BCM5882KFBG_FBGA196~D
1
2@ R615 4.7K_0402_5%~D SC_IO R620 BCM5882_SCRST
1 2 K1 M10 2 1 0_0402_5%~D 1 2
R619 1K_0402_5%~D IDDQ_EN SC_RST
2 N14 +SC_PWR 1 2
SC_PWR_N14
@ C486
1 2 P1 P14 HF_RX_TEST1 @ R618 0_0402_5%~D

CORE_PWRDN SC_PWR_P14 SC_TEST
R622 1K_0402_5%~D L10 2 1 SCC_CMDVCC_N U33C HF_RX_TEST3
SC_VCC R623 0_0402_5%~D
1 2 E12
C
1 R624 1K_0402_5%~D ALDO_PWRDN
1 2 RFTAG_VRXP A6
BCM5882 A8 RFREADER_TXP1 C
HF_RFIDTAG_VRX_P HF_TX_P
1 2 REF_XOUT R625 1 2 0_0402_5%~D RFTAG_VRXN B6 HF_RFIDTAG_VRX_N HF_TX_N B8 RFREADER_TXN1
R627 0_0402_5%~D All XTAL components and traces should be R628 0_0402_5%~D
C5 A10 RFREADER_RXP
REF_XIN placed/layout on top layer. The gnd/pwr +1.2V_ALW_AVDD +2.5V_ALW_AVDD HF_RFIDTAG_VTX HF_RX_P RFREADER_RXN
1 2 BCM5882KFBG_FBGA196~D C487 should be placed HF_RX_N
B10
@ R612 10M_0402_5%~D layer below will provide shielding from
closer to pin A5
27.12Mhz interference which might affect +3.3V_ALW_USH
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
4.7U_0603_6.3V6K~D
10U_0603_6.3V6M~D
Y4 1 2 A5 B9 HF_RX_TEST0
XI 1 3 XO cellular certification. C487 0.01U_0402_16V7K~D HF_RFIDTAG_VREF HF_RX_TEST0
C9 HF_RX_TEST1
IN OUT HF_RX_TEST1 HF_RX_TEST2
2 2 1 2 2 1 1 +1.2V_ALW_AVDD B4 C10
HF_RFIDTAG_DVDD1P2 HF_RX_TEST2
C490
C491
2 4 E9 HF_RX_TEST3
GND GND +3.3V_ALW_SC +3.3V_ALW +5V_ALW_SC +5V_ALW HF_RX_TEST3
4.7K_0402_5%~D
5.1M_0402_5%~D
C494
C495
C488
C496
C489
1 1
2
27.12MHZ_12PF_1N227120CC0B~D @ PJP63 @ PJP64 +2.5V_ALW_AVDD C6 D7 +RFID_AVDD1P2
1 1 2 1 1 2 2 HF_RFIDTAG_AVDD2P5_C6 HF_TX_AVDD1P2
R629
R630
C492 C493 1 2 1 2 E6 F8
12P_0402_50V8J~D 15P_0402_50V8J~D HF_RFIDTAG_AVDD2P5_E6 HF_RX_AVDD1P2
HF_RX_ADC_AVDD1P2 D10
2 2
PAD-OPEN1x1m PAD-OPEN1x1m F9 +RFID_AVDD2P5
1
HF_RX_AVDD2P5
D6 A7
HF_RFIDTAG_AVSS_D6 HF_TX_AVDD2P5
B5
Smart Card +3.3V_ALW_SC
SBOOT
POR_EXTR RFID MODE A4
HF_RFIDTAG_AVSS_B5
HF_RFIDTAG_DVSS
HF_TX_AVDD3P3_D8
HF_TX_AVDD3P3_B7
D8
B7
+RFID_AVDD3P3
+3.3V_ALW_SC
3.3M_0402_5%~D
Component VOLTAGE CURRENT
2
1 2 PORADJ C7
HF_TX_AVSS_C7
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D
R634
1 2 PORADJ @ R631 4.7K_0402_5%~D 1 1 1 D25-D28 POP NOPOP C8
+5V_ALW_SC HF_TX_AVSS_C8
R632 4.7K_0402_5%~D 1 2 CLKDIV2 E7
HF_TX_AVSS_E7
1
C497
C498
C499
1 2 CLKDIV1 R633 4.7K_0402_5%~D R636,R644 3K NOPOP

R635 4.7K_0402_5%~D R636 A9
1
2 2 2 HF_RX_AVSS_A9
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D
15K_0402_1%~D B11
HF_RX_AVSS_B11
2 1
U34 E8
2
HF_RX_ADC_AVSS1
C500
C501
1 RFREADER_RXP 1 2 RFREADER_RXP_C D9
B PORADJ VDD(intf) C502 0.1U_0402_16V4Z~D L39 HF_RX_ADC_AVSS2 B
18 PORadj VDD 17
CLKDIV1 6 1 2 3 150NH_0805CS-151EGTS_2%~D
CLKDIV1 +3.3V_ALW_USH
CLKDIV2 7 16 1 RFREADER_TXP1 1 2 BCM5882KFBG_FBGA196~D
SCC_CMDVCC_N_R CLKDIV2 VDDP
2
390P_0603_50V8G~D
390P_0603_50V8G~D
BCM5882_SCRST 3 15 +SC_VCC 1 1
RSTIN VCC
C503
C504
2 1SCC_CMDVCC_N 5 @ D25 DA204U_SOT323-3~D +3.3V_ALW_USH 3
BCM5882_GPIO25 CMDVCCN R638 0_0402_5%~D SC_RST
2 14 1 2 1
@ R637 BCM5882_GPIO26 EN_5V/3VN RST R639 22_0402_5%~D SC_CLK
4 13 1 2 3 2
0_0402_5%~D
AUX1UC
AUX2UC
21
EN_1.8VN
AUX1UC
CLK
I/O
AUX1
9
10
R640
R641
R642
1
1
2
2
100_0402_5%~D
0_0402_5%~D
0_0402_5%~D
SC_IO
SC_C4
SC_C8
+3.3V_ALW_USH
2
1
@ D26
DA204U_SOT323-3~D
2 2
RFID
22 11 1 2
@
PAD~D T154 AUX2UC AUX2

BCM5882_IO 20 8 R643 1 2 0_0402_5%~D SC_DET @ D27 DA204U_SOT323-3~D
BCM5882_SCDET I/OUC PRESN JCS1 CONN@
19 OFFN RFREADER_RXN 1 2 RFREADER_RXN_C 1
BCM5882_SCCLK 23 C505 0.1U_0402_16V4Z~D RFREADER_TXN1_PI 1
24 2
XTAL1 XTAL2 +SC_VCC +3.3V_ALW 2
10P_0402_50V8J~D
10P_0402_50V8J~D
2 2 3
3
1
25 12 CONN@ 4
GPAD GND 4
.47U_0402_6.3V6-K~D
C506
C507
JBCM1 R644 RFREADER_TXP1_PI 5 7

15K_0402_1%~D 5 G1
TDA8034HN_HVQFN24_4X4~D 2 1 6 8
1 1 UART_RX/GPIO0 1 <18> CONTACTLESS_DET# 6 G2
2
2
C508
UART_TX/GPIO1 3 5 TYCO_2041084-6~D
2
3 G1
+SC_VCC
SC_VCC should be 3X wide as 1
4
4 G2
6 L40
150NH_0805CS-151EGTS_2%~D
regular SC trace width to carry MOLEX_53398-0471~D RFREADER_TXN1 1 2
~60mA max. current per ISO spec
390P_0603_50V8G~D
390P_0603_50V8G~D
C1031 and C646 should be p +3.3V_ALW_USH 1 1
10U_0805_10V4Z~D
0.22U_0402_10V6K~D
C511
C512
Place C508 close +3.3V_ALW_USH 3
laced very close to SC cage pin
0.1U_0402_16V4Z~D
1 2 to U33 pin15 1
@ C509
2
2 2
Hardware enable for USH TPM:Populate R583,
C510
1
+3.3V_ALW_USH D28 @ No Stuff R615.
2 1
C513
JSC1 CONN@ DA204U_SOT323-3~D Hardware disable for USH TPM:No Stuff

A 1 A
1 2 R583, Populate R615.
0.1U_0402_16V4Z~D
2
SC_RST 2 @ U35
3
3 SPI_CS U36 +3.3V_ALW_USH +2.5V_ALW_AVDD +1.2V_ALW_AVDD
4 1 8 1
SC_CLK 4 /CS VCC @ SPI_TXD SPI_RXD L41 BLM18BB100SN1D_2P~D L42 BLM18BB100SN1D_2P~D L43 BLM18BB100SN1D_2P~D
5 1 8
5 D Q DELL CONFIDENTIAL/PROPRIETARY
C556
SC_IO 6 SPI_RXD 2 7 SPI_RST SPI_CLK 2 7 2 1 +RFID_AVDD3P3 2 1 +RFID_AVDD2P5 2 1 +RFID_AVDD1P2

6 DO /HOLD C VSS
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
SC_C4 7 SPI_RST 3 6
7 2 RESET# VCC
3.3U_0603_10V6K~D
1U_0603_10V6K~D
0.1U_0402_16V4Z~D
1U_0603_10V6K~D
1U_0603_10V6K~D
1U_0603_10V6K~D
1U_0603_10V6K~D
SC_C8
SC_DET
8
9
8
BCM5882_GPIO15 3
/WP CLK
6 SPI_CLK SPI_CS 4
S# W#
5 BCM5882_GPIO15
1 2 1 2 2 1 1 1 1
9 SPI_TXD M45PE16-VMW6TG_SO8W8~D Title
1 2 10 4 5
10 GND DIO
C516
C518
C519
C515
C517
C520
C521
C514
C522
R646 11 USH BCM5882 (1/2)
1.5K_0402_5%~D GND W25X32VSSIG_SO8~D BCM5882_GPIO15 1 2 1 2 1 1 2 2 2 2 Size Document Number Rev
12 2
GND R647 4.7K_0402_5%~D 0.3
FCI_10089709-010010LF~D LA-6562P
5 2 1
5 4 3 2 1
U33B
H14
BCM5882
+1.2V_ALW_PLL AVDD_1P2I_REF
+1.2V_ALW_AVDD A11 AVDD_1P2O_A11
A12 AVDD_1P2O_A12 AVSS_LDO12 C11
+2.5V_ALW_AVDD
H13 B13
AVDD_2P5I AVSS_LDO25_B13
E10 AVDD_2P5O_E10 AVSS_LDO25_C12 C12
+3.3V_ALW_USH E11
AVDD_2P5O_E11
AVSS_PLL B14
A13
AVDD25_LDO12_A13
4.7U_0603_6.3V6K~D
B12 AVDD25_LDO12_B12 AVSS_REF F13
D D
1 PLL_AVSS D12
+1.2V_ALW_PLL A14 AVDD25_PLL_A14
C523
E13
PLL_DVSS
+3.3V_ALW_USH 2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
10U_0603_6.3V6M~D
1 1 1 D11
AVDD33_LDO25
C524
C525
C526
POR_AVSS G13
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
10U_0603_6.3V6M~D
+SC_PWR P13
2 2 2 OTP_PWR
2 2 2 2 2 2 2 1
C534
1U_0402_6.3V6K~D
0.1U_0402_16V4Z~D
C527
C528
C529
C530
C531
C532
C533
1 2 +1.2V_ALW_PLL D14 PLL_AVDD_1P2I
E14
1 1 1 1 1 1 1 2 PLL_AVDD_1P2O
C1161
C535
C14 F4
PLL_DVDD_1P2I VSSC_F4
F5
2 1 VSSC_F5
D13 VDDC_D13 VSSC_F6 F6
+VDDC_5882 F3 F7
VDDC_F3 VSSC_F7
J4 VDDC_J4 VSSC_F10 F10
J5 F11
VDDC_J5 VSSC_F11
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
J6 F12
VDDC_J6 VSSC_F12
2 2 2 2 2 2 2 J7 G5
VDDC_J7 VSSC_G5
J8 VDDC_J8 VSSC_G6 G6
C536
C537
C538
C539
C540
C541
C542
J10 VDDC_J10 VSSC_G7 G7
+VDDC_5882 J11 G8
1 1 1 1 1 1 1 VDDC_J11 VSSC_G8
K7 VDDC_K7 VSSC_G9 G9
+3.3V_ALW_USH K8 G10
VDDC_K8 VSSC_G10
G11
VSSC_G11
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
E4 VDDO_33_E4 VSSC_G12 G12
2 2 2 2 J2 VDDO_33_J2 VSSC_H5 H5
K3 H6
VDDO_33_K3 VSSC_H6
C543
C544
C545
C546
L8 H7
C VDDO_33_L8 VSSC_H7 C
N10 VDDO_33_N10 VSSC_H8 H8
1 1 1 1 H9
VSSC_H9
G4 H10
VDDO_33CORE_G4 VSSC_H10
H3 VDDO_33CORE_H3 VSSC_H11 H11
H4 VDDO_33CORE_H4 VSSC_H12 H12
J3 J9
VDDO_33CORE_J3 VSSC_J9
VSSC_J12 J12
M13 K2
VDDO_33SC_M13 VSSC_K2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
10U_0603_6.3V6M~D
N13 VDDO_33SC_N13 VSSC_K6 K6
2 2 1 K13
VSSC_K13
L6 VDDO_LPC_L6 VSSC_K14 K14
C547
C548
C549
M6 L5
VDDO_LPC_M6 VSSC_L5
VSSC_M8 M8
1 1 2 M14
VSSC_M14
K10 N9
VDDO_SC_K10 VSSC_N9
K12 N11
VDDO_SC_K12 VSSC_N11
L12 N12
VDDO_SC_L12 VSSC_N12
L13 P3
VDDO_SC_L13 VSSC_P3
P4
VSSC_P4
D5 VDDO_VAR_D5
E5
VDDO_VAR_E5
+3.3V_RUN 4@ +3.3V_RUN_TCM N5
CLK_PCI_TPM_CHA PJP61 VESD
LOW:Power Down Mode 1 2
1
High:Working Mode BCM5882KFBG_FBGA196~D

@ China TCM: NationZ & Jetway co-lay
RE5 PAD-OPEN1x1m
33_0402_5%~D
+3.3V_RUN_TCM
2
1 4@ U37
B @ B
CE3 10
USH BCM5882 and China TCM Z8H172T Option
27P_0402_50V8J~D VDD_0
19
2 VDD_1 PART/PIN Ref Des TCM Enable TPM Enable ALL TPM/TCM Disable
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
10U_0603_6.3V6M~D
VDD_2 24
4@ C551
4@ C552
4@ C553
4@ C550
2 2 2 1 TCM circuit All 4@ POP @ @
1 2 C_TPM_LPC_EN 28
<34,40> SP_TPM_LPC_EN
4@ R650 1 2 0_0402_5%~D LPC_LAD0_R 26
LPCPD#
11
PU R583 @ POP @
<14,34,40,41> LPC_LAD0
4@ R649 1 2 0_0402_5%~D LPC_LAD1_R 23
LAD0 GND_11
18 1 1 1 2 USH_LPCEN
<14,34,40,41> LPC_LAD1
4@ R648 1 2 0_0402_5%~D LPC_LAD2_R 20
LAD1 GND_18
25
PD R615 POP @ @
<14,34,40,41> LPC_LAD2 LPC_LAD3_R LAD2 GND_25
4@ R651 1 2 0_0402_5%~D 17 4
<14,34,40,41> LPC_LAD3
4@ R652 0_0402_5%~D LAD3 GND_4 SIO 5028 ->SP_TPM_LPC_EN PU R772 @ @ @
+3.3V_RUN_TCM PU RH268 @ POP POP
21 5 JETWAY_PIN5 PCH GPIO39 ->TPM_ID1
<15> CLK_PCI_TPM_CHA
1 2 LPC_LFRAME#_R 22
LCLK NC_5
12
PD RH271 POP @ @
<14,34,40,41> LPC_LFRAME# LFRAME# NC_12
4@ R653 1 2 0_0402_5%~D PCI_RST#_R 16 13 JETWAY_CLK14M
<14,17,37,38,40,41> PCH_PLTRST#_EC
4@ R654 0_0402_5%~D 27
LRESET# NC_13 JETWAY_CLK14M <15> PU RH267 @ POP @
<14,34,40,41> IRQ_SERIRQ
1 2 CLKRUN#_R 15
SERIRQ
1
PCH GPIO38 ->TPM_ID0
1
<16,40,41> CLKRUN#
2 4@ R655 0_0402_5%~D 7
CLKRUN# NC_1
2
PD RH270 POP @ POP
@ R656 4.7K_0402_5%~D TCM_BA1 PP NC_2
3 6
TCM_BA0 BA_1 NC_6
9 BA_0 NC_8 8
14
+3.3V_RUN_TCM NC_P JETWAY_CLK14M
1
1
4@
C554 @ JETWAY_PIN5
1
1U_0402_6.3V6K~D RE6
@ R657 @ R658 SSX44-B_TSSOP28~D 2 33_0402_5%~D 2
10K_0402_5%~D 10K_0402_5%~D
2
@C555
@C555
1 0.1U_0402_16V4Z~D
2
A @ 1 A
TCM_BA0
TCM Vender POP CE4
TCM_BA1 NationZ R660, R659, C554, C550 27P_0402_50V8J~D
2
1
4@ 4@
R659
1K_0402_5%~D
R660
1K_0402_5%~D Compal Electronics, Inc.
USH BCM5882 (2/2)
2

LA-6562P
5 4 3 2 1
A B C D E
NOTE1:
THESE 1394 SIGNALS ARE HIGH SPEED
DIFFERENTIAL PAIRS AND MUST BE KEPT EQUAL
LENGTH WITH A DIFFERENTIAL IMPEDANCE (Z0)
OF 110 OHMS.
NOTE2:
If used OZ600RJ1-A R680 need change to 5.1K ohm_1%.
If used OZ600RJ1-B R680 need change to 191 ohm _1%.
+1.5V_RUN @ R678 1 2 0_0402_5%~D
1
NOTE3: 1
If used OZ600RJ1-A POP R679 JUMP +3.3V_RUN. +3.3V_RUN R679 1 2 0_0402_5%~D +MMI_VCC_IN +SKT_VCC
If used OZ600RJ1-B CAN POP R679 or R678 JUMP +3.3V_RUN or +1.5V_RUN. 1 1
0.1U_0402_10V7K~D
1.5V_RUN for POWER SAVING MODE. 1 1
C573 C574 C575
C576
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D 0.1U_0402_10V7K~D 2 2
2 2
+3.3V_RUN
@ PJP59 +MMI_DVDD
1 2 +3.3V_RUN_OZ600 1 1
0.1U_0402_10V7K~D
4.7U_0603_6.3V6K~D
PAD-OPEN1x1m L47 C577 C578
1 1 1 2 +MMI_1394_VCCH 4.7U_0603_6.3V6K~D 0.1U_0402_10V7K~D
BLM18AG601SN1D_0603~D 2 2
C579
C580
BLM18AG601SN1D_0603~D
0.1U_0402_10V7K~D
2 2 1 2 +MMI_PE_VDDH
L46 1
+MMI_AVDD
C582
1 1 1 1
0.1U_0402_10V7K~D
4.7U_0603_6.3V6K~D
C581 C1185
C583
2
C584
0.1U_0402_10V7K~D 0.01U_0402_16V7K~D
2 2 2 2
28
33
34
24
10
35
11
42
1
9
U39
PE_VDDH
1394_VDDH
1394_VDDH
3.3VDDH
MMI_VCC_IN
VDDH
DVDD
DVDD
AVDD
IO_VOUT
SD/MMC_CLK_R 2 1 SD/MMC_CLK
L45 @ RE7 33_0402_5%~D
1
CPB- 4 3 TPB-
4 3 @
2 1 4 25 +3.3V_RUN_CARD RE8
CPB+ 1 TPB+ R680 191_0402_1%~D PE_REXT MMI_VCC_OUT 33_0402_5%~D
2
1 2
2
DLW21SN900HQ2L_0805_4P~D 1 2 PCIE_PTX_MMIRX_N6_C 5
<15> PCIE_PTX_MMIRX_N6 PE_RXM
COMMON MODE COKE COIL IS OPTIONAL FOR EMI PURPOSE. C586 0.1U_0402_10V7K~D 6 15 1
PCIE_PTX_MMIRX_P6_C PE_RXP XD_CD# MS_CD# @
2
<15> PCIE_PTX_MMIRX_P6 1 2 16 2
L48 @ C587 0.1U_0402_10V7K~D MS_CD# SD/MMCCD# CE5
17
CPA- TPA- PCIE_PRX_MMITX_P6_C SD_CD# 27P_0402_50V8J~D
4 3 2 1 7
4 3 <15> PCIE_PRX_MMITX_P6 C588 0.1U_0402_10V7K~D PE_TXP 2
CPA+ 1 2 TPA+ 2 1 PCIE_PRX_MMITX_N6_C 8 14 SDWP

1 2 <15> PCIE_PRX_MMITX_N6 C585 0.1U_0402_10V7K~D PE_TXM SD_WPI/XD_WPO
13
DLW21SN900HQ2L_0805_4P~D XD_RE# SD/MMC_CLK_R
36
MMI_CLK/XD_CE#
<15> CLK_PCIE_MMI# 2 12
PE_REFCLKM XD_WE# SD/MMCCMD_R SD/MMCCMD
<15> CLK_PCIE_MMI 3 37 1 2
PE_REFCLKP MMI_BS/CMD/ALE R1206 33_0402_5%~D
<17> PLTRST_MMI# 18
PE_RST#
22
<15> MMICLK_REQ# MULTI_IO2
38 SD/MMCDAT7_R 1 2 SD/MMCDAT7
MMI_D7 SD/MMCDAT6_R R1198 33_0402_5%~D SD/MMCDAT6
39 1 2
MMI_D6 SD/MMCDAT5_R R1199 33_0402_5%~D SD/MMCDAT5
40 1 2
J1394 CONN@ MMI_D5 SD/MMCDAT4_R R1200 33_0402_5%~D SD/MMCDAT4
41 1 2
CPB- R1055 0_0402_5%~D TPB- MMI_D4 SD/MMCDAT3_R R1201 33_0402_5%~D SD/MMCDAT3
1 1 2 26 43 1 2
TPB- CPB+ R1056 0_0402_5%~D TPB+ 1394_TPBN MMI_D3 MS_XD_D2_R R1202 33_0402_5%~D MS_XD_D2
2 1 2 27 44 1 2
TPB+ CPA- R1057 0_0402_5%~D TPA- 1394_TPBP MS_XD_D2 SD/MMCDAT2_R R1582 33_0402_5%~D SD/MMCDAT2
5 3 1 2 29 45 1 2
GND TPA- CPA+ R1058 0_0402_5%~D TPA+ 1394_TPAN SD_D2/XD_RB# MS_XD_D1_R R1203 33_0402_5%~D MS_XD_D1
6 4 1 2 30 46 1 2
GND TPA+ 1394_TPAP MS_XD_D1 SD/MMCDAT1_R R1583 33_0402_5%~D SD/MMCDAT1
31 47 1 2
TYCO_2010017-1 1394_TPBIAS SD_D1/XD_CLE SD/MMCDAT0_R R1204 33_0402_5%~D SD/MMCDAT0
48 1 2
53.6_0402_1%~D
53.6_0402_1%~D
53.6_0402_1%~D
53.6_0402_1%~D
MMI_D0 R1205 33_0402_5%~D

1
1394_XI 19
1394_XO 1394_XI
R683
R684
R685
R686
20
1394_XO
1 2 +1394_REF 32
2
R687 5.9K_0402_1%~D 1394_REF

23
MULTI_IO1
270P_0402_50V7K~D
5.11K_0402_1%~D
1U_0402_6.3V6K~D
1
1 1 21
1394_CPS
R690
GPAD
C589
C590
3 3
2 2 +3.3V_RUN_CARD
2
OZ600RJ1LN-B_QFN48_6X6~D
49
JSD1 CONN@
7
VDD
9 44
VCC VCC
0.1U_0402_16V4Z~D
4.7U_0603_10V6K~D
PLACE THESE PARTS NEAR OZ600RJ1 NOTE7: 1 1 SD/MMCDAT0 22
SD/MMCDAT1 DAT0
TERMINAL 49 (GND) IS THE EXPOSED PAD 23
DAT1 CD
27
C570
C572
ON THE BOTTOM OF PACKAGE AND MUST BE SD/MMCDAT2 1 28
SD/MMCDAT3 DAT2 R/-B
SOLDERED TO GND OF PCB. 2
CD/DAT3 -RE
29
C591 1 2 6.8P_0402_50V8D~D 1394_XI 2 2 SD/MMCDAT4 3 30
SD/MMCDAT5 DAT4 -CE
5 31
DAT5 CLE
1
SD/MMCDAT6 19 32
Y5 SD/MMCDAT7 DAT6 ALE
21 33
DAT7 -WE
24.576MHZ_12PF_1YG24576CE1C~D 34
SD/MMCCMD -WP
4
2
C592 1 CMD
2 6.8P_0402_50V8D~D R1060 1 2 0_0402_5%~D 1394_XO SD/MMC_CLK 18
CLK
24 36
SD/MMCCD# COM(SW) D0
25 37
SDWP CD(SW) D1
45 38
WP(SW) D2
39
SD/MMCDAT0 D3
14 40
MS_XD_D1 DATA0 D4
15 41
MS_XD_D2 DATA1 D5
13 42
SD/MMCDAT3 DATA2 D6
11 43
DATA3 D7
SD/MMC_CLK 10
MS_CD# SCLK
12 26
SD/MMCCMD INS GND
16 35
BS GND
6 46
VSS GND1
8 47
VSS GND2
17 48
VSS GND3
20 49
VSS GND4
4 T-SOL_152-1300302601_NR 4
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, OZ600 Card Reader
LA-6562P
A B C D E
5 4 3 2 1
+3.3V_RUN +3.3V_PCIE_WWAN +3.3V_ALW_PCH
PCIE_MCARD1_DET# 1 2
1 2 R692 100K_0402_5%~D
2.2K_0402_5%~D
2.2K_0402_5%~D
USB_MCARD2_DET# 2 1 @ R693 0_0402_5%~D
1
@R1159
@
@R1160
@
R694 100K_0402_5%~D
R1159
R1160
1 2 WLAN_RADIO_DIS#_R
<40> WLAN_RADIO_DIS#
D31
+3.3V_PCIE_WWAN RB751S40T1_SOD523-2~D
2
2 1 WWAN_SMBCLK
D
PCIE_MCARD2_DET# 1 2
<7,12,13,14,15,28> DDR_XDP_WAN_SMBCLK
<7,12,13,14,15,28> DDR_XDP_WAN_SMBDAT
R1157
2
0_0402_5%~D
1 WWAN_SMBDAT
Mini WLAN/WIMAX H=4 D
R695 100K_0402_5%~D R1158 0_0402_5%~D
USB_MCARD1_DET# 1 2 PCIE_MCARD1_DET# +3.3V_RUN
@ R698 0_0402_5%~D
Mini WWAN/GPS/LTE/UWB H=5.2 +3.3V_WLAN +3.3V_WLAN
JMINI2 +1.5V_RUN PCIE_MCARD1_DET# 1 2

USB_MCARD2_DET# 1 2 PCIE_MCARD2_DET# +3.3V_PCIE_WWAN +3.3V_PCIE_WWAN <29,38,40> PCIE_WAKE# PCIE_WAKE# 1 2 @ R699 100K_0402_5%~D
@ R697 0_0402_5%~D JMINI1 COEX2_WLAN_ACTIVE 1 2 USB_MCARD1_DET#
1 2 3 3 4 4 1 2
<42> COEX2_WLAN_ACTIVE COEX1_BT_ACTIVE R700 1
1 1 2 2 2 0_0402_5%~D 5 5 6 6 R701 100K_0402_5%~D
<42> COEX1_BT_ACTIVE R702 0_0402_5%~D
3 4 7 8
3 4 <15> MINI2CLK_REQ# 7 8
5 5 6 6 +1.5V_RUN 9 9 10 10 1 2
MINI1CLK_REQ# 7 8 11 12
<15> MINI1CLK_REQ# 7 8 +SIM_PWR <15> CLK_PCIE_MINI2# 11 12
9 10 UIM_DATA 13 14 MSDATA C595 4700P_0402_25V7K~D
9 10 <15> CLK_PCIE_MINI2 13 14
CLK_PCIE_MINI1# 11 12 UIM_CLK 15 16
<15> CLK_PCIE_MINI1# CLK_PCIE_MINI1 11 12 UIM_RESET 15 16 HOST_DEBUG_TX <41>
13 14
<15> CLK_PCIE_MINI1 13 14 UIM_VPP
15 16
15 16
17 17 18 18
<41> HOST_DEBUG_RX WLAN_RADIO_DIS#_R
19 20
<41> MSCLK 19 20
17 17 18 18 21 21 22 22 2 1 PCH_PLTRST#_EC
19 20 WWAN_RADIO_DIS# PCIE_PRX_WLANTX_N2 23 24 R703 0_0402_5%~D
19 20 WWAN_RADIO_DIS# <40> <15> PCIE_PRX_WLANTX_N2 23 24
21 22 1 2 PCIE_PRX_WLANTX_P2 25 26
PCIE_PRX_WANTX_N1 21 22 PCH_PLTRST#_EC <14,17,35,38,40,41> <15> PCIE_PRX_WLANTX_P2 25 26
23 24 R704 0_0402_5%~D 27 28
<15> PCIE_PRX_WANTX_N1 PCIE_PRX_WANTX_P1 23 24 0.1U_0402_10V7K~D 27 28
25 25 26 26 29 29 30 30
<15> PCIE_PRX_WANTX_P1 C596 1 PCIE_PTX_WLANRX_N2_C
27 27 28 28 <15> PCIE_PTX_WLANRX_N2 2 31 31 32 32
0.1U_0402_10V7K~D 29 30 WWAN_SMBCLK C598 1 2 PCIE_PTX_WLANRX_P2_C 33 34
29 30 <15> PCIE_PTX_WLANRX_P2 33 34
<15> PCIE_PTX_WANRX_N1
C597 1 2 PCIE_PTX_WANRX_N1_C 31 31 32 32 WWAN_SMBDAT 0.1U_0402_10V7K~D 35 35 36 36 USBP4-
USBP4- <17>
<15> PCIE_PTX_WANRX_P1
C599 1 2 PCIE_PTX_WANRX_P1_C 33 34 PCIE_MCARD1_DET# 37 38 USBP4+
USBP4+ <17>
0.1U_0402_10V7K~D 33 34 USBP5- COEX2_WLAN_ACTIVE <18> PCIE_MCARD1_DET# 37 38 USB_MCARD1_DET#
35 36 USBP5- <17> 39 40 USB_MCARD1_DET# <14,18>
35 36 39 40
1 2 PCIE_MCARD2_DET# 37 37 38 38 USBP5+
USBP5+ <17> 41 41 42 42 WIMAX_LED#
<17> PCIE_MCARD2_DET#_R R725 0_0402_5%~D USB_MCARD2_DET# WLAN_LED#
39 39 40 40 USB_MCARD2_DET# <18> 1 43 43 44 44
41 42 LED_WWAN_OUT# 45 46
41 42 <15> PCH_CL_CLK1 45 46 MSDATA
43 44 @ C600 47 48 1 2
C 43 44 <15> PCH_CL_DATA1 47 48 MSDATA <41> C
45 46 33P_0402_50V8J~D 1 2 49 50 @ R706 0_0402_5%~D
45 46 2 <15> PCH_CL_RST1# 49 50
47 48 R707 0_0402_5%~D 51 52
47 48 51 52
49 50 53 54
49 50 G1 G2
51 51 52 52
+3.3V_PCIE_WWAN 53 54 +3.3V_WLAN
G1 G2 LOTES_AAA-PCI-047-P10-A
+1.5V_RUN +3.3V_WLAN CONN@
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
33P_0402_50V8J~D
22U_0805_6.3VAM~D
33P_0402_50V8J~D
330U_D2E_6.3VM_R25~D
330U_D2E_6.3VM_R25~D
LOTES_AAA-PCI-047-P10-A
1 1 CONN@
100K_0402_5%~D
100K_0402_5%~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
4.7U_0603_6.3V6K~D
1 1 1 1 1 @
2
+ + +3.3V_PCIE_WWAN
C610
C611
C612
C613
C614
C615
C1176
R718
R705
1 1 1 1 1 1 1 1
@ C603
2 2 2 2 2 2 2
C601
C602
C604
C605
C606
C607
C608
5
1
2 2 2 2 2 2 2 2
100K_0402_5%~D
2
WIMAX_LED# 4 3 WIRELESS_LED#
R719
Q124B
2
2
G
1
WLAN_LED# 1 6
+1.5V_RUN LED_WWAN_OUT# 3 1 WIRELESS_LED# <40,44>
Q124A
S
Q77
33P_0402_50V8J~D
0.047U_0402_16V4Z~D
1 1
1/2 Minicard Flash Card H=4
+3.3V_PCIE_FLASH +3.3V_PCIE_FLASH
C593
C594
Primary Power Aux Power

B 2 2
PWR Voltage JMINI3
B
PCIE_WAKE# 1 2
Rail Tolerance Peak Normal Normal COEX2_WLAN_ACTIVE 1 2 3
1 2
4
R709 0_0402_5%~D 3 4
5 6 +1.5V_RUN
MINI3CLK_REQ# 5 6
<15> MINI3CLK_REQ# 7 7 8 8
+3.3V +-9% 1000 750 9
9 10
10 Confirm with DELL about UWB
CLK_PCIE_MINI3# 11 12
SIM Card Push-Push +3.3Vaux +-9% 330 250
250 (Wake enable)
5 (Not wake enable)
<15> CLK_PCIE_MINI3#
<15> CLK_PCIE_MINI3
CLK_PCIE_MINI3 13
15
11
13
15
12
14
16
14
16
+SIM_PWR +1.5V +-5% 500 375 NA 17 18

17 18
19 20
19 20
JSIM1 CONN@ 21 21 22 22 2 1 PCH_PLTRST#_EC
1 5 PCIE_PRX_WPANTX_N5 23 24 R710 0_0402_5%~D
UIM_RESET VCC GND UIM_VPP <15> PCIE_PRX_WPANTX_N5 PCIE_PRX_WPANTX_P5 23 24
2 RST VPP 6 25 25 26 26
UIM_CLK UIM_DATA <15> PCIE_PRX_WPANTX_P5
3 7 27 28
CLK I/O USB_MCARD3_DET# 27 28
4 8 1 2 PCIE_MCARD3_DET# 0.1U_0402_10V7K~D 29 30
NC NC @ R708 0_0402_5%~D C617 1 PCIE_PTX_WPANRX_N5_C 29 30
1 9 <15> PCIE_PTX_WPANRX_N5 2 31 32
GND C618 1 PCIE_PTX_WPANRX_P5_C 31 32
10 <15> PCIE_PTX_WPANRX_P5 2 33 34
C616 GND 0.1U_0402_10V7K~D 33 34 USBP6-
35 36 USBP6- <17>
1U_0402_6.3V6K~D MOLEX_475531001~D PCIE_MCARD3_DET# 35 36 USBP6+
37 38 USBP6+ <17>
2 <18> PCIE_MCARD3_DET# 37 38 USB_MCARD3_DET#
39 39 40 40
+3.3V_RUN 1 2 41 42
@R711
@ R711 100K_0402_5%~D 41 42
43 43 44 44 2 1 +3.3V_ALW_PCH
+1.5V_RUN +3.3V_PCIE_FLASH 45 46 @ R712 100K_0402_5%~D
U40 45 46
47 48
47 48
49 49 50 50 WPAN Noise
51 52
51 52
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
4.7U_0603_6.3V6K~D
UIM_RESET 1 6 UIM_VPP 53 54 USB_MCARD3_DET#

G1 G2
1 1 1 1 1 1 1 1 1
@ C621
2 5 +SIM_PWR LOTES_AAA-PCI-047-P10-A @
C619
C620
C622
C623
C624
C625
C626
A CONN@ C627 A
4700P_0402_25V7K~D
2 UIM_CLK UIM_DATA 2
3 4
33P_0402_50V8J~D
33P_0402_50V8J~D
33P_0402_50V8J~D
33P_0402_50V8J~D
1 1 1 1 DELL CONFIDENTIAL/PROPRIETARY
@ C628
@ C629
@ C630
@ C631
SRV05-4.TCT_SOT23-6~D
2 2 2 2 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Mini Card
LA-6562P
5 4 3 2 1
5 4 3 2 1
Power Control for Mini card1

+15V_ALW +3.3V_ALW +3.3V_WLAN
Express Card PWR S/W
D +1.5V_RUN +3.3V_RUN +3.3V_SUS D
D
100K_0402_5%~D
6
S
1
+3.3V_CARDAUX +1.5V_CARD
100K_0402_5%~D
5 4 +3.3V_CARD
R714
2
R713
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 Q38
0.1U_0402_16V4Z~D
10U_0603_6.3V6M~D
0.1U_0402_16V4Z~D
10U_0603_6.3V6M~D
0.1U_0402_16V4Z~D
10U_0603_6.3V6M~D
1 1 1
3
R715
2
C635
C634
C633
20K_0402_5%~D 1 1 1 1 1 1
4700P_0402_25V7K~D
2 2 2
C642
C643
C639
C641
C636
C638
1
2
Q39B
2 2 2 2 2 2
C632
5
6
Q39A 2 U41
4
DMN66D0LDW-7_SOT363-6~D 17 15
AUXIN AUXOUT
2 3.3VIN 3.3VOUT 3
<40> AUX_EN_WOWL 2 12 11
1.5VIN 1.5VOUT
1
R717 0_0402_5%~D 20 8 CARD_RESET#

1
SHDN# PERST#
<11,40,43,50> RUN_ON 1 2 EXPRCRD_STBY_R# 1 10 EXPRCRD_CPPE#
R716 PCH_PLTRST#_EC STBY# CPPE# CPUSB#
<14,17,35,37,40,41> PCH_PLTRST#_EC 6 9
100K_0402_5%~D SYSRST# CPUSB#
19 OC#
2
+3.3V_RUN 4
NC
+3.3V_CARD 5 NC RCLKEN 18
+1.5V_CARD 13
NC
+1.5V_RUN 14 7
NC GND
16 NC PAD 21
TPS2231MRGPR-2_QFN20_4X4~D
C Power Control for Mini card2 C
+3.3V_ALW +3.3V_PCIE_WWAN
+15V_ALW Q40
100K_0402_5%~D
@ R720
D
6 0_0805_5%~D
S
1
100K_0402_5%~D
5 4 1 2 +3.3V_RUN
1
R722
2 +1.5V_CARD: Max. 650mA, Average 500mA

R721
1
1
Express Card BTB Conn. +3.3V_CARD: Max. 1300mA, Average 1000mA
G
R723
2
1K_0402_5%~D
2
3
4700P_0402_25V7K~D
1
+3.3V_SUS
Q41B
+1.5V_CARD
1
D
C644
MCARD_WWAN_PWREN# 5
Q73
2 MCARD_WWAN_PWREN#
6
Q41A 2 G
4
2.2K_0402_5%~D
2.2K_0402_5%~D
DMN66D0LDW-7_SOT363-6~D S 1
3
1
R731
R732
2 1 2 C645
<40> MCARD_WWAN_PWREN 0.1U_0402_16V4Z~D
@ R724 0_0402_5%~D
1
2
1
R726
2
100K_0402_5%~D 1 2
@ R727 0_0402_5%~D
1 1 JEXP1 CONN@
<17> USBP10- 2 2
2
1
USBP10_D- GND1
2
B USBP10_D+ USB_D- B
<17> USBP10+ 4 4 3 3 3 USB_D+
CPUSB# 4
Power Control for Mini card3 L49 DLW21SN900SQ2_0805~D
CARD_SMBCLK
5
6
CPUSB#
RESERVED
RESERVED
<41> CARD_SMBCLK 7
CARD_SMBDAT SMB_CLK
<41> CARD_SMBDAT 8
SMB_DAT
9
+1.5V
10
+15V_ALW +3.3V_ALW Q42 +3.3V_PCIE_FLASH +1.5V
11
SI3456DDV-T1-GE3_TSOP6~D <29,37,40> PCIE_WAKE# WAKE#
+3.3V_CARDAUX 12 +3.3VAUX
100K_0402_5%~D
CARD_RESET# 13 PERST#
D
6 14
S
+3.3V_CARD +3.3V
1
100K_0402_5%~D
5 4 1 15 +3.3V
1
R729
2 16
<15> EXPCLK_REQ# CLKREQ#
R728
1 C646 1 EXPRCRD_CPPE# 17 CPPE#

1
0.1U_0402_16V4Z~D 18
G
2 <15> CLK_PCIE_EXP# REFCLK-

R730 C649 19
<15> CLK_PCIE_EXP
2
20K_0402_5%~D 0.1U_0402_16V4Z~D REFCLK+

20
2
2 GND
<15> PCIE_PRX_EXPTX_N3 21
PER_N0
3
4700P_0402_25V7K~D
<15> PCIE_PRX_EXPTX_P3 22
2
C647 0.1U_0402_10V7K~D PER_P0

1 23
GND
Q43B
1 2 PCIE_PTX_EXPRX_N3_C 24
<15> PCIE_PTX_EXPRX_N3 PET_N0
C650
5 1 2 PCIE_PTX_EXPRX_P3_C 25
<15> PCIE_PTX_EXPRX_P3 PET_P0
26 GND
6
Q43A 2 C648 0.1U_0402_10V7K~D

4
DMN66D0LDW-7_SOT363-6~D 27
GND
28 GND
<40> MCARD_MISC_PWREN 2 29
GND
30
GND
1
TYCO_1759762-1_NR TYCO_1759762-1_NR
R733
A 100K_0402_5%~D A
2
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, PCIE-SATA SW / PCIE PWR
LA-6562P
5 4 3 2 1
2 1
CONN@
JDOCK1
DOCK_DET_1 1 2 DOCK_AC_OFF
1 2 DOCK_AC_OFF <40,57>
3 3 4 4
<32> DOCK_LOM_SPD10LED_GRN# DPD_CA_DET DPC_CA_DET DOCK_LOM_SPD100LED_ORG# <32>
5 6
<27> DPD_CA_DET 5 6 DPC_CA_DET <27>
7 7 8 8
C690 2 1 0.1U_0402_10V7K~D DPD_DOCK_LANE_P0 9 10 DPC_DOCK_LANE_P0 C691 2 1 0.1U_0402_10V7K~D
<16> DPD_PCH_LANE_P0 DPD_DOCK_LANE_N0 9 10 DPC_DOCK_LANE_N0 DPC_PCH_LANE_P0 <16>
C679 2 1 0.1U_0402_10V7K~D 11 12 C680 2 1 0.1U_0402_10V7K~D
<16> DPD_PCH_LANE_N0 11 12 DPC_PCH_LANE_N0 <16>
13 13 14 14
C683 2 1 0.1U_0402_10V7K~D 17 18 C684 2 1 0.1U_0402_10V7K~D
19 19 20 20
C685 2 1 0.1U_0402_10V7K~D 23 24 C686 2 1 0.1U_0402_10V7K~D
25 25 26 26
C689 2 1 0.1U_0402_10V7K~D 29 30 C694 2 1 0.1U_0402_10V7K~D
31 32
DPD_DOCK_AUX 31 32 DPC_DOCK_AUX
<27> DPD_DOCK_AUX 33 33 34 34 DPC_DOCK_AUX <27>
DPD_DOCK_AUX# 35 36 DPC_DOCK_AUX#
<27> DPD_DOCK_AUX# 35 36 DPC_DOCK_AUX# <27>
37 38
DPD_PCH_DOCK_HPD 37 38 DPC_PCH_DOCK_HPD
<16> DPD_PCH_DOCK_HPD 39 40 DPC_PCH_DOCK_HPD <16>
B 39 40 B
+NBDOCK_DC_IN_SS 41 41 42 42 ACAV_DOCK_SRC# <57>
0.033U_0402_16V7K~D
0.033U_0402_16V7K~D
1 43 44 1
BLUE_DOCK 43 44
<25> BLUE_DOCK 45 45 46 46 DAT_DDC2_DOCK <25>
C695
C696
47 48 CLK_DDC2_DOCK <25>
47 48
2
49
49 50
50
2
Close to DOCK
51 52
RED_DOCK 53
51 52
54 SATA_PRX_DKTX_P5 2 1
Its for Enhance ESD on dock issue.
<25> RED_DOCK 53 54 SATA_PRX_DKTX_N5 SATA_PRX_DKTX_P5_C <14>
Close to DOCK 55 55 56 56 C697 2 1 0.01U_0402_16V7K~D SATA_PRX_DKTX_N5_C <14>
57 58 C698 0.01U_0402_16V7K~D
Its for Enhance ESD on dock issue. GREEN_DOCK 59
57 58
60 SATA_PTX_DKRX_P5 1 2
<25> GREEN_DOCK 59 60 SATA_PTX_DKRX_N5 SATA_PTX_DKRX_P5_C <14>
61 62 C699 1 2 0.01U_0402_16V7K~D
61 62 C700 0.01U_0402_16V7K~D SATA_PTX_DKRX_N5_C <14>
63 64
63 64
<25> HSYNC_DOCK 65 65 66 66 USBP8+ <17>
<25> VSYNC_DOCK 67 67 68 68 USBP8- <17>
69 70 DPC_PCH_DOCK_HPD
DPD_PCH_DOCK_HPD 69 70
<41> CLK_MSE 71 72 USBP9+ <17>
71 72
<41> DAT_MSE 73 73 74 74 USBP9- <17>
75 76
75 76
2
<30> DAI_BCLK# 77 78 CLK_KBD <41>
77 78
2
79 80 R758
<30> DAI_LRCK# 79 80 DAT_KBD <41>
R757 81 82 100K_0402_1%~D
81 82
100K_0402_1%~D <30> DAI_DI 83 84
83 84
<30> DAI_DO# 85 86
1
85 86
87 88
1
87 88
<30> DAI_12MHZ# 89 89 90 90
91 92
91 92
93 93 94 94
95 96
95 96
<40> D_LAD0 97 97 98 98
BREATH_LED# <41,44>
<40> D_LAD1 99 100
99 100 DOCK_LOM_ACTLED_YEL# <32>
101 102
101 102
<40> D_LAD2 103 104
103 104 DOCK_LOM_TRD0+ <32>
<40> D_LAD3 105 106
105 106 DOCK_LOM_TRD0- <32>
107 108
107 108 +3.3V_ALW
<40> D_LFRAME# 109 110
109 110 DOCK_LOM_TRD1+ <32> +LOM_VCT
<40> D_CLKRUN# 111 111 112 112
DOCK_LOM_TRD1- <32>
113 114
113 114 DOCK_DET#
<40> D_SERIRQ 115 116 1 1 2
115 116 @ R755 100K_0402_5%~D
<40> D_DLDRQ1# 117 118 +LOM_VCT
117 118 C701
119 120
119 120 1U_0402_6.3V6K~D
<17> CLK_PCI_DOCK 121 122 DOCK_LOM_TRD2+ <32>
121 122 2
123 124 DOCK_LOM_TRD2- <32>
123 124
125 125 126 126
<41> DOCK_SMB_CLK 127 128 DOCK_LOM_TRD3+ <32>
127 128
<41> DOCK_SMB_DAT 129 130 DOCK_LOM_TRD3- <32>
129 130
131 132
131 132
<41,47,57> DOCK_SMB_ALERT# 133 134 DOCK_DCIN_IS+ <55>
133 134
<47> DOCK_PSID 135 136 DOCK_DCIN_IS- <55>
135 136
137 137 138 138
139 140 D32
<41> DOCK_PWR_BTN# 139 140 DOCK_POR_RST# <41>
141 142 RB751S40T1_SOD523-2~D
SLICE_BAT_PRES# 141 142 DOCK_DET_R#
<40,47,57> SLICE_BAT_PRES# 143 143 144 144 1 2 DOCK_DET# <40>
145 149 +DOCK_PWR_BAR
GND1 PWR2
+DOCK_PWR_BAR 146 150
PWR1 PWR2
147 151
PWR1 PWR2
3
148 152
PWR1 GND2
SM24.TCT_SOT23-3~D
4.7U_0805_25V6K~D
0.1U_0603_50V4Z~D
0.1U_0603_50V4Z~D
C703
D33
1
1 @ 1 153 159
Shield_G Shield_G
C702
@ 154 160
Shield_G Shield_G
CE6
155 Shield_G Shield_G 161

156 162 2
1
2 2 Shield_G Shield_G
157 Shield_G Shield_G 163
158 164
A Shield_G Shield_G A
DAI_12MHZ# DAI_BCLK# CLK_PCI_DOCK
JAE_WD2F144WB1
1
@ RE11
@RE11 @ RE12 R756
10_0402_5%~D 10_0402_5%~D 33_0402_5%~D
2
1 1 1
@CE8
@CE8 @CE9
@CE9 C704
4.7P_0402_50V8C~D 4.7P_0402_50V8C~D 12P_0402_50V8J~D
2 2 2
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DOCKING CONN
2 1
5 4 3 2 1
+3.3V_ALW
1 2 DYN_TURB_PWR_ALRT#
R796 10K_0402_5%~D
1 2 PCIE_WAKE#
R759 10K_0402_5%~D
+3.3V_ALW
1 2 DCIN_CBL_DET#
R761 100K_0402_5%~D
1 1 1 1 1 1
1 2 CPU_DETECT# C705 C706 C707 C708 C709 C710

R763 100K_0402_5%~D 10U_0805_6.3V6M~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_10V7K~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D
2 2 2 2 2 2
D SLICE_BAT_PRES# D
1 2
R760 100K_0402_5%~D
A17
B30
A43
A54
B5
U46 +3.3V_ALW
+3.3V_ALW2
VCC1
VCC1
VCC1
VCC1
VCC1
ACAV_IN_NB <41,55,57> 1 2 C711
CRT_SWITCH B52 B63 SIO_SLP_A# 0.1U_0402_16V4Z~D
<25> CRT_SWITCH GPIOA0 GPIOI1 SIO_SLP_A# <16,51>
5
1 2 USB_SIDE_EN# MDC_RST_DIS# A49 A60 0.75V_DDR_VTT_ON
<45> MDC_RST_DIS# MCARD_MISC_PWREN GPIOA1 GPIOI2/TACH0 0.75V_DDR_VTT_ON <50>
R768 10K_0402_5%~D B53 A61 1
P
<38> MCARD_MISC_PWREN GPIOA2 GPIOI3 SIO_SLP_S4# <16> B
1 2 ESATA_USB_PWR_EN# DCIN_CBL_DET# A50 B65 4 2 1
<47> DCIN_CBL_DET# LID_CL_SIO# GPIOA3 GPIOI4 SIO_SLP_S3# <16> O DOCK_AC_OFF <39,57>
R769 10K_0402_5%~D B54 A62 2 D34
GPIOA4 GPIOI5 IMVP_PWRGD <53> A
G
A51 B66 1 2 RB751S40T1_SOD523-2~D
GPIOA5 GPIOI6 IMVP_VR_ON <53>
1
PCIE_WAKE# B55 A63 R765 0_0402_5%~D U47
<29,37,38> PCIE_WAKE#
3
GPIOA6 GPIOI7 DOCK_AC_OFF_EC TC7SH08FU_SSOP5~D R770
A52
GPIOA7 33K_0402_5%~D
B67
+3.3V_RUN USB_SIDE_EN# GPIOJ0 AUX_EN_WOWL <38> DOCK_AC_OFF_EC <57> +3.3V_ALW
<46> USB_SIDE_EN# A33 A64 WLAN_LAN_DISB# <32>
EN_I2S_NB_CODEC# GPIOB0 GPIOJ1/TACH1 SIO_SLP_LAN#
<30> EN_I2S_NB_CODEC# B36 A5 SIO_SLP_LAN# <16,32>
2
USH_PWR_STATE# GPIOB1 GPIOJ2/TACH2 SIO_SLP_SUS#
<34> USH_PWR_STATE# A34 B6 SIO_SLP_SUS# <16>
EN_DOCK_PWR_BAR GPOC2 GPIOJ3
<57> EN_DOCK_PWR_BAR B37 GPOC3 GPIOJ4 A6
PANEL_BKEN_EC MODC_EN GPIO_PSID_SELECT <47>
<24> PANEL_BKEN_EC A35 B7 MODC_EN <29>
WIRELESS_ON#/OFF ENVDD_PCH GPOC4 GPIOJ5 DOCK_HP_DET
1 2 <16,24> ENVDD_PCH B38 A7 DOCK_HP_DET <30>
R766 100K_0402_5%~D LCD_TST GPOC5 GPIOJ6 DOCK_MIC_DET WLAN_LAN_DISB#
<24> LCD_TST A36 B8 DOCK_MIC_DET <30> 2 1
SP_TPM_LPC_EN PSID_DISABLE# GPOC6/TACH4 GPIOJ7 R771 100K_0402_5%~D
1 2 A37 GPIOC7
@ R772 10K_0402_5%~D <47> PSID_DISABLE# PBAT_PRES# ME_FWP
<47,57> PBAT_PRES# B40 GPIOD0 GPIOK0 A8 ME_FWP <14>
1 2 LCD_TST DOCKED A38 B9 MASK_SATA_LED# MIC_MUTE# 2 1
<32> DOCKED GPIOC1 GPIOK1/TACH3 MASK_SATA_LED# <44>
R767 100K_0402_5%~D DOCK_DET# B41 B10 R773 100K_0402_5%~D
<39> DOCK_DET# AUD_NB_MUTE# GPIOC0 GPIOK2 LED_SATA_DIAG_OUT# 1.8V_RUN_PWRGD <50>
A39 A10 LED_SATA_DIAG_OUT# <44>
<30> AUD_NB_MUTE# MCARD_WWAN_PWREN GPIOB7 GPIOK3 TEMP_ALERT#_R
B42 B11 1 2TEMP_ALERT# TEMP_ALERT# <14,18>
SYS_LED_MASK# <38> MCARD_WWAN_PWREN LCD_VCC_TEST_EN GPIOB6 GPIOK4 RUN_ON R738 0_0402_5%~D +3.3V_RUN
1 2 <24> LCD_VCC_TEST_EN A40 GPIOB5 GPIOK5 A11 RUN_ON <11,38,43,50>
R775 10K_0402_5%~D CCD_OFF B43 B12 2 1 MIC_MUTE#
<24> CCD_OFF AUD_HP_NB_SENSE GPIOB4 GPIOK6 MIC_MUTE# <46>
<30,46> AUD_HP_NB_SENSE A41 A12 @
@R806
R806 1K_0402_5%~D
ESATA_USB_PWR_EN# GPIOB3 GPIOK7 SPI_WP#_SEL <14> D_CLKRUN#
<45> ESATA_USB_PWR_EN# B44 2 1
C GPIOB2 R777 100K_0402_5%~D C
GPIOL0/PWM7 B60
A57 GPIOL1 1 2 D_SERIRQ 2 1
MODULE_ON GPIOL1/PWM8 R1568 10K_0402_5%~D R780 100K_0402_5%~D
<57> MODULE_ON B32 B64
SLICE_BAT_ON GPIOD1 GPIOL2/PWM0 D_DLDRQ1#
<57> SLICE_BAT_ON A31 GPIOD2 GPIOL3/PWM1 B68 2 1
SLICE_BAT_PRES# B33 A9 R782 100K_0402_5%~D
<39,47,57> SLICE_BAT_PRES# MODULE_BATT_PRES# GPIOD3 GPIOL4/PWM3
B15 B1
<47,57> MODULE_BATT_PRES# CHARGE_MODULE_BATT GPIOD4 GPIOL5/PWM2
A15 GPIOD5 GPIOL6 A18
<57> CHARGE_MODULE_BATT CHARGE_PBATT B16 A44
<57> CHARGE_PBATT DEFAULT_OVRDE GPIOD6 GPIOL7/PWM5 RUN_ON
<57> DEFAULT_OVRDE A16 GPIOD7 2 1
B34 R786 100K_0402_5%~D
GPIOM1
GPIOM3/PWM4 B39
A1 B51 CPU_VTT_ON 2 1
<44> VOL_MUTE_LED# GPIOE0/RXD GPIOM4/PWM6
B2 R789 100K_0402_5%~D
GPIOE1/TXD
A2 LPC_LAD[0..3] <14,34,35,41>
MCARD_PCIE_SATA# GPIOE2/RTS# LPC_LAD0 0.75V_DDR_VTT_ON 2
B3 A27 1
PAD~D T168 @ CPU_DETECT# GPIOE3/DSR# LAD0 LPC_LAD1 R790 100K_0402_5%~D
<7> CPU_DETECT# A3 A26
GPIOE4/CTS# LAD1 LPC_LAD2 SLICE_BAT_ON
B45 B26 2 1
MOD_SATA_PCIE#_DET GPIOE5/DTR# LAD2 LPC_LAD3 R791 100K_0402_5%~D
A42 B25
<29> MOD_SATA_PCIE#_DET GPIOE6/RI# LAD3 LPC_LFRAME#
B4 A21 LPC_LFRAME# <14,34,35,41>
GPIOE7/DCD# LFRAME# PCH_PLTRST#_EC
LRESET# B22 PCH_PLTRST#_EC <14,17,35,37,38,41>
A28 CLK_PCI_5048
PCICLK CLK_PCI_5048 <17>
ZODD_WAKE# A59 B20 CLKRUN#
<29> ZODD_WAKE# BCM5882_ALERT# GPIOF0 CLKRUN# LPC_LDRQ0# CLKRUN# <16,35,41>
<34> BCM5882_ALERT# B62 A23 LPC_LDRQ0# <14>
GPIOF1 LDRQ0# LPC_LDRQ1#
<16> SUSACK# A58 A22 LPC_LDRQ1# <14>
GPIOF2 LDRQ1# IRQ_SERIRQ
B61 B21 IRQ_SERIRQ <14,34,35,41>
GPIOF3/TACH8 SER_IRQ CLK_SIO_14M
A56 A32 CLK_SIO_14M <15>
VGA_ID GPIOF4/TACH7 14.318MHZ/GPIOM0
B59 GPIOF5 CLK32/GPIOM2 B35 EC_32KHZ_ECE5048 <41>
A55
SLP_ME_CSW_DEV# GPIOF6
<14,18> SLP_ME_CSW_DEV# B58
GPIOF7 D_LAD0
B29
DLAD0 D_LAD1 D_LAD0 <39>
B28
LAN_DISABLE#_R DLAD1 D_LAD2 D_LAD1 <39>
<32> LAN_DISABLE#_R B47 A25
B CHARGE_EN GPIOG0/TACH5 DLAD2 D_LAD3 D_LAD2 <39> B
<57> CHARGE_EN A45 GPIOG1 DLAD3 A24
SYS_LED_MASK# D_LFRAME# D_LAD3 <39>
<44> SYS_LED_MASK# B48 GPIOG2 DLFRAME# B23 D_LFRAME# <39>
DYN_TURB_PWR_ALRT# A46 A19 D_CLKRUN#
<55> DYN_TURB_PWR_ALRT# GPIOG3 DCLKRUN# D_DLDRQ1# D_CLKRUN# <39>
<14,18> SIO_EXT_WAKE# R797 1 2 0_0402_5%~D B49 B24
GPIOG4 DLDRQ1# D_DLDRQ1# <39>
WIRELESS_LED# A47 A20 D_SERIRQ
+3.3V_ALW <37,44> WIRELESS_LED# PCH_PCIE_WAKE# GPIOG5 DSER_IRQ D_SERIRQ <39>
B50
<16> PCH_PCIE_WAKE# WLAN_RADIO_DIS# GPIOG6
<37> WLAN_RADIO_DIS# A48
GPIOG7/TACH6 BC_INT#_ECE5048
A29 BC_INT#_ECE5048 <41>
BC_INT# BC_DAT_ECE5048
B31 BC_DAT_ECE5048 <41>
WIRELESS_ON#/OFF BC_DAT BC_CLK_ECE5048
<46> WIRELESS_ON#/OFF B13 GPIOH0 BC_CLK A30 BC_CLK_ECE5048 <41>
1 2 VGA_ID BT_RADIO_DIS# A13
<42> BT_RADIO_DIS# GPIOH1
R800 100K_0402_5%~D WWAN_RADIO_DIS# A53
<37> WWAN_RADIO_DIS# SYS_PWROK SYSOPT1/GPIOH2 RUNPWROK
<7,16> SYS_PWROK B57 SYSOPT0/GPIOH3 PWRGD A4
RUNPWROK <7,41>
B14
GPIOH4 SP_TPM_LPC_EN
A14 GPIOH5 OUT65 B56 SP_TPM_LPC_EN <34,35>
CPU_VTT_ON B17 +3.3V_ALW
<52,56> CPU_VTT_ON GPIOH6
<16> PCH_DPWROK 1 2 B18
VGA_ID @R802
@ R802 0_0402_5%~D GPIOH7
1 2 B19 2 1
@R803
@ R803 100K_0402_5%~D TEST_PIN R804 1K_0402_5%~D +CAP_LDO trace width 20 mils
1
B46 +CAP_LDO
CAP_LDO CLK_SIO_14M CLK_PCI_5048 R805
1
B27 100K_0402_5%~D
VSS C714
C1
EP
1
4.7U_0603_6.3V6K~D @ R795
2
DB Version 0.4 2 @R794
@ R794 10_0402_5%~D
VGA_ID0 ECE5028-LZY_DQFN132_11X11~D 10_0402_5%~D LID_CL_SIO# 2 1 LID_CL# <44,46>
R807 10_0402_5%~D
Discrete 0 1
2
UMA 1 1 1 C716
0.047U_0402_16V4Z~D
@ C712 @ C713 2
A 4.7P_0402_50V8C~D 4.7P_0402_50V8C~D A
2 2
ME_FWP PCH has internal 20K PD.
(suspend power rail)
ME_FWP DELL CONFIDENTIAL/PROPRIETARY
2
@ R793 Compal Electronics, Inc.

1K_0402_5%~D PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, ECE5028
1
LA-6562P
5 4 3 2 1
5 4 3 2 1
+RTC_CELL
+3.3V_ALW +1.05V_RUN_VTT
H_PROCHOT# <7,53>
1
C720 @ C721
1 2 0.1U_0402_16V4Z~D 1 2 R810 1U_0402_6.3V6K~D
@ R1179 10K_0402_5%~D 100K_0402_5%~D 1 2
1
U50 D
2
1.05V_VTTPWRGD 1 PROCHOT#_EC 2 @ Q47
P
<52,56> 1.05V_VTTPWRGD B
4 1.05V_0.8V_PWROK G SSM3K7002FU_SC70-3~D POWER_SW_IN# 1 2
O 1.05V_0.8V_PWROK <14,53> <22> POWER_SW_IN# POWER_SW#_MB <31,42>
0.8V_VCCPWROK 2 1 2 S 1 R811 10K_0402_5%~D
3
<56> 0.8V_VCCPWROK A
G
@ R812 100K_0402_5%~D
TC7SH08FU_SSOP5~D C722
3
+RTC_CELL R815 +3.3V_ALW 1U_0402_6.3V6K~D
0_0402_5%~D 2
1 2 +RTC_CELL_VBAT 1 2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
10U_0805_6.3V6M~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
+3.3V_ALW 1 R1180 0_0402_5%~D
C723 1 1 1 1 1 1 1 1 1 +RTC_CELL
D D
1 2 BC_DAT_ECE5048 0.1U_0402_16V4Z~D
2
C724
C727
C728
C729
C730
C731
C725
C726
C732
R814 100K_0402_5%~D
1
2 1 BC_DAT_EMC4022 @C733
@ C733
R816 100K_0402_5%~D 2 2 2 2 2 2 2 2 2 R819 1U_0402_6.3V6K~D
2 1 BC_DAT_ECE1117 100K_0402_5%~D 1 2
B64
A11
A22
B35
A41
A58
A52
A26
R817 100K_0402_5%~D U51
B3
2
1 2 PBAT_SMBDAT
VBAT
VTR[1]
VTR[2]
VTR[3]
VTR[4]
VTR[5]
VTR[6]
VTR[7]
VTR[8]
R818 2.2K_0402_5%~D DOCK_PWR_SW# 1 2
<22> DOCK_PWR_SW# DOCK_PWR_BTN# <39>
1 2 PBAT_SMBCLK 1 R825 10K_0402_5%~D
R820 2.2K_0402_5%~D
2 1 LPC_LDRQ#_MEC PS/2 INTERFACE MISC INTERFACE C734
@R821
@ R821 100K_0402_5%~D SML1_SMBDATA A5 A10 SYSTEM_ID 1U_0402_6.3V6K~D
<15> SML1_SMBDATA SML1_SMBCLK GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA GPIO021/RC_ID1 BOARD_ID 2
<15> SML1_SMBCLK B6 B10
CHARGER_SMBDAT CLK_TP_SIO GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK GPIO020/RC_ID2 DDR_ON
1 2 <42> CLK_TP_SIO A37 B14 DDR_ON <49,50>
R827 2.2K_0402_5%~D DAT_TP_SIO GPIO110/PS2_CLK2/GPTP-IN6 GPIO025/UART_CLK HOST_DEBUG_TX
<42> DAT_TP_SIO B40 B44 HOST_DEBUG_TX <37>
CHARGER_SMBCLK CLK_KBD GPIO111/PS2_DAT2/GPTP-OUT6 GPIO120/UART_TX HOST_DEBUG_RX
1 2 <39> CLK_KBD A38 B46 HOST_DEBUG_RX <37>
R828 2.2K_0402_5%~D DAT_KBD GPIO112/PS2_CLK1A GPIO124/GPTP-OUT5/UART_RX RUNPWROK
<39> DAT_KBD B41 B26
DOCK_SMB_ALERT# CLK_MSE GPIO113/PS2_DAT1A VCC_PRWGD EN_INVPWR RUNPWROK <7,40>
2 1 <39> CLK_MSE A39 A25
R762 10K_0402_5%~D DAT_MSE GPIO114/PS2_CLK0A GPIO060/KBRST EN_INVPWR <24> +RTC_CELL
<39> DAT_MSE B42 GPIO115/PS2_DAT0A GPIO101/ECGP_SCLK B36
+3.3V_M PBAT_SMBDAT PCH_SATA_MOD_EN# <14>
<47> PBAT_SMBDAT B59 B37
PBAT_SMBCLK GPIO154/I2C1C_DATA/PS2_CLK1B GPIO103/ECGP_MISO XFR_ID_BIT# TOUCH_SCREEN_PD# <24>
<47> PBAT_SMBCLK A56 B38
GPIO155/I2C1C_CLK/PS2_DAT1B GPIO105/ECGP_MOSI
1
1 2 DAI_GPU_R3P_SMBDAT A34 DDR_HVREF_RST_GATE @ C738
R829 2.2K_0402_5%~D GPIO102/HSPI_SCLK DYN_TUR_CURRNT_SET# DDR_HVREF_RST_GATE <7> R870 1U_0402_6.3V6K~D
A35
DAI_GPU_R3P_SMBCLK GPIO104/HSPI_MISO CPU1.5V_S3_GATE DYN_TUR_CURRNT_SET# <55> 100K_0402_5%~D
1 2 A36 1 2
R822 2.2K_0402_5%~D GPIO106/HSPI_MOSI MSDATA CPU1.5V_S3_GATE <11>
JTAG INTERFACE GPIO116/MSDATA A40 MSDATA <37>
JTAG_TDI A51 B43 MSCLK
2
GPIO145/I2C1K_DATA/JTAG_TDI GPIO117/MSCLK MSCLK <37>
JTAG_TDO B55 A45 SIO_A20GATE
JTAG_CLK GPIO146/I2C1K_CLK/JTAG_TDO GPIO127/A20M PS_ID SIO_A20GATE <18> LAT_ON_SW#
B56 GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK GPIO153/LED3 A55 PS_ID <47> 1 2 LAT_ON_SW_BTN# <31>
+3.3V_ALW JTAG_TMS A53 A57 BAT1_LED# Bat2 = Amber LED 1 @ R877 10K_0402_5%~D
GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS GPIO156/LED1 BAT1_LED# <44>
JTAG_RST# B57 B61 BAT2_LED# Bat1 = Blue LED
JTAG_RST# GPIO157/LED2 BAT2_LED# <44>
B65 FWP# @ C740
@C740
nFWP
1
10K_0402_5%~D
A46 PROCHOT#_EC 20mA drive pins 1U_0402_6.3V6K~D

PROCHOT#/PWM4 2
R824
1 2 C736 High active +3.3V_RUN

JTAG_RST# citcuit 0.1U_0402_16V4Z~D FAN PWM & TACH
close to U51.B57 DOCK_POR_RST# B22 GENERAL PURPOSE I/O 1 2 VOL_MUTE
<39> DOCK_POR_RST# GPIO050/FAN_TACH1 VOL_MUTE <46>
1
SUS_ON A21 B2 R884 1K_0402_5%~D
2
<43> SUS_ON GPIO051/FAN_TACH2 GPIO001/ECSPI_CS1

AUX_ON B23 A2 DOCK_SMB_ALERT# R799
JTAG_RST# <32> AUX_ON BREATH_LED# GPIO052/FAN_TACH3 GPIO002/ECSPI_CS2 VOL_UP DOCK_SMB_ALERT# <39,47,57>
B24 B8 R886 1 2 1K_0402_5%~D 10K_0402_5%~D
<39,44> BREATH_LED# GPIO053/PWM0 GPIO014/GPTP-IN7/HSPI_CS1 VOL_UP <46>
C PCH_ALW_ON A23 B18 R887 1 2 1K_0402_5%~D VOL_DOWN C
<43> PCH_ALW_ON GPIO054/PWM1 GPIO040/GPTP-OUT3/HSPI_CS2 VOL_DOWN <46>
<24> BIA_PWM_EC BIA_PWM_EC B25 A8 ME_SUS_PWR_ACK
2
GPIO055/PWM2 GPIO015/GPTP-OUT7 ME_SUS_PWR_ACK <16>
1
1 HDDC_EN A24 B9 1.5V_SUS_PWRGD RUNPWROK

<28> HDDC_EN GPIO056/PWM3 GPIO016/GPTP-IN8 1.5V_SUS_PWRGD <49>
100_0402_5%~D
0.1U_0402_16V4Z~D
@ A9 PM_APWROK
1
GPIO017/GPTP-OUT8 PM_APWROK <16>

R836
C735
A14 1.05V_A_PWRGD
GPIO026/GPTP-IN1 1.05V_A_PWRGD <51>
1
ALW_PWRGD_3V_5V D
2
BC-LINK GPIO027/GPTP-OUT1
B15 ALW_PWRGD_3V_5V <48> @
JTAG1 BC_CLK_ECE5048 A43 A17 DEVICE_DET# 2
2
<40> BC_CLK_ECE5048 GPIO123/BCM_A_CLK GPIO041 DEVICE_DET# <29> <43> RUN_ON_ENABLE#
Q45
@SHORT PADS~D BC_DAT_ECE5048 B45 B39 RESET_OUT# G
<40> BC_DAT_ECE5048 GPIO122/BCM_A_DAT GPIO107/nRESET_OUT RESET_OUT# <16>
CONN@ BC_INT#_ECE5048 A42 A44 A_ON S
3
<40> BC_INT#_ECE5048 BC_CLK_EMC4022 GPIO121/BCM_A_INT# GPIO125/GPTP-IN5 PCH_RSMRST# A_ON <43,51>
A12 B47 PCH_RSMRST# <14,16>
<22> BC_CLK_EMC4022 GPIO022/BCM_B_CLK GPIO126
2
BC_DAT_EMC4022 B13 A54 AC_PRESENT

<22> BC_DAT_EMC4022 GPIO023/BCM_B_DAT GPIO151/GPTP-IN4 AC_PRESENT <16>
BC_INT#_EMC4022 A13 B58 SIO_PWRBTN#
2
<22> BC_INT#_EMC4022 GPIO024/BCM_B_INT# GPIO152/GPTP-OUT4 SIO_PWRBTN# <16>

B20
GPIO044/BCM_C_CLK +3.3V_ALW_PCH
A18
GPIO043/BCM_C_DAT
B19
GPIO042/BCM_C_INT# SMBUS INTERFACE
BC_CLK_ECE1117 A20 A3 DOCK_SMB_DAT
<42> BC_CLK_ECE1117 GPIO047/LSBCM_D_CLK GPIO003/I2C1A_DATA DOCK_SMB_DAT <39>
<42> BC_DAT_ECE1117 BC_DAT_ECE1117 B21 B4 DOCK_SMB_CLK AC_PRESENT 1 2
GPIO046/LSBCM_D_DAT GPIO004/I2C1A_CLK DOCK_SMB_CLK <39>
BC_INT#_ECE1117 A19 A4 LCD_SMBDAT R835 10K_0402_5%~D
+3.3V_ALW <42> BC_INT#_ECE1117 GPIO045/LSBCM_D_INT# GPIO005/I2C1B_DATA
BEEP A16 B5 LCD_SMBCLK
<30> BEEP SIO_SLP_S5# GPIO032/GPTP-IN3/BCM_E_CLK GPIO006/I2C1B_CLK BAY_SMBDAT
B16 B7 +3.3V_ALW
<16> SIO_SLP_S5# GPIO31/GPTP-OUT2/BCM_E_DAT GPIO012/I2C1H_DATA/I2C2D_DATA BAY_SMBDAT <29,47>
ACAV_IN_NB A15 A7 BAY_SMBCLK
<40,55,57> ACAV_IN_NB GPIO30/GPTP-IN2/BCM_E_INT# GPIO013/I2C1H_CLK/I2C2D_CLK BAY_SMBCLK <29,47>
10K_0402_5%~D
B48 DAI_GPU_R3P_SMBDAT LCD_SMBCLK 2 1

GPIO130/I2C2A_DATA
1
1
10K_0402_5%~D
10K_0402_5%~D
100K_0402_5%~D
@R850
@
B49 DAI_GPU_R3P_SMBCLK R418 2.2K_0402_5%~D

GPIO131/I2C2A_CLK
R847
R848
R849
R850
HOST INTERFACE A47 CHARGER_SMBDAT LCD_SMBDAT 2 1

SIO_EXT_SMI# GPIO132/I2C1G_DATA CHARGER_SMBCLK CHARGER_SMBDAT <55>
A6 B50 R420 2.2K_0402_5%~D
<14,17> SIO_EXT_SMI# GPIO011/nSMI GPIO140/I2C1G_CLK CHARGER_SMBCLK <55>
SIO_RCIN# A27 B52 CARD_SMBDAT DOCK_SMB_DAT 2 1
<18> SIO_RCIN# GPIO061/LPCPD# GPIO141/I2C1F_DATA/I2C2B_DATA CARD_SMBDAT <38>
LPC_LDRQ#_MEC B29 A49 CARD_SMBCLK R838 2.2K_0402_5%~D
2
LDRQ# GPIO142/I2C1F_CLK/I2C2B_CLK CARD_SMBCLK <38>

CONN@
JDEG1 IRQ_SERIRQ A28 B53 USH_SMBDAT DOCK_SMB_CLK 2 1
<14,34,35,40> IRQ_SERIRQ SER_IRQ GPIO143/I2C1E_DATA USH_SMBDAT <34>
1 PCH_PLTRST#_EC B30 A50 USH_SMBCLK R841 2.2K_0402_5%~D
1 MSCLK <14,17,35,37,38,40> PCH_PLTRST#_EC CLK_PCI_MEC LRESET# GPIO144/I2C1E_CLK USH_SMBCLK <34> DEVICE_DET#
2 <17> CLK_PCI_MEC A29 2 1
2 MSDATA LPC_LFRAME# PCI_CLK R1118 100K_0402_5%~D
7 3 <14,34,35,40> LPC_LFRAME# B31
G1 3 HOST_DEBUG_TX LPC_LAD0 LFRAME# VOL_MUTE
8 G2 4 4 1 2 <14,34,35,40> LPC_LAD0 A30 LAD0 DELL PWR SW INF 2 1
5 R853 1 2 0_0402_5%~D HOST_DEBUG_RX LPC_LAD1 B32 A59 R1169 100K_0402_5%~D
5 <14,34,35,40> LPC_LAD1 LAD1 BGPO0
6 R855 0_0402_5%~D LPC_LAD2 A31 B63 LAT_ON_SW# VOL_UP 2 1
6 <14,34,35,40> LPC_LAD2 LPC_LAD3 LAD2 VCI_IN2# ALWON
B33 A60 R1170 100K_0402_5%~D
<14,34,35,40> LPC_LAD3 LAD3 VCI_OUT ALWON <48>
ACES_85204-06001~D CLKRUN# A32 A63 VCI_INT1# VOL_DOWN 2 1
<16,35,40> CLKRUN# CLKRUN# VCI_IN1#
SIO_EXT_SCI# A33 B67 POWER_SW_IN# R1197 100K_0402_5%~D
+3.3V_ALW <18> SIO_EXT_SCI# GPIO100/nEC_SCI VCI_IN0#
B1 ACAV_IN BAY_SMBDAT 2 1
VCI_OVRD_IN ACAV_IN <22,55,57> +1.05V_RUN_VTT
A1 DOCK_PWR_SW# R854 2.2K_0402_5%~D
VCI_IN3# trace width 20 mils BAY_SMBCLK
B MASTER CLOCK 2 1 B
MEC_XTAL1 A61 PECI B51 +PECI_VREF 1 2 R856 2.2K_0402_5%~D
XTAL1 PECI_VREF
49.9_0402_1%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
MEC_XTAL2 2 1 MEC_XTAL2_R A62 A48 PECI_EC_R 1 2 R862 0_0402_5%~D DYN_TUR_CURRNT_SET# 2 1

XTAL2 PECI PECI_EC <7>
1
R1068 0_0402_5%~D B62 DB Version 0.12 R863 43_0402_5%~D 1 R1171 100K_0402_5%~D

GPIO160/32KHZ_OUT
R857
R858
R859
R860
R861
I2S B17 R863 close to

I2S_DAT U51& least 250mils C737 XFR_ID_BIT#
B27 1 2 2 1
I2S_CLK
VSS_RO
VR_CAP
B34 B28 @ R864 1 2 100K_0402_5%~D 0.1U_0402_16V4Z~D R943 10K_0402_5%~D

NC1 I2S_WS
VSS[1]
VSS[4]
2
AGND
A64 @ R865 100K_0402_5%~D

2
CONN@
JTAG2 NC2
1 2 B68
EP
<40> EC_32KHZ_ECE5048 NC3

1 @ R867 0_0402_5%~D
1 JTAG_TDI
2 Depopulated R867 for ECE5028 use MEC5055-LZY_DQFN132_11X11~D
B66
B11
B60
B12
B54
C1
2 JTAG_TMS
7 3 R864 & R865 +5V_RUN
G1 3 JTAG_CLK
8 G2 4 4 for MEC5045 need to used 0 ohm
5 JTAG_TDO for MEC5055 need to used 100K ohm. CLK_KBD 2 1
5 R845 4.7K_0402_5%~D
6
6 DAT_KBD
least 2 1
ACES_85204-06001~D +3.3V_ALW R875 C744 REV 15mil 15mil R846 4.7K_0402_5%~D
CLK_MSE 2 1
R851 4.7K_0402_5%~D
240K 4700p X00 1
2
C739
2 1 MSDATA DAT_MSE 2 1
4.7U_0603_6.3V6K~D
R875 R869 10K_0402_5%~D R852 4.7K_0402_5%~D

32 KHz Clock 62K_0402_5%~D 130K 4700p X01 2 +3.3V_ALW +3.3V_ALW R873
2 1 A_ON
100K_0402_5%~D
* 62K 4700p X02 1 2 AUX_ON
1
C741 BOARD_ID R874 2.7K_0402_5%~D

1 2 33K 4700p 1 2 DDR_ON
2
2
R876 100K_0402_5%~D +RTC_CELL
39P_0402_50V8J~D 1 8.2K 4700p R871 R872 1 2 SUS_ON
Y6 C744 1K_0402_5%~D 10K_0402_5%~D R878 100K_0402_5%~D VCI_INT1# 2 1
MEC_XTAL2 4 G 3 4700P_0402_25V7K~D 4.3K 4700p 1 2 PCH_ALW_ON R1156 100K_0402_5%~D
R880 100K_0402_5%~D
2K 4700p
1
1
2 1 2 DOCK_POR_RST#
MEC_XTAL1 1 +3.3V_M SYSTEM_ID FWP# R881 100K_0402_5%~D
G 2
1K 4700p
4700P_0402_25V7K~D
1 2 EN_INVPWR
32.768KHZ_12.5PF_Q13MC1461000~D R882 100K_0402_5%~D
1
C743 1 2 1 2 1.05V_0.8V_PWROK
1 2 R893 @ R879 R883 10K_0402_5%~D
C742
100K_0402_5%~D 10K_0402_5%~D
39P_0402_50V8J~D BOARD_ID rise time is measured from 5%~68%. 1 2 RESET_OUT#
2 @ R843 8.2K_0402_5%~D
2
A PCH_PWRGD# 1 2 CPU1.5V_S3_GATE A
PCH_PWRGD# <22>
R889 100K_0402_5%~D
Place closely pin A29
1
D
CLK_PCI_MEC RESET_OUT# 2 Q48
1=JTAG interface Reset disabled G SSM3K7002FU_SC70-3~D
_ID for BID
1
S 0=Reset JTAG interface

3
@ R885 function
10_0402_5%~D DELL CONFIDENTIAL/PROPRIETARY
2
1 Compal Electronics, Inc.

@ C747 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
4.7P_0402_50V8C~D
2 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, EMC5055
LA-6562P
5 4 3 2 1
5 4 3 2 1
Touch Pad
Pitch: 0.5
+3.3V_TP
D D
JTP1 CONN@
BlueTooth +3.3V_BT
4.7K_0402_5%~D
4.7K_0402_5%~D
1 1
1
TP_CLK 2
R903 2
R902
TP_DATA 3 1 2 1 2
3 +3.3V_RUN
4 R1129 0_0402_5%~D
4 C748
+3.3V_TP 5 +3.3V_ALW 1 2
PS2_DAT_TS 5 @ R1130 0_0402_5%~D 0.1U_0402_16V4Z~D
6 9
2
2
PS2_CLK_TS 6 G1
7 7 G2 10
2 1 TP_DATA 8 Pitch: 1.0
<41> DAT_TP_SIO 8
L54 BK1608HM601-T_0603~D
2 1 TP_CLK TYCO_2041070-8 CONN@
<41> CLK_TP_SIO
L55 BK1608HM601-T_0603~D JBT1
10P_0402_50V8J~D
10P_0402_50V8J~D
1
1
10P_0402_50V8J~D
10P_0402_50V8J~D
1 1 1 1 2
<17> BT_DET# 2
<37> COEX1_BT_ACTIVE 3
3
C752
C751
C750
C749
<34> BT_COEX_STATUS2 4 4
<34> BT_PRI_STATUS 5
2 2 2 2 5
6 6
<44> BT_ACTIVE
<40> BT_RADIO_DIS# 7
7
<37> COEX2_WLAN_ACTIVE 8
8
9
9
10 10
<17> USBP11- 11 11
<17> USBP11+ 12
12
13 G1
14
G2
LOTES_YBA-WTB-010-K01~D
100P_0402_50V8J~D
33P_0402_50V8J~D
110K_0402_5%~D
@ C754
C C
1 1
+3.3V_TP +3.3V_TP
C753
R904
TP_CLK
TP_DATA
2 2
SD05.TCT_SOD323-2~D
SD05.TCT_SOD323-2~D
+3.3V_RUN 1 2
2
1 R1161 0_0603_5%~D
1
+3.3V_ALW 1 2
C755 @R1162
@ R1162 0_0603_5%~D
@ D36
@ D37
0.1U_0402_16V4Z~D
2 2
2
Place close to @ R1133
1K_0402_5%~D
JTP1.7 Place close to JTP1 connector 1 2 BT_COEX_STATUS2
+3.3V_BT
@ R1134
1K_0402_5%~D
1 2 BT_PRI_STATUS
Keyboard
B B
Pitch: 1.0
+3.3V_ALW +5V_RUN JKB1 CONN@

1
<18> KB_DET# PS2_CLK_TS 1
2
PS2_DAT_TS 2
1 1 3
3
+3.3V_ALW 4 4
C756 C758 +5V_RUN 5
0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 5
6
2 2 <41> BC_INT#_ECE1117 6
<41> BC_DAT_ECE1117 7 7
8
8
<41> BC_CLK_ECE1117 9 9
10
10
Place close to JKB1 11
GND
12
GND
FCI_10089709-010010LF~D
Power Switch for debug
1 2
<31,41> POWER_SW#_MB 1 2
A A
1
@ C759
@C759
100P_0402_50V8J~D @ PWRSW1
2 @SHORT PADS~D
Place on Bottom DELL CONFIDENTIAL/PROPRIETARY
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Touch PAD/Int KB
LA-6562P
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW +3.3V_ALW_PCH
DC/DC Interface +5V_RUN Source
+3.3V_ALW_PCH Source @ 1 2 +3.3V_ALW2 +15V_ALW +5V_ALW Q50
+15V_ALW PJP67 PAD-OPEN 43X118 SI4164DY-T1-GE3_SO8~D +5V_RUN
+3.3V_ALW2 8 1
1
Q49 @ 7 2
10U_0805_10V4Z~D
6 SI3456DDV-T1-GE3_TSOP6~D R906 6 3
S
1
1
5 4 100K_0402_5%~D 5 1
10U_0805_6.3V6M~D
@ @ 2 R909 R910
@
1
20K_0402_5%~D
C761
R907 R905 1 100K_0402_5%~D 20K_0402_5%~D
@ 1
4
R908
100K_0402_5%~D 100K_0402_5%~D 5V_RUN_ENABLE
G
2
C760
2
2
3
ALW_ENABLE
2
<20> ALW_ENABLE 2
2200P_0402_50V7K~D
2
3
D Q52B D
@ RUN_ON_ENABLE# 5 DMN66D0LDW-7_SOT363-6~D 1
<41> RUN_ON_ENABLE#
Q51B 1
C763
ALW_ON_3.3V# 5 DMN66D0LDW-7_SOT363-6~D @
4
C762
6
3300P_0402_50V7K~D 2
4
@Q51A
@ Q51A 2 Q52A
<41> PCH_ALW_ON 2 <11,38,40,50> RUN_ON 2
1
+3.3V_RUN Source
+3.3V_ALW Q55 +3.3V_RUN
+15V_ALW NTMS4920NR2G_SO8~D
+3.3V_SUS Source +15V_ALW 8 1
10U_0805_6.3V6M~D
+3.3V_ALW Q54 7 2
1
20K_0402_5%~D
SI3456DDV-T1-GE3_TSOP6~D +3.3V_SUS 6 3 1
1
R912 5
C764
R913
R911 6 100K_0402_5%~D
S
+3.3V_ALW2 100K_0402_5%~D 5 4
4
2
10U_0805_6.3V6M~D
2
2
1
20K_0402_5%~D
1 1
2
3.3V_RUN_ENABLE
G
1
C765
R914
3
R915 SUS_ENABLE
1
100K_0402_5%~D 2 D
1
2
3
2
G Q56 C766
2
Q53B S SSM3K7002FU_SC70-3~D 470P_0402_50V7K~D
3
SUS_ON_3.3V# 5 DMN66D0LDW-7_SOT363-6~D 2
1
C C
6
C767
4
Q53A 4700P_0402_25V7K~D
DMN66D0LDW-7_SOT363-6~D 2
<41> SUS_ON 2
1
Discharg Circuit +1.5V_RUN Source

Q59
+3.3V_M +1.5V_MEM NTGS4141NT1G_TSOP6~D
+3.3V_M Source +15V_ALW +1.5V_RUN
D
+3.3V_ALW Q58 6
S
1
+15V_ALW SI3456DDV-T1-GE3_TSOP6~D +3.3V_M 5 4
10U_0805_6.3V6M~D
+3.3V_ALW2 R916
20K_0402_5%~D
2
D
1
6 39_0603_5%~D R920 1 1
S
1
5 4 100K_0402_5%~D
G
10U_0805_6.3V6M~D
C769
R921
R917 2
3
1
1
20K_0402_5%~D
100K_0402_5%~D
+3.3V_M_CHG
1 1 @
2
R918 2
G
2
C768
R919
100K_0402_5%~D 1.5V_RUN_ENABLE
2
A_ENABLE
2
2
2
3
1
1
D
Q57B 2 Q62 C771
1
A_ON_3.3V# 5 DMN66D0LDW-7_SOT363-6~D D G SSM3K7002FU_SC70-3~D 4700P_0402_25V7K~D
1 2
Q60
A_ON_3.3V# 2 S
3
6
C770 G
4
Q57A 4700P_0402_25V7K~D S
3
B DMN66D0LDW-7_SOT363-6~D 2 B
<41,51> A_ON 2
1
+1.05V_RUN Source
+15V_ALW +1.05V_M Q63
Discharg Circuit SI4164DY-T1-GE3_SO8~D
8 1
+1.05V_RUN
1
+3.3V_SUS +3.3V_ALW_PCH +5V_RUN +1.5V_RUN +3.3V_RUN +1.05V_RUN +1.5V_CPU_VDDQ +0.75V_DDR_VTT 7 2
10U_0805_6.3V6M~D
R930 6 3
1
20K_0402_5%~D
100K_0402_5%~D 5 1
1
C772
R931
@ R922 @ R928 @ R923 @ R924 R929 @ R925 R926
4
1K_0402_5%~D 1K_0402_5%~D 1K_0402_5%~D 1K_0402_5%~D 39_0603_5%~D 39_0402_5%~D 220_0402_5%~D R927 1.05V_RUN_ENABLE
22_0603_5%~D 2
2
2
1
D
2200P_0402_50V7K~D
+3.3V_ALWPCH_CHG
+5V_RUN_CHG
+1.5V_RUN_CHG
+3.3V_RUN_CHG
+1.05V_RUN_CHG
+1.5V_CPU_VDDQ_CHG
Q64
+3.3V_SUS_CHG
+DDR_CHG
G SSM3K7002FU_SC70-3~D 1
S
C773
2
<7,11> RUN_ON_CPU1.5VS3#
1
1
D D D D D
@ Q67
@ Q68
@ Q70
1
D D
@ Q65
@ Q66
Q69
Q72
RUN_ON_ENABLE# 2 2 2 2 2
1
SUS_ON_3.3V# ALW_ON_3.3V# 2 G G G G D G
2
Q71
G G S S S S 2 S
3
3
A G A
S S
3
3 S
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, POWER CONTROL
LA-6562P
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW HDD LED solution for White LED

+5V_ALW
1
R938
3
R932 +5V_ALW 100K_0402_5%~D Q83A
10K_0402_5%~D +5V_ALW 1 2
+3.3V_ALW DMN66D0LDW-7_SOT363-6~D
1 6 2
3
Q82A
6
Q74B Q74A DMN66D0LDW-7_SOT363-6~D Q81
DMN66D0LDW-7_SOT363-6~D DMN66D0LDW-7_SOT363-6~D PDTA114EU_SC70-3~D Battery LED
2
1
4 3 1 2 1 6 2 MASK_BASE_LEDS#
<14> SATA_ACT#_R
D59 RB751S40T1_SOD523-2~D R940 1 2 2
1
Q75 47K_0402_5%~D +5V_ALW 1 2 BATT_WHITE <46>
PDTA114EU_SC70-3~D C774 R941 4.7K_0402_5%~D
1
5
1
D D
1 2 0.1U_0402_16V4Z~D
1
MASK_SATA_LED# D62 RB751S40T1_SOD523-2~D +5V_ALW
P
BATT_YELLOW <46>
NC
1
<40> MASK_SATA_LED#
2 4 BAT2_LED R942
<41> BAT2_LED# A Y 100K_0402_5%~D
3
1 2 SATA_LED U54
SATA_LED <46> Q83B
R934 4.7K_0402_5%~D NC7SZ04P5X_NL_SC70-5~D
2
<40> LED_SATA_DIAG_OUT#
5 4 3 2
Q82B Q84
4
MASK_BASE_LEDS# DMN66D0LDW-7_SOT363-6~D PDTA114EU_SC70-3~D
5
SYS_LED_MASK#
1
+3.3V_ALW
R945
3
100K_0402_5%~D
Q92A
+3.3V_ALW 1 2
1 6 2
Q88
+3.3V_ALW PDTA114EU_SC70-3~D
2
Q89A MASK_BASE_LEDS#
6
WIRELESS LED solution for White LED
1
+3.3V_ALW
1
R947 1 2 2 +3.3V_ALW
1
+5V_ALW 47K_0402_5%~D 1 2
R937 C775 R946 150_0402_5%~D
1
5
1
100K_0402_5%~D 0.1U_0402_16V4Z~D
2
R948 +3.3V_ALW
NC
3
2 4 BAT1_LED 100K_0402_5%~D
2
<41> BAT1_LED# A Y
Q78A
3
DMN66D0LDW-7_SOT363-6~D U55
2
NC7SZ04P5X_NL_SC70-5~D Q92B R949
1 6 2
3
<37,40> WIRELESS_LED#
DMN66D0LDW-7_SOT363-6~D 4.7K_0402_5%~D
Q79 5 4 3 2 1 2 BATT_WHITE_LED <24>
PDTA114EU_SC70-3~D
2
C Q89B Q93 C
4
MASK_BASE_LEDS# DMN66D0LDW-7_SOT363-6~D PDTA114EU_SC70-3~D
5
R951
3
150_0402_5%~D
1
SYS_LED_MASK# 1 2 BATT_YELLOW_LED <24>
<42> BT_ACTIVE 5
Q78B
4
1 2 WIRELESS_LED <46>
1
R939 4.7K_0402_5%~D
R944
100K_0402_5%~D
2
+5V_ALW
1
+5V_ALW
R953
100K_0402_5%~D
3
SPK Status LED Q95B
2
4 3 2
+3.3V_ALW
6
B B
Q94
PDTA114EU_SC70-3~D
5
Q95A
C777
0.1U_0402_16V4Z~D 2 +5V_ALW
1
1
1 2 <40> SYS_LED_MASK# 1 2 BREATH_WHITE_LED <24>
R954 R955 4.7K_0402_5%~D
1
47K_0402_5%~D +5V_ALW
+3.3V_RUN R956
100K_0402_5%~D
3
1
Q101B
P
NC
2
+3.3V_RUN <39,41> BREATH_LED#
R1109 @ 2 4 BREATH_LED#_R DMN66D0LDW-7_SOT363-6~D
10K_0402_5%~D A Y
4 3 2
G
U57
6
NC7SZ04P5X_NL_SC70-5~D Q96
2
3
@ Q119
3
PDTA114EU_SC70-3~D
5
Q101A
2
1
S
3 1 2 MASK_BASE_LEDS# LED1
<40> VOL_MUTE_LED# BREATH_BLUE_LED_SNIFF
1 2 2 1
1
R957 1K_0402_5%~D
Q102 @ +3.3V_ALW LTW-C193TS5_WHITE~D
G
Place LED1 close to SW1

2
PDTA114EU_SC70-3~D C778
MASK_BASE_LEDS# 0.1U_0402_16V4Z~D
1
1 2 1 2
@R1059
@ R1059 1K_0402_5%~D R_SPK_LED# <46>
5
U58
SYS_LED_MASK# 1
P
<40> SYS_LED_MASK# B MASK_BASE_LEDS#
O 4
LID_CL# 2
<40,46> LID_CL# A
G
TC7SH08FU_SSOP5~D EMI CLIP
3
CLIP1
EMI_CLIP
1
Fiducial Mark LED Circuit Control Table GND
A @ FD1 A
1 SYS_LED_MASK# LID_CL#
FIDUCIAL MARK~D @ H1
@H1 @ H2 @ H3 @ H4
@H4 @ H5 @ H6
@H6 @ H7 @ H8 @ H9
@H9 @ H10 @ H11
@H11 @ H26 @ H27
@H27
H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P3 H_2P3
@ FD2
1
Mask All LEDs (Sniffer Function) 0 X
Mask Base MB LEDs (Lid Closed) 1 0
1
FIDUCIAL MARK~D
@ FD3
Do not Mask LEDs (Lid Opened) 1 1 DELL CONFIDENTIAL/PROPRIETARY
1
@ H12
@H12 @ H13 @ H14 @ H15
@H15 @ H19 @ H20
@H20 @ H21 @ H22
@H22 @ H23
@H23 @ H25
FIDUCIAL MARK~D H_3P2 H_3P2 H_3P2 H_3P2 H_6P1 H_2P5 H_8P0X2P5 H_2P8 H_8P0X2P5N H_2P8 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
@ FD4 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, PAD and Standoff
1 NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
1

FIDUCIAL MARK~D LA-6562P
5 4 3 2 1
5 4 3 2 1
+5V_USB_PWR1
150U_B2_6.3V-M~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
0.1U_0402_16V4Z~D
+3.3V_RUN
ESATA Repeater 1
1 @ 1 @ 1
0.01U_0402_16V7K~D
0.1U_0402_16V4Z~D
+
2
0_0402_5%~D
0_0402_5%~D
C667
C1151
C1152
C668
+3.3V_RUN 1 1 @
R742
R743
2 2 2 2
C662
1 2 ESATA_PWRSAVE JESA1 CONN@
C661
R741 0_0402_5%~D 1
2 2 USBP1_D- VBUS
2
1
D USBP1_D+ D- USB D
3 D+
U44 4 GND
7 EN VCC 6
18 10
ESATA_PTX_DRX_P4_C ESATA_PTX_DRX_P4 CAD VCC ESATA_PTX_DRX_P4_RP
<14> ESATA_PTX_DRX_P4_C 2 1 16 1 2 SATA_PTX_DRX_P4 5
C664 0.01U_0402_16V7K~D VCC C671 0.01U_0402_16V7K~D GND
1 AINP VCC 20 6 A+
ESATA_PTX_DRX_N4_C 2 1 ESATA_PTX_DRX_N4 2 ESATA_PTX_DRX_N4_RP 1 2 SATA_PTX_DRX_N4 7 ESATA
<14> ESATA_PTX_DRX_N4_C AINM A-
C663 0.01U_0402_16V7K~D 9 C672 0.01U_0402_16V7K~D 8
ESATA_PRX_DTX_N4_C PA GND
2 1 ESATA_PRX_DTX_N4 4 BOUTM PB 8 ESATA_PRX_DTX_N4_RP 1 2 SATA_PRX_DTX_N4 9 B-
<14> ESATA_PRX_DTX_N4_C C666 0.01U_0402_16V7K~D C673 0.01U_0402_16V7K~D
5 10
ESATA_PRX_DTX_P4_C BOUTP B+
<14> ESATA_PRX_DTX_P4_C 2 1 ESATA_PRX_DTX_P4 AOUTP 15 ESATA_PTX_DRX_P4_RP ESATA_PRX_DTX_P4_RP 1 2 SATA_PRX_DTX_P4 11 GND
C665 0.01U_0402_16V7K~D 3 14 ESATA_PTX_DRX_N4_RP C674 0.01U_0402_16V7K~D
GND AOUTM
13 GND
17 11 ESATA_PRX_DTX_P4_RP 12
GND BINP ESATA_PRX_DTX_N4_RP GND
19 12 13
GND BINM GND
21 14
EP GND
15 GND
1
MAX4951BECTP+TGH7_TQFN20_4X4~D
@ R745 @R746
@ R746 FOX_3Q38111-RA5C5-8H
0_0402_5%~D 0_0402_5%~D
2
L51
4 3 USBP1_D+
<17> USBP1+ 4 3
1 2 USBP1_D-
<17> USBP1- 1 2
DLW21SN900SQ2_0805~D
1 2
@R736
@ R736 0_0402_5%~D
C C
1 2
@R737
@ R737 0_0402_5%~D
D73
USBP1_D- 2
1
USBP1_D+ 3
+5V_USB_PWR2 CONN@
L50 JUSB1
4 3 USBP0_D+ 1 8
<17> USBP0+ 4 3 VBUS G
150U_B2_6.3V-M~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
USBP0_D- 2 7
+5V_USB_PWR2 +5V_USB_PWR1 D- G
0.1U_0402_16V4Z~D
1 USBP0_D+ 3 6
USBP0_D- @ @ D+ G
<17> USBP0- 1 2 1 1 1 4 5
1 2 + GND G
C651
C1153
C1154
C654
+5V_ALW U45 DLW21SN900SQ2_0805~D
PJP7
@ 1 10 USB_OC0# <17> 1 2 SUYIN_020173GR004M57HZL
+5V_ALW_FUSE GND FAULT1# @ R734 0_0402_5%~D 2 2 2 2
2 1 2 9
2 1 IN OUT1
10U_0805_10V4Z~D
3 8
IN OUT2
0.1U_0402_16V4Z~D
4 7 1 2
JUMP_43X79 EN1# ILIM @ R735 0_0402_5%~D
1 1 <40> ESATA_USB_PWR_EN# 5 6
EN2# FAULT#2
1
11
T-PAD
C669
C670
B R747 B
TPS2560DRCR-PG1.1_SON10_3X3~D 24.9K_0402_1%~D
2 2 D72
USBP0_D- 2
2
1
USBP0_D+ 3
CONN@
JMDC1
+3.3V_ALW_PCH
1 2
<14> PCH_AZ_MDC_SDOUT
PCH_AZ_MDC_SDOUT 3
GND1
IAC_SDATA_OUT
RES0
RES1
4 W=20 mil
5 6
GND2 3.3V
<14> PCH_AZ_MDC_SYNC 7 8
MDC_SDIN IAC_SYNC GND3
MDC CONN. H=5.5, Pitch=0.8 <14> PCH_AZ_MDC_SDIN1 1 2 9
IAC_SDATA_IN GND4
10
4.7U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
RH37 33_0402_5%~D PCH_AZ_MDC_RST1# 11 12 PCH_AZ_MDC_BITCLK <14> 1 1
IAC_RESET# IAC_BITCLK
C676
C675
GND
GND
GND
GND
GND
GND
1 3 PCH_AZ_MDC_RST1# 2 2
D
<14> PCH_AZ_MDC_RST#
+5V_ALW TYCO_1-1775149-2~D
13
14
15
16
17
18
Q44
G
2
R751 C677 Connector for MDC Rev1.5
1
100K_0402_5%~D 10P_0402_50V8J~D
A PCH_AZ_MDC_BITCLK 2 A
R752 1 BITCLK_TERM 1 2
10K_0402_5%~D R753 10_0402_5%~D
2
PCH_AZ_MDC_SDOUT 2 1 SDOUT_TERM 1 2
~D R754 10_0402_5%~D
2
C678
<40> MDC_RST_DIS#
10P_0402_50V8J~D DELL CONFIDENTIAL/PROPRIETARY
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, USBx2/ESATA/MDC
LA-6562P
5 4 3 2 1
5 4 3 2 1
D D
power 20mil
JSF1 CONN@
1 1
<18> IO1_LOOP#
2 2
<40,44> LID_CL#
+3.3V_ALW 3 3
4 4
<40> WIRELESS_ON#/OFF
1 5 5 G1 7
C1184 6 8
0.1U_0402_16V4Z~D 6 G2
TYCO_2041084-6~D
2
normal trace 50ohm

SNIFFER /Hall SENSOR IO BOARD
C C
TYCO_2041300-2
USBx2 /CRT/ AUDIO JACK IO BOARD
MEDIA BOARD
65 66
GND GND
63 64
GND GND
61 GND GND 62
59 60
59 60
<17> USBP2+ 57 58 +5V_ALW
CONN@ 57 58
<17> USBP2- 55 56 1
JLED1 55 56 C1181
53 54
B MEDIA_DET# 53 54 0.1U_0402_16V4Z~D B
1 1 <17> USBP3+ 51 51 52 52
<18> MEDIA_DET#
Defult on, 2
3
2 <17> USBP3- 49
47
49 50 50
48 2
3 47 48
WIRELESS_ON/OFF#: 4 4 <25> RED_CRT
RED_CRT 45 45 46 46
5 43 44
LOW: ON 6
5
6 <25> GREEN_CRT
GREEN_CRT 41
43
41
44
42
42 +5V_RUN
7 39 40
HIGH: OFF <44> R_SPK_LED# BATT_YELLOW 8
7 BLUE_CRT 37
39 40
38
<44> BATT_YELLOW 8 <25> BLUE_CRT 37 38 +3.3V_RUN
BATT_WHITE 9 35 36
<44> BATT_WHITE 9 35 36
SATA_LED 10 DAT_DDC2_CRT 33 34
<44> SATA_LED WIRELESS_LED 10 <25> DAT_DDC2_CRT CLK_DDC2_CRT 33 34
<44> WIRELESS_LED 11 11 <25> CLK_DDC2_CRT 31 31 32 32
MIC_MUTE# 12 29 30
<40> MIC_MUTE# VOL_MUTE 12 HSYNC_BUF 29 30
13 13 <25> HSYNC_BUF 27 27 28 28
<41> VOL_MUTE VOL_DOWN VSYNC_BUF MIC_IN_R
14 <25> VSYNC_BUF 25 26
<41> VOL_DOWN VOL_UP 14 25 26 MIC_IN_R <30>
15 15 23 23 24 24
<41> VOL_UP AUD_HP_OUT_R
16 <40> USB_SIDE_EN# 21 22 AUD_HP_OUT_R <30>
16 21 22
19 20
<17> USB_OC1# 19 20
17 17 18
GND AUD_HP_NB_SENSE 17 18
18 15 16
GND <30,40> AUD_HP_NB_SENSE 15 16 AUD_HP_OUT_L
13 14 AUD_HP_OUT_L <30>
TYCO_1-2041084-6 IO_LOOP# 13 14
11 12
<18> IO_LOOP# AUD_MIC_SWITCH 11 12
<30> AUD_MIC_SWITCH 9 9 10 10
7 8
7 8
5 5 6 6
3 4
3 4
1 2
1 2
JBTB1 CONN@
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, IO BOARD
LA-6562P
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
+COINCELL
ESD Diodes COIN RTC Battery
1
PR1
DA204U_SOT323~D
DA204U_SOT323~D
DA204U_SOT323~D
3
2
1K_0402_5%~D
PD33
PD34
PD32
PL21 +3.3V_ALW +3.3V_RTC_LDO
2
Media Bay Battery Connector @ @ @ FBMJ4516HS720NT_1806~D
1 2
Z4012
100K_0402_5%~D
1
1
Current rating:7A per pin. JRTC1
1
@ PJP36 +COINCELL 1 3
MBATT+_C 1 G
2 1 MPBATT+ 2 4
2 G
3
D D
MBATT1 PR501
PR504
0.1U_0603_25V7K~D
1
1 100_0402_5%~D PR502 PAD-OPEN 2x2m~D +RTC_CELL TYCO_2-1775293-2~D
1 Z5304 100_0402_5%~D PR503
PC302
2 1 2 BAY_SMBCLK 45
2
2 Z5305 100_0402_5%~D
3 1 2 BAY_SMBDAT 45 44
2
3 Z5306
4 1 2 MODULE_BATT_PRES#
2200P_0402_50V7K~D
4 PD1
5
1
5
6
6
1
RB715F_SOT323~D
PC301
1
7 PC1
GND 1U_0603_10V4Z~D
8
2
GND
2
SUYIN_150010GR006M500ZR Move to power schematic
GND +3.3V_ALW
ESD Diodes
PL22 +3.3V_ALW
FBMJ4516HS720NT_1806~D
1 2
DA204U_SOT323~D
DA204U_SOT323~D
DA204U_SOT323~D
3
1
PD2
PD3
PD4
100K_0402_5%~D
PL1
PR2
@ @ @ FBMJ4516HS720NT_1806~D
1 2
Primary Battery Connector
1
2
PBATT+_C PBATT+
11 PBAT_PRES# 44
0.1U_0603_25V7K~D
GND
1
10
GND
PC2
9 PR4 @ PQ1
9 100_0402_5%~D PR3
C 8 C
2
8 Z4304 100_0402_5%~D PR5 FDN338P_NL_SOT23-3~D
7 1 2 PBAT_SMBCLK 45
2200P_0402_50V7K~D
7 Z4305 100_0402_5%~D @ PD5

6 1 2 PBAT_SMBDAT 45
6 Z4306
5 1 2 1 2 1 3
3
5 DOCK_SMB_ALERT# 43,44
1
PC3
4
4 RB751V-40_SOD323-2~D
3
3
2
2
2
2
2
1
1
@ PR6
PBATT1 1 2
43,44,57 SLICE_BAT_PRES#
SUYIN_200275MR009G50PZR 0_0402_5%~D
1
@ PC4
1500P_0402_7K~D
2
GND +5V_ALW
+3.3V_ALW
DA204U_SOT323~D
3
2
PD6
@ PR7 PU1
2.2K_0402_5%~D
2
1 2 GND 43 DOCK_PSID 1 6 GPIO_PSID_SELECT 44
0_0402_5%~D NO IN
PR8
2 5 +5V_ALW
PL2 PR9 GND V+
1
BLM18BD102SN1D_0603~D 33_0402_5%~D
NB_PSID D NB_PSID_TS5A63157
S
2 1 1 3 1 2 3 4 PS_ID 45
NC COM
PQ2 TS5A63157DCKR_SC70-6~D
100K_0402_1%~D
2
FDV301N_NL_SOT23-3~D +5V_ALW
G
2
+5V_ALW
PR10
+5V_ALW
DA204U_SOT323~D
2
2
10K_0402_1%~D
DA204U_SOT323~D
1
B B
C
PD8
PQ3
PR11
2
3
B MMST3904-7-F_SOT323~D
PD9
E @
15K_0402_1%~D
3
2
@
1
1
@ PD7
PR12
SM24_SOT23 PR13
GND 1 2
1
PSID_DISABLE# 44
1
PR14 @ 10K_0402_5%~D
0_0402_5%~D
1 2 DCIN_CBL_DET# 44
.47U_0402_6.3V6-K~D
DC_IN+ Source
2
PC5
@ +DC_IN +DC_IN_SS
PQ4
FDS6679AZ_SO8~D
1 8
PL3 S D
2 7
FBMJ4516HS720NT_1806~D S D
3 6
+DC_IN S D
1 2 4 5
G D
1
1M_0402_5%~D
VZ0603M260APT_0603
2
0.022U_0805_50V7K~D
100K_0402_5%~D
10U_1206_25V6M~D
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
1
1
PC6
PR15
1
PD10
1
1
PC7
PC8
PC9
PR16
PC11
2
2
0.1U_0603_25V7K~D
1
PJPDC1 PR18
4.7K_0805_5%~D
2
1
1 @ 1 2 SOFT_START_GC 57
2
0.1U_0603_25V7K~D
1
1
PC10
2
2
2 -DCIN_JACK 10K_0402_5%~D
@ PR17
3
3
1
2
PC12
4
2
4 +DCIN_JACK
PR19
5
2
5
A 6 A
6 @
7
7
2
MOLEX_87438-0743 PL4
1 2
0.1U_0603_25V7K~D
1

PC13
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D +DCIN
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 0.3
LA-6562P
5 4 3 2 1
5 4 3 2 1
+3.3V_ALWP/ +5V_ALWP/ +5V_ALW2 / +15V_ALWP/ +3.3V_RTC_LDO
@ PL19
1 2 +DC1_PWR_SRC
PJP46
+PWR_SRC 1 2
PAD-OPEN 4x4m
Pop 10 Ohm for MAX17020
2
PJP47 +5V_VCC1
0_0805_5%~D
0_0805_5%~D
D D
+5V_ALW2 1 2
0.1U_0805_50V7M~D
2200P_0402_50V7K~D
PR20
PR21
10U_1206_25V6M~D
10U_1206_25V6M~D
10U_1206_25V6M~D
0.1U_0805_50V7M~D
2200P_0402_50V7K~D
PAD-OPEN1x1m @ PR22
1
10_0603_5%~D
10U_1206_25V6M~D
10U_1206_25V6M~D
10U_1206_25V6M~D
1
1
PC19
PC20
PC21
PC22
PC23
2 1
4.7U_0603_6.3V6K~D
PC14
PC15
PC16
PC17
PC18
2
2
1
@
PC24
@
+3.3V_ALW2
2
0.1U_0603_25V7K~D
1
PC25
1U_0402_6.3V4Z~D
@ PR24
0_0402_5%~D
1U_0603_10V6K~D
1
1
0_0402_5%~D
PC26
2
1
PR23
PC27
1 2
2
@ PR25
2
0_0402_5%~D
2
1 2
+5V_ALW2P
+5V_3V_REF
EN_3V_5V
+3.3V_ALW2
PC28
5 Volt +/-5% +3.3V_RTC_LDO
0.1U_0603_25V7K~D
1
GNDA_3V5V 1 2 GNDA_3V5V PR27
VIN
Thermal Design Current : 6.8A 0_0402_5%~D
LDOREFIN 1 2 3.3 Volt +/-5%
Peak Current : 9.7A
Thermal Design Current : 4.7A
0.1U_0402_10V7K~D
@ PR26
OCP_MIN : 11.6A PR28
2
0.1U_0402_10V7K~D
3
0_0603_5%~D @
PC30
33
Peak current : 6.7A
8
7
6
5
4
3
2
1
5
6
7
8
GNDA_3V5V PU2 1 2
D
FDS8878 1N SO8
1
+5V_ALWP 0_0402_5%~D
PC29
PAD
LDOREFIN
IN
RTC
VCC
TON
D
D
D
D
LDO
ONLDO
REF
OCP_MIN : 8A
AO4466L 1N SO8
REFIN2
PQ5
@
Fsw = 400KHz
2
2
PQ6
2 @ PR29
G 249K_0402_1%~D
9 32 4
+5V_ALWP PR30 10
BYP
OUT1
REFIN2
ILIM2
31 1 2 GNDA_3V5V G Fsw = 300KHz
S
294K_0402_1%~D +5V_FB1 11 30 +3.3V_OUT2

FB1 OUT2
S
S
S
C GNDA_3V5V 1 2 12 29 2 PR31 10_0402_5%~D +3.3V_ALWP C
1
PL5 POK1 ILIM1 SKIP POK2

13 28
3
2
1
EN_3V_5V PGOOD1 PG00D2 EN_3V_5V PL6
14 27
3.3UH_FDVE1040-H-3R3M=P3_11.3A_20%~D +5V_ALW_UGATE ON1 ON2 +3.3V_ALW_UGATE 4.7UH_FDVE1040-H-4R7M=P3_10A_20%~D
15 26
+5V_ALWP +5V_ALW_PHASE DH1 DH2 +3.3V_ALW_PHASE +3.3V_ALWP
1 2 16 25 2 1
LX1 LX2
SECFB
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
1
1
AGND
PGND
GNDA_3V5V @
BST1
BST2
0_0402_5%~D
0_0402_5%~D
VDD
0.1U_0603_25V7K~D
5
6
7
8
1
DL1
DL2
FDMS7692 1N POWER56-8
PC32
PC31
D
330U_V_6.3VM~D
330U_V_6.3VM~D
0.1U_0603_25V7K~D
PR32
PR33
D
D
D
D
2
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
1
PC34
PC35
1 1
17
18
19
20
21
22
23
24
AO4406AL 1N SO8
PQ7
@ ISL6236IRZA_QFN32~D
2
1
1
+ @ +
PC33
PC36
PC37
PC38
2
2
G
SECFB
PQ8
4
G
2
2
PR34 PR35 @ PR37
2
2
2 2
S
@ 2.2_0603_5%~D 2.2_0603_5%~D 4.7_1206_5%~D @
S
S
S
1 2+5V_ALW_BOOT +3.3V_ALW_BOOT 1 2
0_0402_5%~D
1
1
1
@
0_0402_5%~D
4.7_1206_5%~D
3
2
1
+3.3V_ALW_LGATE
PR36
PR39
1
1
PR38
@
2
2
+5V_ALW_LGATE
GNDA_3V5V
GNDA_3V5V
GNDA_3V5V PC39 PJP48
1U_0603_10V6K~D
1
+5V_ALWP 2 0.1U_0603_25V7K~D 1 2
+3.3V_ALWP +3.3V_ALWP
PC40
1 1 2
3
+5V_ALW2
2
0.1U_0603_25V7K~D
PAD-OPEN1x1m
1
PD11 GNDA_3V5V
100K_0402_1%~D
100K_0402_1%~D
PC41
BAT54SW-7-F_SOT323-3~D
2
2
PC42
PR40
PR41
2 0.1U_0603_25V7K~D PD13
1
1 1 2 BAT54CW_SOT323~D
B B
3 @
1
PR42 PD12 POK2
2K_0402_5%~D
2 1 BAT54SW-7-F_SOT323-3~D
45 ALWON
3
0_0402_5%~D
1
200K_0402_5%~D
2
PR43
PR45
0_0402_5%~D
PR44
23 THERM_STP# 2 1
2
1
POK1
ALW_PWRGD_3V_5V 45
PJP49 PR46
1 2 PJP51 200K_0402_1%~D
+15V_ALW 2 1 +15V_ALWP 2 1
PAD-OPEN 4x4m
0.1U_0603_25V7K~D
PJP50 PAD-OPEN1x1m
2
+5V_ALWP 1 2 (100mA,20mils ,Via NO.=1)

+5V_ALW
1
PR47
PC43
PAD-OPEN 4x4m 39K_0402_5%~D

2
PJP52
1 2 +3.3V_ALW
+3.3V_ALWP
PAD-OPEN 4x4m
GNDA_3V5V
PJP9
1 2
A PAD-OPEN 4x4m A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DC/DC +3V/ +5V
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.3
LA-6562P
5 4 3 2 1
5 4 3 2 1
1.5 Volt +/-5%

+1.5V_SUS_P(RT8209B) Thermal Design Current: 9.6A
Peak current: 13.8A
OCP_MIN:16.6A
D
Fsw:300KHz D
@ PL28
1 2
PJP10
1.5V_PWR_SRC 1 2 +PWR_SRC
PAD-OPEN 4x4m
2200P_0402_50V7K~D
0.1U_0805_50V7M~D
10U_1206_25V6M~D
10U_1206_25V6M~D
10U_1206_25V6M~D
1
1
PC44
PC45
PC46
PC47
PC48
5
PQ22
FDMS7692_SO8~D
2
PR49 @ @
C C
255K_0402_1%~D
1 2
4
PR50 PR48
GNDA_1.5V PC50
0_0402_5%~D 2.2_0603_5%~D
DDR_ON 1 2 BST_1.5VP 1 2 1 2
3
2
1
45
2
0.1U_0603_25V7K~D
1
@ PC51 @ PR508 PL7
15
14
1
1U_0402_6.3V4Z~D 300K_0402_5%~D PU3 1UH_FDUE1040D-1R0M=P3_21.3A_20%~D
1 2
EN/DEM
NC
BOOT
+1.5V_SUS_P
2
2 13 DH_1.5VP
TON UGATE
1
@
PR51 LX_1.5VP PC53
330U_SX_2VY~D
330U_SX_2VY~D
2200P_0402_50V7K~D
3 12
0.1U_0402_10V7K~D
VOUT PHASE
5
10_0402_5%~D 0.1U_0603_25V7K~D
2
+5V_ALW PQ21
0_0402_5%~D
1 2 4 11 1 2 1 1
FDMS0310S_DFN8-5
+5V_ALW VDD CS
1
PR55
+ +
PR53
PC56
PC57
PC58
PC59
5 10 7.68K_0402_1%~D
FB VDDP
2
1
6 9 DL_1.5VP 4
PGOOD LGATE
2
PGND
PC49 @ PR56 2 2
GND
1
4.7U_0603_6.3V6K~D 4.7_1206_5%~D
2
2
B @ PC615 PC52 B
2 1 RT8209MGQW_WQFN14_3P5X3P5 4.7U_0805_10V4Z~D
7
3
2
1
1
1
GNDA_1.5V +3.3V_ALW 47P_0402_50V8J~D
GNDA_1.5V
PR52
10K_0402_1%~D
100K_0402_1%~D
1 2 GNDA_1.5V
1
1
PR59
PR54
10K_0402_1%~D
2
PJP11
2
1 2
1.5V_SUS_PWRGD PAD-OPEN 4x4m
45 GNDA_1.5V
PJP13
+1.5V_SUS_P 1 2 +1.5V_MEM
PAD-OPEN 4x4m
PJP12
A
1 2 A
PAD-OPEN1x1m
GNDA_1.5V
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.5V_MEM
LA-6562P
5 4 3 2 1
5 4 3 2 1
1.8 Volt +/-5%

Thermal Design Current: 0.82 A
+1.8V_RUNP Peak current: 1.17 A
+3.3V_ALW PJP14
+1.8V_PWR_SRC
OCP_MIN: 1.4 A
2 1
PAD-OPEN 2x2m~D
Fsw:1.1MHz
10U_0805_6.3V6M~D
22U_0805_6.3V4Z~D
0.1U_0603_25V7K~D
PC68
2
1
PC66
PC67
1
D PR60 D
2
@ 0_0603_5%~D
2
+1.8V_VDD
13
14
15
16
17
PU4
VIN
VIN
PGND
PGND
TPAD
PR61
PC69
1 2 12 1 +1.8V_EN 2 1 RUN_ON
VDD EN 12,28,38,44,47
GNDA_1.8V 0.1U_0402_10V7K~D 24k_0402_1%~D
11 AGND RES 2
TPS51311RGTR_QFN16_3X3~D
PR64
PC70 PR63
1 2 2 1 +1.8V_FB 10 3 2 1 +3.3V_RUN
FB PGOOD
0.012U_0402_16V7K~D 10_0402_1%~D
+1.8V_RUNP
PR65 PR66 PC71 10K_0402_5%~D

2 1 2 1 2 1 +1.8V_COMP 9 4 +1.8V_VBST
COMP VBST
2K_0402_1%~D 1.43K_0402_1%~D 0.018U_0402_16V7K~D 44 1.8V_RUN_PWRGD
MODE
PC72
1K_0402_1%~D
3.3_0603_1%~D
2
SW
SW
SW
2 1
1
PR67
PR68
100P_0402_50V8J~D
1
PC73
+1.8V_MODE
2
C
2 1 C
GNDA_1.8V PR69 0.22U_0603_10V7K~D

PJP15 1 2 PL8
1 2 2UH_#A915AY-H-2R0M=P3_3.3A_20%~D
57.6K_0402_1%~D +1.8V_SW 2 1 +1.8V_RUNP
PAD-OPEN1x1m
680P_0603_50V8J~D
47P_0402_50V8J~D
22U_0805_6.3V4Z~D
22U_0805_6.3V4Z~D
PC74
GNDA_1.8V GNDA_1.8V
1
PC75
PC76
PC77
@
2
1
PR70
4.7_0805_5%~D
2
@
+0.75V_DDR_VTT PJP16
+1.8V_RUNP 2 1 +1.8V_RUN
PAD-OPEN 2x2m~D
DDR3 Termination
B B
+5V_ALW
0.75Volt +/-5%
4.7U_0805_10V4Z~D
PU5 Thermal Design Current: 0.7A

2
RT9026GFP_MSOP10~D
Peak current: 1A
PC78
PJP17 +V_DDR_REF
+1.5V_MEM 2 1 DC_1+0.75V_VTT_PWR_SRC 1 10
1
VDDQSNS VIN
PAD-OPEN 2x2m~D 2 VLDOIN
+0.75V_P
8
0.1U_0603_25V7K~D
GND
VTTREF 6
3 PR71
VTT
2
PC81
0_0402_5%~D PJP18
10U_0805_6.3V6M~D
0.1U_0603_25V7K~D
2
5 9 +0.75V_S5 2 1 2 1
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
VTTSNS S5 +0.75V_DDR_VTT
PC82
PC83
PR72 +0.75V_P
1
PGND
7 +0.75V_S3 2 1 PAD-OPEN 2x2m~D

GND
1
S3
2
2
PC79
PC80
0_0402_5%~D
1
11
DDR_ON 40,46
A A
0.75V_DDR_VTT_ON 39
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT +0.75V_DDR_VT/+1.8V_RUN
5 4 3 2 1
5 4 3 2 1
Fsw:300KHz 1.05 Volt +/-5%

+1.05V_M Thermal Design Current : 2.9A
Peak current : 4.2A
OCP_MIN :5A
D D
@ PL29
1 2
PJP40
1.05VM_PWR_SRC 1 2 +PWR_SRC
PAD-OPEN 4x4m
2200P_0402_50V7K~D
0.1U_0805_50V7M~D
10U_1206_25V6M~D
10U_1206_25V6M~D
10U_1206_25V6M~D
1
1
PC62
PC64
PC61
PC65
PC63
5
6
7
8
PR184
2
226K_0402_1%~D
AO4466L 1N SO8
D
D
D
D
1 2 @ @
@ PR336
PQ52
0_0402_5%~D
SIO_SLP_A# 1 2 4
17,44 GNDA_1.05VM G
PR199 PR188
C PC288 C
S
S
S
0_0402_5%~D 2.2_0603_5%~D
A_ON 1 2 BST_1.05VM 1 2 1 2
3
2
1
45,47
0.1U_0603_25V7K~D
1
PL26 +1.05V_MP
15
14
1
@ PC285 PU16 1.8UH_PCMB104T-1R8MS_15A_20%
1U_0402_6.3V4Z~D 1 2
EN/DEM
NC
BOOT
2
2 13 DH_1.05VM
TON UGATE
1
@
330U_SX_2VY~D
PR194 LX_1.05VM PC291
2200P_0402_50V7K~D
3 12
0.1U_0402_10V7K~D
VOUT PHASE
5
6
7
8
10_0402_5%~D 0.1U_0603_25V7K~D
AO4406AL 1N SO8
1
2
+5V_ALW 1 2 4 11 1 2 +5V_ALW
VDD CS
1
+
PC294
PR178
PC290
PC282
5 10 6.2K_0402_1%~D
FB VDDP
2
PQ18
1
DL_1.05VM 2
6 PGOOD LGATE 9 4
2
PC287 PGND @ PR204
GND
4.7U_0603_6.3V6K~D 4.7_1206_5%~D
2
2
PC289
PC616
@ RT8209MGQW_WQFN14_3P5X3P5 4.7U_0805_10V4Z~D
7
3
2
1
2 1
1
GNDA_1.05VM
47P_0402_50V8J~D GNDA_1.05VM
B +3.3V_ALW B
PR198
GNDA_1.05VM
100K_0402_1%~D
1 2
10K_0402_1%~D
1
1
PR77
PR200
24.9K_0402_1%~D
2
1.05V_A_PWRGD
45
PJP22
+1.05V_MP 1 2 +1.05V_M
PAD-OPEN 4x4m
PJP20
1 2
PAD-OPEN1x1m
A A
GNDA_1.05VM
Title
+1.05V_M
0.3
LA-6562P
5 4 3 2 1
5 4 3 2 1
+1.05VTT_RUN
@ PL30
1 2
PC108
PJP23
1U_0402_6.3V6K~D +1.05VTT_PWR_SRC 1 2 +5V_ALW
2 1 PAD-OPEN 4x4m
10U_1206_25V6M~D
10U_1206_25V6M~D
10U_1206_25V6M~D
10U_0805_10V4Z~D
10U_0805_10V4Z~D
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
D D
PC112
PC113
1
1
+1.05VTT_VX
@ PC147
@ PC192
@ PC109
PC110
PC111
1.05Volt +/-5%
2
GNDA_1.05VTT
17
16
Thermal Design Current : 6A
2
PU7
PC114
VIN
VIN
PC115 100P_0402_50V8J~D +3.3V_ALW 0.22U_0603_10V7K~D Peack current : 8.5A
1
2 1 PR89
2.2_0603_5%~D OCP_MIN : 10.2A
1 VCCA VBST 15 +1.05VTT_BST 1 2
PR90 PC116 2 14 +1.05VTT_PWRGD PR91

5.6K_0402_5%~D 680P_0402_50V7K~D GND PGOOD 0_0402_5%~D CPU_VTT_ON 44,58 Fsw:1MHz
2 1 2 1 +1.05VTT_COMP 3 13 +1.05VTT_EN 1 2
COMP EN 22.1K_0402_1%~D
+1.05VTT_VFB 4 12 +1.05VTT_FSET 2 1
VFB FSET @ PR92
PR93 +1.05VTT_SENSE 5 11 +1.05VTT_MODE
2K_0402_0.5%~D VOUT MODE
2
2 1 +1.05VTT_SS 6 10 +1.05VTT_IMON GNDA_1.05VTT
+1.05VTT_SENSE
SS IMON PR95
1
22K_0402_5%~D
0.01U_0402_16V7K
PGND
PGND
PC118
2 1 1 2
SW
2
1
PR94 PC117
0_0402_5%~D 1800P_0402_50V7K~D SN1003055RUWR_QFN17_3P5X3P5~D
9
+1.05VTTP
GNDA_1.05VTT PL10
0.42UH_ETQP4LR42AFM_20A_20%~D
+1.05VTT_VX
C C
+1.05VTT_VX 2 1
GNDA_1.05VTT
PC130
PC124
1
1
@
1.33K_0402_1%~D
20K_0402_0.5%~D
3.09K_0402_0.5%~D
@ PR97
PC128
PC131
PC119
47U_0805_4V6M~D
47U_0805_4V6M~D
6800P_0402_25V7K~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
0.1U_0603_25V7K~D
1
1
0.1U_0603_25V7K~D
2
PR505
PR96
PC120
PC129
PC121
PC122
PC123
PC125
PC126
PC127
@ PR98 0_0402_5%~D
2
2 1
2
2
2
1
PR100
10_0402_5%~D
@ PR99
7.68K_0805_1%~D
2
GNDA_1.05VTT
PR105
1 2
0_0402_5%~D
PR102
GNDA_1.05VTT +1.05VTT_SENSE 1 2 VTT_SENSE 11
0_0402_5%~D
VTT_GND 11
PR101
B B
2 1 +5V_RUN PJP25
PJP24
9.31K_0402_1%~D 1 2 2 1
PR103 PAD-OPEN 43X118
+1.05VTT_PWRGD PAD-OPEN1x1m
1 2 1.05V_VTTPWRGD 45,58
PJP26
0_0402_5%~D +1.05VTTP 1 2 +1.05V_RUN_VTT
GNDA_1.05VTT
PR104 PAD-OPEN 43X118
2 1
13.3K_0402_1%~D
A A
Title
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.05V_RUN_VTT
LA-6562P
5 4 3 2 1
5 4 3 2 1
+VCC_PWR_SRC
@ PC401
VCC_core
10U_1206_25VAK~D
10U_1206_25VAK~D
2200P_0402_50V7K~D
0.1U_0603_25V7K~D
5
0.033U_0402_16V7K~D
10U_1206_25VAK~D
Thermal Design Current : 38A
AON6414AL_DFN~D
1
PC132
1 2
PC351
PC133
PC134
PC135
Peak current : 53A
2
PQ9
UGATE3 4
OCP min : 63.6A PC136
0.33U_0603_10V7K~D
PR118 +5V_ALW PR107 PC137
1 2 2 1 2.2_0603_5%~D 0.22U_0603_10V7K~D
3
2
1
PC138 BOST3 2 1 BT3_1 1 2
1_0603_1%~D 1U_0603_10V6K~D PU8 PL11
2 1 5 1 0.36UH_FDUE1040J-H-R36M=P3 33A_20%~D
VDD BST
2 PR109 1 6 8 PHASE3 4 1 +VCC_CORE
D
40.2K_0402_1%~D P1_SW SKIP DH D
2 1
1
2 7 P3_SW 3 2P3_Vo
470P_0603_50V8J~D
PWM LX
Layout Note: PH1 PR111 PR110 4.32K_0402_1%~D PQ11
PQ12
PC139
AON6704L_DFN8-5
AON6704L_DFN8-5
1
1 2 2 1 2 1 P2_SW 3 4
PC142 close to PIN19
2
GND DL 2.1K_0402_1%~D PR114
10K_0402_1%_ERTJ0EG103FA~D 2.1K_0402_1%~D PR112 4.32K_0402_1%~D 9 @ @ PR113 1_0402_5%~D
P3_SW EP LGATE3
2 1 4 4
1
MAX17491GTA+T_TQFN8_3X3~D
2
PR115 4.32K_0402_1%~D
2.2_1206_1%~D
PR117
1
+Vcore_VCC PC140 PR120
3
2
1
3
2
1
PR121 0_0402_5%~D PR122 10_0402_5%~D 2200P_0402_50V7K~D 2 1
2
+5V_ALW 1 2 +Vcore_VDD 1 2 @ 22.1K_0402_1%~D
2
1K_0402_1%~D
215K_0402_1%~D
215K_0402_1%~D
5.62K_0402_1%~D
5.62K_0402_1%~D
2.2U_0603_10V7K~D
1
2
PC143 @ PC144
1
2.2U_0603_10V7K~D
PC142
PR123
PR124
PR125
PR126
PR127
1 2
1U_0603_10V6K~D
+Vcore_CSPA3
PC141
GNDA_VCC 1 2
2
@ PC145 1000P_0402_50V7K~D
2
<15,43> 1.05V_0.8V_PWROK 1 2 GNDA_VCC 1 2 PC146
1
@ PR129 0_0402_5%~D 0.22U_0603_16V7K~D
1000P_0402_50V7K~D 2 1
<42> IMVP_VR_ON 1 2 +Vcore_IMAXA
@ PR131 0_0402_5%~D
+GFX_IMAXB +Vcore_CSNA
100K_0402_1%_TSM0B104F4251RZ~D
100K_0402_1%_TSM0B104F4251RZ~D
+Vcore_CSPAAVE
+VGFX_THERMB
+Vcore_THERMA
1 2
10K_0402_1%~D
162K_0402_1%~D
137K_0402_1%~D
+VCC_PWR_SRC
2
+Vcore_CSPA3
+Vcore_CSPA2
+Vcore_CSPA1
+Vcore_PWMA
PR132 200K_0402_1%~D
+Vcore_CSNA
+Vcore_TONA
2
+Vcore_VCC
PR133
PR134
PR135
+Vcore_EN
+Vcore_SR
GNDA_VCC +VCC_PWR_SRC PJP27
PH2
PH3
1 2 +PWR_SRC
+VGFX_PWR_SRC 1 2 +VGFX_TONB @
1
PR136 200K_0402_1%~D PAD-OPEN 4x4m
10U_1206_25VAK~D
10U_1206_25VAK~D
2200P_0402_50V7K~D
1
0.1U_0603_25V7K~D
5
100U_25V_M~D
100U_25V_M~D
100U_25V_M~D
10U_1206_25VAK~D
AON6414AL_DFN~D
10_0402_1%~D @ PR506 1 1 1
1
PC148
PC154
PC155
PC156
2 1
49
48
47
46
45
44
43
42
41
40
39
38
37
PU9 + + +
PC352
PC151
PC152
PC153
PQ13
PR138 10_0402_1%~D GNDA_VCC
CSPA3
CSPA2
CSPA1
TPAD
EN
VCC
SR
TONA
CSNA
CSPAAVE
THERMB
THERMA
DRVPWMA
2
<10> VSSSENSE 1 2 +Vcore_GNDSA 4
C 2 2 2 C
1
PC149
@ PC150 1000P_0402_50V7K~D
1
1000P_0402_50V7K~D 1 36 +GFX_IMAXB
Local sense resister put HW side
2
3
2
1
GNDA_VCC TONB IMAXB
2 35 +Vcore_IMAXA PR141 PC157 PL12
2
PR139 PR140 12K_0402_1%~D GNDSA IMAXA 2.2_0603_5%~D 0.22U_0603_10V7K~D 0.36UH_FDUE1040J-H-R36M=P3 33A_20%~D

<10> VCCSENSE 1 2 2 1 +Vcore_FBA 3 34 BOST2 2 1 BT2_1 1 2
FBA BSTA2
4 1 +VCC_CORE
1
2 1 10_0402_1%~D PC158 +Vcore_VRHOT# 4 33 PHASE2

VRHOT# LXA2
1
1000P_0402_50V7K~D GNDA_VCC P2_SW 3 2P2_Vo
470P_0603_50V8J~D
UGATE2
PQ16
10_0402_1%~D @ PR507 PQ15
PC159
5 32
2
AON6704L_DFN8-5
AON6704L_DFN8-5
AGND DHA2
1
GNDA_VCC
2
@ PR143 75_0402_5%~D +VGFX_FBB 6 31 LGAT2 2.1K_0402_1%~D PR145
FBB DLA2 @ @ PR144 1_0402_5%~D
+1.05V_RUN_VTT 1 2
+VGFX_GNDSB 7 30 4 4
GNDSB PGNDA
2
PR146 8 29 +Vcore_VDD
2.2_1206_1%~D
<54> +GFX_CSPBAVE CSPBAVE VDDA
PR148
1 2
2.2U_0603_10V7K~D
<7,43> H_PROCHOT#
1
9 28 PC161 PR152
3
2
1
3
2
1
0_0402_5%~D <54> +GFX_CSPB1 CSPB1 DLA1 2200P_0402_50V7K~D
PC160
2 1
2
1 2 10 MAX17411GTM+_TQFN48_6X6~D 27 @ 22.1K_0402_1%~D
2
<54> +GFX_CSNB CSNB DHA1
PC168 43P_0402_50V8J 11 26 @ PC162
<54> +GFX_CSPB2 CSPB2 LXA1
1 2
PR149 10_0402_5%~D +GFX_POKB 12 25 +Vcore_CSPA2
POKB BSTA1 @ PC164 1000P_0402_50V7K~D
1 2
DRVPWMB
GNDA_VCC 1 2 PC166
ALERT#
PR153 0.22U_0603_16V7K~D
PGNDB
AGND
POKA
VDDB
BSTB
10_0402_1%~D 1000P_0402_50V7K~D
VDIO
2 1
DHB
DLB
CLK
LXB
<11> VSS_AXG_SENSE 1 2 +VGFX_GNDSB

1
PC163 +Vcore_CSNA
13
14
15
16
17
18
19
20
+Vcore_VDIO 21
+Vcore_ALERT# 22
23
+Vcore_POKA 24
1000P_0402_50V7K~D
1
@ PC165
2
+Vcore_VDD
+Vcore_CLK
1000P_0402_50V7K~D
GNDA_VCC <54> +GFX_DRVPWMB
2
B <54> +GFX_BSTB +VCC_PWR_SRC B
PR156 PR157 8.06K_0402_1%~D

GNDA_VCC
10U_1206_25VAK~D
10U_1206_25VAK~D
0.1U_0603_25V7K~D
2200P_0402_50V7K~D
<54> +GFX_LXB
5
<11> VCC_AXG_SENSE 1 2 2 1+VGFX_FBB
10U_1206_25VAK~D
<54> +GFX_DHB
AON6414AL_DFN~D
1
10_0402_1%~D
PC169
PC353
PC170
PC171
PC172
1 2
<54> +GFX_DLB
1
PC167
PQ17
+VCC_GFXCORE
2
PR158 10_0402_5%~D 1000P_0402_50V7K~D PC173 0.1U_0402_25V6K~D UGATE1 4
1 2
2
GNDA_VCC 2 1 PR161 PC174

PR159 130_0402_1%~D 2.2_0603_5%~D 0.22U_0603_10V7K~D
3
2
1
+3.3V_RUN 2 1 BOST1 2 1 BT1_1 1 2
+1.05V_RUN_VTT
@ PR160 130_0402_1%~D PL13
2 1 0.36UH_FDUE1040J-H-R36M=P3 33A_20%~D
+GFX_POKB PR162 54.9_0402_1%~D
PHASE1 4 1 +VCC_CORE
<10> VIDSOUT 1 2
10K_0402_1%~D
2
1
PR164 0_0402_5%~D P1_SW 3 2P1_Vo
0_0402_5%~D
470P_0603_50V8J~D
<10> VIDALERT_N PQ19
PQ20
PR165
PR166
PC175
1 2
AON6704L_DFN8-5
AON6704L_DFN8-5
1
PR167 0_0402_5%~D
2
<10> VIDSCLK 1 2 2.1K_0402_1%~D PR170
@ PR168 0_0402_5%~D @ @ PR169 1_0402_5%~D
PR171
1
LGATE1 4 4
1
<42> IMVP_PWRGD 2 1 +Vcore_POKA
2
2.2_1206_1%~D
PR173
0_0402_5%~D
1
PC176 PR176
3
2
1
3
2
1
2200P_0402_50V7K~D 2 1
2
@ 22.1K_0402_1%~D
2
@ PC177
1 2
+Vcore_CSPA1
@ PC178 1000P_0402_50V7K~D
GNDA_VCC 1 2 PC179
0.22U_0603_16V7K~D
A 1000P_0402_50V7K~D 2 1 A
PJP28
1 2 +Vcore_CSNA
@ PC180 @ PC180
GNDA_VCC 1 2
PAD-OPEN1x1m
GNDA_VCC 1000P_0402_50V7K~D
Title
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL VCORE_MAX17411
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-6562P
5 4 3 2 1
5 4 3 2 1
+VGFX_PWR_SRC VCC_GFXCORE
2200P_0402_50V7K~D
10U_1206_25VAK~D
10U_1206_25VAK~D
0.1U_0603_25V7K~D
Peak current : 33A
5
PQ56
10U_1206_25VAK~D
AON6414AL_DFN~D
AON6414AL_DFN~D
@ PQ55
@PQ55
OCP min : 39.6A
1
PC181
PC182
PC183
PC184
PC403
@
2
D G_UGATE2 @ D
4 4
@ @ @ @
+5V_ALW @ PR179 @ PC185

2.2_0603_5%~D 0.22U_0603_10V7K~D
3
2
1
3
2
1
@ PC186 G_BOST2 2 1 GBT2_1 1 2
1U_0603_10V6K~D PU10 @PL14
@ PL14
2 1 5 1 0.45UH_FDUE1040D-R45M 23.5A_20%~D
VDD BST
6 8 G_PHASE2 4 1 +VCC_GFXCORE
SKIP DH
1
470P_0603_50V8J~D
2 7 GP2_SW 3 2 GP2_Vo
11 +GFX_DRVPWMB PWM LX
PQ58
PC187
AON6704L_DFN8-5
AON6704L_DFN8-5
@ PQ57
@PQ57
1
3 4 +Vcore_VCC
2
GND DL
0_0402_5%~D
@PR181
@ PR181
1
9 @ @ @ PR180
@PR180 1_0402_5%~D
EP
PR150
G_LGATE2 4 4 2.1K_0402_1%~D
1
MAX17491GTA+T_TQFN8_3X3~D
2
2.2_1206_1%~D
@
PR182
2
1
@ PC188 @ PR186
3
2
1
3
2
1
2200P_0402_50V7K~D 2 1
2
@ 11K_0402_1%~D
2
@ PC189
1 2
8,45 +GFX_CSPB2 @ PC190 1000P_0402_50V7K~D
GNDA_VCC 1 2 @ PC191
0.22U_0603_16V7K~D
1000P_0402_50V7K~D 2 1
C C
8,45 +GFX_CSNB
@PL24
@ PL24
1 2
+VGFX_PWR_SRC
PJP29
1 2 +PWR_SRC
2200P_0402_50V7K~D
10U_1206_25VAK~D
10U_1206_25VAK~D
0.1U_0603_25V7K~D
PAD-OPEN 4x4m
5
PQ38
10U_1206_25VAK~D
AON6414AL_DFN~D
AON6414AL_DFN~D
PQ24
1
PC193
PC194
PC195
PC196
PC404
2
2
4 4
11 +GFX_DHB
PR189 PC197
2.2_0603_5%~D 0.22U_0603_10V7K~D
3
2
1
3
2
1
2 1 GBT1_1 1 2
11 +GFX_BSTB PL15
0.36UH_FDUE1040J-H-R36M=P3 33A_20%~D
4 1 +VCC_GFXCORE
11 +GFX_LXB 5
2200P_0402_50V7K~D
470P_0603_50V8J~D
B B
0.1U_0402_10V7K~D
470U_D2_2VM_R4.5M~D
470U_D2_2VM_R4.5M~D
GP1_SW 3 2 GP1_Vo
PQ26
PC198
+GFX_CSPBAVE
AON6704L_DFN8-5
AON6704L_DFN8-5
PQ25 1 1
1
2
1
1_0402_5%~D
PC201
PC202
+ +
0_0402_5%~D
PR191
PC200
PC199
@ @ PR190
2.1K_0402_1%~D
PR147
4 4
2
1
11 +GFX_DLB 2 2
2
2.2_1206_1%~D
PR193
1
1
@PC402
@ PC402 PC203 @ PR196
3
2
1
3
2
4700P_0402_25V7K~D 1 2 1
2
0.033U_0402_16V7K~D @ 11K_0402_1%~D
2
1 2
@ PC204
1 2
PC208 PR119 +GFX_CSPB1
0.33U_0603_10V7K~D 1_0603_1%~D 8,45 +GFX_CSPB1 @ PC205 1000P_0402_50V7K~D
1 2 1 2 GNDA_VCC 1 2 @ PC206
0.22U_0603_16V7K~D
1000P_0402_50V7K~D 2 1
PR201
2 1 +GFX_CSNB
40.2K_0402_1%~D 8,45 +GFX_CSNB @ PC207
GNDA_VCC 1 2
PH4 PR203
1 2 2 1 2 1 GP1_SW 1000P_0402_50V7K~D
10K_0402_1%_ERTJ0EG103FA~D 2.1K_0402_1%~D PR202 1.43K_0402_1%~D
2 1 GP2_SW
A 8,45 +GFX_CSNB @ PR300 4.32K_0402_1%~D A
8,45 +GFX_CSPBAVE
Title
+VCORE/+GFXCORE
0.3
LA-6562P
5 4 3 2 1
5 4 3 2 1
populate:
@ PD14 BQ24747:PR511,PR512,PR513,PR514,PR509,PC406,PQ59
ES2AA-13-F_SMA2 @ PL16 ISL88731:PC405,PR515,PR516,PR517,PR518,PR519,PR520,PC407,PC244,PC245,PQ43
2 1 FBMJ4516HS720NT_1806~D
2 1 depop:
BQ24747:PC405,PR515,PR516,PR517,PR518,PR519,PR520,PC407,PC244,PC245,PQ43
PQ27 PR205 ISL88731:PR511,PR512,PR513,PR514,PR509,PC406,PQ59
SI4835DDY-T1-GE3_SO8~D +SDC_IN 0.01_1206_1%~D +PWR_SRC CHAGER_SRC
8 1 PJP33
7 2 4 1 1 2
+DC_IN_SS
6 3
0.1U_0603_25V7K~D
5 3 2 PAD-OPEN 4x4m
0.1U_0603_25V7K~D
@
47P_0402_50V8J~D
1
1
D D
PC210
PC211
4
PC209
PR206
2
1
1 2 PR207 D @
DC_BLOCK_GC 57
1 2 2 PQ28
57 CSS_GC
0_0402_5%~D G NTR4502PT1G_SOT23-3~D
1
0_0402_5%~D D S
3
2 PQ30A
G NTGD4161PT1G_TSOP6~D
PQ29 S
S
NTR4502PT1G_SOT23-3~D
D
5 6 DOCK_DCIN_IS+ 43
E2 AC_OK=17.7 Volt
CSSN_1
CSSP_1
G
1
PR217 PQ30B
@ PR208 NTGD4161PT1G_TSOP6~D PR521
TI bq24745 = 316K 10K_0402_5%~D +3.3V_ALW 0_0402_5%~D
0_0402_5%~D
S
Intersil ISL88731 = 226K
D
2 1 2 4 1 2
0_0402_5%~D
DOCK_DCIN_IS- 43 DYN_TURB_PWR_ALRT#
100K_0402_1%~D
Maxim = 383K
1
PR209
PR210
100K_0402_1%~D
1
1
@ PR522
PR211
G
3
1
+SDC_IN PR510 0_0402_5%~D
MAX8731A_LDO MAX8731_REF PC212 PC213 100K_0402_5%~D
PR212
1 2 H_PROCHOT#
PR213 0.1U_0603_25V7K~D 0.1U_0603_25V7K~D @ PC292 PR216
10K_0402_1%~D
10K_0402_5%~D
2
57 +CHGR_DC_IN 1 2 1 2 1 2 1 2 0_0402_5%~D
2
1
1
1 2
316K_0402_1%~D
DK_CSS_GC 57
2
1_0805_5%~D ICREF 0.1U_0603_25V7K~D
PR214
PR215
2
PR509 @ PC214
PR217
GNDA_CHG 0_0402_5%~D 1U_0603_10V6K~D
28
27
1
@ PC215 GNDA_CHG PU11 ICOUT 1 2 DYN_TUR_PWR_VO 1 2 GNDA_CHG
1U_0603_10V6K~D
2
0.1U_0805_50V7M~D
CSSN
ICREF
CSSP
PR219 DCIN 22
PC405
2 1 26
1
DCIN ICOUT
1
49.9K_0402_1%~D PR218
2 1 2 2.2_0603_1%~D PR220 @
BAT54HT1G_SOD323-2~D
PR221 ACIN BOOT BOOT_D 33_0603_1%~D @
25 1 2
2
BOOT
1 2 13
15.8K_0402_1%~D
PC216 23,45,57 ACAV_IN ACOK
1
0_0402_5%~D
PC217
10U_1206_25V6M~D
10U_1206_25V6M~D
1
0.1U_0603_25V7K~D
2200P_0402_50V7K~D
0.1U_0603_25V7K~D
1
1
C 2 1 11 C
VDDSMB
5
6
7
8
5
6
7
8
GNDA_CHG
PD15
PR222
1
0.01U_0402_25V7K~D PC222
PC218
PC219
PC220
PC221
10
D
D
D
D
D
D
D
D
2
SCL
SI4800BDY-T1-E3_SO8~D
1U_0603_10V6K~D
2
GNDA_CHG +5V_ALW @ 21 MAX8731A_LDO
PQ31
PQ32
9 1 2
2
2
SDA VDDP
GNDA_CHG 14 4 4
NC CHG_UGATE G G
24
MAX8731_IINP UGATE
8
VICM
1
S
S
S
S
S
S
23 2 PR223 1 +VCHGR_B
PC223 PHASE
6
3
2
1
3
2
1
3300P_0402_50V7K~D
FBO
1
0.1U_0402_10V7K~D 1_0603_1%~D
2
1 2 5 @ PC224
EAI 220P_0402_50V7K~D
1
GNDA_CHG PR224 21 1 2 4 20 CHG_LGATE PL17
4.7K_0402_5%~D
200K_0402_5%~D PC225 PR225 EAO LGATE 5.6UH_HMU1356B-5R6-F_8A_20%~D PR227 +VCHGR
PC226
45 CHARGER_SMBCLK
56P_0402_50V8~D
1
2200P_0402_50V7K~D 7.5K_0402_5%~D 0.01_1206_1%~D
2
PR226
45 CHARGER_SMBDAT
2
MAX8731_REF @ 1+VCHGR_L
PC227
3 19 2 4 1
VREF PGND
18
PC228 PR228 CSOP
3 2
1.8K_1206_5%~D
2
23 MAX8731_IINP
1
120P_0402_50VNPO~D 1 2 7 17
10U_1206_25V6M~D
10U_1206_25V6M~D
10U_1206_25V6M~D
3
0.1U_0603_25V7K~D
CE CSON
5
6
7
8
10K_0402_5%~D
PR229
1 2
0_0402_5%~D
0_0402_5%~D
8.45K_0402_1%~D
220P_0402_50V8J~D
1
1
15 VFB 1 PR230 2 +VCHGR PC234
2
0.1U_0402_10V7K~D
VFB
1
1
1000P_0603_50V7K~D
PR232
PC229
12
1U_0603_10V6K~D
GND
0.01U_0402_25V7K~D
0.01U_0402_25V7K~D
0.01U_0402_25V7K~D
100_0402_5%~D @
PR231
PR233
PC236
PC237
PC238
PC239
16
2
NC
1
PQ33
PC230
PC231
PC232
PC233
PC235
29
2
2
TP
2
@ 4 PR234
2
2
4.7_1206_5%~D
2
@ @ @ @ BQ24747RHDR_QFN28_5X5~D
PJP34
1
PC240 D
1 2
3
2
1
1
0.1U_0603_25V7K~D PC241 @ PC293 2
1 2 1 2 1 2 G
PAD-OPEN1x1m S
3
GNDA_CHG 0.1U_0603_25V7K~D 0.1U_0603_25V7K~D
GNDA_CHG
Maximum charging current is 7.2A GNDA_CHG ACAV_IN @
B B
GNDA_CHG PQ34
RHU002N06_SOT323-3~D
+5V_ALW
100P_0402_50V8J~D
0.01U_0402_25V7K~D
DYN_TUR_CURRENT_SET# MAX8731_REF
1
DYN_TUR_PWR_VO +3.3V_ALW
PC244
PC245
100K_0402_5%~D
2
+DC_IN MAX8731_REF
PR519
65W High PR236
10K_0402_1%~D
2
MAX8731_REF +5V_ALW @ @ 1M_0402_1%~D
47K_0402_1%~D
100K_0402_5%~D
232K_0402_1%~D
2
1
@ PR518 @ 1 2
100K_0402_1%~D
1
10K_0402_5%~D
PR520
PR235
PR237
PR239
90W Low
1
1 2 +5V_ALW
1
PR238
PR513 @
1
2
100K_0402_1%~D @ PR516 @ PR517
2
8
8
10K_0402_5%~D 10K_0402_5%~D PU12B PU12A @
1
PR511 MAX8731_IINP D @ PR240

1 2 1 2 5 3
P
P
2
1.87M_0402_1%~D + PQ43 +
7 2 1 1 2
ICOUT ICREF O G RHU002N06_SOT323-3~D O 0_0402_5%~D ACAV_IN_NB 44,45,57
1 2 1 2 6 2
22.6K_0402_1%~D
41.2K_0402_1%~D
100P_0402_50V8J~D
- -
G
G
S
42.2K_0402_1%~D
3
220P_0402_50V8J~D
100P_0402_50V8J~D
1
1
@ PR515 LM393DR_SO8~D LM393DR_SO8~D
4
4
1
1
10K_0402_5%~D
PC407
PC242
PR241
PC243
PR243
73.2K_0402_1%~D
46.4K_0402_1%~D
PR242
100P_0402_50V8J~D
1
2
1
@ @
PR512
PR514
PC406
2
2
2
2
2
1
D
DYN_TUR_CURRNT_SET#
2
G
S
3
A PQ59 A
RHU002N06_SOT323-3~D
GNDA_CHG
Adapter Protection Circuit fot Turbo Mode DELL CONFIDENTIAL/PROPRIETARY

Title
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Charger
5 4 3 2 1
5 4 3 2 1
@ PL25
1 2
VCC_SA
PJP35
VCCSA_PWR_SRC 1 2 +PWR_SRC
PAD-OPEN 43X118 Peak current : 6A
10U_1206_25V6M~D
10U_1206_25V6M~D
2200P_0402_50V7K~D
0.1U_0603_25V7K~D
+5V_RUN
1 1 2
OCP min : 7.2A
1
D D
PC246
PC247
PC249
PC250
1U_0603_10V6K~D
PC248
1 2
2
2 2 1
1
PR244
2.2_0805_5%~D
VCCSA_LGATE
5
6
7
8
VCCSA_VCC
1U_0603_10V6K~D
0.1U_0402_10V7K~D
1
1
PC251
PC252
PQ35
4 AO4466L_SO8~D
2
2
20
1
PU13
LGATE
PVCC
3
2
1
GNDA_VCCSA GNDA_VCCSA
PL18
2 19 1UH_FDVE0630-H-1R0M=P3_11.9A_20%~D
PGND VCC PR245 2 1 +SA_VCC
2.2_0603_1%~D PC253
2200P_0402_50V7K~D
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
330U_D2_2VY_R7M~D
3 18 VCCSA_BOOT
1 2 1 2
0.1U_0402_10V7K~D
GNDA_VCCSA GND BOOT
1
5
6
7
8
1
0.22U_0603_10V7K~D @ PC254
1
+
PC255
PC256
PC257
PC260
VCCSA_UGATE 1000P_0603_50V7K~D
10_0402_5%~D
4 17
RTN UGATE
PR246
PC258
AO4406AL 1N SO8
1 2
2
2
2
2
PQ36
VCCSA_VID1 5 16 VCCSA_PHASE PR247
VID1 PHASE @PR248
@ PR248
4 12.7K_0402_1%~D
2
C 2.2_1206_1%~D C
VCCSA_VID0 6 15 VCCSA_EN VCCSA_LGATE
PC261
1
+1.05V_RUN VID0 EN
2
2 1
3
2
1
VCCSA_SREF 7 14 VCCSA_PWRGD
SREF PGOOD PR251 .015U_0603_25V7K~D
.068U_0603_16V7~D
0_0402_5%~D
PR253
2
PR250 VCCSA_SET0 8 13 1 2 1.05V_VTTPWRGD 45,54
1
SET0 FSEL
PC262
@ PR249 113K_0402_1%~D 2 1
0_0402_5%~D VCCSA_SENSE 12
PR252 @ PR254
1
VCCSA_SET1 9 12 0_0402_5%~D 1 2 CPU_VTT_ON 44,54

2
SET1 VO 0_0402_5%~D
OCSET
1
0_0402_5%~D PR255
1
10_0402_5%~D
2 1
FB
12 VCCSA_VID_1 +3.3V_RUN
1
GNDA_VCCSA
PR257
PR256 10K_0402_5%~D
10
11
2
140K_0402_1%~D GNDA_VCCSA
PR410 1 2 0.8V_VCCPWROK 45
2
1K_0402_5%~D ISL95870AHRUZ_UTQFN20_1P8X3P2
VCCSA_FB
2
PR258
@ PR260 0_0402_5%~D
PR259
1
4.12K_0402_1%~D VCCSA_OCSET
1 2 1 2
PR262
47.5K_0402_1%~D
0_0402_5%~D
1
VCCSA_VO 2 1
+1.05V_RUN
PR261
GNDA_VCCSA
12.7K_0402_1%~D
2
2
@ PR263
B 10K_0402_5%~D B
1
PR265
0_0402_5%~D
2 1 +GND_VCC_SA 12
2
PR266
1
1K_0402_5%~D
@ PR267
4.12K_0402_1%~D
1
GNDA_VCCSA
PJP37
2 1
0.9V 0.8V
PAD-OPEN1x1m
VCCSA_VID_1 0 1
PJP38
+SA_VCC 1 2 +VCC_SA
A GNDA_VCCSA A
PAD-OPEN 43X118
output voltage adjustable network

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL ISL95870A +VCC_SA
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-6562P
5 4 3 2 1
5 4 3 2 1
PQ39 PD17
SI4835DDY-T1-GE3_SO8~D 2
1 8 MPBATT+ PR283 1
2 7 1 8 330K_0402_5%~D 3
+VCHGR S D
3 6 2 7
S D PDS5100H-13_POWERDI5-3~D PD16
5 3 6 1 2
0.1U_0603_25V7K~D
S D PQ41 ES2AA-13-F_SMA2
4 5
100K_0402_5%~D
G D
1
8 1 2 1
390K_0402_5%~D
620K_0402_5%~D
4
D S
1
FDS6679AZ_SO8~D
PR270
PC264
PR271
PR272
7 2
0.47U_0805_25V7K~D
PQ40 MPBATT_IN_SS D S
6 3 PQ37
D S
5 4
2
D G
8 1
2
PR274 FDS6679AZ_SO8~D D S
7 2
33_0603_5%~D D S
+DOCK_PWR_BAR 6 3
D S
1
PD18
PC263
1 2 5 4
D G
2N7002DW-T/R7_SOT363-6~D
RB751V-40_SOD323~D
1
2 1
10K_0402_5%~D
1U_0603_25V6-K~D
2
3
FDS6679AZ_SO8~D
PR273
2
D D
PD19
1
2N7002DW-T/R7_SOT363-6~D
PQ42B
RB751V-40_SOD323~D PR268
PC265
390K_0402_5%~D
PR276
5 2 1 330K_0402_5%~D
2
2
2
1
PR269
499K_0402_1%~D
4
1
6
PR275
0_0402_5%~D
2
PQ42A
CHARGE_MODULE_BATT
1
1 2 2
2
PR277 0_0402_5%~D PR278
STSTART_DCBLOCK_GC
330K_0402_5%~D
1
PQ45 1 2 PD20
FDS6679AZ_SO8~D 2
PQ44 PBATT+ 1 8 1
SI4835DDY-T1-GE3_SO8~D S D
2 7 3
S D PBATT_IN_SS
1 8 3 6
S D PDS5100H-13_POWERDI5-3~D
2 7 4 5
390K_0402_5%~D
+VCHGR G D
1
3 6 PQ46
620K_0402_5%~D
1
PR282
5 8 1
0.1U_0603_25V7K~D
D S
PR281
7 2
100K_0402_5%~D
D S
2
6 3 +PWR_SRC
4
D S
1
PR279
PC266
5 4
2200P_0402_50V7K~D
0.1U_0603_25V7K~D
PR284 D G
2
2
33_0603_5%~D FDS6679AZ_SO8~D
2
1
PR297
PC267
PC268
1 2
1
20K_0402_1%~D
3
2N7002DW-T/R7_SOT363-6~D
PD21
2
RB751V-40_SOD323~D
1U_0603_25V6-K~D
1 2 1
5
1
1
PQ49B
PC270
10K_0402_5%~D
390K_0402_5%~D
1
PD23
PR286
4
2
2N7002DW-T/R7_SOT363-6~D
RB751V-40_SOD323~D
PR291
2
6
2N7002DW-T/R7_SOT363-6~D
PR280 2 1
20K_0402_1%~D
2
PQ47A
1
2N7002DW-T/R7_SOT363-6~D
C 2 C
499K_0402_1%~D
1
6
2N7002DW-T/R7_SOT363-6~D
PR292
PQ49A
6
PQ47B
2N7002DW-T/R7_SOT363-6~D
CHARGE_PBATT
1 2 2 5
2
3
PQ48A
2N7002DW-T/R7_SOT363-6~D
PR293 0_0402_5%~D
6
2
1
PQ48B
PR287
PQ50A
1 5 2 PR323
0_0402_5%~D
MODULE_ON
1
2
RB751V-40_SOD323~D
PD30 2 1 2 DEFAULT_OVRDE
RB751V-40_SOD323~D
RB751V-40_SOD323~D
0_0402_5%~D
PR285
499K_0402_1%~D
4
1
RB751V-40_SOD323~D
2 1 0_0402_5%~D
1
2
PR289
PD22
1
RB751V-40_SOD323~D
RB751V-40_SOD323~D
PD24
PD25
PD26
2
MPBATT+ @
PD31
2
PR355
1
1 2 2 1 PBATT+ PD27
510K_0402_5%~D
CHARGE_EN
1
2N7002DW-T/R7_SOT363-6~D
0_0402_5%~D
200K_0402_1%~D
1
PR471
1
RB751V-40_SOD323~D
2N7002DW-T/R7_SOT363-6~D
PR290
0_0402_5%~D
3
SLICE_BAT_ON
3
PR296
2
PQ54B
2
PQ50B
5 @ PR473 100K_0402_5%~D
2N7002DW-T/R7_SOT363-6~D
5 1 2
2
6
2 4
4
PQ54A
PR295
0_0402_5%~D
SLICE_BAT_PRES#
PR298
1 2 2 1 2 MODULE_BATT_PRES#
DEFAULT_OVRDE PR294 0_0402_5%~D
0_0402_5%~D
1
1
499K_0402_1%~D
PBATT+
1
PR288
PBAT_PRES# +DOCK_PWR_BAR 1 2
@ PR299 0_0402_5%~D PR301
2
2
1 2 0_0402_5%~D
B +DC_IN_SS PR302 0_0402_5%~D @ PR306
B
0_0402_5%~D
1
1 2
+CHGR_DC_IN PR305 0_0402_5%~D
1
<55>
CHGVR_DCIN
DK_PWRBAR
+DC_IN 1 2 CD3301_DCIN
DC_IN_SS
PR307 47_0805_5%~D
1
PC271
0.1U_0603_50V4Z~D
2
+5V_ALW
P50ALW
36
35
34
33
32
31
30
29
28
1 2
PU14 PR309 0_0402_5%~D
<47> SOFT_START_GC
1 2
NC
CHARGERVR_DCIN
DK_PWRBAR
GND
NC
BLK_MOSFET_GC
DSCHRG_MOSFET_GC
PBatt+
DC_IN_SS
+3.3V_ALW2
CD_PBATT_OFF 1 2 SLICE_BAT_ON <42>
PR310 100K_0402_5%~D PR311 0_0402_5%~D
<41> ACAV_DOCK_SRC# 1 2ACAVDK_SRC
1 2 DOCK_AC_OFF <41,42>
PR312 0_0402_5%~D 1 27 PR313 0_0402_5%~D
DC_IN P50ALW
2 26
ERC1 SS_GC PBATT_OFF DK_AC_OFF
+SDC_IN 1 2 3 25 1 2
PR314 0_0402_5%~D ERC1 DK_AC_OFF_EN
4 24 1 2 3301_ACAV_IN_NB ACAV_IN_NB <42,43,55>
ACAVDK_SRC ACAV_IN_NB PR316
0_0402_5%~D 1M_0402_5%~D
5 23
CD3301_SDC_IN GND GND DK_AC_OFF_EN PR315
6 22 1 2 DOCK_AC_OFF_EC <42>
SDC_IN DK_AC_OFF_EN SL_BAT_PRES# PR317 0_0402_5%~D
7 21
<55> DC_BLOCK_GC ACAVIN DC_BLK_GC SL_BAT_PRES# BLKNG_MOSFET_GC
8 20
P33ALW2 9 ACAV_IN BLKNG_MOSFET_GC
19
P33ALW2 NBDK_DCINSS
EN_DK_PWRBAR
<23,43,55> ACAV_IN 1 2
SS_DCBLK_GC
PR318 0_0402_5%~D
DK_CSS_GC
1 2 SLICE_BAT_PRES# <41,42,47>
RB751V-40_SOD323~D
PWR_SRC
PR320 0_0402_5%~D
CSS_GC
RB751V-40_SOD323~D
P33ALW
37
TP
1
ERC3
ERC2
1 2 1 2
GND
+3.3V_ALW2 +NBDOCK_DC_IN_SS
PR319 0_0402_5%~D PR322 0_0402_5%~D
PD29
PD28
CD3301RHHR_QFN36_6X6~D
10
11
12
13
14
15
16
17
18
A PQ51 A
2
0.1U_0603_25V7K~D
FDN338P_NL_SOT23-3~D <55> CSS_GC P33ALW 1 2

ERC2
<55> DK_CSS_GC +3.3V_ALW

PR324 0_0402_5%~D
1
ERC3
PC273
1 3
1
DOCK_SMB_ALERT#
<41,42,47>
PC273 1 2 EN_DOCK_PWR_BAR <42>
2
0.047U_0603_25V7K~D
PR325 0_0402_5%~D
2
2
0.1U_0402_25V4Z~D
PR321 1 2
PC274
SLICE_BAT_PRES# 1 2
1
1M_0402_5%~D
0_0402_5%~D STSTART_DCBLOCK_GC
PC275
<41,42,47>
@ PR326
1
Title
2
PC272 @ 3301_PWRSRC PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
1500P_0402_7K~D
1
PR327
2
0_0402_5%~D
+PWR_SRC TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Selector
2
5 4 3 2 1
5 4 3 2 1
V ersion Change L ist ( P. I. R . L ist )

R equest
Item Page# Title D ate Issue D escription Solution D escription R ev.
O w ner
D D
1 7 HW 6/15/2010 COMPAL Boot issue Change QC1 control from SUS_ON to RUN_ON_CPU1.5VS3# X01
2 11 HW 6/15/2010 COMPAL Modify net name Change +0.8V_VCC_SA to +VCC_SA X01
Change capacitors from 10uF_0805_10V Y5V to 10uF_0805_6.3V_X5R:

C305,C316,C387,C462,C705,C728,C760,C764,C765,C768,C769,
C772,CC135,CH58,CH73,CH80
Follow PPM recommendation to change
3 6/15/2010 COMPAL Change capacitors from 10uF_0805_6.3V to 10uF_0603_6.3V:
HW material X01
C475,C638,C641,C643
Change resistors to 0402 size: RC134, RH201,RH253,RH208,RH213
Delete RH192 and add PJP51
4 14 HW 6/15/2010 COMPAL De-pop PCH XDP De-pop RH1,RH3~RH10,RH12~RH21,RH24,RH283~RH285,CH1 X01
5 14 HW 6/15/2010 COMPAL Add HDA_SYNC pull up Add RH41 X01

C C
Change ODD connector to 31 pin, add @R1189,RH340 and remove C1168,
6 17,29,42 HW 6/15/2010 COMPAL Change ODD connector from 13 pin to 31 pin X01
C1169,C1170,U87,U88,U89, and connect ODD_DET# to U51.B36
7 18 HW 6/17/2010 COMPAL Remove touch screen PAID pull down circuit Remove RH241 X01
8 18 HW 6/17/2010 COMPAL Follow Intel Design Guide Rev1.0 Change RH149 to 1k and RH150 to 4.7k X01
9 22 HW 6/17/2010 COMPAL Change EMC4002 to EMC4022 Change U9 to EMC4022, remove R866,R404,C279 and add Q16, C277,Reserve C277 X01
10 26 HW 6/17/2010 COMPAL For Safety request Add no stuff D4 and co-lay with F2, change F2 to 2A_8V X01
11 28, 39 HW 6/17/2010 COMPAL Change E-SATA repeater to MAX4951BE Chagne U44 to MAX4591BE and Reserve R1189~R1196 for bypass repeater X01
X01
12 30 HW 6/17/2010 COMPAL Change Codec to ZB version Change U72 to ZB version as 92HD90B2X5NLGXZBX8 and stuff C962
B B
13 46 HW 6/17/2010 COMPAL ME request Change the JBTB1 to TYCO_2041300-2 connector X01
14 33 HW 6/17/2010 COMPAL Change SI2301BDS to C version Change Q36 to SI2301CDS X01
15 33 HW 6/17/2010 BRCOM Change RFID capacitors for more popular Change C502,C505 from 1uF to 0.1uF X01
Link R667 to CIS to have the correct part number and swap SD/MMCCD#
16 33 HW 6/17/2010 COMPAL Link R667 to CIS and modify JSD1 connection X01
from JSD1 pin16 to pin17, SDWP from JSD1 pin17 to pin 18
41 HW 6/17/2010 COMPAL Board ID Change R875 to 130K

17 X01
18 41 HW 6/17/2010 COMPAL Add pull down on SLICE_BAT_ON Add R791 X01
19 11,14,42 HW 6/18/2010 COMPAL EOL concern Change CC176 to SGA00005H0L, change YH1,Y6 to SJ132P7KW1L X01
A Change JKB1 to same as JSC1 A
20 43,46 HW 6/18/2010 COMPAL Change connector X01
Change JLED1 to TYCO_1-2041084-6
X01
21 41 HW 6/17/2010 COMPAL Change BAY_SMBDAT and BAY_SMBCLK pull-up Change R854, R856 pull up power rail to +3.3V_ALWDELL CONFIDENTIAL/PROPRIETARY
resistors to +3.3V_ALW
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT EE P.I.R (1/5)
5 4 3 2 1
5 4 3 2 1

R equest
O w ner
D D
21 43 HW 6/18/2010 COMPAL Change TP pin definition Reverse TP pin definition for PT X01
22 14 HW 6/18/2010 COMPAL Add RTC PAID function Add RTC_DET# and RH355 on PCH GPIO33 X01
Add series resistor and pull up resistors

23 41,42 HW 6/18/2010 COMPAL Add R773,R806,R884,R886,R887,R1169,R1170,R1197 X01
on MIC_MUTE#, VOL_MUTE,VOL_UP,VOL_DOWN
Modify signal name BREATH_BLUE_LED to BREATH_WHITE_LED and

24 24,44 HW 6/18/2010 COMPAL Correct net name for LED signal X01
BREATH_BLUE_LED_SNIFF to BREATH_WHITE_LED_SNIFF
25 41 HW 6/18/2010 COMPAL Correct net name Modify R1132.2 from SUSACK#_R to SUSACK#_EC X01
26 32 HW 6/21/2010 INTEL Remove useless resistors Remove R556, R558, R559, R560 and short the pin1 and pin2 together X01
27 14 HW 6/22/2010 COMPAL Modify BOM Structure Correct RH45 BOM structure X01
C C
24,28,29,
28 HW 6/22/2010 COMPAL Change part for Halogen free Change Q18,Q27,Q30,Q34,Q38,Q40,Q42,Q49,Q54,Q58 to HF part X01
32,37,44
31 44 HW 6/23/2010 COMPAL Solution +1.5V_RUN voltage drop issue Change Q59 from SI3456BDV to NTGS4141NT1G X01
32 27 HW 6/23/2010 COMPAL Add PU 2.2K on PCH_DDPC_CTRLDATA, Add R487~R490 2.2 Kohm pull up to +3.3V_RUN X01
PCH_DDPC_CTRLCLK,PCH_DDPD_CTRLDATA,
PCH_DDPD_CTRLCLK,
34 44 HW 6/25/2010 COMPAL NTMS4107NR2G EOL Change Q55 to NTMS4920NR2G X01
35 14 HW 6/25/2010 COMPAL Follow Intel XDP design Change RH43,RH44,RH45 to 200 ohm X01
36 24 HW 6/25/2010 COMPAL Change LVDS connector to 40 pin Change JLVDS1 to 40 pin X01
37 14 HW 6/23/2010 COMPAL Add serial damping on SPI_CS0#,SPI_CS1# to Add serial damping resistor R935 47 ohm on SPI_CS0#, R936 22ohm on X01
B avoid SPI EA fail issue SPI_CS1# B
38 X01
24 HW 6/25/2010 COMPAL PT panel change touch screen pin definition Change JTS1 pin definition for new TS pin define
39 14,29, HW 7/1/2010 COMPAL Modify Module Bay circuit 1.Remove R1181,R1182,R1189. 2.Change BAY_SMBUS, DEVICE_DET# pull up X01
36,42 power rail from +3.3V_RUN to +3.3V_ALW. 3.Change net name ODD_DET# to
PCH_SATA_MOD_EN#. 4.Add Q123,Q76,R513,R514,R515 for USB_SMI# circuit.
5.De-pop C627,R712
40 7 HW 7/1/2010 COMPAL For support XDP device De-pop RC9 X01
15,18, HW 7/1/2010 COMPAL Base on GPIO map to modify 1. Move SLP_ME_CSW_DEV# from GPIO45 to GPIO28, add MCARD_PCIE_SATA# on
41
41,42 5028 GPIOE3. 2. Remove RH238. 3. Change SLICE_BAT_PRES# pull up power X01
rail from +3.3V_ALW2 to +3.3V_ALW. 4. Add R889
42 24 HW 7/1/2010 COMPAL PWM function Remove R1139,R1140 and add D68,D69 X01
43 11 HW 7/1/2010
VCCSA_VID_1
A
and pop COMPAL
RC138 VCCSA VID circuit X01 A
Title
5 4 3 2 1
5 4 3 2 1

R equest
O w ner
D D
21 22 HW 7/2/2010 COMPAL Modify thermal diode for thermal request Remove C268,C269,use DP1/DN1 for CPU,DP3/DN3 for DIMM,DN5/DP5 for WWAM X01
14,15,32 1. CH18, CH19 change to 12P_0402_50V8J~D
22 HW 7/8/2010 COMPAL Meet Crystal EA chnage caps value. X01
36 2. C470, C471 change to 27P_0402_50V8J~D
3. CH2, CH3 change to 15P_0402_50V8J~
4. C591, C592 6.8P_0402_50V8D~D
O2 suggest
23 36 HW 7/12/2010 COMPAL 1. Add R1198~R1205 33 ohm X01
1. add the damping resistors 33ohm on the
2. RE7 change to 33 ohm
(SD/MMCDAT0-7 and SD/MMCCMD)
2. change the resistor RE7 on the SD/MMC_CLK
to 33ohm.
EMC request
1. Add LE3 BLM18BB221SN at BIA_PWM_LVDS
24 24,45,29 HW 7/12/2010 COMPAL 1.Add 220 ohm bead at BIA_PWM_LVDS for X01
2. L51,L50 change to POP, R734~R737 change to De POP.
PCI noise
3. Reserve CH7 150P
2. Add 90 ohm common mode choke L50,L51
4. add LE2 220 ohm bead instead of R1106.
at USBP0+/- and USBP1+/- for USB R/W noise
C
3. Reserve 150pF bypass capacitor at ODD C
DEVICE_DET
4..Add 220ohm Bead at DMIC_CLK for DMIC noise
25 24,45 HW 7/13/2010 COMPAL PPM recommendation to change material 1.C300, C669 from 10U 16V Y5V 1206 change to 10U 10V Z Y5V 0805 X01
SMSC request X01

26 41 HW 7/13/2010 COMPAL R864 and R865 can be depopulated
1.I2S_CLK, I2S_WS pull down resistors
depopulated
27 33 HW 7/15/2010 COMPAL Hi-Pot EA Fail JLOM1.14 change to NC net; JLOM1.15 change to GND net,Remove C1165,C1166 X01
28 37,44 HW 7/15/2010 COMPAL Modify LED circuit Remove R1578,R1579,R1580,D42,D60,D61, add Q77,Q124,R705,R718,R719 X01
29 26 HW 7/15/2010 COMPAL Meet HDMI EA, EMI 1.L19,L20,L21,L22 change to Populated

X01
2.R470,R471,R468,R469,R462,R466,R451,R459 change to Depopulated
B B
30 37 HW 7/15/2010 COMPAL MINI card CONN from H9.9 change to H9 JMINI1,JMINI2,JMINI3 change to LOTES_AAA-PCI-047-P10-A X01
31 44 HW 7/15/2010 DELL 1.Remove MIC MUTE LED circuit, 1.Remove the R1108,Q119,R1061,Q105 parts as MIC mute circuit X01
2.Reserve SPK MUTE LED circuit 2.Reserve the R1109,Q119,Q102,R1059 parts as SPK mute circuit,
Change Q119 to SSM3K7002FU
32 14,17,18 HW 7/16/2010 COMPAL Follow GPIO MAP 1.Remove R1567~R1577.

X01
40,41 2.U46.B64,A9,A18,A44,B39,B51 connect to GND direct.
3.R796 Net rename to DYN_TURB_PWR_ALRT# then change to 10K value and
pull up to +3.3V_ALW power rail.
4.Add GPIO DYN_TUR_CURRNT_SET# TO U51.A35 and add R1171 10k pull up.
5.SIO_EXT_SMI# GPIO form PCH.GPIO1 change to PCH.GPIO14 and add RH51
10kohm Pull up
6.RH164 change to PCH_GPIO1 net. and remove RH254
33 33 HW 7/19/2010 COMPAL ME change reuqest JLOM1 change to TYCO_2010019-3 X01

A A
34 28,44 HW COMPAL Diode7/19/2010

B751S40T1_SOD523-2~D parts sync X01
Title
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D D
57 36 HW 7/19/2010 COMPAL OZ600RJ1 from A change to B version U39 change to OZ600RJ1LN-B_QFN48 X01
1.Add PJP68 bypass JUMP for +5V_ALW to +5V_ALW_PCH
58 20,43 HW 7/19/2010 COMPAL Cost reduction as +3.3V_ALW_PCH and X01
2.QH4,CH98,RH278 change to NON-POP
+5V_ALW_PCH power control circuit
3.Add PJP67 bypass JUMP for +3.3V_ALW to +3.3V_ALW_PCH
4.Q51,R907,R905,C762,C760,R908,Q49 change to NON-POP
59 24 HW 7/20/2010 COMPAL Meet LCD power sequence spec R413 change to 390 ohm X01
60 24 HW 7/20/2010 COMPAL Corrent Touch screen pin define Modify JTS1 pin define X01
61 29 HW 7/20/2010 COMPAL Q107 change to one channel Q107 change to SSM3K7002FU_SC70-3~D X01
62 17,30,39 HW 7/20/2010 COMPAL EMC suggestion item 1.I2S_12MHZ add @RE9 X01
2.I2S_BCLK add @RE10
3.CLK_PCI_DOCK, RH103 change to 33ohm, R756 change to 33 ohm,
C C704 change to 12pf C
4.DAI_BCLK# add@RE12,@CE9
5.DAI_12MHZ# add @RE11,@CE8
63 26 HW 7/21/2010 COMPAL Safety team request Modify HDMI power circuit about D4,F2,R5 X01
parts
64 37 HW 7/21/2010 COMPAL DF398754 Debug reserve Reserve R725 0 ohm both PCIE_MCARD2_DET#R to PCIE_MCARD2_DET# X01
65 36 HW 7/21/2010 COMPAL Meet 1394 EA SPEC R683,R684,R685,R686 from 56.2 change to 53.6 ohm X01
66 30 HW 7/22/2010 COMPAL EMI snubber and change Audio net name 1.Change net name from I2S_12MHZ to I2S_MCLK X01
2.Reserve R1587~R1590 part at INT_SPK bus
67 41 HW 7/22/2010 COMPAL New GPIO MAP 1.Pull up R943 to +3.3V_ALW on XFR_ID_BIT# of ECE5055-GPIO105 X01
2.R712,R711,C627 change to de-pop
B B
68 40 HW 7/23/2010 COMPAL TEMP_ALERT# Add 0 ohm jump between EC to PCH Add R738 ohm at TEMP_ALERT# X01
Follow GPIO map to add touch screen power Add TOUCH_SCREEN_PD#, Q125,Q32,R430,R431,C304,C306, and change JTCH1
69 24,42 HW 7/24/2010 COMPAL X01
down control circuit pin 1,pin2 from +5V_RUN to +5V_TSP
70 24 HW 7/26/2010 COMPAL Reserve a 0 ohm option between +5V_RUN and Reserve R1001 0 ohm 0603 between +5V_RUN and +5V_TSP X01
+5V_TSP
71 44 HW 7/26/2010 COMPAL Due to BT_ACTIVE was folating pin, Add R944 100K ohm for BT_ACTIVE pull down X01
so, add 100 Kohm pull down
72 16 HW 7/26/2010 COMPAL PWRBTN# PCH has integrated pull up 20K ohm RH356 change to De pop X01
73 37 HW 7/28/2010 COMPAL PCIE_MCARD1_DET# add resistor pull up to R692 change to pop X01
+3.3V_ALW_PCH
A A
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74 24 HW 9/06/2010 COMPAL In order to use the HF part. Q21 change SB000009K0L to SB000009K1L X02
75 14,18 HW 9/06/2010 Intel Follow Intel request Add RH52 and RH53. X02
76 27 HW 9/10/2010 COMPAL Schematic error that Docking U29.5 netname change from DPC_AUX#_C to DPD_AUX#_C. X02
video output NG of DP & DVI.
77 38,45 HW 9/15/2010 COMPAL For the part consist issue. L49,L50,L51 change SM01002080L to SM070001E0L X02
78 15 HW 9/17/2010 H.ELE. YH2's CL value can't match cd & cg value. CH18 change from 10P to 22P, CH19 change from 10P to 27P. X02
79 30 HW 9/23/2010 IDT MIC detect issue. U72 change version from SA00003ZZ1L(ZB) to SA00003ZZ2L(YA). X02
80 27 HW 9/23/2010 COMPAL 2nd source question. U23 & U29 DP_SW change from SA00000CA0L(TI) to SA00003890L(PERICOM). X02
81 18 HW 9/23/2010 Intel Follow Intel design guide Rev1.2 Change RH149 to 2.2k and RH150 to 0 ohm X02
C C
82 32 HW 9/23/2011 Intel Intel request U31 change version from WG82579LM QMWM A2 to WG82579LM QNGP C0. X02
83 15,32 HW 9/24/2011 H.ELE. modify item 78 CH18 & CH19 change from 22P to 10P and YH2 change from CL=18pF to CL=12pF. X02
YH2's CL value can't match cd & cg value. C470 & C471 change from 33P to 18P and Y3 change from CL=18pF to CL=12pF.
84 24 HW 9/24/2011 COMPAL The PWM can not function correct. R1137 change from 100K to 10K. X02
85 41 HW 9/24/2011 EPSON The frequency skew of Y6 is too big in C741 & C743 change from 33P to 39P, X02
Normal temperature.
86 36 HW 9/25/2011 COMPAL Correct the 53.6 ohm into L end part number. Change the R683,R684,R685,R686 to SD00000HE8L X02
87 24 HW 9/25/2011 COMPAL Meet LCD fall time as 3~10ms spec R413 from 390 ohm change to 220 ohm
X02
88 38 HW 9/25/2011 COMPAL Correct the Express Card PWR S/W into Change the U41 to SA00001SL2L.
B B
L end part number. X02
89 36 HW 9/28/2010 O2Micro O2Micro request. 1. Move C582 to +MMI_1394_VCCH and close to either one pin 28 or pin 33. X02
2. Move C581 to +MMI_PE_VDDH and close to pin1.
3. Add a 0.01uF capacitor on +MMI_PE_VDDH and close to pin1.
90 30,31 HW 9/30/2010 IDT To solve pop noise and detect issue Add U6,Q33,Q46,D70,D71,R425,R33,R38,R424,R161,R352,R1088,C967,C307,C308 X02
Q107 change from SB00000960L(3pin) to SB00000DH0L(6pin)
91 30 HW 9/30/2010 COMPAL EMC request Add bypass cap C1186~C1189 X02
92 14,09 HW 10/04/2010 Intel Following Intel DG ver1.5 1. Add RH31 pull down resister. X02
2. RC96,RC97 no stuff
93 34 HW 10/04/2010 Broadcom Broadcom request(enhancement current amount) L39 & L40 change from SHI00005Y0L(0603 size) to SHI0000CH0L(0805 size). X02
A A
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D 94 11 HW 10/04/2010 COMPAL Change QC5 VGS MAX rating from 12V to 20V Change QC5 from SB52302028L to SB00000HK0L X02 D
95 24,26 HW 10/04/2010 COMPAL Change RB751V to HF part Change D63,D64,D65,D68,D69 to SCS00004L0L X02
96 7,18,41 HW 10/04/2010 COMPAL For cost saving Remove RH159,RH261 X02
97 30 HW 10/06/2010 COMPAL 1. Sync-up with Macallan 14" 1. Remove R1587~R1590, C1186~C1189, change R1183~R1186 to L91~L94 X02
2. EMC request 2. Change Audio signal's diode from 4 of 2pins(SD05.TCT) to 2 of 3pins
(PESD5V0U2BT SCA00000T0L)
98 38 HW 10/06/2010 COMPAL In order to enable Express Card PWR S/W Add connection of pin4,pin5,pin13 and pin14 to power net. X02
2nd source vendor "GMT" to act.
99 26 HW 10/06/2010 COMPAL Follow safety request Pop F2 and de-pop R5 X02
100 45 HW 10/06/2010 COMPAL Remove Bypass ESATA Repeater schematic, Remove R1189~R1196. X02
C because Gen1 EA fail when Bypass ESATA C
Repeater.
101 47,14 Hw 10/06/2010 COMPAL Remove PAID function of RTC 1. JRTC1 change from 3pin to 2pin(SP02000CA0L) and remove detect pin X02
2. UH4.C36 & RH355.2 rename from RTC_DET# to PCH_GPIO33
102 29 HW 10/06/2010 COMPAL For power saving Increase JSATA2 detect pin R1177 from 1k to 100kohm X02
103 46 HW 10/07/2010 COMPAL For NB board space consider. Remove page46 two block MIC detect schematic to IO/B. X02
104 28 HW 10/07/2010 COMPAL For cost saving De-pop the R505,Q28,R500,R499,C393,C394,R504 parts. X02
105 28 HW 10/07/2010 COMPAL Based on support SSD HDD Add +3.3V_RUN on JSATA1 pin8,pin9,pin10 X02
106 30,32,40 HW 10/07/2010 COMPAL GPIO MAP update at 1-Oct-10 1. Add U15, C478 that defect RJ45 cable insert or not if plug in then X02
42 close WLAN power.
B 2. 5048 GPIOB7 rename from AUD_NB_MUTE to AUD_NB_MUTE# B
107 32 HW 10/08/2010 COMPAL Based on IEEE Return Loss EA fail L30~L37 change from SHI00004O0L(22NH) to SHI0000CV0L(5.6NH) X02
108 18,30 HW 10/08/2010 COMPAL Remove PAID function of speaker 1. JSPK1 change from 6pin to 4pin(LTCX002V50L) that remove detect pin X02
2. UH4.D40 & RH269.2 rename from SPEAKER_DET# to GPIO17
109 44 HW 10/11/2010 COMPAL LED brightness test result change R957 to 1K, R955, R941, R949, R939, R934 to 4.7K X02
110 41 HW 10/11/2010 COMPAL BORAD_ID change R875 to 62K. X02
111 17 HW 10/11/2010 Intel Follow Intel check list Rev1.2 Add @RH332 X02
112 31,41 HW 10/12/2010 DELL DELL DM Dennis has confirmed. No stuff “Latitude On” button of SW2,R877,C740 X02
113 24,45 HW 10/13/2010 COMPAL EMC request(for cost saving) 1.UE1,UE2,U13,U86 change from PRTR5V0U2X(SOT143-4)(4pin)to X02
A PESD5V0U2BT(SOT23-3)(3pin) SCA00000T0L. A
2.Diode for UE1,UE2 shall be added, not reserved.

3.Rename UE1 to D73,UE2 to D72,U86 to D74,U13 to D75
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.

Title
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114 28 HW 10/13/2010 COMPAL Follow 14" PJP71 size change to 1X1 X02
D D
115 7 HW 10/14/2010 COMPAL UC1.4 is OD pin,so remove pull down R. Remove RC11 X02
116 28 HW 10/15/2010 COMPAL MikeCC suggest Stuff of R505,C394,R504 X02
117 14,18 HW 10/19/2010 COMPAL Follow Intel debug port DG Connect PCH_GPIO15 to PCH XDP_FN16 X02
118 30 HW 10/19/2010 COMPAL Change Mic detect to external detect Remove R161 and add C1165 X02
C C
B B
A A

Title
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R equest
Item P age# T itle D ate Issue D escription Solution D escription R ev.
O w ner
Change PQ6 from SI4128 to AO4466L.
1 54 +3V/+5V 7/2 Compal EA test fail in 3.3V HS Vds ring Change PQ8 from SI4134 to AO4712L. X01
D D
Remove PR264 and add PR410 connect PR249.1 to do PD. Remove VCCSA_VID_0 X01
net to connect PR249.1 and change net name to VCCSA_VID_1
Change PR250 from 34K to 113K
Change PR256 from 0 to 140K
2 62 +VCC_SA 7/2 Compal VCCSA have the spike to damage CPU Change PR261 and 265 from 2.49K to 0 ohm.
Change PD resister PR266 and PR410 to 1K.
Depop PR260 and PR267
Change PR259 from 274K to 47.5K
3 47 +DCIN 7/16 Compal PR16 down size from 0805 to 0402 Change PR16 from 100k/0805 (SD01510038L) to 100k/0402 (SD02810038L) X01

4 56 +VCC_SA 7/20 Compal VCCSA phase node over Mosfet Vds rating X01

5 56 +1.05V_M 7/20 Compal +1.05V_M phase node over Mosfet Vds rating X01
C
Change PQ18 from SI4172 to AO4712L. C
Change PD14,PD16 from SBR3A40SA-13_SMA2 X01

6 55/57 Charger 7/20 Compal solve leakage issue (SC100003J00) to ES2AA-13-F (SC100005A0L)
Slector
Change PC56 and PC57 from 330U/9m/2.5V

7 49 +1.5V_SUS 7/20 Compal Material shortage issue. X01
(SGA19331D1L) to 330U/9m/2V (SGA20331E0L)
Change PL1 to FBMJ4516HS720NT(SM010009C8L) from FBMA-L18-453215-

PL1 current rating is not enough for 9cell 900LMA90T (SM01002078L) X01
8 47 +DCIN 7/20 Compal
(3.0Ah 1C) discharge current
Add PL22 FBMJ4516HS720NT(SM010009C8L)
Take off PJP45
9 48 +3V/+5V 7/20 Compal PC24 down size to 0603 from 0805 Change PC24 to 4.7u/6.3V/0603 (SE107475K8L) from 4.7u/6.3V/0805
(SE093475K8L) X01
B Reserve 300K PD to avoid VR turn on when B

10 49 +1.5V_SUS 7/20 Richtek EN/DEM is floating. Add PR508 to do PD from PU3 pin1 X01
Reserve 33nF cap parallel with PC136 to

11 53 VCORE 7/20 MAXIN fine tuning VCORE transient Add PC401 33nF/16V/X7R/0402(SE076333K8L) X01
Add 33nF cap parallel with PC208 to fine

12 54 VGFX 7/20 MAXIN Add PC402 33nF/16V/X7R/0402(SE076333K8L)
tuning VGFX transient X01
Change PU11 pin1 net name to ICREF from GNDA_CHG

Reserve adapter protection circuit X01
13 55 Charger 7/21 Compal for turbo mode Change PU11 pin26 net name to ICOUT from VCC
Reserve PR511,PR512,PR513,PR514,PC406,PQ59,PR515,PR516.PR517,PC407
PC244,PC245,PR518,PR519,PR520.PQ43,PC405,PR509,PR510
PQ27 body diode can handle surge current

14 55 Charger 7/21 Compal Depop PD14 SBR3A40SA (SC100003J00) X01
A A
Title
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Power-Change History 1
5 4 3 2 1
5 4 3 2 1

R equest
Item P age# T itle D ate Issue D escription Solution D escription R ev.
O w ner
Change PR202 to 1.43k (SD03414318L) from 5.49k (SD03454918L)
D Change PR203 to 2.1k (SD03421018L) from 2.49k (SD03424918L) D
Change PC208 to 0.33u/10V/X7R (SE080334K8L) from 0.22u/16V/X7R (SE026224K8L)

1 53,54 VGFX_Core 7/21 MAXIM Depop one phase for GFX_core Change PR201 to 40.2k (SD03440228L) from 10K (SD03410028L)
Depop PR204,PR190,PR196,PC206,PR197,PL14,PR181,PR186,PR190,PC191,PR187
PQ21,PQ22,PC184,PC183,PC182,PC181,PC403,PC185,PR179,PC188,PU10,PC186
Pop PR147 and PR150 0 Ohm (SD02800008L) X01
Change PR157 to 8.66k (SD03486618L) from 13.3K (SD03413328L)
Pop PQ38 AON6414L (SB00000NW00)
Pop PQ26 AON6704 (SB00000I90L)
Change PL15 to 0.36u (SH00000HQ0L) from 0.56u (SH00000I20L)
Change PC203 to 4700p (SE075472K8L) from 2200p (SE074222K8L)
2 53 Vcore 7/26 MAXIM MAX17411 version change,setting change. Change PR118,PR119 to 1 ohm (SD014100B8L) from 2 ohm (SD013200B8L) X01
Change PR127 to 215K (SD03421538L) from 100K (SD03410038L)
C
3 53 Vcore 7/26 MAXIM Fine tune Vcore and VGFX_core loadline. Change PR140 to 12K (SD03412020L) from 12.4K (SD00000AJ8L) X01 C
VGFX_Core Change PR157 to 8.87K (SD03488718L) from 8.66K (SD03486618L)
4 53/54 Vcore 7/26 MAXIM Fine tune Vcore and VGFX_core Add PC401 0.033uF (SE076333K8L) X01
VGFX_Core Transient Response. Add PC402 0.033uF (SE076333K8L)
5 55 Charger 7/28 MAXIM Pop adapter protection componment for Pop PR510(SD02810038L),PR511( ),PR512(SD03411038L),PR513(SD03410038L) X01
turbo mode with TI solution. PR514(SD000009R8L),PC406(SE071101J8L),PQ59(SB50206008L)
6 52 9/20 TI TI IC version change, OCP setting change. PR95 change from 0 ohm to 22K ohm. X02
1.05V_VTT
7 52 1.05V_VTT 10/12 TI 1206 MLCC COS issue. Change from 22uF 1206 X5R 8pcs to 47uF 0805 X5R 2pcs and 22uF 0805 X5R 8pcs. X02
B B
Fine tune VCCSA OCP setting for 2nd and Change PR247 and PR262 to 12.7k (SD03412728L) from 11.5k (SD03411528L)
8 56 VCCSA 10/15 Compal X02
3rd source choke
9 47 DCIN 10/15 Compal 6 ~ 7mA leakage current in slice Change PR2 and PR504 to 100K (SD02810038L) from 10K (SD03410028L) X02
Fine tune adapter protection circuit for Pop PR509 Ohm (SD02800008L)
10 55 charger 10/15 Compal 2nd source and reserve H_PROCHOT# Add PR521 and reserve PR522 connect to H_PROCHOT# X02
Compal RF WWAN noise solution. Change PR34,PR35 from 1 ohm to 2.2 ohm. X02
11 48 5V/3.3V 10/15 Kuo. Jimmy
Compal Fine tune Vcore and VGFX_core loadline. Change PR157 to 8.06K(SD03480618L) from 8.87K (SD03488718L) X02
12 53 Vcore 10/27
A
Depopulate PC401,PC402 A
VGFX_Core Fine tune Vcore and VGFX_core
Title
Power-Change History 2
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-6562P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Wednesday, October 27, 2010 Sheet 66 of 66
5 4 3 2 1

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A B C D E

PCB NO : LA-6562P (DA80000JP00)

rPGA Sandy Bridge +

CONN@ : Connector Component

MB Type BOM P/N

TPM EN/ TCM DIS 43193031L01 (R1) 1@ 3@

TPM DIS/ TCM EN 43193031L02 (R1) 2@ 4@

TPM DIS/ TCM DIS 43193031L03 (R1) 2@ 3@

Block Diagram Compal confidential Model: PAL60 Support Frequence 1066/1333

LVDS CONN LVDS 4MB (Socket G1)

SATA 4 ESATA 0 BIO

S5 S4/AC don't exist OFF OFF OFF OFF OFF

Lane 5 MINI CARD-3 (Pink Panther)

Lane 7 10/100/1G LOM

+3.3V_WLAN +3.3V_ALW_PCH +3.3V_SUS +3.3V_LAN +3.3V_RUN +3.3V_M

+VCC_CORE +1.5V_MEM +0.75V_DDR_VTT +1.8V_RUN +1.05V_RUN_VTT +1.05V_M

AO4728 SI3456 SI4164

G8 LAN_SMBDATA 31 LOM SMBUS Address [C8]

(2)PEG_ICOMPO use 12mil connect to RC2

PCI EXPRESS* - GRAPHICS

<16> FDI_CTX_PRX_P0 FDI_CTX_PRX_P0 A22

DP Compensation Sandy Bridge_rPGA_Rev1p0

Follow DG Rev0.71 SM_DRAMPWROK topology +1.05V_RUN_VTT

<22> H_THERMTRIP# 1 2 H_THERMTRIP#_R AN32 SM_RCOMP2 --> 15mil 1

AR27 XDP_TMS RC46 0_0402_5%~D

H_PM_SYNC TMS XDP_TRST#

Buffered reset to CPU +3.3V_RUN VCCPWRGOOD_0_R

DDR SYSTEM MEMORY B

CFG Straps for Processor

AR35 @ T17 PAD~D

PAD~D T28 @ F25 CFG6

Sandy Bridge_rPGA_Rev1p0 CFG7

1: (Default) PEG Train immediately

53AAG35 8.5A 22uF X 12.

PEG AND DDR

1 1 1 1 1 1 1 1 AT21 VAXG3 AP10 VSS31 VSS111 AE35

AT20 VAXG4 AP7 VSS32 VSS112 AE34

AP18 have 10 mil trace width CC1502 1 0.1U_0402_10V7K~D AM29 AC6

AM24 AF7 +1.5V_MEM AM4 AB31

VAXG49 VSS77 VSS157

+1.8V_RUN B6 H23 VCCSA_SENSE <56>

Compal Electronics, Inc.

DDR_A_D40 147 148 DDR_A_D45

153 154 DDR_A_DQS5

DDR_B_WE# 113 114 DDR_CS2_DIMMB#

1 1 1 1 1 1 1 DDR_B_MA13 119 120 M_ODT3

+ DDR_CS3_DIMMB# 121 122

179 180 DDR_B_D60

185 186 DDR_B_DQS#7

1 1 205 GND1 GND2 206

CMOS_CLR1 CMOS setting PCH_AZ_SYNC is sampled

RH282 @ PCH_GPIO15 @RH18

<7,16> SIO_PWRBTN#_R HOOK1 ITPCLK#/HOOK5

PCH_JTAG_TCK TCK1 TDI PCH_JTAG_TMS

JTAG_TCK SATA5TXP SATA_PTX_DKRX_P5_C <39>

1 2 QH7 CougarPoint_Rev_1p0 QH1 BSS138W-7-F_SOT323-3~D

+3.3V_SPI C746 +3.3V_SPI C745

200 MIL SO8 200 MIL SO8

MEM_SMBCLK 6 1 DDR_XDP_WAN_SMBCLK <7,12,13,14,28,37>

& Express/Mini card 1 2