STA: Part 1

Definition, Flow & Important

Terms in STA
Name: Onkar Sanjay Mane
Outline:
• What is Static Timing Analysis?
• Why Static Timing Analysis?
• Design Flow
• STA at Different Design Phases
• Important Concepts:
1. Propagation Delay
2. Slew of a Waveform
3. Skew between Signals
4. Clock Uncertainty
5. Timing Arcs and Unateness
6. Min and Max Timing Paths
7. Clock Domain
8. Operating conditions
©Onkar Sanjay Mane
What is Static Timing Analysis?
• Static Timing Analysis (STA) is a critical method for verifying the timing
performance of a digital design. It differs from timing simulation, which checks
both functionality and timing by applying specific input stimuli and observing
the results over time.
• STA is called "static" because it evaluates the timing of a design without relying
on dynamic input values or running simulations. Instead, it analyses the
design's structure and timing constraints to ensure the design meets the
required performance criteria.
• In contrast to simulation-based timing analysis, which involves applying a
series of input signals, observing behaviour, advancing time, and repeating the
process, STA thoroughly examines all possible signal paths in the design. This
approach guarantees that the timing requirements are satisfied without having
to simulate actual data flows.
©Onkar Sanjay Mane
External environment • Given a design with defined input clocks and an
of design (including
clock definitions)
external environment, the purpose of static timing
analysis (STA) is to ensure that the design can operate
DUA(Design
reliably at the specified clock frequency. The Design
Under Analysis) Under Analysis (DUA) is checked to confirm it
functions safely at the rated speed.
• Key timing checks include setup and hold checks. A
setup check ensures data arrives at a flip-flop within
Static Timing Analysis the given clock period, while a hold check guarantees
(STA) the data is held long enough to prevent unintended
data pass-through. These checks ensure that the data
is correctly captured by the flip-flop and no timing
Timing reports violations occur.
(include violating
paths, if any)
©Onkar Sanjay Mane
 Why Static Timing Analysis?
• Static Timing Analysis (STA) offers a comprehensive verification of all timing
paths in a design, unlike simulation-based methods that can only test portions
of the design based on the input stimuli. Simulation's effectiveness is limited by
the test vectors and becomes impractical for large designs with millions of
gates, making it difficult to achieve exhaustive verification.
• STA, on the other hand, efficiently checks all timing paths, ensuring that designs
with millions of gates are thoroughly validated. Additionally, STA addresses
issues like crosstalk and noise, which can affect a design's performance and
functionality. Unlike logic simulation, STA can evaluate the design's robustness
against these factors, ensuring it operates reliably under various conditions.

©Onkar Sanjay Mane

 RTL SDC (Constraints)

Design Flow Synthesis

Gate-level netlist
o Unoptimized
o Ideal Clock Tree
o No Routes
Logic Optimization
Gate-level netlist
Logic Design
Static Timing o Optimized
Analysis
Physical
Design Gate-level netlist
o Global Route
Placement
Gate-level netlist
Clock Tree Synthesis o Real Clock Tree
Static Timing Gate-level netlist
Analysis incl. o Unoptimized
Routing
Noise , o Ideal Clock Tree
Crosstalk o No Routes
• In a CMOS digital design flow, Static Timing Analysis (STA) is performed at various
stages, but it is typically not done at the RTL level. At this stage, the focus is on
verifying functionality rather than timing, and the necessary timing information is often
not available. STA becomes more relevant after synthesis when the design is at the
gate level.
• Before and after logic optimization, STA is used to identify and address critical timing
paths. During the physical design phase, clock trees are initially considered ideal with
zero delay. As physical design progresses and clock trees are implemented, STA is
performed iteratively to monitor and resolve timing issues.
• Interconnect metal traces introduce parasitic RC effects that significantly impact
signal delays and power dissipation. During logical design, ideal interconnects are
assumed, and wireload models estimate RC values based on cell fanouts. In the
global route phase, approximate RC values are used, while detailed routing provides
accurate RC values and accounts for coupling effects.

©Onkar Sanjay Mane

the static timing analysis can be performed on a gate-level
netlist depending on:

I. How interconnect is modelled - ideal interconnect, wireload model, global

routes with approximate RCs, or real routes with accurate RCs.

II. How clocks are modelled - whether clocks are ideal (zero delay) or
propagated (real delays).

III. Whether the coupling between signals is included – whether any crosstalk
noise is analysed

©Onkar Sanjay Mane

 STA at Different Design Phases
1. At the logical level (gate-level, with no physical design), STA can be performed
using:
o Ideal interconnect or interconnect modelled with a wireload model.
o Ideal clocks with estimated latencies and jitter.

2. During the physical design phase, STA can be conducted with additional
options:
o Interconnect modelling, which may include global routing estimates, real routes
with approximate extraction, or real routes with final sign-off accuracy.
o Real clock trees.
o Analysis including or excluding the effects of crosstalk.
©Onkar Sanjay Mane
Important Concepts A Z
1. Propagation Delay
In a CMOS inverter cell, the
propagation delay is determined by
A
specific measurement points on the
input and output switching 50 % Threshold
Point
waveforms. This delay can be
categorized as: Tf Tr
• Output fall delay (Tf): The time
taken for the output to transition 50 % Threshold
from high to low. Point

• Output rise delay (Tr): The time Z

taken for the output to transition
from low to high.
©Onkar Sanjay Mane
2. Slew of a Waveform
• The slew rate refers to the rate at which a signal changes over time. In static timing
analysis, waveforms—whether rising or falling—are evaluated based on how quickly
they transition, categorizing them as either slow or fast.
• Slew is typically measured by the transition time, which represents how long it takes for
a signal to shift between two specific voltage levels. It's important to note that the
transition time is inversely related to the slew rate: a longer transition time indicates a
slower slew, while a shorter transition time signifies a faster slew.

VDD/Logic - 1

70% VDD

30% VDD

Fall Slew VSS/Logic - 0 Rise Slew

©Onkar Sanjay Mane
 3. Skew between Signals
• Skew refers to the timing
difference between two or more
Clock Skew
signals, which can involve data D Q

signals, clock signals, or both. For Clock Source

Clk
instance, if a clock tree has 500
endpoints and a skew of 50 ps, this D Q

means the time difference PLL Clk

between the longest and shortest

D Q
clock paths is 50 ps.
Clk
• In a clock tree, the starting point is
usually where the clock signal is Clock Latency
generated, and the endpoints are
typically the clock pins of
synchronous elements like flip-
flops. ©Onkar Sanjay Mane
• Clock latency refers to the total time it takes for the clock signal to travel from the
source to an endpoint, while clock skew is the difference in arrival times at the
various endpoints within the clock tree.
• An ideal clock tree assumes the clock source has infinite drive strength, meaning
it can drive an unlimited number of loads without any delay. Additionally, any cells
in the clock tree are considered to have zero delay. During the early stages of
logical design, static timing analysis (STA) is often performed with this ideal clock
tree model to focus primarily on analysing data paths. In such an ideal scenario,
the clock skew is set to 0 ps by default.

©Onkar Sanjay Mane

4. Clock Uncertainty
• Clock uncertainty accounts for various factors, including clock period jitter and
additional margins used in timing verification. Every real clock source
experiences a finite amount of jitter, which represents the window within which
a clock edge can occur.
• The level of clock period jitter is determined by the type of clock generator in
use. Since no clock is ideal, all clocks exhibit some degree of jitter, and this
jitter must be factored into the clock uncertainty specification.
• Before the clock tree is implemented, the expected clock skew of the design
must also be included in the clock uncertainty. It is possible to define different
clock uncertainties for setup checks and hold checks. For hold checks, clock
jitter is typically excluded from the uncertainty, allowing for a smaller clock
uncertainty value.

©Onkar Sanjay Mane

5. Timing Arcs and Unateness
• Each cell in a circuit has multiple timing arcs. For instance, combinational logic
cells like AND, OR, NAND, NOR, and adders have timing arcs that connect each
input to the corresponding output. Sequential cells, such as flip-flops, include
timing arcs from the clock to the outputs and impose timing constraints on the
data pins relative to the clock.

Positive unate arc Negative unate arc Non-unate arc

©Onkar Sanjay Mane

• A timing arc is called positive unate if a rising transition on the input causes the
output to rise or remain unchanged, and a falling transition on the input causes
the output to fall or remain unchanged. For example, the timing arcs of AND and
OR gates are positive unate.
• A negative unate timing arc occurs when a rising transition on the input leads to a
falling transition at the output (or no change), and a falling transition at the input
causes a rising transition at the output (or no change). NAND and NOR gates
typically exhibit negative unate timing arcs.
• In a non-unate timing arc, the output transition depends not only on the direction
of change at one input but also on the states of other inputs. For example, XOR
(exclusive OR) cells have non-unate timing arcs, where the output behavior is
influenced by the input states.

©Onkar Sanjay Mane

6. Min and Max Timing Paths

The total delay for logic propagation through a path is known as the path delay.
This is the sum of delays from the various logic cells and nets along the path. In
most cases, there are multiple paths through which the logic can propagate to its
destination. ©Onkar Sanjay Mane
• The actual path taken depends on the state of other inputs along the logic path. As
shown in the figure, multiple paths exist to reach the destination, allowing both
maximum and minimum timing to be determined.
• The path with the longest delay is called the max path, while the one with the shortest
delay is the min path.
• The max path, also known as the late path, between flip-flops UFF1 and UFF3 follows
through UNAND0, UBUF2, UOR2, and UNAND6. On the other hand, the min path, also
known as the early path, travels through UOR4 and UNAND6.
• In the case of a flip-flop to flip-flop path, like from UFF1 to UFF3, one flip-flop launches
the data while the other captures it. In this example, UFF1 is the launch flip-flop and
UFF3 is the capture flip-flop.
• These terms, launch and capture, always refer to flip-flop to flip-flop paths, and UFF3
would become the launch flip-flop for the next stage.

©Onkar Sanjay Mane

 7.Clock Domain
• In synchronous logic design, a periodic clock signal latches newly computed data
into flip-flops. This data is based on values stored in the flip-flops during the
previous clock cycle. Once the data is latched, it is then used as input to compute
new values for the next clock cycle. This repetitive process ensures that the flip-
flops remain synchronized with the clock, enabling predictable data flow in digital
circuits.
Two clock domains

D Q D Q

D Q D Q
Clk D Q Clk D Q
Clk D Q Clk D Q
Clk Clk

Clk Clk

USBCLK MEMCLK ©Onkar Sanjay Mane

• A clock domain refers to a group of flip-flops that are driven by the same
clock signal, ensuring synchronous operation within that domain. In many
designs, multiple clock domains exist. For example, one clock signal like
USBCLK might drive 200 flip-flops, while another clock, MEMCLK, could
drive 1000 flip-flops, creating distinct clock domains. Each clock domain
operates independently unless data paths cross between them, which
requires careful timing consideration to avoid synchronization issues.
Clock Domain Crossing:
• The relationship between different clock domains is determined by the
presence of data paths connecting them. If data paths exist that begin in
one clock domain and end in another, these domains are considered
related, and crossing between them requires careful timing
considerations. On the other hand, if no such paths exist, the clock
domains are considered independent, meaning there are no timing paths
shared between the two domains.
©Onkar Sanjay Mane
 Clock Domain Crossing

(Can be clock
D Q D Q
synchronizer logic)

Clk Clk

USBCLK MEMCLK

• Why is it important to discuss paths between clock domains? In most designs,

there are numerous clocks, leading to a vast number of potential paths between
clock domains. Distinguishing between real clock domain crossings and those
that are not is a critical part of the timing verification process. This allows
designers to concentrate on validating only the actual timing paths, ensuring
accurate and efficient verification.
©Onkar Sanjay Mane
8. Operating conditions
In static timing analysis (STA) refer to a combination of Process, Voltage, and
Temperature (PVT) under which the analysis is performed. The cell and
interconnect delays are calculated based on these specified conditions.
Semiconductor foundries provide three types of process models for digital
designs: slow, typical, and fast. The slow and fast models represent the
extreme manufacturing variations.
Delay Delay Delay

Worst Worst Worst

Nom Nom Nom

Best Best Best

Slow Typ Fast Min Nom Max Min Nom Max

Delay vs process Delay vs voltage Delay vs temperature

• To ensure a robust design, validation is conducted at these extreme
process corners, as well as at environmental extremes, such as high
temperatures and low power supplies. For example, cell delays are
affected by process variations, power supply fluctuations, and
temperature changes. As the process, voltage, and temperature conditions
vary, the delays in the cells also shift accordingly.
• The selection of the operating condition for STA is influenced by the
availability of cell libraries under different PVT scenarios. The standard
operating conditions include:
1. WCS (Worst-Case Slow): The process is slow, the temperature is high
(e.g., 125°C), and the voltage is low (e.g., nominal 1.2V minus 10%). For
nanometre technologies with low power supplies, another worst-case
corner might include the slow process, lowest power supply, and lowest
temperature.
©Onkar Sanjay Mane
• Interestingly, delays at low temperatures can sometimes be longer than those at
higher temperatures due to reduced threshold voltage (Vt) margins—a
phenomenon known as temperature inversion.
1.TYP (Typical): The process is typical, the temperature is nominal (e.g., 25°C),
and the voltage is nominal (e.g., 1.2V).
2.BCF (Best-Case Fast): The process is fast, the temperature is low (e.g., -40°C),
and the voltage is high (e.g., nominal 1.2V plus 10%).
• For power analysis, different operating conditions are used:
1.ML (Maximal Leakage): The process is fast, the temperature is high (e.g.,
125°C), and the voltage is at its highest (e.g., 1.2V plus 10%), which leads to
maximum leakage power. This condition often correlates with the highest active
power in a design.
2.TL (Typical Leakage): The process is typical, the temperature is high (e.g.,
125°C), and the voltage is nominal (e.g., 1.2V). This is a representative condition
for typical leakage, as chip temperatures rise during normal operation due to
power dissipation. ©Onkar Sanjay Mane