MC74HC244A

Octal 3-State Noninverting

Buffer/Line Driver/
Line Receiver
High−Performance Silicon−Gate CMOS
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The MC74HC244A is identical in pinout to the LS244. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This octal noninverting buffer/line driver/line receiver is designed
to be used with 3−state memory address drivers, clock drivers, and SOIC−20 TSSOP−20
other bus−oriented systems. The device has noninverting outputs and DW SUFFIX DT SUFFIX
two active−low output enables. CASE 751D CASE 948E
The HC244A is similar in function to the HC240A.
PIN ASSIGNMENT
Features
ENABLE A 1 20 VCC
• Output Drive Capability: 15 LSTTL Loads A1 2 19 ENABLE B
• Outputs Directly Interface to CMOS, NMOS, and TTL YB4 3 18 YA1
• Operating Voltage Range: 2.0 to 6.0 V A2 4 17 B4
• Low Input Current: 1 mA YB3 5 16 YA2
• High Noise Immunity Characteristic of CMOS Devices A3 6 15 B3

• In Compliance with the Requirements Defined by JEDEC Standard YB2 7 14 YA3

A4 8 13 B2
No. 7 A
YB1 9 12 YA4
• Chip Complexity: 136 FETs or 34 Equivalent Gates
GND 10 11 B1
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
MARKING DIAGRAMS
Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS 20 20

Compliant HC
HC244A 244A
AWLYYWWG ALYWG
LOGIC DIAGRAM G
2 18 1 1
A1 YA1
SOIC−20 TSSOP−20
4 16 A = Assembly Location
A2 YA2
WL, L = Wafer Lot
6 14 YY, Y = Year
A3 YA3 WW, W = Work Week
G or G = Pb−Free Package
8 12
A4 YA4 (*Note: Microdot may be in either location)
DATA NONINVERTING
INPUTS 11 9 OUTPUTS
B1 YB1 FUNCTION TABLE
Inputs Outputs
13 7 Enable A,
B2 YB2
Enable B A, B YA, YB
15 5 L L L
B3 YB3
L H H
17 3 H X Z
B4 YB4 Z = high impedance

1 ORDERING INFORMATION
OUTPUT ENABLE A PIN 20 = VCC
ENABLES 19 See detailed ordering and shipping information in the package
ENABLE B PIN 10 = GND
dimensions section on page 5 of this data sheet.

© Semiconductor Components Industries, LLC, 2014 1 Publication Order Number:

August, 2014 − Rev. 15 MC74HC244A/D
 MC74HC244A

MAXIMUM RATINGS
Symbol Parameter Value Unit This device contains protection
VCC DC Supply Voltage (Referenced to GND) –0.5 to +7.0 V circuitry to guard against damage
due to high static voltages or electric
Vin DC Input Voltage (Referenced to GND) –0.5 to VCC + 0.5 V fields. However, precautions must
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) –0.5 to VCC + 0.5 V
voltage higher than maximum rated
Iin DC Input Current, per Pin ±20 mA voltages to this high−impedance cir-
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ±35 mA
Vout should be constrained to the
ICC DC Supply Current, VCC and GND Pins ±75 mA range GND v (Vin or Vout) v VCC.
Unused inputs must always be
IIK Input Clamp Current (VI < 0 or VI > VCC) ±20 mA tied to an appropriate logic voltage
IOK Output Clamp Current (VO < 0 or VO > VCC) ±20 mA level (e.g., either GND or VCC).
Unused outputs must be left open.
PD Power Dissipation in Still Air, SOIC Package† 500 mW
TSSOP Package† 450

Tstg Storage Temperature –65 to +150 _C

TL Lead Temperature, 1 mm from Case for 10 Seconds _C
(SOIC, SSOP or TSSOP Package) 260
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: −6.1 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
TA Operating Temperature, All Package Types –55 +125 _C
tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns
(Figure 1) VCC = 4.5 V 0 500
VCC = 6.0 V 0 400
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.

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2
 MC74HC244A

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit
VCC –55 to
Symbol Parameter Test Conditions V 25_C v 85_C v 125_C Unit
VIH Minimum High−Level Input Voltage Vout = VCC – 0.1 V 2.0 1.5 1.5 1.5 V
|Iout| v 20 mA 3.0 2.1 2.1 2.1
4.5 3.15 3.15 3.15
6.0 4.2 4.2 4.2
VIL Maximum Low−Level Input Voltage Vout = 0.1 V 2.0 0.5 0.5 0.5 V
|Iout| v 20 mA 3.0 0.9 0.9 0.9
4.5 1.35 1.35 1.35
6.0 1.8 1.8 1.8
VOH Minimum High−Level Output Vin = VIH 2.0 1.9 1.9 1.9 V
Voltage |Iout| v 20 mA 4.5 4.4 4.4 4.4
6.0 5.9 5.9 5.9
Vin = VIH |Iout| v 2.4 mA 3.0 2.48 2.34 2.2
|Iout| v 6.0 mA 4.5 3.98 3.84 3.7
|Iout| v 7.8 mA 6.0 5.48 5.34 5.2
VOL Maximum Low−Level Output Vin = VIL 2.0 0.1 0.1 0.1 V
Voltage |Iout| v 20 mA 4.5 0.1 0.1 0.1
6.0 0.1 0.1 0.1
Vin = VIL |Iout| v 2.4 mA 3.0 0.26 0.33 0.4
|Iout| v 6.0 mA 4.5 0.26 0.33 0.4
|Iout| v 7.8 mA 6.0 0.26 0.33 0.4
Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA
IOZ Maximum Three−State Leakage Output in High−Impedance State 6.0 ±0.5 ±5.0 ±10 mA
Current Vin = VIL or VIH
Vout = VCC or GND
ICC Maximum Quiescent Supply Cur- Vin = VCC or GND 6.0 4.0 40 160 mA
rent (per Package) Iout = 0 mA

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit

VCC –55 to
Symbol Parameter V 25_C v85_C v125_C Unit
tPLH, Maximum Propagation Delay, A to YA or B to YB 2.0 96 115 135 ns
tPHL (Figures 1 and 3) 3.0 50 60 70
4.5 18 23 27
6.0 15 20 23
tPLZ, Maximum Propagation Delay, Output Enable to YA or YB 2.0 110 140 165 ns
tPHZ (Figures 2 and 4) 3.0 60 70 80
4.5 22 28 33
6.0 19 24 28
tPZL, Maximum Propagation Delay, Output Enable to YA or YB 2.0 110 140 165 ns
tPZH (Figures 2 and 4) 3.0 60 70 80
4.5 22 28 33
6.0 19 24 28
tTLH, Maximum Output Transition Time, Any Output 2.0 60 75 90 ns
tTHL (Figures 1 and 3) 3.0 23 27 32
4.5 12 15 18
6.0 10 13 15
Cin Maximum Input Capacitance − 10 10 10 pF
Cout Maximum Three−State Output Capacitance − 15 15 15 pF
(Output in High−Impedance State)

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Buffer)* 34 pF

* Used to determine the no−load dynamic power consumption: P D = CPD VCC2 f + ICC VCC .

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 MC74HC244A

SWITCHING WAVEFORMS

tr tf VCC
DATA INPUT VCC ENABLE 50%
90%
A OR B 50% A OR B GND
10% GND tPZL tPLZ
tPLH tPHL HIGH
OUTPUT 90% 50% IMPEDANCE
50% OUTPUT Y
YA OR YB 10% VOL
10% tPZH tPHZ
tTLH tTHL 90% VOH
OUTPUT Y 50%
HIGH
IMPEDANCE

Figure 1. Figure 2.

TEST CIRCUITS

TEST POINT TEST POINT

CONNECT TO VCC WHEN
OUTPUT OUTPUT 1 kW
TESTING tPLZ AND tPZL.
DEVICE DEVICE CONNECT TO GND WHEN
UNDER UNDER TESTING tPHZ AND tPZH.
TEST CL* TEST CL*

*Includes all probe and jig capacitance *Includes all probe and jig capacitance

Figure 3. Test Circuit Figure 4. Test Circuit

PIN DESCRIPTIONS

INPUTS function as noninverting buffers. When a high level is

applied, the outputs assume the high impedance state.
A1, A2, A3, A4, B1, B2, B3, B4
(Pins 2, 4, 6, 8, 11, 13, 15, 17) OUTPUTS
Data input pins. Data on these pins appear in noninverted
YA1, YA2, YA3, YA4, YB1, YB2, YB3, YB4
form on the corresponding Y outputs, when the outputs are
(Pins 18, 16, 14, 12, 9, 7, 5, 3)
enabled.
Device outputs. Depending upon the state of the
CONTROLS output−enable pins, these outputs are either noninverting
Enable A, Enable B (Pins 1, 19) outputs or high−impedance outputs.
Output enables (active−low). When a low level is applied
to these pins, the outputs are enabled and the devices

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4
 MC74HC244A

LOGIC DETAIL

TO THREE OTHER
A OR B INVERTERS

ONE OF 8
INVERTERS

VCC
DATA
INPUT
A OR B
YA
OR
YB

ENABLE A OR
ENABLE B

ORDERING INFORMATION
Device Package Shipping†
MC74HC244ADWG SOIC−20 WIDE 38 Units / Rail
(Pb−Free)

MC74HC244ADWR2G SOIC−20 WIDE 1000 / Tape & Reel

(Pb−Free)

MC74HC244ADTG TSSOP−20 75 Units / Rail

(Pb−Free)

MC74HC244ADTR2G TSSOP−20 2500 / Tape & Reel

(Pb−Free)

NLV74HC244ADWR2G* SOIC−20 WIDE 1000 / Tape & Reel

(Pb−Free)

NLV74HC244ADTR2G* TSSOP−20 2500 / Tape & Reel

(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable

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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

SOIC−20 WB
CASE 751D−05
ISSUE H
DATE 22 APR 2015
SCALE 1:1
D
A q
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
20 11 2. INTERPRET DIMENSIONS AND TOLERANCES
M

PER ASME Y14.5M, 1994.

B

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD

X 45 _
PROTRUSION.
M

E
H

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

0.25

5. DIMENSION B DOES NOT INCLUDE DAMBAR

h
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
1 10 DIMENSION AT MAXIMUM MATERIAL
CONDITION.

MILLIMETERS
20X b B DIM MIN MAX
A 2.35 2.65
0.25 M T A S B S A1 0.10 0.25
b 0.35 0.49
c 0.23 0.32
D 12.65 12.95
E 7.40 7.60
A e 1.27 BSC
H 10.05 10.55

L
h 0.25 0.75
SEATING L 0.50 0.90
PLANE
18X e A1 c q 0_ 7_
T
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT* 20
20X
20X
0.52 1.30 XXXXXXXXXXX
XXXXXXXXXXX
AWLYYWWG
20 11

1
11.00
XXXXX = Specific Device Code
1 10 A = Assembly Location
WL = Wafer Lot
YY = Year
1.27 WW = Work Week
PITCH G = Pb−Free Package
DIMENSIONS: MILLIMETERS *This information is generic. Please refer to
*For additional information on our Pb−Free strategy and soldering device data sheet for actual part marking.
details, please download the ON Semiconductor Soldering and Pb−Free indicator, “G” or microdot “ G”,
Mounting Techniques Reference Manual, SOLDERRM/D. may or may not be present.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42343B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: SOIC−20 WB PAGE 1 OF 1

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

TSSOP−20 WB
CASE 948E
ISSUE D
DATE 17 FEB 2016

SCALE 2:1
NOTES:
20X K REF 1. DIMENSIONING AND TOLERANCING PER

ÍÍÍÍ
K
ANSI Y14.5M, 1982.
0.15 (0.006) T U S 0.10 (0.004) M T U S V S K1 2. CONTROLLING DIMENSION: MILLIMETER.

ÍÍÍÍ
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.

ÍÍÍÍ
MOLD FLASH OR GATE BURRS SHALL NOT
20 11 J J1 EXCEED 0.15 (0.006) PER SIDE.
2X L/2 4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
B SECTION N−N SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
L −U− 5. DIMENSION K DOES NOT INCLUDE
PIN 1 DAMBAR PROTRUSION. ALLOWABLE
IDENT DAMBAR PROTRUSION SHALL BE 0.08
N 0.25 (0.010)
(0.003) TOTAL IN EXCESS OF THE K
1 10 DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
M REFERENCE ONLY.
0.15 (0.006) T U S 7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
A N MILLIMETERS INCHES
−V− DIM MIN MAX MIN MAX
F A 6.40 6.60 0.252 0.260
B 4.30 4.50 0.169 0.177
DETAIL E C --- 1.20 --- 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
−W−
C H 0.27 0.37 0.011 0.015
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
D G K 0.19 0.30 0.007 0.012
H K1 0.19 0.25 0.007 0.010
DETAIL E L 6.40 BSC 0.252 BSC
0.100 (0.004) M 0_ 8_ 0_ 8_
−T− SEATING
PLANE
GENERIC
SOLDERING FOOTPRINT MARKING DIAGRAM*
7.06
XXXX
1 XXXX
ALYWG
G

A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
0.65 (Note: Microdot may be in either location)
PITCH
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
16X 16X may or may not be present.
0.36
1.26 DIMENSIONS: MILLIMETERS

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASH70169A Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: TSSOP−20 WB PAGE 1 OF 1

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

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NLV74HC244ADTR2G