EE580

Analog IC Design
Instructor: Prof.

Final Project

Students name: Student ID: 984662 Date: 01/09/2011

Introduction 1. Wide-swing current mirror

Figure 1: The wide-swing cascade current mirror. Ibias typically is set to the nominal or maximum input current, Iin

As shorter channel lengths are used, it becomes more difficult to achieve reasonable OpAmp gains due to transistor output-impedance degradation caused to short-channel effects. And Conventional cascode current mirrors limit the signal swings available. The basic idea of this circuit is to bias the drain-source voltages of transistors Q2 and Q3 to be close to the minimum possible without them going to triode region.

2. Wide-Swing Constant-Transconductance Bias Circuit

The bias circuit, which is shown in Figure 2, has incorporated a wide-swing cascade current mirrors into a constant-transconductance cell. The cascade current-mirrors provide a high outputimpedance without severely limiting the signal swing. The use of the constant- transconductance of the analog circuit to match with the conductance of the bias resistor, Rbias, and is ideally insensitive to the power-supply, process and temperature variations.

Figure 2: Wide-Swing Constant-Transconductance Bias Circuit

Basically, there are three important building blocks in the bias circuit. 1. The constant-transconductance ce11 contains two cascode current mirrors (n-channel and p-channel wide-swing cascade current mirror) which are connected rail-to-rail, and uses positive feedback to stabilize the current generated by the bias resistor. 2. Wide-swing cascode current mirrors are important to a low-voltage design when a high gain and a wide swing are essential. 3. In the event that all currents in the bias loop are zero, M31 will be off. Since M30 operates as a high-impedance load that is always on, the gates of M28 and M29 will be pulled high. These transistors then will inject currents into the bias loop, which will start up the circuit. Once the loop starts up, M31 will come on, sinking all of the current from M30, pulling the gates of M28 and M29 low, and thereby turning them off so they no longer affect the bias loop. This circuit is only one example of a start-up loop, and there are many other variations.

Project 1. Fully-differential fold-cascode Op amp.

IB Vbp1 MC1 VCM Vout + MC3 MC4 MC5

IB MC2

MC6

Vout -

Vcntrl IB MC7

I D7 = I D 4 + I D5 = I bias

MC8

IB

Figure 3: The fully-differential fold-cascode Op amp with Common Mode Feedback Op amps Circuit.

In this project, we need to design The fully-differential fold-cascode Op amp with Common Mode Feedback Op amps Circuit and bias circuit for the Op amp in CIC 0.18um CMOS process.

In figure 3, the second circuit represents VREF which is in red dash line. This circuit is Common Mode Feedback circuit which is used to control Vout value.
Table 1. The specification of the Opamp.

Supply Voltage DC Gain Phase Margin Unity-gain Frequency Slew Rate Differential Output Swing Power Dissipation Loading Capacitor

1.8V10% > 60dB > 50 > 100MHz > 20V/sec 1.8V 10mW 0.5pF

First, based on table 1 and the constant value, we can calculate

' K n = n C OX = 340 A / V 2

' K p = p COX = 70A / V 2

I 3 = Slew rate CL = 20 106 0.5 1012 = 10 A

I1 = I 2 = I3 = 5A 2

I4 = I5
We can notice that the value of

1 1.62 [V DD Vout (min ) ] = = 0.81V 2 2

Then,

S4 = S5 =

2 I5 ' 2 K p VSD 5

And for the bias circuit, PMOS overdrive voltage = 0.25 V NMOS overdrive voltage = 0.22 V

Veff = Veff 20 = Veff 21 =

2I D2 n COX (W / L)

W W I D 21 = I D 20 = V 2 eff 20 = V 2 eff 21 L 20 L 21 (W / L )21 = 1 Veff 21 = 2Veff 20 if (W / L )20 4

VGS 21 = VGS 20 + Rbias I

Veff 21 = Veff 21 2 + Rbias

nCox W
2

2 V eff 21 L 21

After that we can measure all of the bias voltage,

Vb1 = 1.2 V Vb2 = 0.7 V Vb3 = 0.82 V Vb4 = 0.62 V

2. Simulation
Voltage Gain Voltage phase

Gain=69.86 dB

Phase margin = 53

Figure 4: Gain and Phase of Opamp

90%

SR=

dV Out (V/ s) dt

SR fall = 31.513 (V / s )
10%

SRrise = 27.394 (V / s )

Figure 5: Slew rate

Figure 6: Output Swing

3. Corner Simulation

Figure 7: Gain of Corner simulation

Table 2: Specifications Summary

Parameter
Supply voltage(V) Gain(dB) Phase Margin() Unity-gain Frequency(MHz) Slew Rate Differential Output Swing Power Dissipation Load Capacitor

Required value
1.8V10% > 60dB > 50 > 100MHz > 20V/sec 1.8V 10mW 0.5pF

Result value
1.8V 69.86 dB 53 107.92MHz Rise = 27.394 V/s Fall = 31.513 V/ s 0.933 V 1.05 mW 0.5 pF

Conclusion
In this project, the fully-differential fold-cascode Op amp that I have designed, does not meet the required specification. And this circuit still has lots of errors. This is my first time to design this kind of circuit. I realized that to design Op amp, I need more understanding in analog IC design knowledge and also time. This final project is the good starter for me in analog IC design.

HSPICE CODE
OpAmp-Gain, GBW, Phase .protect .lib "rf018.l" tt .unprotect .option limpts=1000 $circuit description VDD VDD GND DC 1.8V VSS VSS GND DC 0.0V EIN+ vin+ vcm vin gnd +0.5 EIN- vin- vcm vin gnd -0.5 VCM vcm gnd DC 0.9 Vin vin gnd dc 0 ac 1 RD vin gnd 1meg CL1 VOUT+ VSS 0.5p CL2 VOUT- VSS 0.5p *-----------------------------opamp----------------------------.param W1=10u W5=20u W3=5u W7=2.3u W9=3u W11=1.5u M1 M2 M3 M4 M5 3 4 2 3 4 Vin- 2 VSS nch L=0.3u W1 m=1 Vin+ 2 VSS nch L=0.3u W1 m=1 Vbn2 VSS VSS nch L=0.3u W3 m=6 vbp1 VDD VDD pch L=0.3u W5 m=5 vbp1 VDD VDD pch L=0.3u W5 m=5 vdd vdd 3 Vss nch L=0.3u W3 m=1 4 Vss nch L=0.3u W3 m=1

M12 vdd M13 vdd

M6 VOUT- vbp2 3 VDD pch L=1.5u W7 M=1 M7 VOUT+ vbp2 4 VDD pch L=1.5u W7 M=1 M8 VOUT- Vbn1 6 VSS nch L=1.2u W9 m=1 M9 VOUT+ Vbn1 7 VSS nch L=1.2u W9 m=1 M10 6 vcntrl VSS VSS nch L=1.5u W11 m=1 M11 7 vcntrl VSS VSS nch L=1.5u W11 m=1

*-----------------------------bias-----------------------------Rb vr vss 3k Mb1 vbp1 vbn1 11 vss nch L=1.0u W=4u Mb2 11 vbn2 vr vss nch L=0.9u W=4u m=3 Mb3 12 vbn2 vss vss nch L=0.9u W=4u Mb4 vbn2 vbn1 12 vss nch L=1.0u W=4u Mb5 vbn1 vbn1 vss vss nch L=1.0u W=1u Mb6 vbn2 vbp2 14 VDD pch L=0.3u W=4u m=2 Mb7 14 vbp1 VDD VDD pch L=0.25u W=4u m=2 Mb8 13 vbp1 VDD VDD pch L=0.25u W=4u m=2 Mb9 vbp1 vbp2 13 VDD pch L=0.3u W=4u m=2 Mb10 vbn1 vbp2 15 VDD pch L=0.3u W=4u m=2 Mb11 15 vbp1 VDD VDD pch L=0.25u W=4u m=2 Mb12 16 vbn2 vss vss nch L=0.9u W=4u Mb13 vbp2 vbn1 16 vss nch L=1.0u W=4u Mb14 vbp2 vbp2 VDD VDD pch L=1.0u W=2u Ms1 17 vss VDD VDD pch L=5u W=1u Ms2 17 vbn1 vss vss nch L=0.5u W=4u Ms3 vbp2 17 vss vss nch L=0.5u W=4u Ms4 vbp1 17 vss vss nch L=0.5u W=4u *---------------------------------------------------------------*-----------------------------CMFB-----------------------------.PARAM WQ0=10u WQ1=10u MQ1 b1 vbp1 vdd vdd pch W=WQ0 L=0.3u M=1 MQ2 b2 vbp1 vdd vdd pch W=WQ0 L=0.3u M=1 MQ3 b5 vout+ b1 vdd pch W=WQ1 MQ4 vcntrl vcm b1 vdd pch W=WQ1 MQ5 vcntrl vcm b2 vdd pch W=WQ1 MQ6 b5 vout- b2 vdd pch W=WQ1 L=0.5u L=0.5u L=0.5u L=0.5u

MQ7 vcntrl vcntrl vss vss nch W=4UL=1u M=1 MQ8 b5 b5 vss vss nch W=4U L=1u M=1 *---------------------------------------------------------------.meas ac unit_GB when vdb(vout+,vout-)=0 fall=1 .print AC vdb(vout+,vout-) vp(vout+,vout-) .AC dec 2000 10 100g .op .option post .option acout=0 CONVERGE=1 GMINDC=1.0000E-12 **********corner************** *.alter FF *.lib 'rf018.l' FF *.alter SS *.lib 'rf018.l' SS *.alter FS *.lib 'rf018.l' FS *.alter SF *.lib 'rf018.l' SF ********************************* .end