GS2011M Low Power Wi-Fi Module Hardware Guide Rev 5.0

GS2011M Low Power Wi-Fi Module
Hardware User Guide

1VV0301482 Rev. 5.0 – 2018-01-10
GS2011M Low Power Wi-Fi Module Hardware User Guide
SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE
NOTICE
While reasonable efforts have been made to assure the accuracy of this document, Telit assumes
no liability resulting from any inaccuracies or omissions in this document, or from use of the
information obtained herein. The information in this document has been carefully checked and is
believed to be reliable. However, no responsibility is assumed for inaccuracies or omissions. Telit
reserves the right to make changes to any products described herein and reserves the right to
revise this document and to make changes from time to time in content hereof with no obligation
to notify any person of revisions or changes. Telit does not assume any liability arising out of the
application or use of any product, software, or circuit described herein; neither does it convey
license under its patent rights or the rights of others.
It is possible that this publication may contain references to, or information about Telit products
(machines and programs), programming, or services that are not announced in your country.
Such references or information must not be construed to mean that Telit intends to announce
such Telit products, programming, or services in your country.
COPYRIGHTS
This instruction manual and the Telit products described in this instruction manual may be,
include or describe copyrighted Telit material, such as computer programs stored in
semiconductor memories or other media. Laws in the Italy and other countries preserve for Telit
and its licensors certain exclusive rights for copyrighted material, including the exclusive right to
copy, reproduce in any form, distribute and make derivative works of the copyrighted material.
Accordingly, any copyrighted material of Telit and its licensors contained herein or in the Telit
products described in this instruction manual may not be copied, reproduced, distributed, merged
or modified in any manner without the express written permission of Telit. Furthermore, the
purchase of Telit products shall not be deemed to grant either directly or by implication, estoppel,
or otherwise, any license under the copyrights, patents or patent applications of Telit, as arises by
operation of law in the sale of a product.
COMPUTER SOFTWARE COPYRIGHTS

The Telit and 3rd Party supplied Software (SW) products described in this instruction manual may
include copyrighted Telit and other 3rd Party supplied computer programs stored in semiconductor
memories or other media. Laws in the Italy and other countries preserve for Telit and other 3rd
Party supplied SW certain exclusive rights for copyrighted computer programs, including the
exclusive right to copy or reproduce in any form the copyrighted computer program. Accordingly,
any copyrighted Telit or other 3rd Party supplied SW computer programs contained in the Telit
products described in this instruction manual may not be copied (reverse engineered) or
reproduced in any manner without the express written permission of Telit or the 3rd Party SW
supplier. Furthermore, the purchase of Telit products shall not be deemed to grant either directly
or by implication, estoppel, or otherwise, any license under the copyrights, patents or patent
applications of Telit or other 3rd Party supplied SW, except for the normal non-exclusive, royalty
free license to use that arises by operation of law in the sale of a product.
1VV0301482 Rev. 5.0 Page 2 of 171 2018-01-10

USAGE AND DISCLOSURE RESTRICTIONS

I. License Agreements
The software described in this document is the property of Telit and its licensors. It is furnished by
express license agreement only and may be used only in accordance with the terms of such an
agreement.
II. Copyrighted Materials
Software and documentation are copyrighted materials. Making unauthorized copies is prohibited
by law. No part of the software or documentation may be reproduced, transmitted, transcribed,
stored in a retrieval system, or translated into any language or computer language, in any form or
by any means, without prior written permission of Telit
III. High Risk Materials
Components, units, or third-party products used in the product described herein are NOT
fault-tolerant and are NOT designed, manufactured, or intended for use as on-line control
equipment in the following hazardous environments requiring fail-safe controls: the operation of
Nuclear Facilities, Aircraft Navigation or Aircraft Communication Systems, Air Traffic Control, Life
Support, or Weapons Systems (High Risk Activities"). Telit and its supplier(s) specifically disclaim
any expressed or implied warranty of fitness for such High Risk Activities.
IV. Trademarks
TELIT and the Stylized T Logo are registered in Trademark Office. All other product or service
names are the property of their respective owners.
V. Third Party Rights
The software may include Third Party Right software. In this case you agree to comply with all
terms and conditions imposed on you in respect of such separate software. In addition to Third
Party Terms, the disclaimer of warranty and limitation of liability provisions in this License shall
apply to the Third Party Right software.
TELIT HEREBY DISCLAIMS ANY AND ALL WARRANTIES EXPRESS OR IMPLIED FROM
ANY THIRD PARTIES REGARDING ANY SEPARATE FILES, ANY THIRD PARTY MATERIALS
INCLUDED IN THE SOFTWARE, ANY THIRD PARTY MATERIALS FROM WHICH THE
SOFTWARE IS DERIVED (COLLECTIVELY “OTHER CODE”), AND THE USE OF ANY OR ALL
THE OTHER CODE IN CONNECTION WITH THE SOFTWARE, INCLUDING (WITHOUT
LIMITATION) ANY WARRANTIES OF SATISFACTORY QUALITY OR FITNESS FOR A
PARTICULAR PURPOSE.
NO THIRD PARTY LICENSORS OF OTHER CODE SHALL HAVE ANY LIABILITY FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
WHETHER MADE UNDER CONTRACT, TORT OR OTHER LEGAL THEORY, ARISING IN ANY
WAY OUT OF THE USE OR DISTRIBUTION OF THE OTHER CODE OR THE EXERCISE OF
ANY RIGHTS GRANTED UNDER EITHER OR BOTH THIS LICENSE AND THE LEGAL TERMS
APPLICABLE TO ANY SEPARATE FILES, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
DAMAGES.
1VV0301482 Rev. 5.0 Page 3 of 171 2018-01-10

APPLICABILITY TABLE
PRODUCT
GS2K based Modules
Software Release
5.5.0
Note: The features described in the present document are provided by the products equipped with
the software versions equal or higher than the versions shown in the table. See also the
Revision History chapter.
1VV0301482 Rev. 5.0 Page 4 of 171 2018-01-10

Table of Contents
Chapter 1 GS2011M Overview ........................................................................................................ 19

1.1 Product Overview ..................................................................................................................19
1.2 GS2011M Module Product Features .....................................................................................19
Chapter 2 GS2011M Architecture .................................................................................................... 23

2.1 Architecture Description ........................................................................................................23
2.2 Wireless LAN and System Control Subsystem .....................................................................25
2.2.1 Onboard Antenna / RF Port / Radio .............................................................................25
2.2.1.1 802.11 MAC .........................................................................................................25
2.2.1.2 802.11 PHY .........................................................................................................26
2.2.1.3 RF/Analog ............................................................................................................27
2.2.2 Network Services Subsystem ......................................................................................27
2.2.2.1 APP CPU .............................................................................................................27
2.2.2.2 Crypto Engine ......................................................................................................27
2.2.3 Memory Subsystem .....................................................................................................27
2.2.3.1 SRAM ..................................................................................................................27
2.2.3.2 ROM ....................................................................................................................28
2.2.3.3 OTP ROM ............................................................................................................28
2.2.3.4 Flash Interface .....................................................................................................28
2.2.4 Clocks ..........................................................................................................................28
2.2.5 Real Time Clock (RTC) Overview ................................................................................29
2.2.5.1 RTC Main Features .............................................................................................29
2.2.5.2 Real Time Clock Counter .....................................................................................31
2.2.5.3 RTC I/O ................................................................................................................31
2.2.5.4 DC_DC_CNTL .....................................................................................................31
2.2.6 GS2011M Peripherals ..................................................................................................31
2.2.6.1 SDIO Interface .....................................................................................................31
2.2.6.2 SPI Interface ........................................................................................................32
2.2.6.3 UART Interface ....................................................................................................32
2.2.6.4 I2C Interface ........................................................................................................33
2.2.6.5 GPIO ....................................................................................................................33
2.2.6.6 ADC .....................................................................................................................33
2.2.6.7 PWM ....................................................................................................................33
2.2.7 System States ..............................................................................................................35
2.2.8 Power Supply ...............................................................................................................38
Chapter 3 Pin-out and Signal Description ........................................................................................ 41

3.1 GS2011Mxx Device Pin-out ..................................................................................................41
3.1.1 GS2011Mxx Module Pins Description ..........................................................................42
Table 7 Errata ..................................................................................................................46
3.1.2 GS2011M Pin MUX Function .......................................................................................47
3.1.3 GS2011M Program and Code Restore Options ...........................................................49
Chapter 4 Electrical Characteristics ................................................................................................. 51

4.1 Absolute Maximum Ratings ...................................................................................................51
4.2 Operating Conditions .............................................................................................................52
4.3 Internal 1.8V Regulator ..........................................................................................................52
4.4 I/O DC Specifications ............................................................................................................53
4.4.1 I/O Digital Specifications (Tri-State) Pin Types 4mA, 12mA, and 16mA ......................53
1VV0301482 Rev. 5.0 Page 5 of 69 2018-01-10

4.4.1.1 I/O Digital Specifications for VDDIO=2.7V to 3.6V ..............................................53

4.4.2 RTC I/O Specifications .................................................................................................54
4.5 Power Consumption ..............................................................................................................55
4.6 802.11 Radio Parameters ......................................................................................................56
4.7 ADC Parameters ...................................................................................................................58
Chapter 5 Package and Layout Guidelines ..................................................................................... 61

5.1 GS2011Mxx Recommended PCB Footprint and Dimensions ...............................................61
5.1.1 Surface Mount Assembly .............................................................................................63
1VV0301482 Rev. 5.0 Page 6 of 69 2018-01-10

About This Manual
This manual describes the GS2011M Low Power module hardware specification.
Refer to the following sections:
• Revision History, page 8
• Audience, page 8
• Standards, page 8
• Certifications, page 8
• Documentation Conventions, page 9
• Documentation, page 12
• Contact Information, Support, page 14
• Returning Products to GainSpan, page 15
• Accessing the GainSpan Portal, page 16
• Ordering Information, page 16
1VV0301482 Rev. 5.0 Page 7 of 69 2018-01-10

Revision History
This version of the GainSpan GS2011M Low Power Wi-Fi Data Sheet contains the
following new information listed in Table 1, page 8.
Table 1 Revision History
Version Date Remarks
Removed reference to external PA, LNA, and control of external RF Switch
(GS2011MIE only). See 2.2.1.2 802.11 PHY, page 26.
Added Errata notification to the Pin Signal and Pin MUX tables regarding
SPI0_OUT and SPI1_OUT signals. See Table 7, page 42 and Table 8,
1.0 June 2015 page 47.
Updated Power Consumption information in Table 15, page 55.
Updated 802.11 Radio Parameters Transmit/Receive Specifications for
1Mbps and 54Mbps in Table 16, page 56.
Updated 802.11 Radio Parameters Output power (average) and Receive
Sensitivity at antenna port in Table 16, page 56.
2.0 February 2016
Updated the Note under 5.1 GS2011Mxx Recommended PCB Footprint and
Dimensions
3.0 July 2016 Updated 802.11 Radio Parameters RF Frequency Range in Table 16, page 56
Corrected the System State - WLAN Continuous Transmit from 16dbm to
4.0 November 2017
15dbm see Table 15, page 55
Updated Output power (average) for GS2011MIE and GS2011MIZ in Table
5.0 January 2018
16, page 56
Audience
This manual is designed to help system designers build low power, cost effective, flexible
platforms to add Wi-Fi connectivity for embedded device applications using the GainSpan
GS2011M based module.
Standards
The standards that are supported by the GainSpan modules are IEEE 802.11 b/g/n.
Certifications
GainSpan GS2011M Low Power Wi-Fi Module has Certification Compliance for the
following:
1VV0301482 Rev. 5.0 Page 8 of 69 2018-01-10

Table 2 Certification Compliance

Category Certification
Radio regulatory Certificates FCC, IC, TELEC, RED
WPS 2.0, WMM, WMM-PS, WPA and WPA2 Enterprise, WPA and WPA2
Wi-Fi Alliance Certificates
Personal.
Hereby, GainSpan Corporation declares that the radio equipment type GS2011MIZ &
GS2011MIE is in compliance with Radio Equipment Directive (RED) 2014/53/EU. The
Declaration of Conformity (DoC) for the same is available at URL:
https://www.telit.com/red/
Documentation Conventions
This manual uses the following text and syntax conventions:
– Special text fonts represent particular commands, keywords, variables, or window
sessions
– Color text indicates cross-reference hyper links to supplemental information
– Command notation indicates commands, subcommands, or command elements
Table 3, page 9, describes the text conventions used in this manual for software procedures
that are explained using the AT command line interface.
Table 3 Document Text Conventions
Convention Type Description

This monospaced font represents command strings entered on a
command syntax command line and sample source code.
monospaced font
AT XXXX
Proportional font Gives specific details about a parameter.

description <Data> DATA
UPPERCASE Indicates user input. Enter a value according to the descriptions that
follow. Each uppercased token expands into one or more other token.
Variable parameter
lowercase Indicates keywords. Enter values exactly as shown in the command

description.
Keyword parameter
Enclose optional parameters. Choose none; or select one or more an

[] unlimited number of times each. Do not enter brackets as part of any
command.
Square brackets
[parm1|parm2|parm3]
1VV0301482 Rev. 5.0 Page 9 of 69 2018-01-10

Table 3 Document Text Conventions (Continued)
Convention Type Description

? Used with the square brackets to limit the immediately following token
Question mark to one occurrence.
Each escape sequence <ESC> starts with the ASCII character 27 (0x1B).
<ESC> This is equivalent to the Escape key.
Escape sequence
<ESC>C
<CR>
Each command is terminated by a carriage return.
Carriage return
<LF>
Each command is terminated by a line feed.
Line feed
<CR> <LF>
Each response is started with a carriage return and line feed with some
Carriage return
exceptions.
Line feed
Enclose a numeric range, endpoints inclusive. Do not enter angle
<> brackets as part of any command.
Angle brackets
<SSID>
Separates the variable from explanatory text. Is entered as part of the
= command.
Equal sign
PROCESSID = <CID>
Allows the repetition of the element that immediately follows it multiple
. times. Do not enter as part of the command.
dot (period)
.AA:NN can be expanded to 1:01 1:02 1:03.
A.B.C.D IPv4-style address.

IP address 10.0.11.123
IPv6-style address.
X:X::X:X
3ffe:506::1
IPv6 IP address Where the : : represents all 0x for those address components not
explicitly given.
Indicates user input of any string, including spaces. No other parameters
LINE may be entered after input for this token.
End-to-line input token
string of words
WORD Indicates user input of any contiguous string (excluding spaces).

Single token singlewordnospaces
1VV0301482 Rev. 5.0 Page 10 of 69 2018-01-10

Table 4, page 11, describes the symbol conventions used in this manual for notification and
important instructions.
Table 4 Symbol Conventions
Icon Type Description

Provides helpful suggestions needed in understanding
Note a feature or references to material not available in the
manual.
Alerts you of potential damage to a program, device,

Alert
or system or the loss of data or service.
Cautions you about a situation that could result in

Caution
minor or moderate bodily injury if not avoided.
Warns you of a potential situation that could result in

Warning
death or serious bodily injury if not avoided.
Electro-Static Discharge Notifies you to take proper grounding precautions

(ESD) before handling a product.
1VV0301482 Rev. 5.0 Page 11 of 69 2018-01-10

Documentation
The GainSpan documentation suite listed in Table 5, page 12 includes the part number,
documentation name, and a description of the document. The documents are available from
the GainSpan Portal. Refer to , page 15 for details.
Table 5 Documentation List
Part Number Document Title Description
Provides an easy to follow guide on
GS2011M Evaluation Board Quick how to unpack and setup GainSpan
1VV0301415
Start Guide GS2000 based module kit for the
GS2011M module.
Provides users steps to program the
on-board Flash on the GainSpan
GS2000 based modules using DOS or
GS2K Module Programming User
1VV0301437 Graphical User Interface utility
Guide
provided by GainSpan. The user guide
uses the evaluation boards as a
reference example board.
Provides a complete listing of AT serial
commands, including configuration
GS2011M Serial-to-Wi-Fi Adapter
1VV0301463 examples for initiating, maintaining,
Command Reference Guide
and evaluating GainSpan Wi-Fi
GS2011M series modules.
commands, including configuration
GS2100M Serial-to-Wi-Fi Adapter
1VV0301463 examples for initiating, maintaining,
Command Reference Guide
and evaluating GainSpan Wi-Fi
GS2100M series modules.
Provides instructions on how to setup
and use the GS2000 based module
GS2K Module Evaluation Board
1VV0301435 evaluation board along with component
Hardware User Guide
description, jumper settings, board
specifications, and pinouts.
Provides information to help Wi-Fi
GS2011M Low Power Wi-Fi Module system designers to build systems using
1VV0301482
Hardware User Guide GainSpan GS2011M module and
develop wireless applications.
1VV0301482 Rev. 5.0 Page 12 of 69 2018-01-10

Table 5 Documentation List (Continued)

Part Number Document Title Description
GainSpan GS2100M Low Power system designers to build systems using
GS2100M-DS-001212
Wi-Fi Module Data Sheet GainSpan GS2100M module and
GS2011MxxS Low Power Wi-Fi system designers to build systems using
1VV0301486
Module Hardware User Guide GainSpan GS2011MxxS module and
GS2011M IP-to-Wi-Fi Adapter commands, including configuration
1VV0301464 Application Command Reference examples for initiating, maintaining,
Guide and evaluation GainSpan IP-to-Wi-Fi
GS2000 based modules.
1VV0301482 Rev. 5.0 Page 13 of 69 2018-01-10

Documentation Feedback
We encourage you to provide feedback, comments, and suggestions so that we can improve
the documentation. You can send your comments by logging into Telit Support Portal. If
you are using e-mail, be sure to include the following information with your comments:
– Document name
– URL or page number
– Hardware release version (if applicable)
– Software release version (if applicable)
Contact Information, Support

For general contact, technical support services, technical questions and to report
documentation errors contact Telit Technical Support at:
TS-SRD@telit.com
We recommend adding “Wi-Fi” in subject of the email. For example, the subject of email
can be “Wi-Fi: Your actual issue or question in brief” like “Wi-Fi: SPI Driver Issue”.
Also, in description of your email, please provide details about the issue, product and
module including software firmware version, module version and type, application being
used, customizations done to application, use case, issue frequency, and ability to recreate
it among other things wherever applicable.
Alternatively, for more Technical Support information or assistance, perform the following
steps:
1. Visit http://www.telit.com, go to Products> Wi-Fi and Blue-tooth, then scroll down to
the Telit Wi- Fi Portal.
2. Click Access the Portal Here icon which will direct you to the GainSpan portal
http://www.gainspan/secure/login.com
1. Log in with your customer Email and Password.
2. Select the Location.
3. Select Q&A tab.
4. Select Ask a New Question.
5. Enter your technical support question, product information, and a brief description.
For detailed information about where you can buy the Telit modules or for
recommendations on accessories and components visit:
http://www.telit.com
Our aim is to make this guide as helpful as possible. Keep us informed of your comments
and suggestions for improvements. Telit appreciates feedback from the users of our
information.
1VV0301482 Rev. 5.0 Page 14 of 69 2018-01-10

Returning Products to GainSpan

If a problem cannot be resolved by GainSpan technical support, a Return Material
Authorization (RMA) is issued. This number is used to track the returned material at the
factory and to return repaired or new components to the customer as needed.
NOTE: Do not return any components to GainSpan Corporation unless you have
first obtained an RMA number. GainSpan reserves the right to refuse shipments
that do not have an RMA. Refused shipments will be returned to the customer by
collect freight.
To return a hardware component:

1. Determine the part number and serial number of the component.
2. Obtain an RMA number from Sales/Distributor Representative.
3. Provide the following information in an e-mail or during the telephone call:
– Part number and serial number of component
– Your name, organization name, telephone number, and fax number
– Description of the failure
4. The support representative validates your request and issues an RMA number for
return of the components.
5. Pack the component for shipment.
Guidelines for Packing Components for Shipment

To pack and ship individual components:
– When you return components, make sure they are adequately protected with
packing materials and packed so that the pieces are prevented from moving
around inside the carton.
– Use the original shipping materials if they are available.
– Place individual components in electrostatic bags.
– Write the RMA number on the exterior of the box to ensure proper tracking.
CAUTION! Do not stack any of the components.
1VV0301482 Rev. 5.0 Page 15 of 69 2018-01-10

Accessing the GainSpan Portal

To find the latest version of GainSpan documentation supporting the GainSpan product
release you are interested in, you can search the GainSpan Portal website by performing the
following steps:
NOTE: You must first contact GainSpan to set up an account, and obtain a
customer user name and password before you can access the GainSpan Portal.
1. Visit http://www.telit.com, go to Products> Wi-Fi and Blue-tooth, then scroll down

the Telit Wi- Fi Portal.
2. Click Access the Portal Here icon which will direct you to the GainSpan portal
http://www.gainspan/secure/login.com
3. Log in using your customer Email and Password.
4. Click the Getting Started tab to view a Quick Start tutorial on how to use various
features within the GainSpan Portal.
5. Click the Agreements tab to download and upload the SLA for ADK and SDK
respectively.
6. Click on the Documents tab to search, download, and print GainSpan product
documentation.
7. Click the Software tab to search and download the latest software versions.
8. Click the Kits Purchased tab to view customer account history.
9. Click the Legal Documents tab to view GainSpan Non-Disclosure Agreement
(NDA).
10. Click the Certifications tab to view GainSpan certifications.
Ordering Information
To order GainSpan’s GS2011Mxx low power module contact a GainSpan Sales/Distributor
Representative. Table 6, page 16 lists the GainSpan device information.
Table 6 GS2011Mxx Ordering Information

Device Description Ordering Number Revision
Low power module with on-board antenna GS2011MIZ 3.3
Low power module with external antenna GS2011MIE 3.3
1VV0301482 Rev. 5.0 Page 16 of 69 2018-01-10

NOTE: Modules ship with test code ONLY. Designers must first program the
modules with a released firmware version. Designers should bring out GPIO27
pin (option to pull this pin to VDDIO during reset or power-on) and UART0 or SPI0
pins to enable programming of firmware into the module. For details refer to the
Programming the GainSpan Modules document.
1VV0301482 Rev. 5.0 Page 17 of 69 2018-01-10

1VV0301482 Rev. 5.0 Page 18 of 69 2018-01-10

Chapter 1 GS2011M Overview
This chapter describes the GainSpan® GS2011M low power module hardware specification
overview.
• Product Overview, page 19
• GS2011M Module Product Features, page 19
1.1 Product Overview

The GS2011M low power based module provides cost effective, low power, and flexible
platform to add Wi-Fi connectivity for embedded devices for a variety of applications, such
as wireless sensors and thermostats. It uses GS2000 SoC, which combines ARM® Cortex
M3-based processors with a 802.11b/g/n Radio, MAC, security, and PHY functions, RTC
and SRAM, up to 4 MB FLASH, and on board and off module certified antenna options.
The module provides a Wi-Fi and regulatory certified IEEE 802.11b/g/n radio with
concurrent network processing services for variety of applications, while leverage existing
802.11 wireless network infrastructures.
1.2 GS2011M Module Product Features

• Family of modules with different antenna and output power options:
• GS2011MIx 22.8mm (0.90in) x 32.5 mm (1.28in) x 3.63mm (0.143in) 48-pin
PCB Surface Mount Package. Two SKU’s are:
– GS2011MIZ (on-board antenna)
– GS2011MIE (external antenna)
• The two SKUs are pin to pin compatible, and the user has to account only for
power consumption, and on-board antenna keep out (if used) to accommodate
“one size fits all” for various end applications.
• Simple API for embedded markets covering a large range of applications
• Fully compliant with IEEE 802.11b/g/n and regulatory domains:
– 802.11n: 1x1 single stream, 20 MHz channels, 400/800ns GI, MCS0 – 7
– Data rates of 7.2, 14.4, 21.7, 28.9, 43.3, 57.8, 65.0, 72.2 Mbps
– 802.11g: OFDM modulation for data rates of 6, 9, 12, 18, 24, 36, 48 and 54
Mb/s
– 802.11b: CCK modulation rates of 5.5 and 11 Mbps; DSSS modulation for
data rate of 1 and 2 Mbps
1VV0301482 Rev. 5.0 Page 19 of 69 2018-01-10

• Wi-Fi Solution:
• Wi-Fi security (802.11i)
– WPA™ - Enterprise, Personal
– WPA2™ - Enterprise, Personal
– Vendor EAP Type(s):
– EAP-TTLS/MSCHAPv2, PEAPv0/EAP-MSCHAPv2,
PEAPv1/EAP-GTC, EAP-FAST, EAP-TLS
• Hardware-accelerated high-throughput AES and RC4 encryption/decryption
engines for WEP, WPA/WPA2 (AES-CCMP and TKIP).
• Additional dedicated encryption HW engine to support higher layer encryption
such as IPSEC (IPv4 and IPv6), SSL/TLS, HTTPs, PKI, digital certificates, RNG,
etc.
• Dual ARM Cortex M3 Processor Platform:
• 1st Cortex M3 processor (WLAN CPU) for WLAN software
– Implements 802.11b/g/n WLAN protocol services
– 320 KB dedicated SRAM
– 512 KB dedicated ROM
• 2nd Cortex M3 processor (APP CPU) for networking software
– Implements networking protocol stacks and user application software
– 384 KB dedicated SRAM
– 512 KB dedicated ROM
• 64KB shared dual ported SRAM for inter-processor communications
• 320KB assignable (under SW control) SRAM
• Support processor clock frequencies for both CPU of up to 120MHz
• Based on Advanced Microprocessor Bus Architecture (AMBA) system
– AMBA Multilayer High-Speed Bus (AHB)
– AMBA Peripheral Bus (APB)
• On-module controller
– Manages read/write/program/erase operations to the 4 MB flash memory
device on the module
– Supports higher performance QUAD SPI protocol operations
– Active power management
1VV0301482 Rev. 5.0 Page 20 of 69 2018-01-10

• Interfaces:
• SDIO:
– Compliant to SDIO v2.0 specification
– Interface clock frequency up to 40 MHz
NOTE: Tested with current test platform up to 33 MHz.
– Data transfer modes: 4-bit, 1-bit SDIO, SPI

– Device mode only (slave)
• SPI:
– Two (2) general-purpose SPI interfaces (each configurable independently as
master or slave)
– The SPI pins are muxed with other functions such as GPIO
– Supports clock rates of up to 30 MHz (master mode) and up to 10 MHz (slave
mode)
– Protocols supported include: Motorola SPI, TI Synchronous Serial Protocol
(SSP) and National Semiconductor Microwire
– Supports SPI mode 0 thru 3 (software configurable)
• UART:
– Two (2) multi-purpose UART interfaces operating in full-duplex mode
– 16450/16550 compatible
– Optional support for flow control using RTS/CTS signaling for high data
transfer rates
– Standard baud rate from 9600 bps up to 921.6 kbps (additional support for
higher non-standard rates using baud rates up to 7.5 MHz
• GPIOs:
– Up to 27 configurable general purpose I/O
• Single 3.3V supply option
• Three (3) PWM output
• I2C master/slave interface
• Two 12-bit ADC channels, sample rate from 10 kS/s to 2 MS/s
• Three (3) RTC I/O that can be configured as:
– Up to three alarm inputs to asynchronously awaken the chip.
– Support of up to two control outputs for power supply and sensors.
• Embedded RTC (Real Time Clock) can run directly from battery.
1VV0301482 Rev. 5.0 Page 21 of 69 2018-01-10

• Power supply monitoring capability.

• Low-power mode operations
– Standby, Sleep, and Deep Sleep
• FCC/IC/ETSI/TELEC/Wi-Fi Certification
1VV0301482 Rev. 5.0 Page 22 of 69 2018-01-10

Chapter 2 GS2011M Architecture
This chapter describes the GainSpan® GS2011M Low Power module architecture.
• Architecture Description, page 23
• Wireless LAN and System Control Subsystem, page 25
2.1 Architecture Description

The GainSpan GS2011M module (see Figure 1, page 24) is based on a highly integrated
GS2000 ultra low power Wi-Fi System-on-Chip (SoC) that contains the following:
• The GS2000 SoC contains two ARM Cortex M3 CPUs, a compatible 802.11
radio, security, on-chip memory, and variety of peripherals in a single package.
– One ARM core is dedicated to Networking Subsystems, and the other
dedicated to Wireless LAN Subsystems.
– The module carries an 802.11/g/n radio with on board 32KHz & 40 MHz
crystal circuitries, RF, and on-board antenna or external antenna options.
• On module 4 Mega Byte FLASH device that contains the user embedded
applications and data such as web pages.
• Variety of interfaces are available such as two UART blocks using only two data
lines per port with optional hardware flow controls, two SPI blocks (one SDIO is
shared function with one for the SPI interfaces), I2C with Master or slave
operation, JTAG port, low-power 12-bit ADC capable of running at up to 2M
samples/Sec., GPIO’s, and LED Drivers/GPIO with 16mA capabilities.
• GS2011Mxx has a VRTC pin that is generally connected to always available
power source such as battery or line power. This provides power to the Real Time
Clock (RTC) block on the SoC. The module contains a 1.8V regulator that is
turned on/off when going into the lowest power mode, i.e., standby mode. The
module also has VDDIO power supply input to provide the logic signal level for
the I/O pins. VDDIO must turn on/off with the VIN_3V3 power.
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Figure 1 GS2011M Block Diagram
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2.2 Wireless LAN and System Control Subsystem

The WLAN CPU subsystem consists of the WLAN CPU, its ROM, RAM, 802.11b/g/n
MAC/PHY, and peripherals. This CPU is intended primarily to implement the 802.11 MAC
protocols. The CPU system has GPIO, Timer, and Watchdog for general use. A UART is
provided as a debug interface. A SPI interface is provided for specific application needs.
The WLAN CPU can access the RTC registers through an asynchronous AHB bridge.
WLAN CPU has only Flash read access to the on-board flash memory. The WLAN
subsystem interacts with the APP subsystem through a set of mailboxes and shared
dual–port memories.
The CPUs provide debug access through a JTAG/serial port. For GS2011M module, the
complete JTAG port is brought out for both CPUs. The CPUs also include code and data
trace and watch point logic to assist in-system debugging of SW.
The WLAN subsystem includes an integrated power amplifier, and provides management
capabilities for an optional external power amplifier. In addition, it contains hardware
support for AES-CCMP encryption (for WPA2) and RC4 encryption (for WEP & WPA
TKIP) encryption/decryption.
2.2.1 Onboard Antenna / RF Port / Radio

The GS2011Mxx modules have fully integrated RF frequency synthesizer, reference clock,
and PA. Both TX and RX chain in the module incorporate internal power control loops. The
GS2011Mxx modules also incorporate an on board antenna option or an external antenna
connector.
2.2.1.1 802.11 MAC

The 802.11 MAC implements all time critical functionality of the 802.11b/g/n protocols. It
works in conjunction with the MAC SW running on the CPU to implement the complete
MAC functionality. It interfaces with the PHY to initiate transmit/receive and CCA. The
PHY registers are programmed indirectly through the MAC block. The MAC interfaces to
the system bus and uses DMA to fetch transmit packet data and save receive packet data.
The MAC SW exchanges packet data with the HW though packet descriptors and pointers.
Key Features
• Compliant to IEEE 802.11 (2012)

• Compliant to IEEE 802.11b/g/n (11n – 2009)
• Long and short preamble generation on frame-by-frame basis for 11b frames
• Transmit rate adaptation
• Transmit power control
• Frame aggregation (AMPDU, AMSDU)
• Block ACK (Immediate, Compressed)
• RTS/CTS, CTS-to-self frame sequences and SIFS
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• Client and AP modes support

• Encryption support including: AES-CCMP, legacy WPA-TKIP, legacy WEP
ciphers and key management
• Wi-Fi Protected Setup 2.0 (WPS2.0) including both PIN and push button options
• 802.11e based QoS (including WMM, WMM-PS)
• Wi-Fi Direct with concurrent mode, including Device/Service Discovery, Group
Formation/Invitation, Client Power Save, WPS-PIN/Push Button
2.2.1.2 802.11 PHY

The 802.11 PHY implements all the standard required functionality and GainSpan specific
functionality for 802.11b/g/n protocols. It also implements the Radar detection
functionality to support 802.11h. The PHY implements the complete baseband Tx and Rx
pipeline. It interfaces with the MAC to perform transmit and receive operations. It
interfaces directly to the ADC and DAC. The PHY implements the Transmit power control,
receive Automatic Gain Control and other RF control signals to enable transmit and
receive. The PHY also computes the CCA for MAC use.
Key Features
• Compliant to 2.4GHz IEEE 802.11b/g/n (11n – 2009)

• Support 802.11g/n OFDM with BPSK, QPSK, 16-QAM and 64-QAM; 802.11b
with BPSK, QPSK and CCK
• Support for following data rates:
– 802.11n (20MHz): MCS0 - 7; 7.2, 14.4, 21.7, 28.9, 43.3, 57.8, 65.0, 72.2
Mbps
– 802.11g: 6, 9, 12, 18, 24, 36, 48, 54 Mbps
– 802.11b: 1, 2, 5.5, 11 Mbps
• Support Full (800ns) & Half (400ns) Guard Interval (GI) modes (SGI and LGI)
• Support Space time block coding (STBC) for receive direction
• Complete front-end radio integration including PA, LNA and RF Switch
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2.2.1.3 RF/Analog
The RF/Analog is a single RF transceiver for IEEE 802.11b/g/n (WLAN). The RF Interface
block provides the access to the RF and analog control and status to the CPU. This block is
accessible only from the WLAN CPU. It implements registers to write static control words.
It provides read only register interface to read static status. It generates the dynamic control
signals required for TX and RX based on the PHY signals. The AGC look up table to map
the gain to RF gain control word is implemented in this block.
2.2.2 Network Services Subsystem
2.2.2.1 APP CPU

The Network services subsystem consists of an APP CPU which is based on an ARM
CORTEX M3 core. It incorporates an AHB interface and a JTAG debug interface. The
network RTOS, network stack, and customer application code run on this CPU.
2.2.2.2 Crypto Engine

The Network services subsystem contains a separate hardware crypto engine that provides
a flexible framework for accelerating the cryptographic functions for packet processing
protocols. The crypto engine has the raw generic interface for cipher and hash/MAC
functions such as AES, DES, SHA, and RC4. It also includes two optional engines to
provide further offload; the PKA and RNG modules. These provide additional methods for
public key acceleration functions and random number generation. The engine includes a
DMA engine that allows the engine to perform cryptographic operation on data packets in
the system memory without any CPU intervention.
2.2.3 Memory Subsystem

The GS2011M module contains several memory blocks.
2.2.3.1 SRAM
The system memory is built with single port and dual port memories. Most of the memory
consists of single port memory. A 64KB dual port memory is used for exchange of data
between the two CPU domains. All the memories are connected to the system bus matrix
in each CPU subsystem. All masters can access any of the memory within the subsystem.
The APP subsystem has 384KB of dedicated SRAM for program and data use.
The WLAN subsystem has 320KB of dedicated SRAM for program and data use.
These memories are divided into banks of 64KB each. The bank structure allows different
masters to access different banks simultaneously through the bus matrix without incurring
any stall. Code from the external Flash is loaded into the SRAM for execution by each
CPU.
In addition, a static shared SRAM is provided. This consists of five 64KB memory blocks.
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At any time, any of these memory blocks can be assigned to one of the CPU subsystem.
These should be set up by the APP CPU SW at initialization time. The assignment is not
intended to change during operation and there is no HW interlock to avoid switching in the
middle of a memory transaction. The assignment to the WLAN CPU should be done
starting from the highest block number going down to lowest block number. This result in
the shared memory appearing as a single bank for each CPU subsystem, independent of the
number of blocks assigned. The shared memory is mapped such that the SRAM space is
continuous from the dedicated SRAM to shared SRAM.
A 64KB dual port memory is used for exchange of data between the two CPU domains.
Each CPU subsystem can read or write to this memory using an independent memory port.
SW must manage the memory access to avoid simultaneous write to the same memory
location. The dual port memory appears as a single bank to each CPU subsystem.
2.2.3.2 ROM
ROM is provided in each CPU subsystem to provide the boot code and other functional
code that are not expected to change regularly. Each CPU has 512KB of ROM.
2.2.3.3 OTP ROM
The GS2000 device includes a 64Kbit OTP ROM used for storing MAC ID and other
information such as security keys etc. The APP and WLAN subsystem each contain
32Kbits (4Kbytes) of OTP memory.
2.2.3.4 Flash Interface

The GS2000 SoC has only internal ROM and RAM for code storage. There is no embedded
Flash memory on the SoC. Any ROM patch code and new application code must reside in
the on-module Flash device of the GS2011M module. Flash access from the two CPUs are
independent. The APP CPU is considered the system Master and the code running on this
CPU is required to initialize the overall chip and common interfaces. WLAN CPU access
to the Flash is restricted to read DMA. Any write to the Flash from the WLAN CPU must
be done through the APP CPU. The operational parameters of the DMA accesses are set by
the APP CPU at system startup. The Flash code is transferred to internal RAM before
execution.
2.2.4 Clocks
The GS2011M includes four basic clock sources:
– Low power 32KHz clock (see 2.2.5 Real Time Clock (RTC) Overview, page 29)
– 40MHz Xtal Oscillator
– PLL to generate the internal 120MHz (CPU) and 80MHz (PHY) clocks from the
40MHz Xtal.
– High speed RC oscillator 80MHz
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Intermediate modes of operation, in which high speed clocks are active but some modules
are inactive, are obtained by gating the clock signal to different subsystems. The clock
control blocks within the device are responsible for generation, selection and gating of the
clocked used in the module to reduce power consumption in various power states.
2.2.5 Real Time Clock (RTC) Overview

To provide global time (and date) to the system, the GS2011Mxx module is equipped with
a low-power Real Time Clock (RTC). The RTC is the always on block that manages the
Standby state. This block is powered from a supply pin (VRTC) separate from the digital
core and may be powered directly from a battery. The RTC implementation supports a
voltage range of 1.6V to 3.6V.
2.2.5.1 RTC Main Features

• One 48-bit primary RTC counter as the primary reference for all timing events and
standby awake management
• 4 programmable IO pins with specific default behavior. These pins are in the RTC
IO domain.
– One (DC_DC_CNTL) is setup as output pin to control external regulator
– Three others (RTC_IO) which can be programmed to be either
– Maximum of two wakeup counters to generate periodic output (32-bit)
– Alarm inputs to wake up the GS2011M module from its sleep states
(deep-sleep/standby)
• Startup control counters with HW and SW override registers
• Power-on-reset control with brown-out detector
• RTC registers to hold RTC and wakeup control bits while the core domain is off
• 1Kbyte latch based memory (1.6-3.6V capable)
• 16KB of SRAM memory, divided into 4 equal blocks (1.2V capable)
• uLDO to supply the SRAM memory
• RTC logic is 1.6-3.6v capable
• 32 KHz RC oscillator
• 32768Hz crystal oscillator
• APB interface for CPU access
• Interrupts to CPU
An overview of RTC block diagram is shown in Figure 2, page 30. The RTC contains a
low-power 32.768KHz RC oscillator which provides fast startup at first application of
RTC power. It also supports an optional 32.768KHz crystal oscillator which can be
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substituted for the RC oscillator under software control. In normal operation the RTC is
always powered up, even in the Power up state.
The dc_dc_cntl programmable counter is 48-bits and provides up to 272 years worth of
standby duration.
For the other RTC_IO pins, the programmable embedded counters (32-bit) are provided to
enable periodic wake-up of the remainder of the external system, and provide a 1.5 days
max period. The RTC_IO pins can be configured as inputs (ALARMS) or output (WAKE
UP) pins.
The RTC includes a Power-On Reset (POR) circuit, to eliminate the need for an external
component. The RTC contains low-leakage non-volatile (battery-powered) RAM, to enable
storage of data that needs to be preserved. It also includes a brown-out detector that can be
disabled by SW.
Total current consumption of the RTC is typically less than 5 μA with 1Kbyte of data
storage, using the 32.768 kHz oscillator.
Figure 2 RTC Interface Diagram
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2.2.5.2 Real Time Clock Counter

The Real Time Counter features:
– 48-bit length (with absolute duration of 272 years).
– Low-power design.
This counter is automatically reset by power-on-reset.
This counter wraps around (returns to “all-0” once it has reached the highest possible
“all-1” value).
2.2.5.3 RTC I/O

There are three (3) RTC I/O (0,1,2) that can be used to control external devices, such as
sensors or wake up the module based on external events or devices.
2.2.5.4 DC_DC_CNTL
During RTC Power-on-Reset (e.g. when the battery is first connected), the dc_dc_cntl pin
is held low; it goes high to indicate completion of RTC power-on-reset. This pin can be
used as an enable into an external device such as voltage regulator. The dc_dc_cntl also is
held low when module is in standby and goes high to indicate wake up from standby.
2.2.6 GS2011M Peripherals
2.2.6.1 SDIO Interface

The SDIO interface is a full / high speed SDIO device (slave). The device supports SPI,
1-bit SD and 4-bit SD bus mode. The SDIO block has an AHB interface, which allows the
CPU to configure the operational registers residing inside the AHB Slave core. The CIS and
CSA area is located inside the internal memory of CPU subsystem. The SDIO Registers
(CCCR and FBR) are programmed by both the SD Host (through the SD Bus) and CPU
(through the AHB bus) via Operational registers. The SDIO block implements the AHB
master to initiate transfers to and from the system memory autonomously.
During the normal initialization and interrogation of the card by the SD Host, the card will
identify itself as an SDIO device. The SD Host software will obtain the card information in
a tuple (linked list) format and determine if that card’s I/O function(s) are acceptable to
activate. If the Card is acceptable, it will be allowed to power up fully and start the I/O
function(s) built into it.
The SDIO interface implements Function 1 in addition to the default Function 0. All
application data transfers are done through the Function 1.
The primary features of this interface are:
• Meets SDIO card specification version 2.0
• Conforms to AHB specification
• Host clock rate variable between 0 and 40 MHz
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NOTE: Tested with current test platform up to 33 MHz.
• All SD bus modes supported including SPI, 1 and 4 bit SD

• Allows card to interrupt host in SPI, 1 and 4 bit SD modes
• Read and Writes using 4 parallel data lines
• Cyclic Redundancy Check CRC7 for command and CRC16 for data
integrity-CRC checking optional in SPI mode
• Programmable through a standard AHB Slave interface
• Writing of the I/O reset bit in CCCR register generates an active low reset output
synchronized to AHB Clock domain
• Card responds to Direct read/write (IO52) and Extended read/write (IO53)
transactions
• Supports Read wait Control operation
• Supports Suspend/Resume operation
2.2.6.2 SPI Interface

The SPI interface is a master slave interface that enables synchronous serial
communications with slave or master peripherals having one of the following: Motorola
SPI-compatible interface, TI synchronous serial interface or National Semiconductor
Microwire interface. In both master and slave configuration, the block performs
parallel-to-serial conversion on data written to an internal 16-bit wide, 8-deep transmit
FIFO and serial to parallel conversion on received data, buffering it in a similar 16-wide, 8
deep FIFO. It can generate interrupts to the CPU to request servicing transmit and receive
FIFOs and indicate FIFO status and overrun/underrun. The clock bit rate is SW
programmable. In master mode, the SPI block in GS2000 can perform up to 30 MHz and
in slave mode up to 10 MHz serial clock. Clock rates higher than 20MHz in master mode
or 6.66MHz in slave mode requires activation of the PLL’s 120MHz clock source. The
interface type, data size and interrupt masks are programmable. It supports DMA working
in conjunction with the uDMA engine.
2.2.6.3 UART Interface

The UART interface implements the standard UART protocol. It is 16450/16550
compatible. It has separate 32 deep transmit and receive FIFOs to reduce CPU interrupts.
The interface supports standard asynchronous communication protocol using start, stop and
parity bits. These are added and removed automatically by the interface logic. The data size,
parity and number of stop bits are programmable. It supports HW based flow control
through CTS/RTS signaling. A fractional baud rate generator allows accurate setting of the
communication baud rate. It supports DMA working in conjunction with the uDMA
engine.
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2.2.6.4 I2C Interface

The I2C interface block implements the standard based two wire serial I2C protocol. The
interface can support both master and slave modes. It supports multiple masters, high speed
transfer (up to 3.4MHz), 7 or 10-bit slave addressing scheme, random and current address
transfer. It also supports clock stretching to interface with slower devices. It can generate
interrupts to the CPU to indicate specific events such as FIFO full/empty, block complete,
no ack error, and arbitration failure.
2.2.6.5 GPIO
The GPIO block provides programmable inputs and outputs that can be controlled from the
CPU SW through an APB interface. Any number of inputs can be configured as an interrupt
source. The interrupts can be generated based on the level or the transition of a pin. At reset,
all GPIO lines defaults to inputs. Each pin can be configured as input or output from SW
control.
2.2.6.6 ADC
The ADC is a 12-bit, low-power, A-to-D converter capable of running at up to 2 Mbps.

The ADC is accessible from the APP CPU only. The ADC contains an internal band-gap
reference which provides a stable 1.4V reference voltage. Alternatively, the ADC can be
programmed to use the VIN_3V3 external supply reference as the full-scale reference.
The ADC uses an input clock range of 10KHz to 2MHz. The input clock is generated by
an internal NCO (Number Controlled Oscillator). A conversion requires 1 clock cycles.
The ADC supports three measurement modes, continuous, single or periodic.
The sample data will be stored in a CPU readable FIFO. The file is an 8-deep FIFO. The
FIFO has SW configurable level interrupt. New samples are dropped if FIFO is full and
new data is received prior to FW servicing the FIFO, then the sample is dropped.
2.2.6.7 PWM
The PWM consists of three identical PWM function blocks. The PWM function blocks can
be used in two modes of operations:
• Independent PWM function blocks providing output signal with programmable
frequency and duty cycle
• Synchronized PWM function blocks with programmable phase delay between
each PWM output
The PWM has the following features:
• 32-bit AMBA APB interface to access control, and status information
• Three identical PWM function blocks
• Each PWM block can be enabled independently
• All three PWM blocks can be started synchronously or chained with
programmable delay
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• Programmable 6-bit prescaler for the input clock (see 2.2.4 Clocks, page 28)
• Programmable frequency and duty cycle using 16 bit resolution in terms of clock
cycles for ON and OFF interval time
• Combined interrupt line with independent masking of interrupts
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2.2.7 System States

Figure 3, page 35 shows the power management/clock states of the GS2011Mxx system.
Figure 3 GS2011Mxx System States
The system states of the GS2011M system are as follows:

Power OFF: No power source connected to the system.
Standby: In the standby state, only the RTC portion of the GS2011M is powered from
the VRTC pin. The other power supplies are turned off by the DC_DC_CNTL pin being
low. To achieve the lowest standby current, other supply pins should be powered on/off
together, controlled by the DC_DC_CNTL pin, including the EN_1V8 pin (which
controls VOUT_1V8), VDDIO, and the VIN_3V3 pin.
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In standby state, the 32.768KHz oscillator keeps running and only the RTC RAM
retains the state (how many banks retain their state is SW configurable). SRAM, CPUs
and I/Os are all in OFF state, as there is no 1.8V and no VDDIO being supplied to the
GS2011M device.
This is the lowest-power-consumption state. In a typical application, the system returns
to the Standby state between periods of activity, to keep the average power very low
and enable years of operation using conventional batteries. During standby, the RTC
isolates itself from the rest of the chip, since the signals from the rest of the chip are
invalid. This prevents corruption of the RTC registers.
Exit from standby occurs when a pre-specified wakeup time occurs, or when one of the
RTC_IO’s configured as alarm inputs sees the programmed polarity of signal edge.
When one of the wakeup conditions occurs, the RTC asserts reset to the chip and sets
the DC_DC_CNTL pin high to enable power to the rest of the module. After power to
the rest of the module is assumed to be good, the isolation between the RTC and the
rest of the chip is released, and the EXT_RESETn pin is released. The system now
starts booting.
NOTE: During first battery plug, i.e., when power is applied the first time to the
RTC power rail (VRTC), the power detection circuit in the RTC also causes a
wakeup request.
System Configuration: When a power-up is requested, the system transitions from the
Standby state to the System Configuration state. In this state, the APP CPU is released
from reset by the RTC. The WLAN CPU remains in the reset state during System
Configuration. The APP CPU then executes the required system configurations,
releases the WLAN CPU from reset, and transitions to the Power-ON state.
The System Configuration state is also entered on transition from the Power-ON state
to the Standby state, to complete necessary preparations before shutting off the power
to the core system.
Power-ON: This is the active state where all system components can be running. The
Power-ON state has various sub-states, in which unused parts of the system can be in
sleep mode, reducing power consumption. Sleep states are implemented by gating the
clock signal off for a specific system component. Additionally, unneeded clock sources
can be turned off. For example, receiving data over a slave SPI interface could be done
with only the 80MHz RC oscillator active, and the 40MHz crystal and PLL turned off.
Sleep: In the Sleep state, the 40MHz crystal and the 80MHz RC oscillator remains
running, but it is gated off to one or both CPUs. Each CPU can independently control
its own entry into Sleep state. Any enabled interrupt will cause the interrupted CPU to
exit from Sleep state, and this will occur within a few clock cycles.
Deep Sleep: Deep sleep is entered only when both CPUs agree that the wakeup latency
is OK. In Deep Sleep mode, the 40MHz crystal oscillator and 80MHz RC oscillator are
turned off to save power, but all power supplies remain turned on. Thus all registers,
memory, and I/O pins retain their state. Any enabled interrupt will cause an exit from
Deep Sleep state.
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NOTE: For the above power states, software controls which clocks stay turned
on in each of the three states.
The following are not system states, but are related design notes:
Power Control: The GS2011M was designed with the intent that power to the
non-RTC portions of the chip be controlled from the DC_DC_CNTL signal. In
applications where it is preferred that an external host control the power, this is OK if
ALL power, including VRTC power, is turned on and off by the external host. In this
case, all state is lost when power goes off, and the latencies from first battery plug
apply.
If these latencies are not acceptable, then the GS2011M MUST control power. The
external host would use an alarm to wake it up, and a serial command to put it into
standby. The DC_DC_CNTL pin would control the power supplies. It is NOT reliable
for the external host to directly control the power supplies if VRTC is to be left turned
on. This is because the RTC would not know when to isolate itself from the rest of the
chip, and might get corrupted during power up or power down.
EXT_RESET_n pin: If the external host is driving the EXT_RESET_n pin, it MUST
do so with an open drain driver. This is because this pin is driven low during power up
by the RTC. In addition, if an external host is connected to the EXT_RESET_n pin,
there must be an external 10K ohm pull-up resistor on the board, pulling up to VDDIO.
This is needed to overcome a possible pull-down in the host at first power application.
It is also recommended that the host not actively assert EXT_RESET_n until all the
startup latencies have expired.
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2.2.8 Power Supply

This section shows various application power supply connections. Figure 4, page 38 shows
the GS2011Mxx always on power supply connection and Figure 5, page 39 shows the
GS2011MIx in battery powered with optimized standby mode.
Figure 4 GS2011Mxx Always ON Power Supply Connection
Notes:
1. Always ON is obtained by tying EN_1V8 to 1 which is the enable for the 1.8V voltage
regulator.
2. With this connection method, standby current will not be optimized.
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Figure 5 GS2011MIx Battery Powered with Optimized Standby Support
Notes:
1. This connection applies for designs (typically battery operated) using GS2011M module and
want to optimized standby (lowest current consumption) state of the module. In this
connection it is important to note the following:
2. Input voltage to VRTC must always be ON to keep the RTC powered so that the 32KHz
crystal is running.
3. VDDIO and VIN_3V3 power should be OFF during this state. Recommendation is to use
DC_DC_CNTL to also control the unit supplying the voltage to VDDIO and VIN_3V3
4. DC_DC_CNTL must be connected to EN_1V8 to so that the internal 1.8V regulator gets
turned OFF when system goes to standby state (i.e., DC_DC_CNTL is de-asserted).
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Chapter 3 Pin-out and Signal Description
This chapter describes the GainSpan® GS2011M Low Power module architecture.
• GS2011Mxx Device Pin-out, page 41
3.1 GS2011Mxx Device Pin-out

Figure 6, page 41 shows the GS2011Mxx device pin-out diagram.
Figure 6 GS2011Mxx Device Pin-out Diagram (Module Top View)
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3.1.1 GS2011Mxx Module Pins Description

Table 7, page 42 describes the GS2011Mxx module pin signal description.
Table 7 GS2011Mxx Module Pin Signal Description

Pins Name Voltage Internal Bias after Drive Signal State Description
Domain Hardware Reset Strength
(mA)
1 GND 0V Not Applicable Analog port Ground
2 JTAG_TCK VDDIO Pull-up (see Note 1) Digital Input JTAG Test Clock
3 JTAG_TDO VDDIO Pull-down (see Note1) Digital Output JTAG Test Data Out
4 JTAG_TDI VDDIO Pull-up (see Note 1) Digital Input JTAG Test Data In
5 JTAG_TMS VDDIO Pull-up (see Note 1) Digital Input JTAG Test Mode Select
JTAG Test Mode Reset
6 JTAG_TRST_n VDDIO Pull-up (see Note 1) Digital Input
(Active Low)
RTC Digital Embedded Real Time Clock
7 RTC_IO_1 VRTC Pull-down (see Note 1) 1
Input/Output Input/Output 1
RTC Digital Embedded Real Time Clock
8 RTC_IO_0 VRTC Pull-down (see Note 1) 1
Input/Output Input/Output 0
Embedded Real Time Clock
9 VRTC VRTC Not Applicable Analog port
Power Supply
VIN_3V3 Regulator
DC_DC_CNTRL/ RTC Digital
10 VRTC (see Note 1) 1 Control Output/RTC Digital
RTC_IO_4 Input/Output
Input/Output
General Analog to Digital
11 ADC_SAR_0 VIN_3V3 Not Applicable Analog Input Converter, Successive
Approximation Register 0
General Analog to Digital
12 ADC_SAR_1 VIN_3V3 Not Applicable Analog Input Converter, Successive
Approximation Register 1
RTC_IO_2 (see RTC Digital Embedded Real Time Clock
13 VRTC Pull-down (see Note 1) 1
Note 2) Input/Output Input/Output 2
Digital GPIO/Serial Peripheral
14 GPIO6/SPI1_DIN VDDIO Pull-down (see Note 1) 4
Input/Output Interface 1 Bus Data Input
GPIO7 / Digital GPIO/Serial Peripheral
15 VDDIO Pull-down (see Note 1) 4
SPI1_DOUTE-1 Input/Output Interface 1 Bus Data Output
Internal 1.8V VOUT
16 VOUT_1V8 VIN_3V3 Not Applicable Analog port
(internally regulated)
Digital GPIO/Serial Peripheral
18 GPIO5/SPI1_CLK VDDIO Pull-down (see Note 1) 4
Input/Output Interface 1 Bus Clock
1VV0301482 Rev. 5.0 Page 42 of 69 2018-01-10

Table 7 GS2011Mxx Module Pin Signal Description (Continued)

(mA)
GPIO/Serial Peripheral
GPIO4/ Digital
19 VDDIO Pull-down (see Note 1) 4 Interface 1 Chip Select_0
SPI1_CS_n_0 Input/Output
(Active Low)
GPIO13/ GPIO/ Serial Peripheral

Digital
20 VDDIO Pull-down (see Note 1) 4 Interface 1 Chip Select_1
SPI1_CS_n_1 Input/Output
(Active Low)
GPIO/Internal RTC Clock
GPIO21/ Digital Circuitry Test Point. This
CLK_RTC Input/Output pin is used for Code
Restore.
GPIO20/ Digital GPIO/Internal RTC Clock
CLK_HS_RC Input/Output Circuitry Test Point
GPIO19/ Digital GPIO/XTAL Clock
CLK_HS_XTAL Input/Output Circuitry Test Point
Digital GPIO/XTAL Clock
24 GPIO10/PWM0 VDDIO Pull-down (see Note 1) 4
Input/Output Circuitry Test Point
Pull-down (see Note 1 Digital GPIO/Inter-Integrated
25 GPIO9/I2C_CLK VDDIO 12
and Note 5) Input/Output Circuit Clock
Pull-down (see Note 1 Digital GPIO/Inter-Integrated
26 GPIO8/I2C_DATA VDDIO 12
and Note 5) Input/Output Circuit Data
GPIO36/ GPIO/SDIO Data Bit0/SPI0
Digital
27 SDIO_DAT0/ VDDIO Pull-down (see Note 1) 4 Transmit Data Output to the
Input/Output
SPI0_DOUTE-1 HOST
GPIO35/
Digital GPIO/SDIO Clock/SPI0
28 SDIO_CLK/ VDDIO Pull-down (see Note 1) 4
Input/Output Clock Input from the HOST
SPI0_CLK
GPIO33/ GPIO/SDIO Data Bit
Digital Input 3/SPI0 Chip Select Input 0
29 SDIO_DAT3/ VDDIO Pull-up (see Note 1) 4
Output from the HOST (Active
SPI0_CS_n_0 Low)
GPIO34/ GPIO/SDIO Command
Digital
30 SDIO_CMD/ VDDIO Pull-down (see Note 1) 4 Input/SPI0 Receive Data
Input/Output
SPI0_DIN Input from HOST
31 VIN_3V3 VIN_3V3 Not Applicable Analog port Single Supply Port
Need to be driven Internal 1.8V regulator
33 EN_1V8 VDDIO Digital Input
HIGH or LOW enable port Active High
1VV0301482 Rev. 5.0 Page 43 of 69 2018-01-10


(mA)
All I/O voltage domain (can
34 VDDIO VDDIO Not Applicable Analog port be tied to VIN_3V3 or tied
to HOST I/O supply)
GPIO26/ Digital GPIO/UART1Clear to Send
UART1_CTS Input/Output input (see Note 7)
GPIO/UART1 1 Request to
GPIO27/ Pull-down (see Note 1 Digital Send Output (see Note 7).
36 VDDIO 4
UART1_RTS and Note 4) Input/Output This pin is used for Program
Mode.
GPIO3/ Digital GPIO/UART1 Receive
UART1_RX Input/Output Input
GPIO32/ GPIO/SDIO_DATA Bit
Digital
38 SDIO_DAT2/ VDDIO Pull-down (see Note 1) 4 2/UART 1 Transmitter
Input/Output
UART1_TX Output
GPIO1/ Digital GPIO/UART0 Transmitter
UART0_TX Input/Output Output.
GPIO/UART0 Request to
GPIO25/ Digital Send Output (see Note 7).
UART0_RTS Input/Output This pin is used for Program
Select.
GPIO0/ Digital GPIO/UART0 Receive
UART0_RX Input/Output Input
GPIO24/ Digital GPIO/UART0 Clear to
UART0_CTS Input/Output Send Input (See Note 7)
16 Digital GPIO/Pulse Width
43 GPIO31/PWM2 VDDIO Pull-down (see Note 1)
(see Note 8) Input/Output Modulation Output 2
16 Digital GPIO/Pulse Width
44 GPIO30/PWM1 VDDIO Pull-down (see Note 1)
(see Note 8) Input/Output Modulation Output 1
Digital GPIO/I2C_CLK (see Note
45 GPIO29/I2C_CLK VDDIO Pull-down (see Note 1) 12
Input/Output 4)
GPIO37/ Pull-down (see Note 1 Digital GPIO/4-bit SDIO DATA bit
46 VDDIO 4
SDIO_DAT1_INT and Note 10) Input/Output 1/SDIO SPI Mode Interrupt
1VV0301482 Rev. 5.0 Page 44 of 69 2018-01-10


(mA)
Module Hardware Reset
Digital Open
EXT_RESET_n Input and Power Supply
47 VDDIO Not Applicable Drain
(see Note 6) Reset Monitor Indicator
Input/Output
Active Low
Programming Voltage for
49 VPP (see Note 9) VPP Not Applicable Analog port
OTP Memory
Notes:
1. Pins with drive strength 4, 12, and 16 have one pull resistor (either up or down, not both),
which is enabled at reset. RTC_IO pins have both pull_up and pull_down resisters. The
RTC_IO pull down resisters are enabled at reset for non DC_DC_CNTL pins.
2. Can be left as no connect.
3. This pin enables programming of the module. If UART1_RTS (GPIO27) is high during
reset or power on then the GS2011M will wait for Flash download via UART0 or SPI0
interface. Route this pin on the base board so it can be pulled up to VDDIO for programming
the module.
4. GPIO29 is the primary function; if using GPIO8/9 as I2C function, then this pin cannot be
used for I2C function.
5. If I2C interface is used, provide 2K Ohm pull-ups, to VIN_3V3, for I2C_CLK and
I2C_DATA.
6. EXT_RESET_n is an active low signal. It is an output during power up, indicating to the
system when GS2011 device is out of power-on-reset. After power-on-reset, this pin is an
input. It is not necessary to assert reset to the GS2011M after power on, since the GS2011
has a built-in power on reset. Also, the EXT_RESET_n signal does not clear the RTC, RTC
RAM, or the SRAM. If the external host is driving the EXT_RESET_n pin, it MUST do so
with an open drain driver. This is because this pin also must be able to be driven by the RTC.
In addition, if an external host is connected to the EXT_RESET_n pin, there must be an
external 10K Ohm pull-up resistor on the board, pulling up to VDDIO.
7. CTS and RTS signals indicate it is clear to send or ready to send when they are LOW. If
signals are high indicates device is not ready.
8. These pins have higher drive strength so they can drive LEDs directly.
9. This pin is generally reserved for GainSpan use, but if a design requires writing to OTP
during production, then design must take into account connection to this pin. Otherwise, it
should be left as a No Connect.
10. In the Serial-to-Wi-Fi firmware when using SPI interface this pin is the host wake-up
signal or the Ready to Send signal.
a. GPIO37 - when using SPI interface this pin is the host wake-up signal or the Ready to
Send signal.
1VV0301482 Rev. 5.0 Page 45 of 69 2018-01-10

Errata
E1. The SPI0_DOUT and SPI1_OUT signals do not disable their drive and become Hi-Z
when the associated chip select pin is high. This applies to all pin MUX locations for the
SPI_DOUT signals. If there are multiple write only devices on the same SPI bus, then this
is not an issue. This only becomes an issue when there are other read/write devices on the
same SPI bus. The workaround is to add an external buffer chip, such as 74LVC1G125
between the SPI_DOUT pin and the SPI bus, with the enable connected to the chip select
signal.
1VV0301482 Rev. 5.0 Page 46 of 69 2018-01-10

3.1.2 GS2011M Pin MUX Function

The GS2011M pins have multiple functions that can be selected using MUX function by
software. Each pin has an independent MUX select register. Table 8, page 47 shows the
various MUX functions for each pin. All pins are GPIO inputs at reset. For pins that are
inputs to functional blocks only one pin may be assigned to any input function. For
example, UART1_RX may be assigned to GPIO3 but not to both GPIO3 and GPIO37.
Table 8 GS2011M Pin MUX Description

Pin# Pin Name Mux3 Mux4 Mux5 Mux6 Mux7 Comments
1 GND
2 jtag_tck
3 jtag_tdo
4 jtag_tdi
5 jtag_tms
6 jtag_trst_n
7 rtc_io_1
8 rtc_io_0
9 VRTC
10 dc_dc_cntl/rtc_io_4
11 adc_sar_0
12 adc_sar_1
13 rtc_io_2
14 gpio6/spi1_din spi1_din wspi_din spi1_dout1 wspi_dout1 spi0_cs_n_1
15 gpio7/spi1_dout1 spi1_dout1 wspi_dout1 spi1_din wspi_din spi0_cs_n_2
16 VOUT_1V8
17 GND
18 gpio5/spi1_clk spi1_clk wspi_clk pwm0 traceclk spi0_cs_n_3
19 gpio4/spi1_cs_n_0 spi1_cs_n_0 wspi_cs_n_0 spi0_cs_n_4 reserved clk_rtc
20 gpio13/spi1_cs_n_1 spi1_cs_n_1 pwm2 spi0_cs_n_5 tracedata[0] wspi_cs_n_1
21 gpio21/clk_rtc clk_rtc spi1_cs_n_2 clk_hs_xtal tracedata[1] spi0_cs_n_6
22 gpio20/clk_hs_rc clk_hs_rc spi1_cs_n_3 clk_hs_xtal tracedata[2] spi0_cs_n_7
23 gpio19_clk_hs_xtal clk_hs_xtal spi1_cs_n_4 pwm2 tracedata[3] spi0_cs_n_8
24 gpio10/pwm0 pwm0 reserved spi1_clk tracedata[0] clk_rtc
25 gpio9/i2c_clk i2c_clk uart1_rx spi1_din tracedata[1] i2s_lcrclk
26 gpio8/i2c_data i2c_data uart1_tx spi1_dout1 tracedata[3] reserved
27 gpio36/sdio_dat0/spi0_dout1 sdio_data0 reserved i2c_data reserved spi0_dout1
28 gpio35/sdio_clk/spi0_clk sdio_clk reserved i2c_clk traceclk spi0_clk Note: only
4mA for i2c
29 gpio33/sdio_dat3/spi0_cs_n_0 sdio_data3 reserved uart1_rts tracedata[0] spi0_cs_n_0
30 gpio34/sdio_cmd/spi0_din sdio_cmd reserved uart1_cts tracedata[1] spi0_din
1VV0301482 Rev. 5.0 Page 47 of 69 2018-01-10

Table 8 GS2011M Pin MUX Description (Continued)

Pin# Pin Name Mux3 Mux4 Mux5 Mux6 Mux7 Comments
31 VIN_3V3 Includes Flash,
PA, ADC,
VDDIO, REG
32 GND
33 EN_1V8
34 VDDIO
35 gpio26/uart1_cts uart1_cts wuart_cts i2s_din spi1_cs_n_13 wssp_clk
36 gpio27/uart1_rts uart1_rts wuart_rts i2s_dout uart1_tx wspi_dout1
37 gpio3/uart1_rx uart1_rx wuart_rx i2s_bitclk spi1_cs_n_14 wspi_din
38 gpio32/sdio_dat2/uart1_tx sdio_data1 wuart_tx uart1_tx tracedata[2] spi1_cs_n_12
39 gpio1/uart0_tx uart0_tx wuart_tx pwm1 tracedata[0] spi1_dout1
40 gpio25/uart0_rts uart0_rts wuart_rts spi1_cs_n_7 tracedata[1] spi1_clk
41 gpio0/uart0_rx uart0_rx wuart_rx pwm2 tracedata[2] spi1_din
42 gpio24/uart0_cts uart0_cts wuart_cts pwm0 tracedata[3] spi1_cs_n_0
43 gpio31/pwm2 pwm2 spi1_dout1 uart1_tx traceclk wuart_tx
44 gpio30/pwm1 pwm1 spi1_din uart1_rx reserved wuart_rx
45 gpio29/i2c_clk i2c_clk spi1_cs_n_20 clk_rtc tracedata[0] pwm0
46 gpio37/sdio_dat1_int sdio_data1 wuart_rx uart1_rx tracedata[3] spi0_cs_n_10
47 ext_reset_n
48 GND
49 VPP Programming
voltage for
OTP memory
Note 1. The SPI0_DOUT and SPI1_OUT signals do not disable their drive and become Hi-Z
when the associated chip select pin is high. This applies to all pin MUX locations for the
SPI_DOUT signals. If there are multiple write only devices on the same SPI bus, then this is
not an issue. This only becomes an issue when there are other read/write devices on the same
SPI bus. The workaround is to add an external buffer chip, such as 74LVC1G125 between the
SPI_DOUT pin and the SPI bus, with the enable connected to the chip select signal.
1VV0301482 Rev. 5.0 Page 48 of 69 2018-01-10

3.1.3 GS2011M Program and Code Restore Options

Table 9, page 49 describes the options available for device program mode and code restore
capabilities. The respective GPIO pins are sampled at reset by device and depending on the
values seen on these pins goes into the appropriate mode. Code for the GS2011M resides
on the internal flash of the module and up to two back-up copies could be stored in flash.
If a software designer wants to restore the execution code to one of the backup copy, it can
be accomplished by asserting the appropriate GPIO pins as shown in the table below during
power up or reset.
Table 9 GS2011M Pin Program and Code Restore

Boot Control Program Program Alternate Interfaces for Program Load
Mode Select/Previous Code Restore
Restore
(GPIO 27) (GPIO 21)
(GPIO 25)
(see Note 1) 0 0 0 Normal boot
Previous Code Restore. Restores prior code
by invalidating the present code image.
Will NOT invalidate the last remaining
0 0 1
page. Note below that GPIO21 and
GPIO25 MUST NOT both be high at reset
release in Run mode (GPIO27=0).
Previous Code Restore. Restores the prior
code revision by invalidating the present
0 1 0
code image. Will NOT invalidate the last
remaining image.
Invalid. DO NOT USE THIS BOOT
CONTROL STATE. This boot control state
0 1 1
can invalidate the last remaining code
image.
Program Mode: UART0 @ 115.2Kbaud;
nothing on GPIO15-18; SPI0 on SDIO
1 0 X
pins. Note: this is the default you get if you
don’t pull the Program Select pin high.
Program Mode using: UART0
@921.6Kbaud; SPI0 on GPIO15-18. Note:
1 1 X
GPIO15-18 are only available on GS2000
SoC, and not on modules.
Note:
1. In Run Mode, boot ROM leaves all GPIO pins as input with pull resistor enabled until flash
code sets them otherwise. In Program Mode, only the pins required for the Program Mode
specified interfaces are set to non-GPIO mode.
1VV0301482 Rev. 5.0 Page 49 of 69 2018-01-10

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1VV0301482 Rev. 5.0 Page 50 of 69 2018-01-10

Chapter 4 Electrical Characteristics
This chapter describes the GainSpan® GS2011M electrical characteristics.

• Absolute Maximum Ratings, page 51
• Operating Conditions, page 52
• Internal 1.8V Regulator, page 52
• I/O DC Specifications, page 53
• Power Consumption, page 55
• 802.11 Radio Parameters, page 56
• ADC Parameters, page 58
4.1 Absolute Maximum Ratings

Conditions beyond those cited in Table 10, page 51 may cause permanent damage to the
GS2011Mxx, and must be avoided. Sustained operation, beyond the normal operating
conditions, may affect the long term reliability of the module.
Table 10 Absolute Maximum Ratings

Parameter Symbol Minimum Typical Maximum Unit
oC
Storage Temperature TST -55 +125
RTC Power Supply VRTC -0.5 4.0 V
I/O Supply Voltage VDDIO -0.5 4.0 V
Single Supply Port VIN_3V3 0.5 4.0 V
OTP Supply VPP TBD V
1
Signal Pin Voltage VI -0.3 Voltage Domain + 0.3 V
Note:
1. Reference domain voltage is the Voltage Domain. Refer to the section on GS2011Mxx
Module Pins Description. For limitations on state voltage ranges, refer to the section
GS2011Mxx Module Pins Description.
1VV0301482 Rev. 5.0 Page 51 of 69 2018-01-10

4.2 Operating Conditions

Table 11, page 52 lists the operating conditions of the GS2011Mxx module.
Table 11 Operating Conditions

Parameter Symbol Minimum Typical Maximum Unit
Extended oC
T -40 +85
Temperature Range A
RTC Power Supply VRTC 1.6 3.3 3.6 V
I/O Supply Voltage VDDIO 2.7 3.3 3.6 V
Single Supply Port
VIN_3V3 2.7 3.3 3.6 V
GS2011MIx
Signal Pin Voltage1 VI 0 Voltage Domain V
2
VPP VPP 5.5 5.75 6.0 V
Notes:
1. Reference domain voltage is the Voltage Domain. Refer to section GS2011Mxx Module
Pins Description.
2. The VPP pin should be left floating when not doing OTP programming operations.
4.3 Internal 1.8V Regulator

Table 12, page 52 lists the internal 1.8V regulator parameters.
VIN_3V3=VDDIO=VRTC=3.3V Temp=25oC fOSC=3.0MHz.
Table 12 Internal 1.8V Regulator

Parameter Symbol Test Minimum Typical Maximum Unit
Conditions
Output Voltage VOUT_1V8 1.8 V
Maximum Output Current IVOUT_1V8 30 50 mA
Oscillation Frequency fOSC 1.6 3.45 MHz
1.8V Regulator Enable “H:
EN_1V8 1.0 VIN_3V3 V
Voltage
1.8V Regulator Enable “L”
EN_1V8 0 0.25 V
Voltage
1VV0301482 Rev. 5.0 Page 52 of 69 2018-01-10

4.4 I/O DC Specifications
4.4.1 I/O Digital Specifications (Tri-State) Pin Types 4mA, 12mA, and 16mA
The specifications for these I/O’s are given for voltage ranges: 2.7V to 3.6V.
4.4.1.1 I/O Digital Specifications for VDDIO=2.7V to 3.6V

Table 13, page 53 lists the parameters for I/O digital specification for VDDIO 2.7V to 3.6V
for Pin Types 4mA, 12mA, and 16mA.
Table 13 I/O Digital Parameters for VDDIO=2.7V to 3.6V

Parameter Symbol Minimum Typical Maximum Unit Note
I/O Supply Voltage VDDIO 2.7 3.3 3.6 V
Input Low Voltage VIL -0.3 0.3*VDDIO V
Input High Voltage VIH 0.7*VDDIO VDDIO V
Pull up/down
Input Leakage Current IL 10 μA
disabled
Tri-State Output Pull up/down
IOZ 10 μA
Leakage Current disabled
Pull-Up Resistor Ru 34K 51K 100K Ω
Pull-Down Resistor Rd 35K 51K 100K Ω
Output Low Voltage VOL 0.4 V
Output High Voltage VOH 0.8*VDDIO V
4 Pin Type 4mA
Low Level Output
IOL 12 mA Pint Type 12mA
Current @ VOL max
16 Pint Type 16mA
4 Pin Type 4mA
High Level Output
IOH 12 mA Pin Type 12mA
Current @ VOH min
16 Pin Type 16mA
3.1 4.2 7 Pin Type 4mA
Output rise time 10%
tTRLH 1.8 2.4 4 ns Pint Type 12mA
to 90% load, 30pF
1.5 2.0 3.4 Pin Type 16mA
3.8 5.0 8 Pin Type 4mA
Output fall time 90% to
tTFHL 1.8 2.5 4.2 ns Pin Type 12mA
10% load, 30pF
1.5 2.1 3.5 Pin Type 16mA
1VV0301482 Rev. 5.0 Page 53 of 69 2018-01-10

4.4.2 RTC I/O Specifications

Table 14, page 54 lists the RTC I/O parameters.
Table 14 RTC I/O Parameters

Parameter Symbol Minimum Typical Maximum Unit Note
Supply Voltage VRTC 1.6 3.6 V
Input Low
VIL -.03 0.3*VRTC V
Voltage
Input High
VIH 0.7*VRTC VRTC+0.3 V
Voltage
Input Leakage
IL 0.1 μA
Current
Pullup Current IPU 1 μA
Pulldown
IPU 1 μA
Current
Output Low IL=1mA or
VOL 0.4 V
Voltage 4mA*
Output High IL=1mA or
VOH VRTC-0.4 V
Voltage 4mA*
*RTC I/O’s are software selectable as 1mA (default) or 4mA drive strength.
1VV0301482 Rev. 5.0 Page 54 of 69 2018-01-10

4.5 Power Consumption

Table 15, page 55 lists the power consumption for the GS2011Mxx. Typical conditions are:
VIN_3V3=VDDIO=VRTC=3.3V Temp=25oC.
Table 15 Power Consumption in Different States

System State Current (Typical)1
Hibernate (only VRTC ON, 32KHZ Clock OFF) 0.26 μA
Standby (VRTC ON, 32KHZ ON, VIN_3V3 and VDDIO OFF) 4-8 μA
Deep Sleep (see Note 2) 460 μA
WLAN Continuous Transmit (1 Mbps, 15 dBm) 300 mA
WLAN Continuous Receive (1 Mbps, -91 dBm sensitivity) 95 mA
IEEE 802.11 PS-Poll, DTIM=1 (see Note 3) 4 mA
IEEE 802.11 PS-Poll, DTIM=3 (see Note 3) 1.7 mA
IEEE 802.11 PS-Poll, DTIM=10 (see Note 3) 855 μA
Notes:
1. Depends on firmware version.
2. One Sigma (+140μA).
3. This is average current draw measurements.
1VV0301482 Rev. 5.0 Page 55 of 69 2018-01-10

4.6 802.11 Radio Parameters

Table 16, page 56 lists the 802.11 Radio parameters. Test conditions are:
Table 16 802.11 Radio Parameters - (Typical - Nominal Conditions)

Parameter Minimum Typical Maximum Unit Notes
RF Frequency Range 2400 2497 MHz N/A
HT20
Radio bit rate 1 Mbps N/A
MCS7
Transmit/Receive Specification for GS2011M
16 11b, 1Mbps
13.5 11b, 5.5Mbps
13 11b, 11Mbps
Output power 15 11g, 6Mbps
(average) for 15 dBm 11g, 18Mbps
GS2011MIE 11 11g, 54Mbps
15 11n, MCS0
15 11n, MCS3
6 11n, MCS7
16 11b, 1Mbps
12 11b, 5.5Mbps
11 11b, 11Mbps
Output power 12 11g, 6Mbps
(average) for 12 dBm 11g, 18Mbps
GS2011MIZ 10 11g, 54Mbps
12 11n, MCS0
12 11n, MCS3
5 11n, MCS7
Spectrum Mask dBr Meets 802.11 requirement for selected data rates
-90 11b, 1Mbps, BPSK/DSSS
-84 11b, 11Mbps
Receive Sensitivity at -86 11g, 6Mbps
dBm
antenna port -71 11g, 54Mbps, 64-QAM/OFDM
-86 11n, MSC0
-67 11n, MCS7, 64-QAM/OFDM
1VV0301482 Rev. 5.0 Page 56 of 69 2018-01-10

NOTE: TX output power and RX sensitivity are firmware dependent. All the
values provided for these parameters are measured at the antenna port based on
5.2.1 GA firmware.
1VV0301482 Rev. 5.0 Page 57 of 69 2018-01-10

4.7 ADC Parameters

Table 17, page 58 lists the ADC parameters. Test conditions are:
Table 17 ADC Parameters

ADC Resolution - 12 - Bits
Conversion Speed (FS) 0.01 - 2 Msps
Internal
0 1.4 V
Input Voltage Full Scale Reference
range External
0 VIN_3V3 V
Reference
ADC Integral
- - +2 LSB
Non-Linearity (INL)
ADC Differential
- - +1 LSB see Note 1
non-linearity (DNL)
FS=2Mbps,
Internal
800 μA reference
(Reference
Buffer on) 3.3V
FS=32KHz,
Internal
550 μA reference
(Reference
Buffer on) 3.3V
Active Current
FS=2Mbps,
External
450 μA reference
(Reference
Buffer off) 3.3V
FS=32KHz,
External
180 μA reference
(Reference
Buffer off) 3.3V
ADC Offset Error -30 - 30 mV
1VV0301482 Rev. 5.0 Page 58 of 69 2018-01-10

Table 17 ADC Parameters (Continued)

ADC Gain Error -8 - 8 LSB see Note 2
Error in Internal
Reference Voltage -5 - 5 %
without Trim
Error in Internal
Reference Voltage with -2.5 2.5 %
Trim
Notes:
1. No missing codes.
2. This is the gain of the ADC core measured in External reference mode.
1VV0301482 Rev. 5.0 Page 59 of 69 2018-01-10

1VV0301482 Rev. 5.0 Page 60 of 69 2018-01-10

Chapter 5 Package and Layout Guidelines
This chapter describes the GainSpan® GS2011M package and layout guidelines.
• GS2011Mxx Recommended PCB Footprint and Dimensions, page 61
5.1 GS2011Mxx Recommended PCB Footprint and Dimensions

Figure 7, page 61 shows the GS2011MIx Module PCB Footprint. Figure 8, page 62 shows
the GS2011MIx Module Dimensions.
Figure 7 GS2011MIx Module Recommended PCB Footprint (in inches)
1VV0301482 Rev. 5.0 Page 61 of 69 2018-01-10

Figure 8 GS2011MIx Module Dimensions (in inches)
Notes:
1. All Dimensions are in inches. Tolerances shall be + 0.010 for .xxx and + 0.02 for .xx inches.
2. For Boards using PCB or Ceramic Antenna, we recommend:
– Have Only Air on BOTH sides of antenna.
– Hang Antenna over edge of base board (best)
– Or Cut notch in base board under antenna area
– No metal or FR4 encircling antenna area
– Antenna at edge of base board, not interior of base board
– Nothing conductive near antenna (e.g. battery, display, wire)
3. The 3 RF shield mounting holes and 2 test fixture alignment holes (circled in red in Figure
7, page 61 and Figure 8, page 62) have exposed metal. These areas must not have metal
on the customer board.
4. For best RF performance, we recommend:
– Using power(PWR) or the GND planes from module back to power supply.
– Isolating PWR/GND from high frequency or high current components. For example, a
notch in GND plane to isolate from host uC
– Using at least 3 vias when either power or GND changes layers. This applies particularly
at the module GND pins and at the VIN_3V3 pins.
– Providing a 10 uF capacitor at the VIN_3V3 pin and using 3 vias both sides of the
capacitor.
1VV0301482 Rev. 5.0 Page 62 of 69 2018-01-10

– Keep high speed signals away from RF areas of module.

5. For area under Module, we recommend two options:
– No metal of any kind under module “not on any layer”
– Having full GND plane under module (layer 1 or layer 2) with no “HOT” vias under
module (over 100KHz) and may route signals below GND plane. Also no metal traces are
to be present in the circle, around shield and alignment holes.
6. If any metal is present on layer 1 then extra thick solder mask under the module is required
7. In performing SMT or manual soldering of the module to the base board, first align the row
of pins from #18 through #31 onto the base board and then match the other two rows.
In addition to the guidelines, note the following suggestions:
1. External Bypass capacitors for all module supplies should be as close as possible to the
module pins.
2. Never place the antenna very close to metallic objects.
3. External monopole antennas need a reasonable ground plane area for antenna efficiency.
4. Do not use a metallic or metalized plastic for the end product enclosure when using
on-board antenna.
5. If the module is enclosed in a plastic case, have reasonable clearance from plastic case to
on-board antenna.
5.1.1 Surface Mount Assembly

The reflow profile is shown in Figure 9, page 63. The recommended reflow parameters are
summarized in Table 18, page 64.
Figure 9 Reflow Temperature Profile
1VV0301482 Rev. 5.0 Page 63 of 69 2018-01-10

Table 18 Recommended Reflow Parameters

Preheat
2
Temperature Ramp up rate for (A) 1.5~3.5 oC/s
Pre-heat time (B)3 80 to 130 seconds
Pre-heat starting temperature (C1) 125 to 135 oC
Pre-heat ending temperature (C2) 180 to 200 oC
Heating5
Peak Temperature range (D) 240 to 250 oC
Melting time4 that is the time over 220 oC (E) 50 to 75 seconds
Cool Down Ramp (F) >2 oC/s
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Notes:
1. Perform adequate test in advance as the reflow temperature profile will vary according to the
conditions of the parts and boards, and the specifications of the reflow furnace.
2. Max number of reflow supported are two.
3. Temperature uniformity inside the IR reflow oven must be tightly controlled and multiple
thermocouples should be used. An example of possible thermocouple locations is given in
Figure 10, page 66. The locations should also include multiple points INSIDE the module
RF shield (e.g., TC1, TC5, and TC7 in Figure 10, page 66). The temperature profile of
ALL thermocouples must meet the requirements of Table 18, page 64.
4. Pay close attention to “Melting Time over 220oC”. Sufficient time is necessary to
completely melt all solder.
5. Be careful about rapid temperature rise in preheat zone as it may cause excessive slumping
of the solder paste.
6. If the preheat is insufficient, rather large solder balls tend to be generated. Conversely, if
performed excessively, fine balls and large balls will generate in clusters at a time.
7. If the temperature is too low, non-melting tends to be caused in the area with large heat
capacity after reflow.
8. Be careful about sudden rise in temperature as it may worsen the slump of solder paste.
9. Be careful about slow cooling as it may cause the positional shift of parts and decline in
joining at times.
10. A no clean flux should be used during SMT process.
Note: The modules are shipped in sealed trays with the following conditions (see Figure 11,
page 67).
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Figure 10 Thermocouple Locations
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Figure 11 Module Moisture Conditions
1VV0301482 Rev. 5.0 Page 67 of 69 2018-01-10

1VV0301482 Rev. 5.0 Page 68 of 69 2018-01-10

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GS2011M Low Power Wi-Fi Module

Hardware User Guide

SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE

COMPUTER SOFTWARE COPYRIGHTS

1VV0301482 Rev. 5.0 Page 2 of 171 2018-01-10

USAGE AND DISCLOSURE RESTRICTIONS

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GS2K based Modules

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Chapter 1 GS2011M Overview ........................................................................................................ 19

Chapter 2 GS2011M Architecture .................................................................................................... 23

Chapter 3 Pin-out and Signal Description ........................................................................................ 41

Chapter 4 Electrical Characteristics ................................................................................................. 51

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4.4.1.1 I/O Digital Specifications for VDDIO=2.7V to 3.6V ..............................................53

Chapter 5 Package and Layout Guidelines ..................................................................................... 61

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About This Manual

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Table 2 Certification Compliance

Table 3 Document Text Conventions

Convention Type Description

Proportional font Gives specific details about a parameter.

lowercase Indicates keywords. Enter values exactly as shown in the command

Enclose optional parameters. Choose none; or select one or more an

1VV0301482 Rev. 5.0 Page 9 of 69 2018-01-10

Table 3 Document Text Conventions (Continued)

Convention Type Description

A.B.C.D IPv4-style address.

WORD Indicates user input of any contiguous string (excluding spaces).

1VV0301482 Rev. 5.0 Page 10 of 69 2018-01-10

Table 4 Symbol Conventions

Icon Type Description

Alerts you of potential damage to a program, device,

Cautions you about a situation that could result in

Warns you of a potential situation that could result in

Electro-Static Discharge Notifies you to take proper grounding precautions

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Table 5 Documentation List (Continued)

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Contact Information, Support

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Returning Products to GainSpan

To return a hardware component:

Guidelines for Packing Components for Shipment

CAUTION! Do not stack any of the components.

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Accessing the GainSpan Portal

1. Visit http://www.telit.com, go to Products> Wi-Fi and Blue-tooth, then scroll down

Table 6 GS2011Mxx Ordering Information

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Chapter 1 GS2011M Overview

1.1 Product Overview

1.2 GS2011M Module Product Features

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