Operational Amplifier

Differential Amplifiers

Operational Amplifiers:

The operational amplifier is a direct-coupled high gain amplifier usable from 0 to over 1MH Z to which
feedback is added to control its overall response characteristic i.e. gain and bandwidth. The op-amp exhibits
the gain down to zero frequency.

Such direct coupled (dc) amplifiers do not use blocking (coupling and by pass) capacitors since these would
reduce the amplification to zero at zero frequency. Large by pass capacitors may be used but it is not possible
to fabricate large capacitors on a IC chip. The capacitors fabricated are usually less than 20 pf. Transistor,
diodes and resistors are also fabricated on the same chip.

Differential Amplifiers:

Differential amplifier is a basic building block of an op-amp. The function of a differential amplifier is
to amplify the difference between two input signals.

How the differential amplifier is developed? Let us consider two emitter-biased circuits as shown in fig. 1.

Fig. 1

The two transistors Q1 and Q2 have identical characteristics. The resistances of the circuits are equal, i.e. R E1 =
R E2, RC1 = R C2 and the magnitude of +VCC is equal to the magnitude of ?VEE. These voltages are measured
with respect to ground.

To make a differential amplifier, the two circuits are connected as shown in fig. 1. The two +VCC and ?VEE
supply terminals are made common because they are same. The two emitters are also connected and the parallel
combination of RE1 and RE2 is replaced by a resistance RE. The two input signals v1 & v2 are applied at the
base of Q1 and at the base of Q2. The output voltage is taken between two collectors. The collector
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resistances are equal and therefore denoted by RC = RC1 = RC2.

Ideally, the output voltage is zero when the two inputs are equal. When v1 is greater then v2 the output
voltage with the polarity shown appears. When v1 is less than v2, the output voltage has the opposite polarity.

The differential amplifiers are of different configurations.

The four differential amplifier configurations are following:

1. Dual input, balanced output differential amplifier.

2. Dual input, unbalanced output differential amplifier.
3. Single input balanced output differential amplifier.
4. Single input unbalanced output differential amplifier.

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Fig. 2

These configurations are shown in fig. 2, and are defined by number of input signals used and the way an
output voltage is measured. If use two input signals, the configuration is said to be dual input, otherwise it is
a single input configuration. On the other hand, if the output voltage is measured between two collectors, it is
referred to as a balanced output because both the collectors are at the same dc potential w.r.t. ground. If the
output is measured at one of the collectors w.r.t. ground, the configuration is called an unbalanced output.

A multistage amplifier with a desired gain can be obtained using direct connection between successive stages
of differential amplifiers. The advantage of direct coupling is that it removes the lower cut off frequency
imposed by the coupling capacitors, and they are therefore, capable of amplifying dc as well as ac input
signals.

Dual Input, Balanced Output Differential Amplifier:

The circuit is shown in fig. 1, v1 and v2 are the two inputs, applied to the bases of Q1 and Q2 transistors.
The output voltage is measured between the two collectors C1 and C2 , which are at same dc potentials.

D.C. Analysis:

To obtain the operating point (ICC and VCEQ) for differential amplifier dc equivalent circuit is drawn
by reducing the input voltages v1 and v2 to zero as shown in fig. 3.

Fig. 3

The internal resistances of the input signals are denoted by RS because RS1= RS2. Since both emitter biased
sections of the different amplifier are symmetrical in all respects, therefore, the operating point for only one
section need to be determined. The same values of ICQ and VCEQ can be used for second transistor Q2.

Applying KVL to the base emitter loop of the transistor Q1.

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The value of RE sets up the emitter current in transistors Q1 and Q2 for a given value of VEE. The
emitter current in Q1 and Q2 are independent of collector resistance RC.

The voltage at the emitter of Q1 is approximately equal to -VBE if the voltage drop across R is
negligible. Knowing the value of IC the voltage at the collector VCis given by

VC =VCC ? IC RC

and VCE = VC ? VE

=VCC?ICRC+VBE

VCE = VCC + VBE ? ICRC (E-2)

From the two equations VCEQ and ICQ can be determined. This dc analysis applicable for all types
of differential amplifier.

Example - 1

The following specifications are given for the dual input, balanced-output differential amplifier of fig.1:
RC = 2.2 k , RB = 4.7 k , Rin 1 = Rin 2 = 50 , +VCC = 10V, -VEE = -10 V, dc =100 and VBE = 0.715V.
Determine the operating points (ICQ and VCEQ) of the two transistors.

Solution:

The value of ICQ can be obtained from equation (E-1).

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The voltage VCEQ can be obtained from equation (E-2).

The values of ICQ and VCEQ are same for both the transistors.

Dual Input, Balanced Output Difference Amplifier:

The circuit is shown in fig. 1 v1 and v2 are the two inputs, applied to the bases of Q1 and Q2 transistors.
The output voltage is measured between the two collectors C1 and C2, which are at same dc potentials.

Fig. 1

A.C. Analysis :

In previous lecture dc analysis has been done to obtain the operatiing point of the two transistors.

To find the voltage gain Ad and the input resistance Ri of the differential amplifier, the ac equivalent circuit
is drawn using r-parameters as shown in fig. 2. The dc voltages are reduced to zero and the ac equivalent of
CE configuration is used.

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Fig. 2

Since the two dc emitter currents are equal. Therefore, resistance r'e1 and r'e2 are also equal and designated
by r'e . This voltage across each collector resistance is shown 180° out of phase with respect to the input
voltages v1 and v2. This is same as in CE configuration. The polarity of the output voltage is shown in
Figure. The collector C2 is assumed to be more positive with respect to collector C1 even though both are
negative with respect to to ground.

Applying KVL in two loops 1 & 2.

Substituting current relations,

Again, assuming RS1 / and RS2 / are very small in comparison with RE and re' and therefore neglecting
these terms,

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Solving these two equations, ie1 and ie2 can be calculated.

The output voltage VO is given by

VO = VC2 - VC1

= -RC iC2 - (-RC iC1)

= RC (iC1 - iC2)

= RC (ie1 - ie2)

Substituting ie1, & ie2 in the above expression

Thus a differential amplifier amplifies the difference between two input signals. Defining the difference
of input signals as vd = v1 ? v2 the voltage gain of the dual input balanced output differential amplifier
can be given by

(E-2)

Differential Input Resistance:

Differential input resistance is defined as the equivalent resistance that would be measured at either input
terminal with the other terminal grounded. This means that the input resistance Ri1 seen from the input
signal source v1 is determined with the signal source v2 set at zero. Similarly, the input signal v1 is set at
zero to determine the input resistance Ri2 seen from the input signal source v2. Resistance RS1 and RS2 are
ignored because they are very small.

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Substituting ie1,

Similarly,

The factor of 2 arises because the re' of each transistor is in series.

To get very high input impedance with differential amplifier is to use Darlington transistors. Another ways
is to use FET.

Output Resistance:

Output resistance is defined as the equivalent resistance that would be measured at output terminal with
respect to ground. Therefore, the output resistance RO1 measured between collector C1 and ground is equal to
that of the collector resistance RC. Similarly the output resistance RO2 measured at C2 with respect to ground
is equal to that of the collector resistor RC.

RO1 = RO2 = RC (E-5)

The current gain of the differential amplifier is undefined. Like CE amplifier the differential amplifier is a
small signal amplifier. It is generally used as a voltage amplifier and not as current or power amplifier.

Example - 1

The following specifications are given for the dual input, balanced-output differential amplifier: RC = 2.2 k ,
RB = 4.7 k , Rin 1 = Rin 2 = 50 , +VCC= 10V, -VEE = -10 V, dc =100 and VBE = 0.715V.

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a. Determine the voltage gain.

b. Determine the input resistance
c. Determine the output resistance.

Solution:

(a). The parameters of the amplifiers are same as discussed in example-1 of lecture-1. The operating point of
the two transistors obtained in lecture-1 are given below

ICQ = 0.988 mA
VCEQ=8.54V

The ac emitter resistance

Therefore, substituting the known values in voltage gain equation (E-2), we obtain

b). The input resistance seen from each input source is given by (E-3) and (E-4):

(c) The output resistance seen looking back into the circuit from each of the two output terminals is given by
(E-5)

Ro1 = Ro2 = 2.2 k

A dual input, balanced output difference amplifier circuit is shown in fig. 1.

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Fig. 1

Inverting & Non ? inverting Inputs:

In differential amplifier the output voltage vO is given by

VO = Ad (v1 ? v2)
When v2 = 0, vO = Ad v1
& when v1 = 0, vO = - Ad v2
Therefore the input voltage v1 is called the non inventing input because a positive voltage v1 acting alone
produces a positive output voltage vO. Similarly, the positive voltage v2 acting alone produces a negative
output voltage hence v2 is called inverting input. Consequently B1 is called noninverting input terminal and
B2 is called inverting input terminal.

Common mode Gain:

A common mode signal is one that drives both inputs of a differential amplifier equally. The common mode
signal is interference, static and other kinds of undesirable pickup etc.

The connecting wires on the input bases act like small antennas. If a differential amplifier is operating in an
environment with lot of electromagnetic interference, each base picks up an unwanted interference voltage. If
both the transistors were matched in all respects then the balanced output would be theoretically zero. This is
the important characteristic of a differential amplifier. It discriminates against common mode input signals. In
other words, it refuses to amplify the common mode signals.

The practical effectiveness of rejecting the common signal depends on the degree of matching between the
two CE stages forming the differential amplifier. In other words, more closely are the currents in the input
transistors, the better is the common mode signal rejection e.g. If v1 and v2 are the two input signals, then
the output of a practical op-amp cannot be described by simply

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v0 = Ad (v1 ? v2 )

In practical differential amplifier, the output depends not only on difference signal but also upon the
common mode signal (average).

vd = (v1 ? vd )

and vC = ½ (v1 + v2 )

The output voltage, therefore can be expressed as

vO = A1 v1 + A2 v2

Where A1 & A2 are the voltage amplification from input 1(2) to output under the condition that input 2 (1)
is grounded.

The voltage gain for the difference signal is Ad and for the common mode signal is AC.

The ability of a differential amplifier to reject a common mode signal is expressed by its common mode
rejection ratio (CMRR). It is the ratio of differential gain Ad to the common mode gain AC.

Date sheet always specify CMRR in decibels CMRR = 20 log CMRR.

Therefore, the differential amplifier should be designed so that is large compared with the ratio of the
common mode signal to the difference signal. If = 1000, vC = 1mV, vd = 1 V, then

It is equal to first term. Hence for an amplifier with = 1000, a 1 V difference of potential between two
inputs gives the same output as 1mV signal applied with the same polarity to both inputs.

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Dual Input, Unbalanced Output Differential Amplifier:

In this case, two input signals are given however the output is measured at only one of the two-collector w.r.t.
ground as shown in fig. 2. The output is referred to as an unbalanced output because the collector at which
the output voltage is measured is at some finite dc potential with respect to ground..

Fig. 2

In other words, there is some dc voltage at the output terminal without any input signal applied. DC analysis is
exactly same as that of first case.

AC Analysis:

The output voltage gain in this case is given by

The voltage gain is half the gain of the dual input, balanced output differential amplifier. Since at the output
there is a dc error voltage, therefore, to reduce the voltage to zero, this configuration is normally followed by
a level translator circuit.

Differential amplifier with swamping resistors:

By using external resistors R'E in series with each emitter, the dependence of voltage gain on variations of
r'e can be reduced. It also increases the linearity range of the differential amplifier.

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Fig. 3, shows the differential amplifier with swamping resistor R'E. The value of R'E is usually large enough
to swamp the effect of r'e.

Fig. 3

Example-1

Consider example-1 of lecture-2. The specifications are given again for the dual input, unbalanced-output
differential amplifier: RC = 2.2 k , RB= 4.7 k , Rin1 = Rin2= 50 , +VCC = 10V, -VEE= -10 V, dc =100 and
VBE= 0.715V.

Determine the voltage gain, input resistance and the output resistance.

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Solution:

Since the component values remain unchanged and the biasing arrangement is same, the ICQ and VCEQ
values as well as input and output resistance values for the dual input, unbalanced output configuration must
be the same as those for the dual input, balanced output configuration.

Thus, ICQ = 0.988 mA

VCEQ = 8.54 V
Ri1 = Ri2 = 5.06 k
Ro = 2.2 k

The voltage gain of the dual input, unbalanced output differential amplifier is given by

Constant Current Bias:

In the dc analysis of differential amplifier, we have seen that the emitter current IE depends upon the value
of dc. To make operating point stable IE current should be constant irrespective value of dc.

For constant IE, RE should be very large. This also increases the value of CMRR but if RE value is increased to
very large value, IE (quiescent operating current) decreases. To maintain same value of IE, the emitter supply VEE
must be increased. To get very high value of resistance RE and constant IE, current, current bias is used.

Figure 5.1

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Fig. 1, shows the dual input balanced output differential amplifier using a constant current bias. The resistance R E is
replace by constant current transistor Q3. The dc collector current in Q3 is established by R1, R2, & RE.

Applying the voltage divider rule, the voltage at the base of Q3 is

Because the two halves of the differential amplifiers are symmetrical, each has half of the current IC3.

The collector current, IC3 in transistor Q3 is fixed because no signal is injected into either the emitter or
the base of Q3.

Besides supplying constant emitter current, the constant current bias also provides a very high source
resistance since the ac equivalent or the dc source is ideally an open circuit. Therefore, all the
performance equations obtained for differential amplifier using emitter bias are also valid.

As seen in IE expressions, the current depends upon VBE3. If temperature changes, VBE changes and current IE
also changes. To improve thermal stability, a diode is placed in series with resistance R1as shown in fig. 2.

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 Operational Amplifier

Fig. 2
This helps to hold the current IE3 constant even though the temperature changes. Applying KVL to the
base circuit of Q3.

Therefore, the current IE3 is constant and independent of temperature because of the added diode D. Without
D the current would vary with temperature because VBE3 decreases approximately by 2mV/° C. The diode
has same temperature dependence and hence the two variations cancel each other and IE3 does not vary
appreciably with temperature. Since the cut ? in voltage VD of diode approximately the same value as the
base to emitter voltage VBE3 of a transistor the above condition cannot be satisfied with one diode. Hence
two diodes are used in series for VD. In this case the common mode gain reduces to zero.

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Some times zener diode may be used in place of diodes

and resistance as shown in fig. 3. Zeners are available
over a wide range of voltages and can have matching
temperature coefficient

The voltage at the base of transistor QB is

Fig. 3

The value of R2 is selected so that I2 1.2 IZ(min) where IZ is the minimum current required to cause the zener
diode to conduct in the reverse region, that is to block the rated voltage VZ.

Current Mirror:

The circuit in which the output current is forced to equal the input current is said to be a current mirror
circuit. Thus in a current mirror circuit, the output current is a mirror image of the input current. The current
mirror circuit is shown in fig. 4.

Fig. 4

Once the current I2 is set up, the current IC3 is automatically established to be nearly equal to I2. The current
mirror is a special case of constant current bias and the current mirror bias requires of constant current bias

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and therefore can be used to set up currents in differential amplifier stages. The current mirror bias
requires fewer components than constant current bias circuits.

Since Q3 and Q4 are identical transistors the current and voltage are approximately same

For satisfactory operation two identical transistors are necessary.

The operation amplifier:

An operational amplifier is a direct coupled high gain amplifier consisting of one or more differential
(OPAMP) amplifiers and followed by a level translator and an output stage. An operational amplifier is
available as a single integrated circuit package.

The block diagram of OPAMP is shown in fig. 1.

Fig. 1

The input stage is a dual input balanced output differential amplifier. This stage provides most of the voltage

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gain of the amplifier and also establishes the input resistance of the OPAMP.The intermediate stage of
OPAMP is another differential amplifier which is driven by the output of the first stage. This is usually
dual input unbalanced output.

Because direct coupling is used, the dc voltage level at the output of intermediate stage is well above ground
potential. Therefore level shifting circuit is used to shift the dc level at the output downward to zero with
respect to ground. The output stage is generally a push pull complementary amplifier. The output stage
increases the output voltage swing and raises the current supplying capability of the OPAMP. It also
provides low output resistance.

Level Translator:

Because of the direct coupling the dc level at the emitter rises

from stages to stage. This increase in dc level tends to shift the
operating point of the succeeding stages and therefore limits the
output voltage swing and may even distort the output signal.

To shift the output dc level to zero, level translator circuits

are used. An emitter follower with voltage divider is the
simplest form of level translator as shown in fig. 2.

Thus a dc voltage at the base of Q produces 0V dc at the output.

It is decided by R1 and R2. Instead of voltage divider emitter
follower either with diode current bias or current mirror bias as
shown in fig. 3 may be used to get better results.

In this case, level shifter, which is common collector amplifier, Fig. 2

shifts the level by 0.7V. If this shift is not sufficient, the output
may be taken at the junction of two resistors in the emitter leg.

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Fig. 3

Fig. 4, shows a complete OPAMP circuit having input different amplifiers with balanced output,
intermediate stage with unbalanced output, level shifter and an output amplifier.

Fig. 4
Lecture - 6: Practical Operational Amplifier
The symbolic diagram of an OPAMP is shown in fig. 1.

741c is most commonly used OPAMP available in IC package. It is an 8-pin DIP chip.

Parameters of OPAMP:

The various important parameters of OPAMP are follows:

1.Input Offset Voltage:

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Input offset voltage is defined as the voltage

that must be applied between the two input
terminals of an OPAMP to null or zero the
output fig. 2, shows that two dc voltages are
applied to input terminals to make the output
zero.

Vio = Vdc1 ? Vdc2

Vdc1 and Vdc2 are dc voltages and RS represents

the source resistance. Vio is the difference of
Vdc1 and Vdc2. It may be positive or negative.
For a 741C OPAMP the maximum value of Vio
is 6mV. It means a voltage ± 6 mV is required
to one of the input to reduce the output offset Fig. 2 voltage to zero. The
smaller the input offset voltage the better the differential amplifier,

because its transistors are more closely

matched.

2. Input offset Current:

The input offset current Iio is the difference between the currents into inverting and
non-inverting terminals of a balanced amplifier.

Iio = | IB1 ? IB2 |

The Iio for the 741C is 200nA maximum. As the matching between two input terminals is
improved, the difference between IB1 and IB2 becomes smaller, i.e. the Iio value decreases
further.For a precision OPAMP 741C, Iio is 6 nA

3.Input Bias Current:

The input bias current IB is the average of the current entering the input terminals of a
balanced amplifier i.e.

IB=(IB1+IB2)/2

For 741C IB(max) = 700 nA and for precision 741C IB = ± 7 nA

4. Differential Input Resistance: (Ri)

Ri is the equivalent resistance that can be measured at either the inverting or non-
inverting input terminal with the other terminal grounded. For the 741C the input
resistance is relatively high 2 M . For some OPAMP it may be up to 1000 G ohm.

5. Input Capacitance: (Ci)

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Ci is the equivalent capacitance that can be measured at either the inverting and noninverting
terminal with the other terminal connected to ground. A typical value of Ci is 1.4 pf for the 741C.

6. Offset Voltage Adjustment Range:

741 OPAMP have offset voltage null capability. Pins 1 and 5 are marked offset null for this
purpose. It can be done by connecting 10 K ohm pot between 1 and 5 as shown in fig. 3.

Fig. 3

By varying the potentiometer, output offset voltage (with inputs grounded) can be reduced to zero
volts. Thus the offset voltage adjustment range is the range through which the input offset voltage
can be adjusted by varying 10 K pot. For the 741C the offset voltage adjustment range is ± 15 mV.

Parameters of OPAMP:

7. Input Voltage Range :

Input voltage range is the range of a common mode input signal for which a differential amplifier remains
linear. It is used to determine the degree of matching between the inverting and noninverting input terminals.
For the 741C, the range of the input common mode voltage is ± 13V maximum. This means that the common
mode voltage applied at both input terminals can be as high as +13V or as low as ?13V.

8. Common Mode Rejection Ratio (CMRR).

CMRR is defined as the ratio of the differential voltage gain Ad to the common mode voltage gain ACM

CMRR = Ad / ACM.

For the 741C, CMRR is 90 dB typically. The higher the value of CMRR the better is the matching between
two input terminals and the smaller is the output common mode voltage.

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9. Supply voltage Rejection Ratio: (SVRR)

SVRR is the ratio of the change in the input offset voltage to the corresponding change in power supply
voltages. This is expressed in V / V or in decibels, SVRR can be defined as

SVRR = Vio / V

Where V is the change in the input supply voltage and Vio is the corresponding change in the offset
voltage.

For the 741C, SVRR = 150 µ V / V.

For 741C, SVRR is measured for both supply magnitudes increasing or decreasing simultaneously, with
R3 10K. For same OPAMPS, SVRR is separately specified as positive SVRR and negative SVRR.

10. Large Signal Voltage Gain:

Since the OPAMP amplifies difference voltage between two input terminals, the voltage gain of the amplifier
is defined as

Because output signal amplitude is much large than the input signal the voltage gain is commonly called
large signal voltage gain. For 741C is voltage gain is 200,000 typically.

11. Output voltage Swing:

The ac output compliance PP is the maximum unclipped peak to peak output voltage that an OPAMP can
produce. Since the quiescent output is ideally zero, the ac output voltage can swing positive or negative. This
also indicates the values of positive and negative saturation voltages of the OPAMP. The output voltage never
exceeds these limits for a given supply voltages +VCC and ?VEE. For a 741C it is ± 13 V.

12. Output Resistance: (RO)

RO is the equivalent resistance that can be measured between the output terminal of the OPAMP and
the ground. It is 75 ohm for the 741C OPAMP.

Example - 1

Determine the output voltage in each of the following cases for the open loop differential amplifier of fig. 4:

a. vin 1 = 5 m V dc, vin 2 = -7 µVdc

b. vin 1 = 10 mV rms, vin 2= 20 mV rms

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Fig. 4

Specifications of the OPAMP are given below:

A = 200,000, Ri = 2 M , R O = 75 , + VCC = + 15 V, - VEE = - 15 V, and output voltage swing = ± 14V.

Solution:

(a). The output voltage of an OPAMP is given by

Remember that vo = 2.4 V dc with the assumption that the dc output voltage is zero when the input signals
are zero.

(b). The output voltage equation is valid for both ac and dc input signals. The output voltage is given by

Thus the theoretical value of output voltage vo = -2000 V rms. However, the OPAMP saturates at ± 14
V. Therefore, the actual output waveform will be clipped as shown fig. 5. This non-sinusoidal waveform
is unacceptable in amplifier applications.

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Fig. 5

13. Output Short circuit Current :

In some applications, an OPAMP may drive a load resistance that is approximately zero. Even its output
impedance is 75 ohm but cannot supply large currents. Since OPAMP is low power device and so its output
current is limited. The 741C can supply a maximum short circuit output current of only 25mA.

14. Supply Current :

IS is the current drawn by the OPAMP from the supply. For the 741C OPAMP the supply current is 2.8 m A.

15. Power Consumption:

Power consumption (PC) is the amount of quiescent power (vin= 0V) that must be consumed by the
OPAMP in order to operate properly. The amount of power consumed by the 741C is 85 m W.

16. Gain Bandwidth Product:

The gain bandwidth product is the bandwidth of the OPAMP when the open loop voltage gain is reduced to
1. From open loop gain vs frequency graph At 1 MHz shown in. fig. 6, It can be found 1 MHz for the 741C
OPAMP frequency the gain reduces to 1. The mid band voltage gain is 100, 000 and cut off frequency is
10Hz.

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Fig. 6

17. Slew Rate:

Slew rate is defined as the maximum rate of change of output voltage per unit of time under large
signal conditions and is expressed in volts / secs.

To understand this, consider a charging current of a capacitor shown in fig. 7.

Fig. 6

If 'i' is more, capacitor charges quickly. If 'i' is limited to Imax, then rate of change is also limited.
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Slew rate indicates how rapidly the output of an OPAMP can change in response to changes in the input
frequency with input amplitude constant. The slew rate changes with change in voltage gain and is normally
specified at unity gain.

If the slope requirement is greater than the slew rate, then distortion occurs. For the 741C the slew rate is low
0.5 V / S. which limits its use in higher frequency applications.

18. Input Offset Voltage and Current Drift:

It is also called average temperature coefficient of input offset voltage or input offset current. The input offset
voltage drift is the ratio of the change in input offset voltage to change in temperature and expressed in V /°
C. Input offset voltage drift = ( Vio / T).

Similarly, input offset current drift is the ratio of the change in input offset current to the change
in temperature. Input offset current drift = ( Iio / T).

For 741C,

Vio /T = 0.5 V / C. Iio/

T = 12 pA / C.

Example - 2

An operational amplifier has a slew rate of 2 V / µs. If the peak output is 12 V, what is the power bandwidth?

Solution:

The slew rate of an operational amplifier is

As for output free of distribution, the slews determines the maximum frequency of operation fmax for a
desired output swing.

so
So bandwidth = 26.5 kHz.

Example - 3

For the given circuit in fig. 1. Iin(off) = 20 nA. If Vin(off) = 0, what is the differential input voltage?. If A =
105, what does the output offset voltage equal?

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Fig. 1

Solutin:

Iin(off) = 20 nA
Vin(off) = 0

(i) The differential input voltage = Iin(off) x 1k = 20 nA x 1 k = 20µ V

(ii) If A = 105 then the output offset voltage Vin(off) = 20 µ V x 105 = 2

volt Output offset voltage = 2 volts.

Open loop OPAMP Configuration:

In the case of amplifiers the term open loop indicates that no connection, exists between input and output
terminals of any type. That is, the output signal is not fedback in any form as part of the input signal.

In open loop configuration, The OPAMP functions as a high gain amplifier. There are three open
loop OPAMP configurations.

The Differential Amplifier:

Fig. 1, shows the open loop differential amplifier in which input signals vin1 and vin2 are applied to the
positive and negative input terminals.

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Fig. 1

Since the OPAMP amplifies the difference the between the two input signals, this configuration is called the
differential amplifier. The OPAMP amplifies both ac and dc input signals. The source resistance Rin1 and
Rin2 are normally negligible compared to the input resistance Ri. Therefore voltage drop across these
resistances can be assumed to be zero.

Therefore

v1 = vin1 and v2 = vin2.

vo = Ad (vin1 ? vin2 )

where, Ad is the open loop gain.

The Inverting Amplifier:

If the input is applied to only inverting terminal and non-inverting terminal is grounded then it is
called inverting amplifier.This configuration is shown in fig. 2.

v1= 0, v2 = vin.

vo = -Ad vin

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Fig. 2

The negative sign indicates that the output voltage is out of phase with respect to input 180 ° or is of
opposite polarity. Thus the input signal is amplified and inverted also.

The non-inverting amplifier:

In this configuration, the input voltage is applied to non-inverting terminals and inverting terminal is ground
as shown in fig. 3.

v1 = +vin v2 = 0

vo = +Ad vin

This means that the input voltage is amplified by Ad and there is no phase reversal at the output.

Fig. 3

In all there configurations any input signal slightly greater than zero drive the output to saturation level. This
is because of very high gain. Thus when operated in open-loop, the output of the OPAMP is either negative or
positive saturation or switches between positive and negative saturation levels. Therefore open loop op-amp
is not used in linear applications.

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Closed Loop Amplifier:

The gain of the OPAMP can be controlled if fedback is introduced in the circuit. That is, an output signal is
fedback to the input either directly or via another network. If the signal fedback is of opposite or out phase
by 180° with respect to the input signal, the feedback is called negative fedback.

An amplifier with negative fedback has a self-correcting ability of change in output voltage caused by
changes in environmental conditions. It is also known as degenerative fedback because it reduces the output
voltage and,in tern,reduces the voltage gain.

If the signal is fedback in phase with the input signal, the feedback is called positive feedback. In
positive feedback the feedback signal aids the input signal. It is also known as regenerative feedback.
Positive feedback is necessary in oscillator circuits.

The negative fedback stabilizes the gain, increases the bandwidth and changes, the input and output
resistances. Other benefits are reduced distortion and reduced offset output voltage. It also reduces the effect
of temperature and supply voltage variation on the output of an op-amp.

A closed loop amplifier can be represented by two blocks one for an OPAMP and other for a feedback
circuits. There are four following ways to connect these blocks. These connections are shown in fig. 4.

These connections are classified according to whether the voltage or current is feedback to the input in series
or in parallel:

 Voltage ? series feedback

 Voltage ? shunt feedback
 Current ? series feedback
 Current ? shunt feedback

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Fig. 4

In all these circuits of fig. 4, the signal direction is from input to output for OPAMP and output to input
for feedback circuit. Only first two, feedback in circuits are important.

Voltage series feedback:

It is also called non-inverting voltage feedback circuit. With this type of feedback, the input signal drives the
non-inverting input of an amplifier; a fraction of the output voltage is then fed back to the inverting input.
The op-amp is represented by its symbol including its large signal voltage gain Ad or A, and the feedback
circuit is composed of two resistors R1 and Rf. as shown in fig. 5

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Fig. 5

The feedback voltage always opposes the input voltage, (or is out of phase by 180° with respect to input
voltage), hence the feedback is said to be negative.

The closed loop voltage gain is given by

The product A and B is called loop gain. The gain loop gain is very large such that AB >> 1

This shows that overall voltage gain of the circuit equals the reciprocal of B, the feedback gain. It means that
closed loop gain is no longer dependent on the gain of the op-amp, but depends on the feedback of the voltage
divider. The feedback gain B can be precisely controlled and it is independent of the amplifier.

Physically, what is happening in the circuit? The gain is approximately constant, even though differential
voltage gain may change. Suppose A increases for some reasons (temperature change). Then the output
voltage will try to increase. This means that more voltage is fedback to the inverting input, causing v d
voltage to decrease. This almost completely offset the attempted increases in output voltage.

Similarly, if A decreases, The output voltage decreases. It reduces the feedback voltage vf and hence,
vd voltage increases. Thus the output voltage increases almost to same level.
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Different Input voltage is ideally zero.

Again considering the voltage equation,

vO = Ad vd

or vd = vO / Ad

Since Ad is very large (ideally infinite)

vd 0.

and v1 = v2 (ideal).

This says, that the voltage at non-inverting input terminal of an op-amp is approximately equal to that at
the inverting input terminal provided that Ad is very large. This concept is useful in the analysis of closed
loop OPAMP circuits. For example, ideal closed loop voltage again can be obtained using the results

Input Resistance with Feedback:

fig. 1, shows a voltage series feedback with the OPAMP equivalent circuit.

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Fig. 1
In this circuit Ri is the input resistance (open loop) of the OPAMP and Rif is the input resistance of
the feedback amplifier. The input resistance with feedback is defined as

Since AB is much larger than 1, which means that Rif is much larger that Ri. Thus Rif approaches infinity
and therefore, this amplifier approximates an ideal voltage amplifier.

Output Resistance with Feedback:

Output resistance is the resistance determined looking back into the feedback amplifier from the output
terminal. To find output resistance with feedback Rf, input vin is reduced to zero, an external voltage Vo
is applied as shown in fig. 2.

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Fig. 2

The output resistance (Rof ) is defined as

This shows that the output resistance of the voltage series feedback amplifier is ( 1 / 1+AB ) times the output
resistance Ro of the op-amp. It is very small because (1+AB) is very large. It approaches to zero for an ideal
voltage amplifier.

Bandwidth with Feedback:

The bandwidth of an amplifier is defined as the band of frequencies for which the gain remains constant. Fig. 3,
shows the open loop gain vs frequency curve of 741C OPAMP. From this curve for a gain of 2 x 10 5 the
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bandwidth is approximately 5Hz. On the other hand, the bandwidth is approximately 1MHz when the gain is
unity.

Fig. 3

The frequency at which gain equals 1 is known as the unity gain bandwidth. It is the maximum frequency the
OPAMP can be used for.
Furthermore, the gain bandwidth product obtained from the open loop gain vs frequency curve is equal to the
unity gain bandwidth of the OPAMP.
Since the gain bandwidth product is constant obviously the higher the gain the smaller the bandwidth and vice
versa. If negative feedback is used gain decrease from A to A / (1+AB). Therefore the closed loop bandwidth
increases by (1+AB).

Bandwidth with feedback = (1+ A B) x (B.W. without feedback)

ff= fo (1+A B)

Output Offset Voltage:

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In an OPAMP even if the input voltage is zero

an output voltage can exist. There are three cause
of this unwanted offset voltage.

1. Input offset voltage.

2. Input bias voltage.
3. Input offset current.

Fig. 4, shows a feedback amplifier with an output

offset voltage source in series with the open loop
output AVd. The actual output offset voltage with
negative feedback is smaller. The reasoning is
similar to that given for distortion. Some of the
output offset voltage is fed back to the inverting
input. After amplification an out of phase voltage
arrives at the output canceling most of the original
output offset voltage.

Fig. 4
When loop gain AB is much greater than 1, the
closed loop output offset voltage is much smaller
than the open loop output offset voltage.

Voltage Follower:

The lowest gain that can be obtained from a non-inverting amplifier with feedback is 1. When the non-inverting
amplifier gives unity gain, it is called voltage follower because the output voltage is equal to the input voltage
and in phase with the input voltage. In other words the output voltage follows the input voltage.

To obtain voltage follower, R1 is open circuited and Rf is shorted in a negative feedback amplifier of fig. 4.
The resultant circuit is shown in fig. 5.

vout = Avd= A (v1 ? v2)

v1 = vin

v2 =vout

v1 = v2 if A >> 1

vout = vin.

The gain of the feedback circuit (B) is 1.

Fig. 5

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Therefore

Af = 1 / B = 1

Voltage shunt Feedback:

Fig. 1, shows the voltage shunt feedback amplifier using OPAMP.

Fig. 1

The input voltage drives the inverting terminal, and the amplified as well as inverted output signal is also
applied to the inverting input via the feedback resistor Rf. This arrangement forms a negative feedback
because any increase in the output signal results in a feedback signal into the inverting input signal
causing a decrease in the output signal. The non-inverting terminal is grounded. Resistor R1 is connected
in series with the source.

The closed loop voltage gain can be obtained by, writing Kirchoff's current equation at the input node V2.

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The negative sign in equation indicates that the input and output signals are out of phase by 180.
Therefore it is called inverting amplifier. The gain can be selected by selecting Rf and R1 (even < 1).

Inverting Input at Virtual Ground:

In the fig. 1, shown earlier, the noninverting terminal is grounded and the- input signal is applied to the
inverting terminal via resistor R1. The difference input voltage vd is ideally zero, (vd= vO/ A) is the
voltage at the inverting terminals (v2) is approximately equal to that of the noninverting terminal (v1). In
other words, the inverting terminal voltage (v1) is approximately at ground potential. Therefore, it is said
to be at virtual ground.

Input Resistance with Feedback:

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To find the input resistance Miller equivalent

of the feedback resistor Rf, is obtained, i.e.
Rf is splitted into its two Miller components
as shown in fig. 2. Therefore, input
resistance with feedback Rif is then

Fig. 2

Output Resistance with Feedback:

The output resistance with feedback Rof is the

resistance measured at the output terminal of the
feedback amplifier. The output resistance can be
obtained using Thevenin's equivalent
circuit,shown in fig. 3.

iO = i a + ib

Since RO is very small as compared to Rf +(R1

|| R2 )

Therefore,i.e. iO= ia

vO = RO iO + A vd.

vd= vi ? v2 = 0 - B vO

Fig. 3

Similarly, the bandwidth increases by (1+

AB) and total output offset voltage reduces by
(1+AB).

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