SYMBIOSIS INSTITUTE OF TECHNOLOGY, PUNE

Constituent of Symbiosis International (Deemed University), Pune

Department of Electronics and Telecommunication

Engineering

Electronic Devices and Circuits

Lab Manual

Department of Electronics and Telecommunication Engineering

 SYMBIOSIS INSTITUTE OF TECHNOLOGY, PUNE
Constituent of Symbiosis International (Deemed University), Pune

Vision, Mission and PEOs of E&TC Department

Department Vision:
To be a leading source of Electronics and Telecommunication of globally competent engineers that
meets the needs of evolving industry and society.

Department Mission:

• Facilitate learning of cutting-edge technologies in association with

industry and contribute towards the latest knowledge generation for
better employability and sustainability.
• Promote innovation, research and development enabling higher
education, entrepreneurship, and lifelong learning.
• Provide a platform for harnessing leadership qualities imbibed with
social and ethical values.

Department Program Educational Objectives:

PEO1: Graduates will have a strong understanding of the basics of science and engineering as
well as analytical skills to solve real world problems.
PEO2: Graduates will gain technical proficiency in Electronics and Telecommunication field
and scale new heights in profession through lifelong learning.
PEO3: Graduates will embrace professional and ethical manners at all the levels and
constantly evolve in multidisciplinary approach leading towards sustainability.
PEO4: Graduates will utilize engineering acumen with communication skills, leadership
qualities and spirit of team work to exhibit qualities for imparting services to society.

Department of Electronics and Telecommunication Engineering

 SYMBIOSIS INSTITUTE OF TECHNOLOGY, PUNE
Constituent of Symbiosis International (Deemed University), Pune

List of Experiment

S. No. Name of Experiment

1. Study of Clipper Circuits
2. Study of Clamper Circuits
3. Find the Performance parameters of CE amplifier Av,
Ai Ri, Ro.
4. Study of JFET transfer characteristics.
5. Find the Performance parameter of JFET amplifier.
6. Study of MOSFET V-I characteristics.
7. Build and test single stage CS amplifier using FET.
Calculate Ri, Ro and Av.
8. Simulate frequency response of single stage CS amplifier (use same
circuit) and find the bandwidth.
9. Simulate Voltage-Series feedback amplifier and calculate Rif, Rof,
Avf and Bandwidth.
10. Simulate current series feedback amplifier and find Rif, Rof, Gmf
and Bandwidth.
11. Simulate LC oscillator using FET.
12. Simulate MOSFET/ CMOS Inverter.

Department of Electronics and Telecommunication Engineering

Experiment Name: Study of Clipper Circuits

Objective: In this practical, the series and parallel clipper circuits will be analysed
Theory:
The circuit with which the waveform is shaped by removing (or clipping) a portion of the
applied wave is known as a clipping circuit. This kind of processing is useful for signal shaping,
circuit protection, radars, digital and other electronic systems. In other words, clippers can
“clip” off a portion of the input signal without distorting the remaining part of the incoming
wave. The simplest form of clipping circuits is Diode clippers. These clippers can remove
signal voltages above or below a specified level.
Depending on the orientation of the diode, clippers are classified as-
1. Positive clippers
2. Negative clippers
3. Combination clippers.
There are two general categories of clippers-
1. Series clippers
2. Parallel clippers
Positive clippers:
A positive clipper is that which removes the positive half-cycles of the input voltage. During
the positive half cycle, the diode turns on and looks like a short across the output terminals.
Ideally, the output voltage is zero. On the negative half cycle, the diode is open. In that case, a
negative cycle appears across the output. But practically silicon diode takes 0.7V for
conduction Therefore the clipping level is not zero, but 0.7V.
Negative clippers:
A negative clipper is that which removes the negative half-cycles of the input voltage. If we
reverse the polarity of the diode in positive clipper circuit, we get a negative clipper. The
clipping level is at -0.7V. These both positive and negative clippers circuits are the type of
parallel clipper. The parallel configuration is defined as one where the diode is in a branch
parallel to the load.
The series and parallel clippers are shown in Figure 1.
 Figure 1: Series and parallel clipper configurations

Equipment:
1. Oscilloscope
2. Dual DC power supply
3. DMM
4. Function generator

Components:
(1) Diodes
(2) Resistors: __________________

Schematic

Figure 2: Series and parallel clipper circuits

Procedure:
1. Implement the circuit on the breadboard.
2. With the help of function generator set sine wave of 1 kHz frequency and amplitude
2Vpp approximately this is the input signal of clipper which we want to clip.
 3. Monitor output signal at terminal output terminal with the help of oscilloscope. Record
your observation as image file.
4. Repeat steps (1-3) for all clipper configurations.

Computer Simulation:
5. Build the circuit given in Figures 1 on LT Spice simulator.

6. Perform Transient Analysis following steps (1-3). Compare the results of the waveforms
generated experimentally and through simulation.

Questions:
1. What is the effect of threshold voltage of the diode on the output?
2. What is the difference between clipper and clamper?
3. What will happen of we increase the frequency of the applied input signal?
Experiment Name: Study of Clamper Circuits
Objective: In this practical, the different clamper circuit will be studied.
Theory:
A circuit that places either the positive or negative peak of a signal at a desired DC level is
known as a clamping circuit, or we can say that the clamping network is one that will clamp a
signal to a different dc level. Suppose the input signal of a clamping network is a sine wave
having a peak-to-peak value of 10V.The clamper adds the DC component and pushes the signal
upwards or downwards according to the configuration. The point should be noted here is that
the clamping circuit does not change the peak to peak or R.M.S. value of the waveform. To do
so, a clamping circuit uses a capacitor, together with a diode and a load resistor RL. The
operation of a clamper is based on the principle that charging time of a capacitor is made very
small as compared to its discharging time.

(a)

(b)
Figure 1: Clamper circuits (a) Positive (b) Negative

Equipment:
1. Oscilloscope
2. Dual DC power supply
3. DMM
4. Function Generator

Components:
(1) Dode
(2) Resistor: __________________
(3) Capacitor: __________________
Schematic

(a)

(b)
Figure 2: Clamper circuit configurations (a) Positive (b) Negative

Procedure:
1. Implement the circuit on the breadboard.
2. With the help of function generator set sine wave of 1 kHz frequency and amplitude
2Vpp approximately this is the input signal of clipper which we want to clip.
3. Monitor output signal at terminal output terminal with the help of oscilloscope. Record
your observation as image file.
4. Repeat steps (1-3) for all clipper configurations.

Computer Simulation:
5. Build the circuit given in Figures 2(a-b) on LT-Spice simulator.

6. Perform Transient Analysis following steps (1-3). Compare the results of the waveforms
generated experimentally and through simulation.

Questions:
1. How to properly set the capacitor time constant?
2. How the threshold voltage of the diode effects the output?
3. What is the reason for deviation is the simulated and experimental results?
Experiment Name: Find the performance parameters of CE amplifier 𝐀𝐯 , 𝐀𝐢 , 𝐑 𝐢 , 𝐑 𝐎

Objective: In this practical, the Performance parameters of CE amplifier will be evaluated.

Theory:
Current relations in CE configurations
𝐼𝐸 = 𝐼𝐶 + 𝐼𝐵
𝐼𝐶 = 𝐼𝐸 +𝐼𝐶𝐸𝑂
𝐼𝐶 = 𝐼𝐵
Where,
𝐼𝐶 = Collector current
𝐼𝐶𝐸𝑂 = current through collector to emitter when base is open.
 = common emitter DC current gain.  ranges between 20 - 300.
Voltage Gain:
The ratio of Output Voltage (𝑉𝑜 ) to the Input Voltage (𝑉𝑖 ) is known as voltage amplification or
voltage gain of amplifier.
𝑉
Voltage Gain (Av ) = 𝑉𝑜
𝑖

Operating Parameters of Common Emitter Amplifier:

Voltage Gain: It is the ratio of output voltage (𝑉𝑜𝑢𝑡 ) obtained to input voltage (𝑉𝑖𝑛 ).
𝑉𝑜𝑢𝑡
Av =
𝑉𝑖𝑛

Input Impedance: It is the ratio of input voltage (𝑉𝑖𝑛 ) to Input Current (𝐼𝑖𝑛 ).
𝑉𝑖𝑛
𝑍𝑖𝑛 = 𝐼𝑖𝑛

To measure the input impedance a known resistor (𝑅𝑆 ) is placed in series before the input
coupling capacitor and the impedance could be calculated using the equation.

𝑍𝑖𝑛 = 𝑅𝑆 /(Av /Av ’-1)

Where, Av = voltage gain without the resistor (𝑅𝑆 )
Av’= voltage gain with the resistor (𝑅𝑆 )

3. Output Impedance: It is the ratio of Output Voltage (𝑉𝑜𝑢𝑡 ) to Output Current (𝐼𝑜𝑢𝑡 ).
𝑉𝑜𝑢𝑡
𝑍𝑜𝑢𝑡 = 𝐼𝑜𝑢𝑡
To measure the Output impedance a known resistor (𝑅𝑆 ) is placed from output to ground and
the output impedance could be calculated using the equation.

𝑍𝑜𝑢𝑡 = (Av /Av ’-1)* 𝑅𝑆

Where,
Av = voltage gain without the resistor (Rs)
Av = voltage gain with the resistor (Rs)

4. Current Gain: It is the ratio of output current (𝐼𝑜𝑢𝑡 ).) to Input current (𝐼𝑖𝑛𝑝𝑢𝑡 ).).

𝐼𝑜𝑢𝑡
𝐴𝑖 = 𝐼
𝑖𝑛𝑝𝑢𝑡

𝐴𝑖 = - Av * 𝑍𝑖𝑛 /𝑅𝐿
The comment emitter amplifier with voltage divider biasing is shown in Figure 1. The voltage
divider biasing method is widely used because operating point of transistor can be made almost
independent of beta () and provides good stabilization of operating point. If this circuit is used
to amplify AC voltages, some more components must be added to it.

Figure 1: CE amplifier

Equipment:
1. Oscilloscope
2. Dual DC power supply
3. DMM
4. Trainer Kit
5. Function Generator

Components:
(1) BJT
(2) Resistor: __________________
(3) Connecting Wires: __________________
Schematic

Figure 2: CE amplifier with voltage divider biasing

Procedure:
1. Connect Test point 2 and Test point 3, Test point 4 and Test point 5, Test point 6 and Test
point 7, using 2mm patch cords.

2. Connect Test point 2 and Test point 3, Test point 4 and Test point 5, Test point 6 and Test
point 7, using 2mm patch cords.

3. Connect +12V DC power supply at their indicated position from external source. Switch
‘On’ the power supply.

4. For the measurement of Quiescent Point measure the VCE by connecting Voltmeter
between Test point 4 and Test point 6. Measure Collector current (𝐼𝐶 ) by connecting
Ammeter between Test point 4 and Test point 5.

5. Connect a sinusoidal signal of 10mV (p-p) at 25KHz frequency at the Test point 1 (Input
of amplifier) from external source.

6. Observe the amplified output on oscilloscope by connecting Test point 8 (output of

amplifier) to Oscilloscope.

7. Calculate Voltage gain of amplifier. Connect Load resistor of 1KΩ ohms at the output and
find the voltage gain of amplifier with load resistor.

8. Calculate input impedance, output impedance, and current gain of amplifier using the
mentioned formulas with resistance 1KΩ Ohm.

Computer Simulation:
9. Build the circuit given in Figures 2 on LTSpice simulator.

10. Perform DC operating analysis to calculate the β, α and dc bias currents.

11. Perform the AC analysis to evaluate the Input impedance, Output impedance, voltage gain
and current gain of the amplifier. Also, calculate the bandwidth of the amplifer.

12. Perform the time domain analyse to analyse the signal processing capability and input-
output phase relation.

Data Tables:
Record the values of Av , Ai , R i , R O .
Table 1: Parameters of CE amplifier
Theoretical Experimental Simulated
Voltage gain
Current gain
Input Impedance
Output Impedance

Questions:
1. Why voltage divider biasing is preferred over other types of biasing?
2. How the voltage gain can be increased?
Experiment Name: Find the performance parameter of JFET amplifier

Objective: In this practical, the important performance parameter of JFET amplifier will be
measured.

Theory:
The amplifier circuit consists of an N-channel JFET as shown in Figure 1. The amplifier circuit
is connected in a common source configuration. The amplifier is biased using the self-bias
configuration. Unlike a bipolar transistor circuit, the junction FET takes virtually no input gate
current allowing the gate to be treated as an open circuit. The self-bias configuration requires
only one dc supply to establish the desired operating point.

Figure 1: JFET amplifier

The capacitor 𝐶𝑆 across the source resistance assumes its open-circuit equivalence for
dc, allowing 𝑅𝑆 to define the operating point. Under ac conditions, the capacitor assumes
the short-circuit state and “short circuits” the effects of 𝑅𝑆 . If left in the ac, gain will be
reduced. Substituting the ac equivalent model for the JFET results in the configuration of
Figure 2. Replacing the dc supply 𝑉𝐷𝐷 by a short-circuit equivalent has grounded one end
𝑜𝑓 𝑅𝐷 . The small signal model used to calculate the input impedance, output impedance and
voltage gain is presented in Figure 2. The 𝑍𝑖𝑛 , 𝑍𝑜𝑢𝑡 and 𝐴𝑣 are calculated using the Equations 1-4.

Figure 2: Small signal model of the JFET amplifier

𝑍𝑖𝑛 = 𝑅𝐺 (1)
Setting 𝑉𝑖𝑛 = 0 V sets 𝑉𝑔𝑠 and 𝑔𝑚 𝑉𝑔𝑠 to zero, and

𝑍𝑜𝑢𝑡 ≌ 𝑅𝐷 (𝑟𝑑 = ∞Ω) (2)

The voltage gain can be calculated using Equation 4.
𝑉𝑔𝑠 = 𝑉𝑖𝑛

𝑉𝑜𝑢𝑡 = ─𝑔𝑚 𝑉𝑔𝑠 (𝑟𝑑 //𝑅𝐷 ) (3)

𝐴𝑣 ≌ ─𝑔𝑚 𝑅𝐷 (𝑟𝑑 ≥ 10𝑅𝐷 ) (4)

Frequency Response and Bandwidth

Frequency response of an amplifier is the variation in its behaviour with changes in the input
signal frequency as it shows the band of frequencies over which the output (and the gain)
remains fairly constant. The range of frequencies either big or small between 𝑓𝐿 and 𝑓𝐻 is called
the circuits bandwidth as shown in Figure 3. So, from this we are able to determine at a glance
the voltage gain (in dB) for any sinusoidal input within a given frequency range. The frequency
response is generally analysed in log domain in the form of Bode plot. Bode diagram is a
logarithmic presentation of the frequency response.
Frequency points 𝑓𝐿 and 𝑓𝐻 relate to the lower corner or cut-off frequency and the upper corner
or cut-off frequency points respectively were the circuits gain falls off at high and low
frequencies. These points on a frequency response curve are known commonly as the -3dB
(decibel) points. So, the bandwidth is simply given as:
Bandwidth = 𝑓𝐻 ─𝑓𝐿 (5)

Figure 3: Bode plot to calculate Bandwidth of an amplifier

Schematic

Figure 4: JFET amplifier for LTSpice implementation

Procedure:
Computer Simulation:
1. Calculate the theoretical input impedance, output impedance and voltage gain using
Equations 1-4.

2. Build the circuits given in Figures 2 in LTSpice simulator.

3. Select the resistor values appropriately to bias the JFET amplifier in saturation region.

4. Perform the DC operating point analysis to measure the dc drain current and node voltages
to establish that the amplifier is working in the saturation region.

5. To evaluate the input impedance, remove the input coupling capacitor 𝐶1 and perform the
AC analysis. Apply an AC current of 1A at the input node ‘G’ and measure the resulting
voltage generated at the node. The low frequency value of the generated voltage will be the
input resistance 𝑅𝑖 .

6. To evaluate the output impedance, ground the input node. Remove the output coupling
capacitor 𝐶2 and perform the AC analysis. Apply an AC current of 1A at the output node
‘D’ and measure the resulting voltage generated at the node. The low frequency value of
the generated voltage will be the input resistance 𝑅𝑜 .

7. To evaluate the voltage gain, perform the AC analysis on the circuit shown in Figure 4,
with coupling and bypass capacitors connected. Connect a load resistance 𝑅𝐿 and apply an
AC current of 1A at the input and measure the resulting voltage generated across the output
load resistance 𝑅𝐿 . The resulting voltage will be the gain of the amplifier.
8. To obtain the frequency response, perform the AC analysis on the circuit shown in Figure
4, with coupling and bypass capacitors connected. Connect a load resistance 𝑅𝐿 and apply
an AC current of 1A at the input and measure the resulting voltage generated across the
output load resistance 𝑅𝐿 . The resulting bode plot will give the frequency response of the
amplifier.

9. Also perform the time domain analysis by applying sinusoidal signal of 1Vp-p at 1kHz
frequency and observe the output. Compare the phase difference between input and output
signal.

10. Measure the lower and upper -3dB (decibel) cut off points 𝑓𝐿 and 𝑓𝐻 . Use Equation 5 to
measure the bandwidth.

11. Remove the bypass capacitor and measure the gain and bandwidth of the amplifier. Observe
the change the gain and bandwidth.

12. Compare the simulated and theoretical findings.

Questions:
1. What happens to the gain if the bypass capacitor is removed?
2. What is distortion in amplifier?
3. Why there is a 180-phase difference between input and output?
4. Why self-bias is better compared to fixed bias?
Experiment Name: Study of JFET transfer characteristics

Objective: In this practical, JFET transfer characteristics will be studied.

Theory:
Drain characteristics are obtained between the drain to source voltage (𝑉𝐷𝑆 ) and drain current
(𝐼𝐷 ) taking gate to source voltage (𝑉𝐺𝑆 ) as the constant parameter. 2. Transfer characteristics
are obtained between the gate to source voltage (𝑉𝐺𝑆 ) and drain current (𝐼𝐷 ) taking drain to
source voltage (𝑉𝐷𝑆 ) as the constant parameter.

Equipment:
1. Oscilloscope
2. Dual DC power supply
3. DMM

Components:
(1) JFET transistor: __________________
(2) Resistor (Different values): __________________ __________________

Schematic

Figure 1: Circuit for obtaining drain characteristic of JFET

Procedure:
Drain Characteristics:
1. Connect the circuit as shown in the Figure1.

2. Keep VGS = 0V by varying VGG.

3. Varying VDD gradually in steps of 1V up to 20V note down drain current ID and drain to
source voltage (VDS).
4. Repeat above procedure for VGS = -0.4, -0.8, -1.2 and -1.6 V
5. Compare the results of step 4 for different signal amplitudes and amplifier gains.
6. Save a copy of the oscilloscope display of the output wave forms.
Transfer Characteristics:

7. Set voltage VDS = 4V/8V

8. Varying VDS in steps of 0.5V until the current ID reduces to minimum value.

9. Varying VGG gradually, note down both drain current ID and gate-source voltage (VGS).

10. Repeat above procedure (step 3) for VDS = 4V/ 8V.

11. Plot the drain characteristics by taking VDS on X-axis and ID on Y-axis at a constant VGS.

12. Plot the transfer characteristics by taking VGS on X-axis and taking ID on Y-axis at
constant VDS.

Computer Simulation:
13. Build the circuit given in Figures 2 on LTSpice simulator.

14. Perform DC sweep analysis to plot the drain and transfer characteristics. Do analysis for
different JFET models available and compare the results.

Data Tables:
Experiment Name: Study of MOSFET V-I characteristics

Objective: In this practical, the voltage current characteristics of MOSFET will be studied.
Theory:
MOSFETs are four-terminal, unipolar, voltage-controlled, high input impedance devices which
form an integral part of vast variety of electronic circuits.
These devices can be classified into two types viz., depletion-type and enhancement-type,
depending on whether they possess a channel in their default state or no, respectively. Further,
each of them can be either p-channel or n-channel devices as they can have their conduction
current due to holes or electrons respectively.
In general, any MOSFET is seen to exhibit three operating regions as shown in Figure 1,
1. Cut-Off Region: Cut-off region is a region in which the MOSFET will be OFF as there
will be no current flow through it. In this region, MOSFET behaves like an open switch
and is thus used when they are required to function as electronic switches.
2. Ohmic or Linear Region: Ohmic or linear region is a region where in the current
IDS increases with an increase in the value of VDS. When MOSFETs are made to operate
in this region, they can be used as amplifiers.
3. Saturation Region: In saturation region, the MOSFETs have their IDS constant in spite
of an increase in VDS and occurs once VDS exceeds the value of pinch-off voltage VP.
Under this condition, the device will act like a closed switch through which a saturated
value of IDS flows. As a result, this operating region is chosen whenever MOSFETs are
required to perform switching operations.

Figure 1: MOSFET V-I characteristics

Equipment:
1. Dual DC power supply
2. DMM
Components:
(1) MOSFET: __________________
(2) Resistor (Different values): __________________ __________________

Schematic

Figure 2: Circuit setup for obtaining V-I characteristics

Procedure:
Drain characteristics

Transfer characteristics

Computer Simulation:
1. Build the circuit given in Figures 2 on LTSpice simulator.

2. Perform DC sweep analysis to plot the drain and transfer characteristics. Do analysis for different
MOSFET models available and compare the results.

3. Plot the drain characteristics by taking VDS on X-axis and ID on Y-axis at a constant VGS.

4. Plot the transfer characteristics by taking VGS on X-axis and taking ID on Y-axis at constant VDS.

Data Tables:
Questions:
1. What are the advantages of MOSFET over JFET?
2. To turn NMOS, how much voltage is required?
3. What are the advantages of MOSFET over BJT?
Experiment Name: Build and test single stage CS amplifier using FET. Calculate 𝐑 𝐢𝐧 , 𝐑 𝐨𝐮𝐭
and 𝐀 𝐯 .

Objective: In this practical, the single stage CS amplifier using FET will be analysied using
LTSpice circuit simulator.

Theory:
The amplifier circuit consists of an N-channel JFET as shown in Figure 1. The amplifier circuit
is connected in a common source configuration. The JFET gate voltage 𝑉𝑔𝑠 is biased through
the potential divider network set up by resistors 𝑅1 and 𝑅2 and is biased to operate within its
saturation region. Unlike a bipolar transistor circuit, the junction FET takes virtually no input
gate current allowing the gate to be treated as an open circuit.

Figure 1: CS amplifier

Substituting the ac equivalent model for the JFET results in the configuration of Figure 2.
Replacing the dc supply 𝑉𝐷𝐷 by a short-circuit equivalent has grounded one end of 𝑅1 and
𝑅𝐷 . Since each network has a common ground, 𝑅1 can be brought down in parallel with
𝑅2 . 𝑅𝐷 can also be brought down to ground, but in the output circuit
across 𝑟𝑑 . The resulting ac equivalent network now has the basic format of some of the
networks already analysed. The small model used to calculate the input impedance, output
impedance and voltage gain is presented in Figure 2. The 𝑍𝑖𝑛 , 𝑍𝑜𝑢𝑡 and 𝐴𝑣 are calculated using
the Equations 1-5.

Figure 2: Small signal model of the CS amplifier

𝑍𝑖𝑛 = 𝑅1 //𝑅2 (1)

Setting 𝑉𝑖𝑛 = 0 V sets 𝑉𝑔𝑠 and 𝑔𝑚 𝑉𝑔𝑠 to zero, and

𝑍𝑜𝑢𝑡 = 𝑟𝑑 //𝑅𝐷 (2)

The voltage gain can be calculated using Equation 5.
𝑉𝑔𝑠 = 𝑉𝑖𝑛

𝑉𝑜𝑢𝑡 = ─𝑔𝑚 𝑉𝑔𝑠 (𝑟𝐷 //𝑅𝐷 ) (3)

𝑉𝑜𝑢𝑡 ─𝑔𝑚 𝑉𝑔𝑠 (𝑟𝐷 //𝑅𝐷 )

𝐴𝑣 = = (4)
𝑉𝑖𝑛 𝑉𝑔𝑠

𝐴𝑣 ≌ ─𝑔𝑚 𝑅𝐷 (5)

Schematic

Figure 3: CS amplifier for LTSpice implementation

Procedure:
Computer Simulation:
1. Calculate the theoretical input impedance, output impedance and voltage gain using
Equations 1-5.

2. Build the circuits given in Figures 2 in LTSpice simulator.

3. Select the resistor values appropriately to bias the CS amplifier in saturation region.

4. Perform the DC operating point analysis to measure the dc drain current and node voltages
to establish that the amplifier is working in the saturation region.

5. To evaluate the input impedance, remove the input coupling capacitor 𝐶1 and perform the
AC analysis. Apply an AC current of 1A at the input node ‘G’ and measure the resulting
voltage generated at the node. The low frequency value of the generated voltage will be the
input resistance 𝑅𝑖 .
6. To evaluate the output impedance, ground the input node. Remove the output coupling
capacitor 𝐶2 and perform the AC analysis. Apply an AC current of 1A at the output node
‘D’ and measure the resulting voltage generated at the node. The low frequency value of
the generated voltage will be the input resistance 𝑅𝑜 .

7. To evaluate the voltage gain, perform the AC analysis on the circuit shown in Figure 3,
with coupling and bypass capacitors connected. Connect a load resistance 𝑅𝐿 and apply an
AC current of 1A at the input and measure the resulting voltage generated across the output
load resistance 𝑅𝐿 . The resulting voltage will be the gain of the amplifier.

8. Also perform the time domain analysis by applying sinusoidal signal of 1Vp-p at 1kHz
frequency and observe the output. Compare the phase difference between input and output
signal.

9. Compare the simulated and theoretical findings.

Questions:
1. What is the purpose of the bypass capacitor?
2. What is distortion in amplifier?
3. What is the purpose of the coupling capacitors?
Experiment Name: Simulate frequency response of single stage CS amplifier (use same
circuit) and find the bandwidth.

Objective: In this practical, the bandwidth of the single stage CS amplifier using FET will
be measured using LTSpice circuit simulator.

Theory:
The amplifier circuit consists of an N-channel JFET as shown in Figure 1. The amplifier circuit
is connected in a common source configuration. The JFET gate voltage 𝑉𝑔𝑠 is biased through
the potential divider network set up by resistors 𝑅1 and 𝑅2 and is biased to operate within its
saturation region. Unlike a bipolar transistor circuit, the junction FET takes virtually no input
gate current allowing the gate to be treated as an open circuit.

Figure 1: CS amplifier

Substituting the ac equivalent model for the JFET results in the configuration of Figure 2.
Replacing the dc supply 𝑉𝐷𝐷 by a short-circuit equivalent has grounded one end of 𝑅1 and
𝑅𝐷 . Since each network has a common ground, 𝑅1 can be brought down in parallel with
𝑅2 . 𝑅𝐷 can also be brought down to ground, but in the output circuit
across 𝑟𝑑 . The resulting ac equivalent network now has the basic format of some of the
networks already analysed. The small model used to calculate the input impedance, output
impedance and voltage gain is presented in Figure 2. The 𝑍𝑖𝑛 , 𝑍𝑜𝑢𝑡 and 𝐴𝑣 are calculated using
the Equations 1-5.

Figure 2: Small signal model of the CS amplifier

𝑍𝑖𝑛 = 𝑅1 //𝑅2 (1)

Setting 𝑉𝑖𝑛 = 0 V sets 𝑉𝑔𝑠 and 𝑔𝑚 𝑉𝑔𝑠 to zero, and
 𝑍𝑜𝑢𝑡 = 𝑟𝑑 //𝑅𝐷 (2)
The voltage gain can be calculated using Equation 5.
𝑉𝑔𝑠 = 𝑉𝑖𝑛

𝑉𝑜𝑢𝑡 = ─𝑔𝑚 𝑉𝑔𝑠 (𝑟𝐷 //𝑅𝐷 ) (3)

𝑉𝑜𝑢𝑡 ─𝑔𝑚 𝑉𝑔𝑠 (𝑟𝐷 //𝑅𝐷 )

𝐴𝑣 = = (4)
𝑉𝑖𝑛 𝑉𝑔𝑠

𝐴𝑣 ≌ ─𝑔𝑚 𝑅𝐷 (5)

Frequency Response and Bandwidth

Frequency response of an amplifier is the variation in its behaviour with changes in the input
signal frequency as it shows the band of frequencies over which the output (and the gain)
remains fairly constant. The range of frequencies either big or small between 𝑓𝐿 and 𝑓𝐻 is called
the circuits bandwidth as shown in Figure 3. So, from this we are able to determine at a glance
the voltage gain (in dB) for any sinusoidal input within a given frequency range. The frequency
response is generally analysed in log domain in the form of Bode plot. Bode diagram is a
logarithmic presentation of the frequency response.
Frequency points 𝑓𝐿 and 𝑓𝐻 relate to the lower corner or cut-off frequency and the upper corner
or cut-off frequency points respectively were the circuits gain falls off at high and low
frequencies. These points on a frequency response curve are known commonly as the -3dB
(decibel) points. So, the bandwidth is simply given as:
Bandwidth = 𝑓𝐻 ─𝑓𝐿 (6)

Figure 3: Bode plot to calculate Bandwidth of an amplifier

Schematic

Figure 4: CS amplifier for LTSpice implementation

Procedure:
Computer Simulation:
1. Build the circuits given in Figures 2 in LTSpice simulator.

2. Select the resistor values appropriately to bias the CS amplifier in saturation region.

3. Perform the DC operating point analysis to measure the dc drain current and node voltages
to establish that the amplifier is working in the saturation region.

4. To obtain the frequency response, perform the AC analysis on the circuit shown in Figure
4, with coupling and bypass capacitors connected. Connect a load resistance 𝑅𝐿 and apply
an AC current of 1A at the input and measure the resulting voltage generated across the
output load resistance 𝑅𝐿 . The resulting bode plot will give the frequency response of the
amplifier.

5. Measure the lower and upper -3dB (decibel) cut off points 𝑓𝐿 and 𝑓𝐻 . Use Equation 6 to
measure the bandwidth.

6. Remove the bypass capacitor and measure the gain and bandwidth of the amplifier. Observe
the change the gain and bandwidth.

Questions:
1. What happens to the gain if the bypass capacitor is removed?
2. What is distortion in amplifier?
3. Why there is a 180 phase difference between input and output?
Experiment Name: Simulate Voltage-Series feedback amplifier and calculate 𝐑 𝐢𝐟, 𝐑 𝐨𝐟 , 𝐀𝐯𝐟 ,
and Bandwidth

Objective: In this practical, the Voltage-Series feedback amplifier will be analysed using
LTSpice circuit simulator.

Theory:
The Figure 1 shows an FET amplifier stage with voltage-series feedback. A part of the output
signal (𝑉𝑜 ) is obtained using a feedback network of resistors 𝑅1 and 𝑅2 . The feedback voltage
𝑉𝑓 is connected in series with the source signal 𝑉𝑠 , their difference being the input signal 𝑉𝑖 .
Without feedback the amplifier gain is.

Figure 1: CS amplifier

It can be observed that the gain of the amplifier is reduced.

Schematic

Figure 2: CS amplifier for LTSpice implementation

Procedure:
Computer Simulation:
1. Build the circuits given in Figures 2 in LTSpice simulator.

2. Select the resistor values appropriately to bias the CS amplifier in saturation region.

3. Perform the DC operating point analysis to measure the dc drain current and node voltages
to establish that the amplifier is working in the saturation region.

4. To obtain the frequency response, perform the AC analysis on the circuit shown in
Figure 2, with coupling capacitor connected. Apply the AC current of 1A at the input and
measure the resulting voltage generated across the output load resistance 𝑅𝑜 . The resulting
bode plot will give the frequency response of the amplifier.

5. Measure the lower and upper -3dB (decibel) cut off points 𝑓𝐿 and 𝑓𝐻 and calculate the
bandwidth.

Questions:
1. What happens to the gain after feedback is applied?
2. Why negative feedback is preferred over positive feedback?
Experiment Name: Simulate LC oscillator using FET

Objective: In this practical, the LC oscillator will be studied.

Theory:
Most of the radio frequency oscillators fall into general form where a combination of capacitive
and inductive reactance is used to generate the required frequency. Hartley LC oscillator uses
two capacitors and one inductive in the tank circuit. The amplifier stage uses a transistor in
common emitter configuration. The basic working is similar to Hartley oscillator, where tank
circuit provides 180° phase shift and the JFET amplifier provides another 180º phase shift, to
satisfy the oscillator criterion. The frequency of oscillators is given by,
1
𝑓𝑜 =
2𝜋√𝐿𝑒𝑞 𝐶

𝐿𝑒𝑞 = 𝐿1 + 𝐿2

Schematic

Figure 1: Hartley LC oscillator

Procedure:
Computer Simulation:
1. Build the circuit given in Figures 1 on LT Spice simulator.

2. Select the values of passive components to fix the operating frequency of the oscillator.

3. Perform transient analysis to observe the generated sine wave. Evaluate the simulated
frequency and compare it with the theoretically calculated.
Data Table:

Questions:
1. What is the difference between Hartley and Colpitts Oscillator?
2. Which type of feedback is used in oscillator?
3. What are Barkhausen conditions for Oscillation?
Experiment Name: Simulate MOSFET/ CMOS Inverter

Objective: In this practical, the CMOS inverter circuit will be simulated using LTSpice
software.

Theory:
The inverter is universally accepted as the most basic logic gate doing a Boolean operation on
a single input variable. Figure 1 depicts the general structure of a CMOS inverter. As shown,
the simple structure consists of a combination of an PMOS transistor at the top and a NMOS
transistor at the bottom.
CMOS is also sometimes referred to as complementary-symmetry metal–oxide–
semiconductor. The words "complementary-symmetry" refer to the fact that the typical digital
design style with CMOS uses complementary and symmetrical pairs of p-type and n-type metal
oxide semiconductor field effect transistors (MOSFETs) for logic functions. Two important
characteristics of CMOS devices are high noise immunity and low static power consumption.
Significant power is only drawn while the transistors in the CMOS device are switching
between on and off states. Consequently, CMOS devices do not produce as much waste heat
as other forms of logic, for example transistor-transistor logic (TTL) or NMOS logic, which
uses all n-channel devices without p-channel devices.

(a)

(b)
Figure 1: CMOS Inverter (a) Circuit (b) VTC
Schematic

Figure 2: LTSpice CMOS inverter circuit

Procedure:
Computer Simulation:
6. Build the inverter circuit given in Figures 2 on LTSpice simulator.

7. Perform the DC sweep analysis. Sweep the DC input voltage from ─𝑉𝑆𝑆 to +𝑉𝐷𝐷 and plot
output voltage transfer characteristic (VTC).

8. Note down the point where input intersects the VTC. The point is the threshold voltage of
the inverter. Also, observe which the maximum current flows in the inverter circuit.

9. Perform transient analysis with Sine waveform as input observe the output.

Questions:
1. Why is CMOS logic preferred over BJT?
2. What are the different types of power dissipation that happen in a CMOS inverter?
3. How a CMOS inverter better compared to NMOS resistive inverter?