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BLDC - PMSM Control Application Hardware Design Guidelines

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Z8F80032532

Z8F80032532

TLE987x/6x
Hardware design guideline
Application note

About this document


Scope and purpose
The MOTIXTM MCUs integrate on a single die a 32-bit microcontroller, non-volatile flash memory, analog and
mixed-signal peripherals, communication interfaces along with the driving stages needed for either relay, half-
bridge or full-bridge DC and BLDC motor applications. The MOTIXTM MCU is an industry standard
microcontroller processor (32-bit Arm®* Cortex®-M core) in leading-edge automotive qualified technology
(130 nm smart power process).
The TLE987x/6x family addresses a wide range of smart 3-phase (TLE987x) and 2-phase (TLE986x) brushless
DC motor control applications, like engine cooling fans, auxiliary pumps and fans, sunroof, window lift.
This application note provides the reader with detailed descriptions about hardware design guidelines for the
external components when using the TLE987x/6x devices.

Intended audience
This application note is addressed to embedded hardware and software developers using the TLE987x/6x
devices to design ECUs (electronic control units) for BLDC/PMSM motor control applications.

*
Arm and Cortex are registered trademarks of Arm Limited, UK

Application note Please read the sections “Important notice” and “Warnings” at the end of this document Rev. 1.1
www.infineon.com 2022-04-01
TLE987x/6x
Hardware design guideline
Table of contents

Table of contents
About this document ......................................................................................................................... 1
Table of contents .............................................................................................................................. 2
1 TLE987x/6x family .................................................................................................................... 4
1.1 TLE987x/6x block diagram ...................................................................................................................... 4
1.2 TLE987x/6x family comparison ............................................................................................................... 5
1.3 Application information .......................................................................................................................... 6
2 Power supply generation unit (PGU) .......................................................................................... 9
2.1 Block diagram.......................................................................................................................................... 9
2.2 Input voltage, VS pre-regulator VPRE, and reference voltage VAREF.................................................. 10
2.3 VDDP voltage regulator 5.0 V ................................................................................................................ 12
2.4 VDDC voltage regulator 1.5 V ................................................................................................................ 12
2.5 VDDEXT voltage regulator 5.0 V ............................................................................................................ 13
3 Clock generation unit (CGU) .....................................................................................................14
3.1 Block diagram........................................................................................................................................ 14
3.2 External Input Clock mode.................................................................................................................... 15
3.3 External Crystal mode ........................................................................................................................... 16
3.3.1 Ceramic resonator............................................................................................................................ 17
3.4 Layout recommendations ..................................................................................................................... 17
4 General purpose inputs outputs (GPIO) .....................................................................................18
4.1 Pull-up and pull-down devices and pin state ....................................................................................... 18
4.2 Software settings and hardware considerations ................................................................................. 19
4.3 Serial resistor for high-speed signals ................................................................................................... 19
5 LIN transceiver ........................................................................................................................21
6 High-voltage monitor input ......................................................................................................22
6.1 Block diagram........................................................................................................................................ 22
6.2 Application hints ................................................................................................................................... 22
7 Analog to digital converters (ADC1) ...........................................................................................23
7.1 Software settings and hardware considerations ................................................................................. 23
7.2 Signals ADC1 .......................................................................................................................................... 23
7.3 ADC1 measuring principle ..................................................................................................................... 23
7.4 ADC1 external components design....................................................................................................... 23
7.4.1 Anti-aliasing filter design ................................................................................................................. 24
8 Sigma-delta analog digital converters (ADC3/4) .........................................................................26
8.1 Software settings and hardware considerations ................................................................................. 26
8.2 ADC3/4 measuring principle ................................................................................................................. 26
8.3 ADC3/4 external components design ................................................................................................... 26
9 Bridge driver (excluding charge pump) .....................................................................................29
9.1 Application diagram .............................................................................................................................. 29
9.2 External components ............................................................................................................................ 30
10 Charge pump ..........................................................................................................................33
10.1 Application diagram .............................................................................................................................. 33
10.2 Charge pump: how it works .................................................................................................................. 33
10.2.1 ICP load current calculation ............................................................................................................ 36
10.3 Charge pump external capacitors design............................................................................................. 41
10.3.1 Calculation example ........................................................................................................................ 42

Application note 2 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Table of contents

11 Current sense amplifier ...........................................................................................................43


11.1 Block diagram........................................................................................................................................ 43
11.2 Functional description .......................................................................................................................... 43
11.3 DC characteristics .................................................................................................................................. 44
11.3.1 AC characteristics ............................................................................................................................. 45
11.4 Application hints ................................................................................................................................... 47
11.4.1 Shunt resistor selection ................................................................................................................... 48
11.4.2 Filter network selection ................................................................................................................... 50
11.4.3 Conclusions ...................................................................................................................................... 53
12 Sensor interfaces ....................................................................................................................55
12.1 Implementing different interface connections to TLE987x/6x ............................................................ 55
13 SWD (serial wire debug) interface circuitry ................................................................................57
13.1 Description of the SWD interface .......................................................................................................... 57
13.2 Implementing an SWD interface connection to TLE987x/6x ............................................................... 57
14 Unused pins ............................................................................................................................59
15 Layout guidelines ....................................................................................................................60
15.1 General PCB recommendations ........................................................................................................... 60
15.1.1 Placement of the connectors ........................................................................................................... 61
15.1.2 Floor-planning the PCB .................................................................................................................... 61
15.1.3 Routing the power supply traces ..................................................................................................... 62
15.1.4 Number of PCB layers ...................................................................................................................... 63
15.2 Specific PCB design rules for microcontroller with bridge drivers ...................................................... 64
15.2.1 GND concept ..................................................................................................................................... 64
15.2.2 Layout recommendation for 3-phase motor bridge ....................................................................... 66
15.2.3 Layout recommendation for a current sense shunt ....................................................................... 68
Revision history ...............................................................................................................................69
Disclaimer .......................................................................................................................................70

Application note 3 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
TLE987x/6x family

1 TLE987x/6x family
The TLE987x/6x is a single-chip 3-phase/2-phase motor driver that integrates the industry standard
Arm® Cortex®-M3 core, enabling the implementation of advanced motor control algorithms such as
field-oriented control.
It includes six (TLE987x) or four (TLE986x) fully integrated NFET drivers optimized to drive a 3-phase or 2-phase
motor via external power NFETs, programmable current sources along with slope control for optimized EMC
behavior and an integrated charge pump enabling low-voltage operation. Its peripheral set includes a current
sense amplifier, a successive approximation ADC optionally synchronized with the capture and compare unit
for PWM control, and 16-bit timers. A LIN transceiver to enable communication with the device and several
general-purpose I/O units are also integrated. It includes an on-chip linear voltage regulator to supply external
loads.
Unlike the other members of the TLE987x family, the TLE9879-2QXA40 incorporates two 14-bit sigma-delta
ADCs, which provide a reliable interface for an external GMR/TMR sensor.

1.1 TLE987x/6x block diagram


Figure 1 shows the block diagram of the TLE987x. The TLE986x differs from the TLE987x since it integrates two
bridge drivers, instead of three.

Figure 1 Block diagram of the TLE987x

In the variants with the sigma-delta ADCs, the XTAL1 and XTAL2 pins for the external oscillator are not available.

Application note 4 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
TLE987x/6x family

1.2 TLE987x/6x family comparison


Table 1 and Table 2 list the variants available in the TLE987x/6x product family. The versions with the
sigma-delta ADCs are named using the scheme TLE987x-2Qx.

Table 1 TLE987x product family variants


Product Package Flash RAM Max. operating Interfaces Tj max.
frequency
TLE9871QXA20 VQFN-48 36 kByte 3 kByte 24 MHz PWM 150°C
TLE9873QXW40 VQFN-48 48 kByte 3 kByte 40 MHz PWM + LIN 175°C
TLE9877QXA20 VQFN-48 64 kByte 6 kByte 24 MHz PWM + LIN 150°C
TLE9877QXA40 VQFN-48 64 kByte 6 kByte 40 MHz PWM + LIN 150°C
TLE9877QXW40 VQFN-48 64 kByte 6 kByte 40 MHz PWM + LIN 175°C
TLE9877QTW40 TQFP-48 64 kByte 6 kByte 40 MHz PWM + LIN 175°C
TLE9879QXA20 VQFN-48 128 kByte 6 kByte 24 MHz PWM + LIN 150°C
TLE9879-2QXA40 VQFN-48 128 kByte 6 kByte 40 MHz PWM + LIN 150°C
TLE9879QXA40 VQFN-48 128 kByte 6 kByte 40 MHz PWM + LIN 150°C
TLE9879QXW40 VQFN-48 128 kByte 6 kByte 40 MHz PWM + LIN 175°C
TLE9879QTW40 TQFP-48 128 kByte 6 kByte 40 MHz PWM + LIN 175°C
TLE9872-2QXA40 VQFN-48 256 kByte 8 kByte 40 MHz PWM + LIN 150°C
TLE9872QXA40 VQFN-48 256 kByte 8 kByte 40 MHz PWM + LIN 150°C
TLE9872QTW40 TQFP-48 256 kByte 8 kByte 40 MHz PWM + LIN 175°C

Table 2 TLE986x product family variants


Product Package Flash RAM Max. operating Interfaces Tj max.
frequency
TLE9861QXA20 VQFN-48 36 kByte 3 kByte 24 MHz PWM 150°C
TLE9867QXA40 VQFN-48 64 kByte 6 kByte 40 MHz PWM + LIN 150°C
TLE9867QXA20 VQFN-48 64 kByte 6 kByte 24 MHz PWM + LIN 150°C
TLE9867QXW20 VQFN-48 64 kByte 6 kByte 24 MHz PWM + LIN 175°C
TLE9868QXB20 VQFN-48 128 kByte 4 kByte 20 MHz PWM + LIN 150°C
TLE9869QXA20 VQFN-48 128 kByte 6 kByte 24 MHz PWM + LIN 150°C
TLE9862QXA40 VQFN-48 256 kByte 8 kByte 40 MHz PWM + LIN 150°C

Application note 5 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
TLE987x/6x family

1.3 Application information


Figure 2 and Figure 3 show the TLE987x in an electric-drive application setup controlling a BLDC motor. This is a
very simplified example of an application circuit and bill of materials. The function must be verified in the
actual application. The TLE986x differs from the TLE987x since it has two bridge drivers, instead of three.

Rev. polarity protection

LPF ILT

VBAT
CPF ILT1 CPF ILT2

CVDDP2 CVDDP1 CVDDC1 CVDDC2


EMC filter

DVS
VDDP VDDC
VS CP1H
CVS 2 CVS 1 CCPS1
CP1L
CP2H CCPS2
CP2L
RMON
IGN VCP
MON RVS D CVCP
CMON
VSD
CVS D
RVDH
VDH
LIN LIN CVDH
CLIN D
GND_LIN RGA TE
G

VAREF GH1 TH1 CPH 1


CVA REF RGS CGS
1)
GND_REF S
D
SH1
CEM CP1 G

RGA TE TH2 CPH 2


VDDEXT GH2 RGS CGS
CVDD_EX T2 CVDD_EX T1
RVDDPU D
S
TLE4946-2K SH2
Hall P0.3 CEM CP2 G
RADC
CADC RGA TE TH3 CPH 3
RVDDPU
GH3 RGS CGS
TLE4946-2K
Hall
RADC
P1.4 SH3 S
CADC
U
RVDDPU CEM CP3
D V
RGA TE
TLE4946-2K G W
Hall
RADC P0.2 GL1
CADC TLE987x RGS CGS
TL1

RGA TE
S
G
D
M
GL2
Temperature TL2

sensor P2.2 RGS CGS


D
RGA TE S
G
GL3
TL3
P1.2 RGS CGS

S
SL
ROP AFI LT
OP2 RGA TE

COP AFI LT RShunt

P1.0 OP1 RGA TE


ROP AFI LT
P1.1 Input protection
P2.0 circuit
RESET Input protection
P2.3 circuit
Input protection
P2.4 circuit
TMS
Debug connector
P0.0 P0.1
P0.4
GND P2.5
RTM S
P1.3
GND
BLDC system

1)
Note: Not connected to board GND.

Figure 2 Application schematic example for TLE987x

Application note 6 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
TLE987x/6x family

Rev. Polarity Protection

LPF ILT

VBAT
CPF ILT1 CPF ILT2

CVDDP2 CVDDP1 CVDDC1 CVDDC2


EMC Filter

DVS
VDDP VDDC
VS CP1H
CVS 2 CVS 1 CCPS1
CP1L
CP2H CCPS2
CP2L
RMON
IGN VCP
MON RVS D CVCP
CMON
VSD
CVS D
RVDH
VDH
LIN LIN CVDH
CLIN D
GND_LIN RGA TE
G

VAREF GH1 TH1 CPH 1


CVA REF RGS CGS
1)
GND_REF S
D
SH1
CEM CP1 G

RGA TE TH2 CPH 2


VDDEXT GH2 RGS CGS
CVDD_EX T2 CVDD_EX T1
D
S
SH2
CEM CP2 G
RSI N_P RGA TE TH3 CPH 3
VDD
SIN_P P2.0/ADC3.P GH3 RGS CGS
RSI N_N
SIN_N P2.2/ADC3.N SH3 S
RCOS_P U
TLE5009 COS_P P2.4/ADC4.P CEM CP3
COS_N RCOS_N
P2.5/ADC4.N D V
RGA TE
VGMR P2.3 G W
GND GND GL1
TLE9872-2QTW40 RGS CGS
TL1
CCOS_N

CCOS_P
CVG MR

CSI N_N

CSI N_P

RGA TE
S
G
D
M
GL2
TL2
RGS CGS
D
RGA TE S
P0.3 G
GL3
P0.2 TL3
RGS CGS
P0.1
S
P0.4 SL
ROP AFI LT
P1.4
OP2 RGA TE
P1.3
COP AFI LT RShunt
P1.2
P1.1 OP1 RGA TE
ROP AFI LT
P1.0
RESET

TMS
Debug Connector
P0.0
GND
RTM S

GND
BLDC System

1)
Note: Not connected to board GND.

Figure 3 Application schematic example for TLE987x-2QX

Table 3 External components (BOM)


Symbol Function Component (typical)
CVS1 Filter capacitor at VS pin (TLE987x supply) ≥ 100 nF
CVS2 Bulk capacitor at VS pin (TLE987x supply) > 2.2 μF
CVDDP Output capacitor at VDDP pin (voltage regulator) 470 nF + 100 nF
CVDD_EXT Output capacitor at VDD_EXT pin (voltage regulator) 100 nF
CVDDC Output capacitor at VDDC pin (voltage regulator) 470 nF + 100 nF
CVAREF Filter capacitor at VAREF pin (analog reference) 100 nF
CLIN Filter capacitor at LIN pin 220 pF
CVSD Filter capacitor at VSD pin (charge pump supply) 1 μF
CCPS1 Charge pump capacitor (first stage flying capacitor) 220 nF
CCPS2 Charge pump capacitor (second stage flying capacitor) 220 nF
CVCP Charge pump capacitor (output bulk capacitor) 470 nF
CMON Filter capacitor at MON pin (high-voltage monitor input) 10 nF
CVDH Filter capacitor at VDH pin (drain high-side MOSFET driver) 3.3 nF
Application note 7 Rev. 1.1
2022-04-01
TLE987x/6x
Hardware design guideline
TLE987x/6x family

Symbol Function Component (typical)


CPH1 Bulk capacitor at drain high-side FET (phase U) 220 μF
CPH2 Bulk capacitor at drain high-side FET (phase V) 220 μF
CPH3 Bulk capacitor at drain high-side FET (phase W) 220 μF
COPAFILT Filter capacitor at OP1 and OP2 pins (CSA inputs) Application related
CEMCP1 Filter capacitor at SH1 pin (source high-side FET 1) 1 nF
CEMCP2 Filter capacitor at SH2 pin (source high-side FET 2) 1 nF
CEMCP3 Filter capacitor at SH3 pin (source high-side FET 2) 1 nF
CPFILT1 , CPFILT2 Filter capacitors of the input π-filter Application related
DVS Reverse-polarity protection diode Application related
LPFILT Filter inductor of the input π-filter Application related
RMON Filter resistor at MON pin 3.9 kΩ
RVSD Filter resistor at VSD pin 2Ω
RVDH Filter resistor at VDH pin 1 kΩ
RGATE FET gate resistor 2Ω
ROPAFILT Filter resistor at OP1 and OP2 pins (CSA inputs) Application related
RShunt Shunt resistor Application related
RGS FET gate-source resistor Application related
CGS FET gate-source resistor Application related
RVDDPU Pull-up resistor for Hall sensor Application related
RADC Filter resistor at ADC1 input Application related
CADC Filter capacitor at ADC1 input Application related
RTMS Pull-down resistor at TMS pin (test mode select) Optional
RSIN_P / RSIN_N Filter resistors at ADC3 input pins (sigma-delta version) 10 kΩ
RCOS_P / RCOS_N Filter resistors at ADC4 input pins (sigma-delta version) 10 kΩ
CSIN_P / CSIN_N Filter capacitors at ADC3 input pins (sigma-delta version) 68 nF
CCOS_P / CCOS_N Filter capacitors at ADC4 input pins (sigma-delta version) 68 nF
CVGMR Filter capacitor at GPIO input pin (GMR bridge voltage) 4.7 nF

Application note 8 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Power supply generation unit (PGU)

2 Power supply generation unit (PGU)


The power management unit (PMU) is responsible for generating all required voltage supplies for the
embedded MCU (VDDC, VDDP) as well as for the external supply (VDDEXT).

2.1 Block diagram


Figure 4 shows the structure of the PMU, where the power supply generation unit (PGU) includes the voltage
regulators for the pad supply (VDDP), the core supply (VDDC) and the voltage regulator to supply external
circuits (VDDEXT).

VS

VPRE

VDDP VDDEXT VDDEXT


Power-down supply
5V 5V
CVDDEXT
GND (pin 39)
VDDP
CVDDP
GND (pin 39)
VDDC VDDC
PMU-PCU
1.5 V CVDDC
GND (pin 39)

Power supply generation (PSG)

PMU

Figure 4 Power supply generation block diagram

The submodules of the PMU are:


 Power-down supply: independent analog supply voltage generation for power control unit logic, for the
VDDP regulator and for the VDDC regulator
 VPRE: analog supply voltage pre-regulator. This regulator reduces the power dissipation for the following
regulator stages
 VDDP: 5-V digital voltage regulator used for internal modules and all GPIOs
 VDDC: 1.5-V digital voltage regulator used for internal microcontroller modules and core logic
 VDDEXT: 5-V digital voltage regulator used for external circuits
 PMU-PCU: power control unit responsible for supervising and controlling the 5-V regulator and the
1.5-V regulator

Application note 9 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Power supply generation unit (PGU)

2.2 Input voltage, VS pre-regulator VPRE, and reference voltage VAREF


The VS input is the supply voltage of the VPRE pre-regulator and the power-down supply. VS is derived from the
battery voltage (VBAT), and, if necessary, it must be protected against reverse battery connections using a
diode (DVS) in series to VBAT. The Infineon application note “Reverse Polarity Protection for Embedded
Power ICs” provides a detailed description of the complete circuit for reverse battery protection.
The CVS1 and CVS2 capacitors, placed before the VS pin, respectively act as a filter and a bulk capacitor for the
TLE987x/6x power supply.

Figure 5 Components before VS pin

If data should be saved in the flash memory at power down, the selection of CVS2 should be done in order to
ensure that operations modifying the content of the flash are never interrupted (for example, in case of power
loss). Assuming that at power loss detection all the peripherals are disabled, the power is still consumed by the
MCU and flash erase and write operations. The size of CVS2 can be calculated using the equation:
𝐼×𝑡
𝐶𝑉𝑆2 ≥
∆𝑉
Where:
 I is the current consumption at power down
 t is the time for which the MCU should stay active after power loss
 ΔV is the difference between the voltage at the time when the loss of power is detected and the reset voltage
of the MCU
As reported in the TLE987x/6x product datasheets, the supply voltage in Active mode with reduced
functionality (full MCU and flash operation) has a minimum value of 3 V. For example, assuming 10 mA as the
current consumption during power down, 20 ms as the time needed to save the flash content, and 3 V as ΔV,
then CVS2 must be at least 67 µF.

Table 4 shows the recommended components to connect before the VS pin.

Application note 10 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Power supply generation unit (PGU)

Table 4 Component selection for VS pin


Symbol Function Recommended component
DVS Diode for reverse battery protection PN or Schottky diode
Voltage and current ratings defined according to the
application
CVS1 Filter capacitor Ceramic capacitor
Min. value 100 nF type: X7R
Voltage rating and dielectric type defined according
to the application
CVS2 Bulk capacitor Electrolytic or ceramic capacitor
Min. value 2.2 µF type: X7R
Value, voltage rating, and temperature defined
according to the application

The voltage pre-regulator VPRE generates an internal voltage of about 7 V from the VS input. The output
voltage of VPRE is used as input for the internal voltage regulators, and it is not accessible externally.
The IPRE current is shared between the VDDP and VDDEXT voltage regulators. The table summarizes the
maximum currents allowed for each voltage regulator.

Linear regulator Maximum current


VPRE IPRE = 110 mA
IPRE = IDDP + IDDEXT
VDDP IDDP = 90 mA
IDDEXT = 20 mA
VDDEXT IDDEXT = 40 mA
IDDP = 70 mA
VDDC IDDC = 40 mA

The voltage VAREF is derived from VPRE and it can be used as 5 V reference voltage for the internal
AD converters. The value of the capacitor CVAREF is in the range of 100 nF up to 1 μF.

Application note 11 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Power supply generation unit (PGU)

2.3 VDDP voltage regulator 5.0 V


This 5-V voltage regulator provides the pad supply for the parallel port pins and other 5-V analog functions (for
example, the LIN transceiver).

Notes
1. The output capacitor CVDDP is necessary for the stability of the output voltage.
2. The values of the CVDDP capacitors are specified in the table below.
3. One single ceramic capacitor can be used, as long as the value is within the recommended range.
4. The CVDDP capacitor should be placed as close as possible to the VDDP pin in the layout.
5. For EMC reasons, a ferrite bead can be placed between the VDDP pin and the CVDDP capacitor.

Table 5 Capacitor selection for VDDP


Symbol Function Recommended component
CVDDP Output capacitor at VDDP Ceramic capacitor
Min. value: 470 nF + 1 µF (1.47 µF) type: X7R
Max. value: 2.2 µF + 2.2 µF (4.4 µF) type: X7R
Voltage rating: 10 V or higher
Size and dielectric type defined according to the
application

2.4 VDDC voltage regulator 1.5 V


This 1.5-V voltage regulator provides the power supply for the microcontroller core, the digital peripherals, and
other internal analog 1.5-V functions (for example, ADC2).

Notes
1. The output capacitor CVDDC is necessary for the stability of the output voltage.
2. The values of the CVDDC capacitors are specified in the table below.
3. One single ceramic capacitor can be used, as long as the value is within the recommended range.
4. The CVDDC capacitor should be placed as close as possible to the VDDC pin in the layout.
5. It is NOT possible to place a ferrite bead between the VDDC pin and the CVDDC capacitor.
6. For EMI reasons the ground of the VDDC and the ground of the TLE987x/6x can be separated by placing a ferrite
bead between the two ground points.

Table 6 Capacitor selection for VDDC


Symbol Function Recommended Component
CVDDC Output capacitor at VDDC Ceramic capacitor
Min. value: 100 nF + 330 nF (430 nF) type: X7R
Max. value: 1 µF + 1 µF (2 µF) type: X7R
Voltage rating: 4 V or higher
Size and dielectric type defined according to the
application

Application note 12 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Power supply generation unit (PGU)

2.5 VDDEXT voltage regulator 5.0 V


This 5-V voltage regulator supplies power to external circuits. It can be used, for example, to supply an external
sensor, LEDs, or potentiometers. VDDEXT can be used as the reference for SDADC (ADC3/4), if available in the
product variant.

Notes
1. The output capacitor CVDDEXT is necessary for the stability of the output voltage.
2. The values of the CVDDEXT capacitors are specified in the table below.
3. One single ceramic capacitor can be used, as long as the value is within the recommended limits.
4. The CVDDEXT capacitor should be placed as close as possible to the VDDEXT pin in the layout.
5. In case VDDEXT is not used and disabled, the output capacitor CVDDEXT is not needed. The pin VDDEXT can be
left open.

Table 7 Capacitor selection for VDDEXT


Symbol Function Recommended component
CVDDEXT Output capacitor at VDDEXT Ceramic capacitor
Min. value: 100 nF + 1 µF (1.1 µF) type: X7R
Max. value: 2.2 µF + 2.2 µF (4.4 µF) type: X7R
Voltage rating: 10 V or higher
Dielectric type defined according to the application

Application note 13 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Clock generation unit (CGU)

3 Clock generation unit (CGU)


The clock generation unit (CGU) enables a flexible clock generation. The frequency can be modified to optimize
performance-to-power-consumption ratio. The system clock fSYS can be generated from one of the following
sources:
 Phase-locked loop (PLL) output fPLL
 External clock from external crystal oscillator fOSC
 External clock from external clock input fOSC
 Low-precision clock fLP_CLK

3.1 Block diagram


The CGU consists of a high-precision oscillator circuit (OSC_HP), a PLL module with an internal oscillator
(OSC_PLL), and a configurable clock control unit (CCU). The CGU can convert a low-frequency input or external
clock signal to a high-frequency internal clock.

CGU
OSC_CON PLLCON
CMCON1 SYSCON0

XTAL1 PLL
OSC_HP fPLL
XTAL2
Int
Osc
fOSC_int CCU fSYS

fLP_CLK

LP_CLK

PMU

Figure 6 CGU block diagram

The submodules of the CGU are:


 High-precision oscillator circuit: designed to work with either an external crystal oscillator or an external
stable clock source. It consists of an inverting amplifier with XTAL1 as the input and XTAL2 as the output.

Application note 14 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Clock generation unit (CGU)

 Phase-locked loop (PLL) module: generates the clock fPLL in different modes:
− Prescaler mode (VCO Bypass mode)
− Normal mode
− Free-running mode

The reference frequency fR can be selected to be taken either from the internal oscillator fINT or from an
external clock source fOSC_INT.
The PLL uses up to three dividers to manipulate the reference frequency in a configurable way. Each of
the three dividers can be bypassed corresponding to the PLL operating mode.

 Clock control unit (CCU): enables the selection of the source for fSYS

3.2 External Input Clock mode


The External Input Clock mode is used to directly supply the device with an externally generated clock signal in
the range from 4 MHz to 16 MHz. In this mode, the high-precision oscillator circuit is bypassed and the external
clock signal is directly fed into the PLL module. The input frequency has to be 4 MHz or higher, if the prescaler
mode is used.
The external clock input has to be connected to XTAL1, while XTAL2 is left open (not connected). The negative
terminal of the external clock input has to be connected to the analog GND (pin 39).

External digital VDDP


oscillator

OSC_HP
XTAL1
fXTAL1 fOSC_int

Not XTAL2
connected

Figure 7 External Input Clock mode

Application note 15 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Clock generation unit (CGU)

3.3 External Crystal mode


The External Crystal mode is used to supply the device with an external crystal within in the range from 4 MHz
to 16 MHz. An external oscillator circuity has to be placed, consisting of two load capacitors connected to
XTAL1/GND and XTAL2/GND and an optional serial damping resistor at XTAL2. The GND pin is in this case the
analog GND (pin 39).

External crystal VDDP


or resonator

OSC_HP
XTAL1
fOSC_int

fOSC

XTAL2
RXTAL2

CXTAL1 CXTAL2
GND = pin 39 = VSS

Figure 8 External Crystal mode

The values and the corresponding operating ranges depend on the chosen crystal and have to be determined
and optimized in cooperation with the crystal vendor, using the negative resistance method, which is the most
common test for start-up and oscillation reliability of the oscillator. This method is about the insertion of a test
resistor in series with the quartz crystal and the monitoring of the drive current. Typically, this test does not
result in one set of circuitry values which is the ‘right one’, but it indicates a recommended range. Depending
on further system requirements such as XTAL1 amplitude specification or oscillator frequency, the final
circuitry values of the oscillator are then selected.
More information about the test method can be found in the Infineon application note “Crystal Oscillator
Basics AP56002”.

Symbol Function Recommended component


CXTAL1, Load capacitors for external crystal ≥ 10 V ceramic capacitor X7R/X8R
CXTAL2 oscillator forming an LC tank circuit (low ESR, 0805 package)
which determines the oscillator
frequency
RXTAL2 Serial damping resistor 0-280 Ω

The oscillator can operate for a specified set of crystals with known ESR and parasitic capacitances CIO and CO
up to a specific value.
Choosing different crystals requires detailed consideration of parasitics, external circuitry, frequency range,
and quality of the intended crystal. Its proper operation has to be verified by testing.

Application note 16 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Clock generation unit (CGU)

Table 8 Recommendation for oscillator load capacitors


fOSC 4 MHz 8 MHz 12 MHz 16 MHz
ESRtyp / Ω 120 90 80 70
CIO / pF 3.5 3.5 3.5 3.5
CO / pF 3 3 3 3
CXTAL1 = CXTAL2 / pF 33 18 12 12

3.3.1 Ceramic resonator


Some applications do not require highest clock accuracy, especially for lower temperatures it might not be
necessary to use a quartz crystal and a ceramic resonator can be used instead. These integrated resonator
circuits don’t need additional load capacitors and damping resistors and can be directly connected to XTAL1/2.

3.4 Layout recommendations


Figure 9 shows a layout example for an SMD quartz crystal to be used with the TLE987x/6x.

GND XTAL1 XTAL2

Via to ground island Single ground


and global ground island
Via to ground
island RXTAL2
GND
CXTAL1 CXTAL2

SMD
quartz crystal

Figure 9 CGU layout recommendation

Application note 17 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
General purpose inputs outputs (GPIO)

4 General purpose inputs outputs (GPIO)


The TLE987x/6x has two bidirectional ports (P0, P1) and one analog port (P2). Each pin (n = 0-7) of each
port (x = 0-2) can individually be configured as an input or output by setting the respective Pn bitfield in the
Px_DIR register. If configured as an output, the pin state can be set to high or low by setting the respective
Pn bitfield in the Px_DATA register. Additionally, the pin state can be set to tristate or high impedance with
weak pull-up/pull-down termination by activating the internal pull-up or pull-down devices.
This allows the following output characteristics:
 Push/pull
 Open drain (OD) with internal pull-up device
 OD with external pull-up

And the following input characteristics:


 Tristate
 High-impedance (HI) with weak pull-up termination
 HI with weak pull-down termination

4.1 Pull-up and pull-down devices and pin state


The internal pull-up and pull-down devices can be active to determine the pin state (logical high or low), if no
external source or sink tries to determine the pin state. If the pin voltage is changed by an external source or sink,
a keep or force current will flow from the pull-up or pull-down device, trying to keep or force the pulled state.
This is called a weak termination, since the maximal current to keep the pull-up or pull-down state the devices
can provide is relatively low. The currents that will flow for a specific deviation from the target voltage state are
specified in the electrical characteristics of the parallel ports. These values differ between P0/P1 and P2.

Application note 18 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
General purpose inputs outputs (GPIO)

4.2 Software settings and hardware considerations


A specific GPIO can only be used as an input or an output at the same time. When using the internal pull-up or
pull-down devices, no external pull-up or pull-down shall be used.

Table 9 GPIO configuration settings


State Px_DIR.Pn Px_DATA.Pn Px_OD.Py Px_PUDSEL.Py Px_PUDEN.Py External HW
Push (optional 1 1 0 1 optional: 1 –
pull-up device)
Pull (optional 1 0 0 0 optional: 1 –
pull-down device)
OD with internal 1 0 1 1 1 –
pull-up device
OD with external 1 0 1 0 0 10 kR
pull-up
Tristate 0 Read for NA 0 0 –
pin state
HI with weak 0 Read for NA 1 1 –
pull-up pin state
termination
HI with weak pull- 0 Read for NA 0 1 –
down termination pin state

4.3 Serial resistor for high-speed signals


When using an alternative function of a GPIO, different hardware measures might be needed for optimized
performance and robustness. When, for example, operating logic-level communication interface at the devices,
a serial resistor (RIO) might be necessary to suppress ringing of the signals caused by the LC-circuit formed by
the port-capacitance of the GPIOs (CIO), and the capacitance (CTRACE), and inductance (LTRACE) of the PCB traces.

Figure 10 GPIO serial resistor

VIO is the signal generated by the sending GPIO and VIO2 the signal seen by the receiving GPIO. Each GPIO has a
pin capacitance (P_5.1.19).

Application note 19 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
General purpose inputs outputs (GPIO)

The trace capacitance and inductance depend on the traces’ width (W), length (L), thickness (T), PCB layer
thickness (H) (all dimensions in meter), the PCB’s dielectric constant 𝜀𝑅 , and vacuum permittivity 𝜀0 . The used
formula is only valid for surface traces with an adjacent power or ground plane.
𝑊×𝐿
𝐶𝑇𝑟𝑎𝑐𝑒 = 𝜀𝑅 × 𝜀0 × [𝐹]
𝐻
8×𝐻 𝑊
𝐿 𝑇𝑟𝑎𝑐𝑒 = 0.2 × 𝑙𝑛 ( + ) × 𝐿 [𝑛𝐻]
𝑊 4×𝐻
The trace capacitance and inductance are calculated for a standard trace width of 0.2 mm and thickness of
0.04 mm and a PCB layer thickness of 1.6 mm. VIO is 5 V and rises and falls within 1 ns. VIO and VIO2 are plotted for
different trace lengths and serial resistor dimensions in Figure 11.

Figure 11 GPIO ringing

For traces with a length of 100 mm, a 90 Ω resistor suppresses ringing efficiently. If production spread and
temperature dependency are considered, 220 Ω are sufficient for most applications.

Table 10 Resistor selection for GPIOs


Symbol Function Recommended component
RPU Pull-up for external pin termination 10 kΩ
RIO Serial resistor for high accuracy Min: value 220 Ω
high-speed communication Has to be assessed if needed in the application
Application note 20 Rev. 1.1
2022-04-01
TLE987x/6x
Hardware design guideline
LIN transceiver

5 LIN transceiver
The LIN module is a transceiver for the local interconnect network (LIN) compliant to the LIN2.2 standard,
backward compatible to LIN1.3, LIN2.0 and LIN2.1. It operates as a bus driver between the protocol controller
and the physical network. The LIN bus is a single-wire, bidirectional bus, which is typically used for in-vehicle
networks, using data rates between 2.4 kBaud and 20 kBaud. Additionally, data rates up to 115.2 kBaud are
supported.

VS

LIN transceiver

RBUS LIN.CTRL_STS

LIN
CTRL
Driver, current TxD_1
limiter, and LIN-FSM from
TSD STATUS UART

GND_LIN
Transmitter STATUS

CTRL
RxD_1 to
Filter UART and
TIMER2,
pin T2EX
(T2EXCON=0,
T2EXIS=0)
Receiver
Filter
LIN_Wake

Sleep comparator

GND_LIN

Figure 12 LIN transceiver block diagram

It is recommended to put a 220 pF capacitor between the LIN and the GND_LIN pins. This complies with the
LIN specification 2.2. The GND_LIN pin has to be connected to a global ground net outside of the chip.
In order to avoid interferences with the SoC’s core voltage, it is recommended to connect GND_LIN to the same
ground net of the power MOSFETs – called power GND. It is strongly advised not to wire GND_LIN to a
connector which leaves the PCB. The global ECU ground level shall be used as a reference for the LIN
connection. To reduce digital ground bounce transmitted via LIN, GND_LIN should not be connected directly to
the GND of the TLE987x/6x. It is better to have a slight decoupling by using few millimeters of trace. The LIN
transceiver can be used also with PWM control. In this case, a pull-up resistor between the LIN input and the
battery input voltage should be placed. The value of the pull-up resistor is ≥ 1 kΩ. In case additional filtering is
needed because of EMC issues, common mode chokes before the LIN pin are not recommended. A ferrite bead
placed at GND_LIN is preferred.
Application note 21 Rev. 1.1
2022-04-01
TLE987x/6x
Hardware design guideline
High-voltage monitor input

6 High-voltage monitor input


This module monitors external voltage to detect levels above or below a specified threshold, or it can be used
in Low Power mode to detect a wake-up event at the high-voltage MON pin.

6.1 Block diagram

VS

MON

+ Filter to internal
circuitry
-

MON

Logic

SFR

Figure 13 Monitor input block diagram

6.2 Application hints


The functional description of the high-voltage monitor input is included in chapter 26 of the TLE987x and
TLE986x user manual.
A dedicated R-C filter (RMON and CMON) must be placed before the MON pin, in order to protect it against reverse
polarity connection and voltage transients (ISO pulses), which could violate the absolute maximum ratings of
the MON pin. In fact, in a typical use-case the MON pin could be directly connected to the car battery in order to
sense the supply voltage, especially during power-down. Having no diode placed in series, the MON pin of the
TLE987x would be not protected against reverse polarity connection.
The table below shows the recommended RMON and CMON values. The GND to be used for CMON is the analog or
digital GND. Since the R-C time constant affects the voltage slope on the MON pin, the RMON and CMON values should
be selected according to the application requirements. Due to potential high peak power during transient tests,
the recommended package for RMON is 1206 SMD.

Table 11 Component selection for the MON pin


Symbol Function Recommended component
RMON Filter resistor Min. value 1 kΩ
RMON value and size selected according the application,
package 1206 SMD recommended
CMON Filter capacitor Ceramic capacitor
Min. value 10 nF, typical voltage rating 50 V
CMON value, voltage rating, size, and dielectric type
selected according to the application
Application note 22 Rev. 1.1
2022-04-01
TLE987x/6x
Hardware design guideline
Analog to digital converters (ADC1)

7 Analog to digital converters (ADC1)


The TLE987x/6x has two successive approximation ADCs with 10-bit (ADC1) or respectively 8-bit (ADC2) resolution
to monitor external and internal signals.

7.1 Software settings and hardware considerations


The two ADCs are connected to different signals and have different digital post-processing units, sample and
hold capacitors and attenuator voltage divider networks.

7.2 Signals ADC1


The ADC1’s 8 input channels are used by the analog low-voltage port P2, the internal current sense amplifier and
the VDH pin. The connected signals are shown in the following table.

Table 12 ADC1 channels


Channel Signal Pin
0 P2.0 29
1 CSA Internal
2 P2.2 30
3 P2.3 35
4 P2.4 32
5 P2.5 31
6 VDH Internal
7 NC NA

7.3 ADC1 measuring principle


The channel input voltages are divided with a capacitive voltage divider down to the reference voltage level. This
voltage divider consists of the internal sample and hold capacitor array. The reference voltage for ADC1 is the
bandgap voltage (PMU-VBG). For all ADC1 channels, but channel 6 (VDH), this measurement principle results in a
small current consumption (~10 µA), caused by internal switching currents. VDH has an additional resistive
voltage divider, since VDH is a high-voltage pin.

7.4 ADC1 external components design


The external components used for VDH and the CSA are already described in chapter 9 and 11. For the
remaining low-voltage inputs, an external anti-aliasing low-pass filter can be used. This filter limits the ADC
channel input frequency to half the sampling frequency to fulfill the Nyquist criterion to prevent aliasing of the
input signal. Figure 14 shows the block diagram of ADC1 and the external filter components.
The ADC consists of a multiplexer to switch the channel that should be measured during the actual sequence
onto the ADC module. The ADC module consists of the resistance of the analog input path (RAIN), the switched
capacitance of the analog input path (CAINS), two switches (S1 and S2 ) to decouple the ADC from the multiplexer
inputs to charge the capacitor array (cap array) and the actual sample and hold ADC core (ADCCORE).

Application note 23 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Analog to digital converters (ADC1)

VLV
RADC1IN P2.0
CH0
CSA ADC1
CADC1IN CH1
P2.2
ADCCORE
CH2
P2.3
CH3 RAIN S1 S2 D
P2.4 MUX
CH4
Cap array A
P2.5
CAINS
CH5
VDH
CH6
Rin_VDH,measure
NC
CH7
ATTVDH_1

ATTVDH_2

ATTVDH_3

Figure 14 ADC1 block diagram and external components

7.4.1 Anti-aliasing filter design


The anti-aliasing filter has to be sized to the lowest expected sampling frequency. In the TLE987x the analog
clock fADCI is used to sample the ADC. The cut-off frequency of the external low-pass filter is given with:
𝑓𝐴𝐷𝐶𝐼 1
=
2 2𝜋 × √𝜏𝐴𝐷𝐶1𝐼𝑁 × 𝜏𝐼𝑁

With:

 IN = RAIN × CAINS


 ADC1IN = RADC1IN × CADC1IN

Resulting in a desired time constant for the external anti-aliasing filter of:
1
𝜏𝐴𝐷𝐶1𝐼𝑁 =
(𝑓𝐴𝐷𝐶𝐼 𝑥 𝜋)2 × 𝜏𝐼𝑁
With:
 fADCI(min) = 5 MHz and fADCI(max) = 24 MHz (P_9.2.4)
 RAIN = 2 kΩ (P_9.2.16)
 CAINS = 4 pF (P_9.2.15)
 Resulting in:
− ADC1IN(5 MHz) = 507 ns
− ADC1IN(24 MHz) = 22 ns

Application note 24 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Analog to digital converters (ADC1)

Table 13 Component selection for ADC1


Symbol Function Recommended component
RADC1IN Resistor for anti-aliasing low-pass filter Min. value 1 Ω (fADCI = 5 MHz)
Max. value 2 Ω (fADCI = 24 MHz)
CADC1IN Capacitor for anti-aliasing low-pass filter Min. value 10 nF (fADCI = 24 MHz)
Max. value 470 nF (fADCI = 5 MHz)

Application note 25 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Sigma-delta analog digital converters (ADC3/4)

8 Sigma-delta analog digital converters (ADC3/4)


The TLE987x-2QX variants of the TLE987x have two integrated sigma-delta analog to digital converters (SDADC)
with 14-bit resolution to monitor signals with highest accuracy requirements.

8.1 Software settings and hardware considerations


The SDADCs can be used to build a sensor interface for an external AMR/GMR sensor. The connected signals are:

Table 14 SDADC signals


Signal Pin
ADC3.P 29
ADC3.N 30
ADC4.P 31
ADC4.N 32

8.2 ADC3/4 measuring principle


The differential input channels are divided via a fixed capacitive stage down to the reference voltage level. The
switched-capacitor integrators of the second-order sigma-delta demodulator run at a fixed frequency of 20 MHz.
The integrator output is connected to a quantizer which toggles as soon as the integrator output reaches the
SDADC reference voltage and resets the integrator via a feedback digital to analog converter. The modulated bit
stream is then filtered by a third-order comb filter with an oversampling rate of up to 2048.

8.3 ADC3/4 external components design


An external filter circuit can be used for several purposes. The main applications would be to improve the
SDADC performance by decreasing the signal noise and to protect the device from HF noise, which may couple
into the sensor interface.
The filter has to be dimensioned by the user for a specific target sensor. A suitable sensor would be the
XENSIVTM TLE5009 E2000 analog GMR angle sensor. The sensor interface is shown in the following figure.

Figure 15 SDADC sensor interface

Application note 26 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Sigma-delta analog digital converters (ADC3/4)

To improve the accuracy of the sensor interface, the cut-off frequency (fC) for -3 dB attenuation has to be
decreased. This will decrease the RMS output noise (VNoise) of the SDADC for the maximal signal
amplitude (AX/Ydiff).

The original resolution of sensor is given with AX/Ydiff = 2.8 V and VNoise(fC) = 3 mV
𝐴𝑋𝑌𝑑𝑖𝑓𝑓 2.8 𝑉
𝑛 = 𝑙𝑜𝑔2 × ( ) 𝑏𝑖𝑡 = 𝑙𝑜𝑔2 × ( ) 𝑏𝑖𝑡 ≈ 10 𝑏𝑖𝑡
𝑉𝑁𝑜𝑖𝑠𝑒 (𝑓𝐶 ) 3 𝑚𝑉
The cut-off frequency of the SDADC can be changed with an external RC-filter to match the maximum input
frequency of the SDADC (P_10.1.8), gaining resolution in the sensor while sacrificing bandwidth. Since the
sensors RMS noise is pink-noise the spectral noise density is constant for different cut-off frequencies can be
calculated with the formula below. With fnew = 2 × P_10.1.8 = 2 kHz the new RMS noise results in:

𝑓𝑛𝑒𝑤 2 𝑘𝐻𝑧
𝑉𝑁𝑜𝑖𝑠𝑒(𝑓𝑛𝑒𝑤 ) = 𝑉𝑁𝑜𝑖𝑠𝑒 (𝑓𝐶 ) × √ = 3 𝑚𝑉 × √ = 775 µ𝑉
𝑓𝑐 30 𝑘𝐻𝑧

Improving the resolution by 2 bits.


𝐴𝑋𝑌𝑑𝑖𝑓𝑓 3.7 𝑉
𝑛 = 𝑙𝑜𝑔2 × ( ) 𝑏𝑖𝑡 = 𝑙𝑜𝑔2 × ( ) 𝑏𝑖𝑡 ≈ 12 𝑏𝑖𝑡
𝑉𝑁𝑜𝑖𝑠𝑒 (𝑓𝑛𝑒𝑤 ) 775 µ𝑉
The time constant 𝜏 for the desired RC-filter is therefore given with:
1 1
𝜏 = 𝑅𝑆𝐼𝑁𝐶𝑂𝑆 × 𝐶𝑆𝐼𝑁𝐶𝑂𝑆 = = = 80 µ𝑠
2 × 𝜋 × 𝑓𝑛𝑒𝑤 2 × 𝜋 × 2 𝑘𝐻𝑧

With a dynamic input impedance (P_10.1.15) ZIN = 250 kΩ and the maximum gain error GERR = 0.5% RSINCOS
is given with:
𝑅𝑆𝐼𝑁𝐶𝑂𝑆 (max) = 𝑍𝐼𝑁 × 𝐺𝐸𝑅𝑅 = 250 𝑘𝛺 × 0.5% = 1.25 𝑘𝛺 ≈ 1 𝑘𝛺

Resulting in a CSINCOS of:


𝜏 80 µ𝑠
𝐶𝑆𝐼𝑁𝐶𝑂𝑆 = = = 80 𝑛𝐹 ≈ 100 𝑛𝐹
𝑅𝑆𝐼𝑁𝐶𝑂𝑆 1 𝑘𝛺
To protect the SDADC against HF coupling noise between 200 MHz and 500 MHz, the CHF capacitors have be
selected accordingly.
If RSINCOS can be placed close to the TLE987x-2QX, the capacitor can be calculated with:
1 1
𝐶𝐻𝐹 = = = 3 𝑝𝐹
𝑅𝑆𝐼𝑁𝐶𝑂𝑆 × 2𝜋 × 500 𝑀𝐻𝑧 1 𝑘𝛺 × 2𝜋 × 500 𝑀𝐻𝑧
If RSINCOS cannot be placed close to the TLE987x-2QX or no RC-filter is used, the recommended value for CHF
is 470 pF.

Application note 27 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Sigma-delta analog digital converters (ADC3/4)

Table 15 Component selection for SDADC


Symbol Function Recommended component
RSINCOS Resistor for resolution low-pass filter 1 kΩ
CSINCOS Capacitor for resolution low-pass filter Ceramic capacitor
Min. value has to be calculated as described above
Voltage rating and dielectric type defined according to
the application
CHF HF decoupling capacitor Ceramic capacitor
Min. value 2 pF type: X7R
Min. value 470 pF type: X7R
Voltage rating and dielectric type defined according to
the application

Application note 28 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Bridge driver (excluding charge pump)

9 Bridge driver (excluding charge pump)


The bridge driver is intended to drive external normal-level MOSFETs in bridge configuration. This chapter
provides details about external components, which are needed depending on application requirements.
Detailed information about the bridge driver functioning and configuration is available in the Infineon
application note “TLE986x/TLE987x Bridge Driver”.

9.1 Application diagram


The following application diagram shows the gate drivers for one half-bridge with the (partially optional)
external components, which are described in this chapter.

from battery

VCP DC link

CPH Ax CPH Bx
RVD H
+ VDH
CVD H
VDS

- High Side
Driver CGD D
RGATE
GHx G CS

THx
VREF
RGGND RGS CGS
RS
S
SHx
IPD D ia g CEM CP x DSH RSH
to motor
Low Side
+ Driver CGD D
RGATE
VDS GLx G

TLx
- RGGND RGS CGS

VREF
SL

to ground

Figure 16 Gate drivers for one half-bridge with external components

Application note 29 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Bridge driver (excluding charge pump)

9.2 External components


Component Short description Recommended value
RGATE Gate resistor (optional): suppresses potential oscillations between 2 … 10 Ω
PCB line inductances and MOSFET capacitances
RGS Gate-to-source resistor: terminates the MOSFET gate 100 kΩ
CGS Gate-to-source capacitor (optional): linearizes the intrinsic Depends on MOSFET
MOSFET gate-to-source capacitor
CGD Gate-to-drain capacitor (optional): linearizes the intrinsic MOSFET
gate-to-drain capacitor
CPHAx DC link capacitor A: buffers DC link voltage Depends on
CPHBx DC link capacitor B: suppresses double-digit MHz oscillations application
requirements
RS, CS Snubber (optional): reduces voltage peaks and ringing at motor pin
CEMCPx EMC filter capacitor at the SHx pin: suppresses fast transients 1 nF
at SHx
RVDH, CVDH Low-pass filter at the VDH pin: suppresses high-frequency 1 kΩ, 1 … 3.3 nF
components of DC link voltage
DSH Protection diode at the SHx pin (optional): limits SHx undershoot –
voltages
RSH Source resistor at the SHx pin (optional): suppresses potential 2 … 10 Ω
oscillations from motor phase to SHx pin and synchronizes the
gate channel

Gate resistor
The optional gate resistor RGATE suppresses potential oscillations between PCB line inductances and MOSFET
capacitances, which build up an LC oscillator that can be stimulated by fast transients during MOSFET
switching. The value of RGATE depends on the PCB layout conditions, MOSFET parasitics, and switching speed,
but should be as small as possible, preferably in the range from 2 Ω to 10 Ω.

Gate-to-source resistor
The gate-to-source resistor RGS terminates the gate of the external MOSFET to its source. It should be placed as
close as possible to the MOSFET to keep it turned off, for example, in the case of electromagnetic interference
(EMI) or broken PCB lines. The recommended value is 100 kΩ.

Gate-to-source capacitor
The optional gate-to-source capacitor CGS linearizes the intrinsic MOSFET gate-to-source capacitors and
reduces the tolerance of the total gate-to-source capacitance seen by the gate driver. The value of CGS should
be large enough to dominate the intrinsic MOSFET gate-to-source capacitance CGS_int.
The recommendation is: CGS ≥ 2 × CGS_int.
Notes:
1. The maximum gate charge Qtot_max per MOSFET including the external gate capacitors must not exceed 100 nC
for VQFN variants and 150 nC for TQFP variants.
2. CGS_int is usually not directly given in MOSFET datasheets, but can be estimated from parameters like Ciss or Qgs.

Application note 30 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Bridge driver (excluding charge pump)

Gate-to-drain capacitor
The optional gate-to-drain capacitor CGD linearizes the intrinsic MOSFET gate-to-drain capacitor and reduces
the tolerance of the total gate-to-drain capacitance seen by the gate driver. The placement of CGD is
recommended, if it is important for the application to have a well-controlled linear slew rate at the SHx pin:
ΔVSHx / Δt = IGATE / CGD.
Notes:
1. The maximum gate charge Qtot_max per MOSFET including the external gate capacitors must not exceed 100 nC
for VQFN variants and 150 nC for TQFP variants.
2. In order to avoid unintended switch-on of the MOSFET during fast transients, the following condition must be
met: CGD / CGS ≤ 1 / 10.

DC link capacitors
The DC link capacitors CPHAx and CPHBx serve two purposes:
1. CPHAx serves as a buffer capacitor
2. CPHBx suppresses double-digit MHz oscillations on the DC link voltage

The total value of all DC link capacitors CPH_tot = ∑ (CPHAx + CPHBx) depends on the acceptable DC link voltage ripple
caused by PMW operation and on additional application-specific requirements, like having motors operating in
generator mode or the need to buffer the motor energy in the case of an emergency shutdown of the MOSFETs.

Note: CPH_tot must be large enough to always keep all connected input pins (for example, VDH, VSD)
within their absolute maximum ratings.

As a starting point for the value of CPH_tot, a rule of thumb is 230 µF per 10 A motor current. The bigger part of the
capacitance is covered by electrolytic capacitors CPHAx and the rest by ceramic capacitors CPHBx. It is
recommended to choose capacitors with low ESR and low self-inductance and place them close to their
respective high-side MOSFETs, in order to minimize series resistances and inductances in the high-current path.

Snubber
The optional snubber RS and CS reduces voltage peaks and ringing at the motor pin, which can be caused by
PCB parasitics like series inductances. The values for RS and CS depend on the half-bridge power ratings and on
the parasitics of the selected MOSFET.
Starting values for RS and CS can be derived from the following constraints:

 RS ≤ VDClink / Imotor in order to keep the voltage across RS always smaller than the DC link voltage

 CS ≥ 2 × Coss, where Coss is the output capacitance of the MOSFET


Notes:
1. For RS a resistor with very low self-inductance should be chosen. The resistor power class can be derived from
the maximum energy stored in CS.
2. For CS a capacitor with high peak-current capability should be chosen.

Application note 31 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Bridge driver (excluding charge pump)

EMC filter capacitor at the SHx pin


The EMC filter capacitor CEMCPx at the SHx pin suppresses fast transients coming from the motor pin. The
recommended value is 1 nF. This capacitor should be placed as close as possible to the SHx pin.

Low-pass filter at the VDH pin


The low-pass filter RVDH and CVDH at the VDH pin suppresses high-frequency components on the DC link voltage.
The VDH input serves as the reference voltage of the high-side drain-source comparators and should be stable
right after each MOSFET switching event. Therefore, a time constant in the range of a low single-digit µs value
should be targeted, for example: RVDH = 1 kΩ and CVDH = 1 nF.

Note: RVDH performs an additional protection role by limiting the current out of the VDH pin in the case of
a reverse-polarity event or other undershoots of the DC link voltage.

Protection diode at the SHx pin


The optional protection diode at the SHx pin limits SHx undershoot voltages. This diode is only recommended
if undershoots below the absolute maximum ratings may be expected due to unknown application conditions.

Source resistor at the SHx pin


The optional source resistor at the SHx pin serves two purposes:
 It suppresses the potential oscillations from the motor phase to SHx pin
 It synchronizes the gate channel with small RC filter (τmax = 500 ns)

The recommended value for RSH is in the range from 2 to 10 Ω.

Application note 32 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Charge pump

10 Charge pump
The charge pump is intended to supply the bridge driver integrated in the TLE987x/6x, as well as the Back-EMF
comparators. The purpose of this chapter is to provide a design method for the external capacitors, depending
on the application requirements.

10.1 Application diagram


The following application diagram shows the charge pump and its external components, which are the flying
capacitors CCPS1 / CCPS2 and the output capacitor CVCP. The input voltage of the charge pump is VSD, while
the output voltage is VCP.
VDC is the DC-link voltage after the MOSFET for reverse polarity protection. An RC network can be optionally
placed between VDC and VSD. CVSD is acting as filter capacitor, while RVSD limits the current flowing into VSD
during voltage transients. The recommended values for CVSD and RVSD are 1 µF and 2 Ω.

VDC
CVCP
RVSD

CVSD CCPS1 CCPS2

VSD CP1H CP1L CP2H CP2L VCP

CHARGE PUMP
BDRV
MOSFET
driver

GND

Figure 17 Charge pump application diagram

10.2 Charge pump: how it works


The voltage VCP is generated by a 2-stage charge pump, as a multiplying effect of the input voltage VSD using
two flying capacitors CCPS1 and CCPS2: ideally, each stage of the charge pump can provide a voltage increase
equal to the input voltage. The output capacitor CVCP acts as bulk for the voltage VCP. A detailed description of
the behavior of an n-stage charge pump is available in the following literature:
 “On-Chip High-Voltage Generation in Integrated Circuits Using an Improved Multiplier Technique” by
J.F. Dickson
 “Theoretical and Experimental Analysis of Dickson Charge Pump Output Resistance” by A. Cabrini, L. Gobbi,
and G. Torelli

Application note 33 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Charge pump

The switches of the charge pump are driven by an internal clock (CLK) with a frequency equal to fSW, derived
from the TLE987x/6x system clock. The following pattern applies (Figure 18):
 Clock set to low: the capacitor CCPS1 is charged by VSD, while the energy of CCPS2 is transferred to the
output, boosting the voltage VCP of the capacitor CVCP. Considering VDROP1 as the voltage drop of the
switches of the first stage and ignoring the load current, the average voltage VCPS1 can be expressed as:

𝑉𝐶𝑃𝑆2 = 3 𝑉𝑆𝐷 − 𝑉𝐷𝑅𝑂𝑃2 ; 𝑉𝐶𝑃 = 3 𝑉𝑆𝐷 − 𝑉𝐷𝑅𝑂𝑃

Where: VDROP as the is the total voltage drop of the switches of the charge pump.
 Clock set to high: the energy is transferred from CCPS1 to CCPS2, while the output voltage VCP is buffered
by the bulk capacitor CVCP. Considering VDROP2 as the voltage drop of the switches of the first and second
stage and ignoring the load current, the average voltages VCPS2 and VCP can be expressed as:

𝑉𝐶𝑃𝑆1 = 2 𝑉𝑆𝐷 − 𝑉𝐷𝑅𝑂𝑃1

VSD VSD

CLK CLK
nCLK nCLK
CCPS1 CCPS1

VCPS1 VCPS1
nCLK nCLK
CVCP CVCP

CLK CLK

nCLK nCLK

CCPS2 CCPS2

VCPS2 VCPS2
CLK CLK

nCLK nCLK

BDRV BDRV
MOSFET MOSFET
driver VCP driver VCP

Figure 18 Basic scheme of the charge pump (left: clock set to low; right: clock set to high)

Including now the load current in the calculation, the output voltage VCP can be expressed as:
Equation 1:
𝑉𝐶𝑃 = 3 𝑉𝑆𝐷 − 𝑉𝐷𝑅𝑂𝑃 − 𝑅𝑂𝑈𝑇_𝐴𝑉𝐺 × 𝐼𝐶𝑃

Where:

 ICP is the average output current, as sum of the bias current of the bridge driver and the total current
needed to drive the MOSFETs gates

 ROUT_AVG is the average output resistance of the charge pump, which can be expressed as:
Application note 34 Rev. 1.1
2022-04-01
TLE987x/6x
Hardware design guideline
Charge pump

Equation 2:
2 3
𝑅𝑂𝑈𝑇_𝐴𝑉𝐺 ≈ +
𝑓𝑆𝑊 × 𝐶𝐶𝑃𝑆 4 × 𝑓𝑆𝑊 × 𝐶𝑉𝐶𝑃
Where:
 fSW is the switching frequency of the charge pump, and CCPS1 and CCPS2 are both equal to CCPS

Considering:
Equation 3:
𝑉𝐷𝑅𝑂𝑃 = 𝐼𝐶𝑃 × 𝑅𝐸𝑄

The Equation 1 can be re-arranged as follows:


Equation 4:
𝑉𝐶𝑃 = 3 × 𝑉𝑆𝐷 − 𝐼𝐶𝑃(𝑅𝐸𝑄 + 𝑅𝑂𝑈𝑇_𝐴𝑉𝐺 )

Where:
 REQ is an average resistance, which takes into account the total voltage drop VDROP in respect to the output
current. A value of REQ fitting to the charge pump implemented in the TLE987x is about 100 Ω.
Figure 19 shows the equivalent circuit as expressed by the Equation 4.

VCP

REQ ROUT_AVG
3VSD ICP

Figure 19 Charge pump equivalent circuit

Considering the wide range of the input voltage VSD, the charge pump of the TLE987x limits the output voltage
VCP according to the following relations:
14 𝑉 𝑖𝑓 𝑉𝐶𝑃 − 𝑉𝑆𝐷 ≥ 14 𝑉
𝑉𝐶𝑃 − 𝑉𝑆𝐷 ≅ {
𝑉𝐶𝑃 − 𝑉𝑆𝐷 𝑖𝑓 𝑉𝐶𝑃 − 𝑉𝑆𝐷 < 14 𝑉

Note: Important to note is that the above equations are aiming to provide an equivalent model of the
charge pump considering average values of the electrical parameters, not RMS (root medium
square) values.
For this reason, they should not be used straightforward to calculate the power dissipation of
the charge pump itself.

Application note 35 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Charge pump

10.2.1 ICP load current calculation


The load current ICP of the charge pump is the sum of the currents supplied to each gate, and the bias current
of the bridge driver. In Figure 20 the gate charge and discharge current paths are shown. Referring to this figure,
the following equations can be derived:
Equation 5:
𝐼𝐶𝑃 = 𝑁𝐺 × (𝐼𝐶𝑃𝑀 + 𝐼𝐵𝐼𝐴𝑆 )
Equation 6:
𝐼𝐶𝑃𝑀 = 𝑁𝑀 × 𝑓𝑃𝑊𝑀 × 𝑄𝑀
Equation 7:
𝑄𝑀 = 𝑄𝑀𝑂𝑆𝐹𝐸𝑇 + 𝐶𝐺𝑆𝑒𝑥𝑡 × 𝑉𝐺𝑆 + 𝐶𝐺𝐷𝑒𝑥𝑡 × 𝑉𝐺𝐷
Where:
 NG is the number of half-bridge drivers active in one PWM switching period. This value depends on the PWM
switching scheme and the control technique used in the application. Considering a 3-phase motor, NG is
equal to 1 with block commutation, while NG is equal to 3 with FOC (field-oriented control)
 ICPM is the current of each half-bridge gate driver
 IBIAS is the bias current of each single half- bridge driver. A typical value for IBIAS is about 2 mA
 NM is the number of MOSFETs turned on in one PWM switching period. This value depends on the PWM
switching scheme and the control technique used in the application. For block commutation and FOC NM is
equal to 2
 fPWM is the PWM switching frequency
 QM is the total charge transferred to the high-side (HS) and/or low-side (LS) gate, including the charge of
external capacitors
 QMOSFET is the gate charge of the HS (and/or LS) gate present at a certain VGS
 CGSext is the value of the external gate to source capacitance
 VGS is the gate to source voltage
 CGDext is the value of the external gate to drain capacitance
 VGD is the gate to drain voltage

Application note 36 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Charge pump

VSD

CVCP
RVSD

VSD VCP

ICP
VSD

CHARGE ICH HS
GHx
PUMP
VGS IDIS HS
clamp

GND SHx

to the motor

ICH LS
GLx

VGS IDIS LS
clamp

SL

Rsh

Figure 20 Schematic representation of the high-side and low-side MOSFET gate charge (green) and
discharge (blue) currents paths (left). Bias current in red. Each gate driver block is
repeated 3× in the TLE987x, while 2× in TLE986x

The gate charge QMOSFET can be determined from the characteristics of the MOSFET. A typical gate charge graph
of an automotive Infineon MOSFET (IAUA120N04S5N014) is shown in the Figure 21.

Application note 37 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Charge pump

Figure 21 Gate charge of the IAUA120N04S5N014

In the bridge driver implementation of the TLE987x/6x, the HS and LS gate source voltages VGS are limited by
an internal clamping. In Figure 22 a simplified schematic of the bridge driver is illustrated. It can be assumed
that the MOSFETs ON-resistances and the current sensing resistor Rsh are in the order of magnitude of [mΩ]. As
a consequence the following approximations can be made:
 When HSx is ON and LSx is OFF → VPHx ≅ VSD
 When LSx is ON and HSx is OFF → VPHx ≅ VSL ≅ GND

Taking this into account, the typical average VGSHS (for the HS) and VGSLS (for the LS) voltages can be
estimated as:
Equation 8:
12.5 𝑉 𝑖𝑓 𝑉𝐶𝑃 − 𝑉𝑆𝐷 ≥ 14 𝑉
𝑉𝐺𝑆𝐻𝑆 ≅ {
𝑉𝐶𝑃 − 𝑉𝑆𝐷 − 1.5 𝑉 𝑖𝑓 𝑉𝐶𝑃 − 𝑉𝑆𝐷 < 14 𝑉
12.5 𝑉 𝑖𝑓 𝑉𝐶𝑃 ≥ 14 𝑉
𝑉𝐺𝑆𝐿𝑆 ≅ {
𝑉𝐶𝑃 − 1.5 𝑉 𝑖𝑓 𝑉𝐶𝑃 < 14 𝑉

Application note 38 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Charge pump

VSD

CVCP
RVSD

VSD VCP

ICP
VSD

CHARGE
ICH HS GHx IGSHSx
PUMP HSx
VGS IDIS HS
VGSHSx
clamp CGSext

GND SHx

to the motor
VPHx

ICH LS
GLx IGSLSx
LSx
VGS IDIS LS
VGSLSx
clamp CGSext
VSL
SL

Rsh

Figure 22 Simplified BDRV block diagram with highlight on gate-source voltage clamping. Each gate
driver block is repeated 3× in the TLE987x, while 2× in the TLE986x

A calculation example is provided here below, where no capacitors are connected to the MOSFETs gates and
FOC control with a 3-phase motor is used. For sake of simplicity, we can assume VGS to have the same value for
HS and LS, as well as to be independent from ICP.
 Assumptions:

𝑁𝑀 = 2 ; 𝑓𝑃𝑊𝑀 = 20 𝑘𝐻𝑧 ; 𝑄𝑀𝑂𝑆𝐹𝐸𝑇 ≅ 60 𝑛𝐶 ; 𝑉𝐺𝑆 = 12.5 𝑉


 Considering VGS is equal to 12.5 V, the gate charge shall be consequently increased, since the 60 nC are
estimated for VGS = 10 V:
12.5 𝑉
𝑄𝑀𝑂𝑆𝐹𝐸𝑇 ≅ 60 𝑛𝐶 × = 75 𝑛𝐶
10 𝑉

Application note 39 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Charge pump

 The current for each gate driver is equal to:

𝐼𝐶𝑃𝑀 = 𝑁𝑀 × 𝑓𝑃𝑊𝑀 × 𝑄𝑀𝑂𝑆𝐹𝐸𝑇 ≅ 3 𝑚𝐴


 The total ICP current is:

𝐼𝐶𝑃 = 3 × (𝐼𝐶𝑃𝑀 + 𝐼𝐵𝐼𝐴𝑆 ) ≅ 15 𝑚𝐴

Another calculation example is provided here below, where a capacitor is placed between gate and source, and
no capacitor between gate and drain is connected. The control scheme is always FOC. For sake of simplicity, we
can assume VGS and VGD to have the same value for HS and LS, as well as to be independent from ICP.
 Assumptions:

𝑁𝑀 = 2 ; 𝑓𝑃𝑊𝑀 = 20 𝑘𝐻𝑧 ; 𝑄𝑀𝑂𝑆𝐹𝐸𝑇 = 60 𝑛𝐶


𝑉𝐺𝑆 = 𝑉𝐺𝐷 = 12.5 𝑉 ; 𝐶𝐺𝑆𝑒𝑥𝑡 = 1 𝑛𝐹
 The charge for each gate is then:

12.5 𝑉
𝑄𝑀 = 60 𝑛𝐶 × + 12.5 𝑉 × 1 𝑛𝐹 ≅ 88 𝑛𝐶
10 𝑉
 The current for each gate driver is equal to:

𝐼𝐶𝑃𝑀 = 𝑁𝑀 × 𝑓𝑃𝑊𝑀 × 𝑄𝑀 ≅ 3.5 𝑚𝐴


 The total ICP current is:

𝐼𝐶𝑃 = 3 × (𝐼𝐶𝑃𝑀 + 𝐼𝐵𝐼𝐴𝑆 ) ≅ 16.5 𝑚𝐴

Application note 40 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Charge pump

10.3 Charge pump external capacitors design


The flying capacitors CCPS1 and CCPS2 boost the input voltage VSD to generate the output voltage VCP, while
the output capacitor CVCP is acting as bulk capacitor. The selection of the values and type should consider the
following requirements:
 VCP voltage in steady state: as shown in the Equation 1, the output voltage depends also on the value of
the charge pump capacitors.
 Voltage ripple: the ripple of the flying capacitors can be expressed as:

Equation 9:
𝐼𝐶𝑃
𝑉𝑟𝑖𝑝𝑝𝑙𝑒 =
𝑓𝑆𝑊 × 𝐶
Where:
 C is the value of the capacitor

The voltage ripple of the output capacitor CVCP is equal to the one of the flying capacitors, but divided by 2.
 Dynamic response: the higher the value of the capacitors, the slower will be the start-up time and the
response to load changes. In a typical TLE987x/6x application, this requirement is not critical
 Losses due to ESR (equivalent series resistance): the higher the value of the capacitors, the higher will be
the ESR and so the losses. Using ceramic capacitors, the losses can be considered as not relevant in this
application
 DC bias voltage: ceramic capacitors exhibit lower capacitance values, when the applied voltage increases.
According to the point of load and the desired capacitance value, the voltage rating should be adequately
selected. For a typical application, 50 V capacitors are recommended

A method to select the charge pump capacitors


1. Define the type of MOSFETs of the application
2. Define the switching frequency fPWM of the bridge driver
3. Calculate the load current ICP, as described in the Equation 5
4. Calculate the preliminary values of CCPS and CVCP using the Equation 9. As a rule, we can consider a
maximum ripple of 0.5 V for the flying capacitors CCPS and 0.25 V for CVCP. Moreover, at least 50% higher
capacitance should be taken into account of the DC bias
5. Calculate ROUT_AVG using the Equation 2
6. Calculate VDROP using the Equation 4
7. Calculate VCP voltage using the Equation 4
8. Calculate the voltage VCP vs. VSD using the Equation 8, checking that the gates are driven with a sufficient
voltage in the input voltage range VSD, as required by the application.
The recommended values are 220 nF for the flying capacitors (CCPS1 / CCPS2), and 470 nF for the output
capacitor (CVCP). These values allow to have a VCP voltage sufficiently high within the nominal working
conditions of the charge pump, as well as a low voltage ripple in the load current range.

Application note 41 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Charge pump

10.3.1 Calculation example


A calculation example is provided here below.
1. Identify the MOSFETs, for example: IAUA120N04S5N014
2. Define the switching frequency:

𝑓𝑃𝑊𝑀 = 20 𝑘𝐻𝑧
3. Calculate ICP, considering VGS = 12.5 V, NM = 2, and no external capacitors connected to the gates:

𝐼𝐶𝑃 ≅ 15 𝑚𝐴
4. Calculate preliminary values for CCPS and CVCP, considering a charge pump frequency of 250 kHz and a
voltage ripple of 0.4 V and 0.2 V for CCPS and CVCP respectively:
𝐶𝐶𝑃𝑆 = 150 𝑛𝐹 → +50% → 220 𝑛𝐹
𝐶𝑉𝐶𝑃 = 300 𝑛𝐹 → +50% → 470 𝑛𝐹
5. Calculate ROUT_AVG:

𝑅𝑂𝑈𝑇_𝐴𝑉𝐺 = 43 𝛺
𝐼𝐶𝑃 × 𝑅𝑂𝑈𝑇𝐴𝑉𝐺 ≅ 0.65 𝑉

6. Calculate the voltage drop:

𝑉𝐷𝑅𝑂𝑃 = 𝐼𝐶𝑃 × 𝑅𝐸𝑄 ≅ 1.5 𝑉

7. Calculate VCP versus VSD:

𝑉𝐶𝑃 − 𝑉𝑆𝐷 ≅ 2 × 𝑉𝑆𝐷 − 2.2 𝑉


8. Considering from 8 V to 18 V as VSD voltage range, calculate the voltages VCP vs VSD, VGSHS and VGSLS:

VCP-VSD VGSHS VGSLS


VSD = 18 V 14 V 12.5 V 12.5 V
12 V 14 V 12.5 V 12.5 V
10 V 14 V 12.5 V 12.5 V
8V 13.8 V 12.3 V 12.5 V

From the table, the minimum VGS voltage is equal to 12.3 V, so the MOSFETs can be correctly driven in every
condition.

Application note 42 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Current sense amplifier

11 Current sense amplifier


The current sense amplifier (CSA) is an analog circuit capable of amplifying the differential input voltage by a
programmable gain G.
Despite being actually a voltage amplifier, it is specifically designed for shunt current measurements. For this
purpose, the pins OP2 and OP1 are connected to the terminals of a suitably designed shunt resistor, through
which the current to be measured flows, and a filter network.

11.1 Block diagram

VZERO

CSA CSA->CTRL.VZERO

OP2 Vp GR

0
R
ADC1 - CH1
+ Vo
OPA 1
-
R
Vn
OP1 GR
G

CSA->CTRL.GAIN

Figure 23 CSA block diagram and application schematic for shunt current measurement

11.2 Functional description


Figure 23 shows the block diagram of the CSA together with the registers and logic related to its setup.
The amplifier is built around an OPA configured as a differential amplifier with an output voltage offset.
The amplifier’s output is permanently connected to the ADC1 channel 1, which means it is loaded by a fixed
impedance. It is an integrated closed-loop amplifier and it can be used only as such. What follows will describe
the entire CSA configuration and behavior.

Application note 43 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Current sense amplifier

11.3 DC characteristics
The differential input voltage is defined as:
𝑉𝑖𝑑 = 𝑂𝑃2 − 𝑂𝑃1 = 𝑉𝑝 − 𝑉𝑛

The ideal DC transfer characteristics can be calculated as:


𝑉𝑜 = 𝑉𝑍𝐸𝑅𝑂 + 𝐺 𝑉𝑖𝑑
𝑉𝑍𝐸𝑅𝑂 = 0.4 𝑉𝐴𝑅𝐸𝐹
𝑉𝑖𝑑 = 0 → 𝑉𝑜 = 𝑉𝑍𝐸𝑅𝑂
Where:
 VZERO is the output voltage offset
 VAREF is the reference voltage of ADC

If, for example, VAREF is generated by the internal reference voltage generator, its nominal value is 5 V. As a
consequence VZERO = 2 V, which allows the ADC1 channel 1 to measure positive and negative values of Vid.

The linear output voltage range of the amplifier is (see P_13.1.4 of the datasheet):
𝑚𝑖𝑛, max{𝑉𝑜 } = 𝑉𝑂𝑈𝑇 = 𝑉𝑍𝐸𝑅𝑂 ± 1.5 𝑉
With the use of the internal VAREF generator, Vo can assume any value between 0.5 V and 3.5 V.
The Vo range limits the differential linear input range, which also depends on the gain setting according to
(see P_13.1.1 of the datasheet):
𝑚𝑖𝑛, max{𝑉𝑖𝑑 } = 𝑉𝐼𝑋 = ±1.5 𝑉 ⁄𝐺
Outside these ranges, the CSA characteristics are not linear and therefore undefined.
Because it is not an ideal circuit, the OPA exhibits an input offset VOS. Because of this, the output voltage can be
expressed by:
𝑉𝑜 = 𝑉𝑍𝐸𝑅𝑂 + 𝐺 (𝑉𝑖𝑑 ± 𝑉𝑂𝑆 )
𝑉𝑖𝑑 = 0 → 𝑉𝑜 = 𝑉𝑍𝐸𝑅𝑂 ± 𝐺 𝑉𝑂𝑆 = 𝑉𝑍𝐸𝑅𝑂 ± 𝑉𝑂𝑂𝑆
This implies that the direct measurement of VZERO by means of CSA->CTRL.VZERO = 1 will differ from the value of
Vo with Vid = 0 with CSA->CTRL.VZERO = 0. This difference equals to the output offset VOOS (see parameter
P_13.1.17). The measurements can be used to calculate this difference in the application software and to
compensate the offset.
The common mode input voltage is defined as:
𝑂𝑃2 + 𝑂𝑃1 𝑉𝑝 + 𝑉𝑛
𝑉𝑖𝑐𝑚 = =
2 2
Considering also the contribution of Vicm and the common mode rejection ratio DC_CMRR (see parameter
P_13.1.8 for grade 1 devices in conjunction with P_13.1.27 for grade 0 devices) the DC characteristics can be
expressed as:
𝑉𝑜 = 𝑉𝑍𝐸𝑅𝑂 ± 𝑉𝑂𝑂𝑆 + 𝐺 (𝑉𝑖𝑑 + 𝑉𝑖𝑐𝑚 ⁄𝐶𝑀𝑅𝑅𝑙𝑖𝑛 )
𝐷𝐶_𝐶𝑀𝑅𝑅
𝐶𝑀𝑅𝑅𝑙𝑖𝑛 = 10 20

Application note 44 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Current sense amplifier

Figure 24 shows a graphical representation of the differential DC characteristics and the input/output range.

VOUT
max VOUT

max VOOS
VZERO
min VOOS

G
min VOUT

min VIX max VIX VIX

Figure 24 Differential DC characteristics

11.3.1 AC characteristics
The CSA can be modeled as a three-port network with two input ports and one output port, as shown in
Figure 25. The two input ports represent OP2 and OP1, while the output port represents VOUT. Voltages for all
three ports are referred to the ground potential GND.
By considering the specific characteristics of the CSA, the three-port network can be expressed as:
Equation 10:
𝑣𝑜 = 𝐴𝑑 𝑣𝑖𝑑 + 𝐴𝑐𝑚 𝑣𝑖𝑐𝑚
{ 𝑣𝑝 = 𝑍𝑝𝑝 𝑖𝑝 + 𝑍𝑝𝑛 𝑖𝑛
𝑣𝑛 = 𝑍𝑛𝑝 𝑖𝑝 + 𝑍𝑛𝑛 𝑖𝑛

Where:
Equation 11:
𝑣𝑖𝑑 = 𝑣𝑝 − 𝑣𝑛
{ 𝑣𝑝 + 𝑣𝑛
𝑣𝑖𝑐𝑚 =
2
The first equation in Equation 10 represents the output behavior, while the other two represent the input
behavior of the CSA. The nominal value of the input impedances can be expressed as:
𝑣𝑝 𝑣𝑝
𝑍𝑝𝑝 = | = (𝐺 + 1)𝑅 𝑍𝑝𝑛 = | =0
𝑖𝑝 𝑖𝑛 𝑖
𝑖𝑛 =0 𝑝 =0

𝑣𝑛 𝑣𝑛
𝑍𝑛𝑝 = | =𝐺𝑅 𝑍𝑛𝑛 = | =𝑅
𝑖𝑝 𝑖𝑛 𝑖
𝑖𝑛 =0 𝑝 =0

Application note 45 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Current sense amplifier

ip

OP2 ip io
vp (G+1)R
io Ad vid
vp

vn
CSA vo Acm vicm
vo

G R ip
OP1 in vn
R
in

Figure 25 CSA AC simplified three-port model

Figure 25 shows a schematic representation of the input equations and its impedances. This representation
together with the equations are necessary to design the external current-sensing and filtering network.
The resistors R have nominal values of 1.25 kΩ (see P_13.1.25 of the datasheet) and G changes according the
programmed gain.
The closed-loop nature of the CSA ensures the user that the stability is guaranteed in any application condition.
The open-loop transfer function of the CSA together with its gain and phase margins are designed and fixed
for each G gain configuration. Therefore, only the closed-loop transfer functions are described here.
The DC common mode gain can be derived from the CMRR as:
𝐴𝑑
𝐴𝑐𝑚 =
𝐶𝑀𝑅𝑅
The typical AC differential gain transfer function is shown in Figure 26 and defined as:
𝑣𝑜 (𝑠)
𝐴𝑑 (𝑠) =
𝑣𝑖𝑑 (𝑠)
A simplified analytical expression for each transfer function can be used in order to identify the typical
frequency and time-domain parameters. A dominant-pole approximation of Ad(s) is:
𝑣𝑜 (𝑠) 𝐺
𝐴𝑑 (𝑠) = ≈ 4
𝑣𝑖𝑑 (𝑠) 𝑠
( + 1)
𝜔𝑝

Application note 46 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Current sense amplifier

Figure 26 AC differential gain transfer function

The typical values of ωp for each gain setting are shown in Table 16. Being a 4th-order transfer function, its step
response in the time domain has a fairly complex analytical expression. However, the time constant τp and its
relation to the settling time Ts can be defined as:
1
𝜏𝑝 = 𝑇𝑠 ≈ 9 𝜏𝑝
𝜔𝑝

The settling time Ts is defined as the time between the instant when the step is applied at Vid and the instant in
which Vo remains confined within ±2% of its final value. Table 16 shows the values of the estimated typical Ts
and τp for each gain setting.

Table 16 Typical values for gain settings


Gain [V/V] 10 20 40 60
ωp [Mrad/s] 50 27 17 12
τp [ns] 20 37 57 84
Settling time [ns] 185 330 520 760

11.4 Application hints


The CSA is designed to measure the differential voltage across a shunt resistor through which the current to be
measured flows. A typical circuit implementation of the sensing network is shown in Figure 27.
Because of the parasitic inductance introduced by the shunt resistor and the PCB traces, the signal across the
shunt resistor presents spikes and ringings. This effect must be compensated by a filtering network as shown
in Figure 27.
The following chapters describe a procedure for designing the shunt resistor and the filter network.

Application note 47 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Current sense amplifier

IM

RLP
ip vp OP2
io

CSA
Rsh
vsh CLP vo
Lsh
RLP
in vn
OP1
Lst

Figure 27 Typical circuit implementation

11.4.1 Shunt resistor selection


In a typical application, the input pins OP2 and OP1 are connected to an external shunt resistor so that:
𝑉𝑖𝑑 = 𝑅𝑠ℎ 𝐼𝑀
𝑉𝑜 = 𝑉𝑍𝐸𝑅𝑂 + 𝐺 𝑅𝑠ℎ 𝐼𝑀
Where:
 IM is the current to measure
 Rsh is the nominal resistance of the shunt resistor

This equation represents the ideal DC behavior of the CSA, so it is only valid once all the dynamics of the system
are eliminated. However, it is still a valid design equation for the choice of Rsh and G.

Indeed, because of the limited output voltage range of the CSA, one has to consider the behavior under
maximum current:
𝑉𝑜 𝑚𝑎𝑥 = 𝑉𝑍𝐸𝑅𝑂 + 1.5 𝑉 > 𝑉𝑍𝐸𝑅𝑂 + 𝐺 𝑅𝑠ℎ 𝐼𝑀 𝑚𝑎𝑥
This leads to the 1st design equation:
1.5 𝑉
𝑅𝑠ℎ < 𝑅𝑠ℎ 𝑚𝑎𝑥 =
𝐺 𝐼𝑀 𝑚𝑎𝑥

Note: This equation should be used so that Rsh is as close as possible to its maximum limit in order to
take the greatest advantage of the Vo range.

Since the output voltage is eventually measured by the ADC1 channel 1, one has to consider the relation
between the current resolution ΔIM and the ADC1 resolution ΔVo:
𝑉𝐴𝑅𝐸𝐹
∆𝑉𝑜 = < 𝐺 𝑅𝑠ℎ ∆𝐼𝑀 𝑚𝑖𝑛
210 − 1

Application note 48 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Current sense amplifier

Using the internal reference leads to ΔVo ≈ 4.5 mV. From this condition, the 2nd design equation derives:
∆𝑉𝑜
𝑅𝑠ℎ > 𝑅𝑠ℎ 𝑚𝑖𝑛 =
𝐺 ∆𝐼𝑀 𝑚𝑖𝑛

Note: This equation should be used so that Rsh is as far as possible to its minimum limit.

Another effect to consider is the power dissipation of the shunt resistor:

𝑃𝐷 𝑠ℎ = 𝑅𝑠ℎ 𝐼𝑀 𝑅𝑀𝑆 2

In order to limit the power dissipation to a certain value PDshmax, the 3rd design equation should be applied:
𝑃𝐷 𝑠ℎ 𝑚𝑎𝑥
𝑅𝑠ℎ < 𝑅𝑠ℎ 𝐷 =
𝐼𝑀 𝑅𝑀𝑆 2

The following considerations are also relevant when selecting a shunt resistor:
1. The higher the gain, the lower the bandwidth, as seen in Figure 26
2. The values of commercial current sensing resistors are discrete and limited
3. More shunt resistors in parallel are possible to increase the total maximum power dissipation

Design example: Selecting a shunt resistor


 IM(t) is a square-wave current with:
− IMmax = 10 A
− IMmin = 0 A
− Duty cycle = 80%
 VAREF = 5 V (internal)
 ΔIMmin = 100 mA
 PDshmax = 1 W

To find the optimal shunt resistance, the best approach is to consider the three design equations for each gain
setting G = {10, 20, 40, 60}:
1. From the 1st design equation:
1.5 𝑉
𝑅𝑠ℎ < 𝑅𝑠ℎ 𝑚𝑎𝑥 = = {15 ; 7.5 ; 3.75 ; 2.5} 𝑚Ω
𝐺 10 𝐴
2. From the 2nd design equation:
4.5 𝑚𝑉
𝑅𝑠ℎ > 𝑅𝑠ℎ 𝑚𝑖𝑛 = = {4.5 ; 2.25 ; 1.225 ; 0.75} 𝑚Ω
𝐺 100 𝑚𝐴
3. From the 3rd design equation:
1𝑊
𝑅𝑠ℎ < 𝑅𝑠ℎ 𝐷 = = 12.5 𝑚Ω
80 𝐴2
Figure 28 shows a graphical representation of the design equations above. It shows that any gain setting can fit
the case, given that Rsh falls in the selection area.

Application note 49 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Current sense amplifier

On the base of this analysis and consideration 1. and 2., a suboptimal choice for this use case would be a 7 mΩ
resistor with a gain setting G = 20. This will lead to the following actual values:
𝑉𝑜 𝑚𝑎𝑥 = 2 + 20 × 7 𝑚Ω × 10𝐴 = 3.4 𝑉
4.5 𝑚𝑉
∆𝐼𝑀 = ≈ 32.2 𝑚𝐴
20 × 7 𝑚Ω
𝑃𝐷 𝑠ℎ = 7 𝑚Ω × 80 𝐴2 = 560 𝑚𝑊

Figure 28 Graphical representation of the design example values

11.4.2 Filter network selection


The goal of the filter network design is to shape the dynamics of the CSA input voltage so that it is the best
representation of the measured current. In practice, the design goal is to choose the values of the low-pass filter
components RLP and CLP that damp the ringings caused by the parasitic inductance Lsh.

Vo as function of IM needs to be expressed. This could be done in the time domain, but the AC analysis in the
frequency domain can simplify the design procedure. The total CSA gain transfer function can be defined as:
𝑣𝑜 (𝑠)
𝐻(𝑠) =
𝑖𝑀 (𝑠)
Further H(s) can be broken down as a function of the CSA differential and common mode gains from the input
pins OP2 and OP1 to the input of the ADC1:
𝑣𝑜 (𝑠) 𝐴𝑑 (𝑠) 𝑣𝑖𝑑 (𝑠) + 𝐴𝑐𝑚 (𝑠) 𝑣𝑖𝑐𝑚 (𝑠) 𝑣𝑖𝑑 (𝑠)
𝐻(𝑠) = = ≈ 𝐴 (𝑠)
𝑖𝑀 (𝑠) 𝑖𝑀 (𝑠) 𝑖𝑀 (𝑠) 𝑑

Note: The above simplification is possible because both common mode input signal and gain are
negligible compared to the differential ones.

In the frequency domain, the goal mentioned above translates into obtaining a response as flat as possible,
ideally a constant response across the whole frequency spectrum. As known, Ad(s) has a flat gain, but within
limited bandwidth (see Figure 26 and Table 16), so the effect of the shunt and filter network has to preserve this
level of fidelity.

Application note 50 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Current sense amplifier

IM (G+1)R
RLP ip vp OP2 io

Rsh Ad vid
CLP vid vo
Lsh Acm vicm
R G R ip
RLP in vn
OP1

Figure 29 CSA input filter and graphical representation of the CSA impedances

In conclusion, the best dynamic performances obtainable (without introducing any additional reactive device)
is the one of the CSA. This requires:
𝑣𝑖𝑑 (𝑠)
𝑍𝑇 (𝑠) = = 𝑅𝑠ℎ
𝑖𝑀 (𝑠)
This will be eventually the condition for calculating one of the design equations.
The analytical calculation of ZT(s) from the schematic in Figure 29 leads to:
𝑠 𝐿𝑠ℎ
𝑣𝑖𝑑 (𝑠) 𝐹 (1 + )
𝑅𝑠ℎ
𝑍𝑇 (𝑠) = = 𝑅𝑠ℎ
𝑖𝑀 (𝑠) 𝐿
𝑠 2 𝐶𝐿𝑃 𝐿𝑠ℎ 𝐹 + 𝑠 ( 𝑠ℎ + 𝐶𝐿𝑃 (𝑅𝑠ℎ + 2 𝑅𝐿𝑃 )) 𝐹 + 1
2𝑅

2𝑅
𝐹=
2 𝑅 + 𝑅𝑠ℎ + 2 𝑅𝐿𝑃
For s = 0, which means in DC regime, the transimpedance can be expressed as:
𝑍𝑇 (𝑠)|𝑠=0 = 𝑅𝑠ℎ 𝐹
This means that the factor F introduces a DC error. This factor indeed represents the portion of the DC current IM
that flows through the low pass filter resistors RLP and the input stage of the CSA (because of its non-infinite
input resistance R).
This error can be minimized by considering that Rsh << R and by imposing the 1st design equation:
𝑅
𝑅𝐿𝑃 <
𝑝
This condition leads to a DC gain error of:
𝑅𝑠ℎ − 𝑅𝑠ℎ 𝐹 1
𝐸𝑟𝑟𝑍𝑇 % = %< %
𝑅𝑠ℎ 1+𝑝

Application note 51 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Current sense amplifier

For example, for p = 100 the error would be less than 1%. It is therefore good practice to choose a value of RLP
between 1 Ω and 15 Ω.
The following considerations can then be applied:
 If p = 100 then F ≈ 1
 Rsh << RLP
 Lsh / 2R ≈ 0

These assumptions will lead to a final simplified transfer function:


𝑠𝐿 𝑠
𝑣𝑖𝑑 (𝑠) 1 + 𝑠ℎ 1+
𝑅𝑠ℎ 𝜔𝑧
𝑍𝑇 (𝑠) = ≈ 𝑅𝑠ℎ 2 = 𝑅𝑠ℎ 2
𝑖𝑀 (𝑠) 𝑠 𝐶𝐿𝑃 𝐿𝑠ℎ + 𝑠 𝐶𝐿𝑃 2 𝑅𝐿𝑃 + 1 𝑠 𝑠
+ +1
𝜔0 2 𝑄𝜔0
The parasitic inductance introduces a 2nd-order dynamics and a zero in the filter transfer function. The zero will
boost the transfer function, increasing the high frequency content of the step response. The poles instead,
depending on the filter values, could:
 Introduce a resonance (Q > 1/√2), which will result in a fast, but overshooting step response
 Split, one in low frequency and one at high frequency (Q < 1/√2) obtaining a slow, but smooth step response.

None of these effects is desirable because the goal is to obtain a flat response (at least within the bandwidth of
the CSA). A third option would be to try to cancel the dynamic of the zero with one of the poles. Partial cancelation
of the zero is indeed possible when:
𝐿𝑠ℎ
𝐶𝐿𝑃 =
2 𝑅𝐿𝑃 𝑅𝑠ℎ
This is the 2nd design equation. The pole/zero cancellation is never perfect in practice, because of the uncertainty
and variation of the passives values. So, this method gives the suboptimal value of CLP that maximizes the
bandwidth of the filter.
This design equation has to be considered as a starting point recommendation for the customer’s design. The
designer shall make use of the analytical tools shown in this chapter to choose the CLP value considering the
design’s specifications.
In Figure 30 the effect of four different CLP values on the normalized transfer functions and step responses can be
observed:
𝐻(𝑠) 𝑍𝑇 (𝑠)
;
𝐺 𝑅𝑠ℎ 𝑅𝑠ℎ

Application note 52 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Current sense amplifier

11.4.3 Conclusions
When all the design equations are used to select the current sensing and filter network, the transfer function from
measured current to output of the CSA can be simplified as:
𝑣𝑜 (𝑠) 𝑅𝑠ℎ 𝐺
𝐻𝑜𝑝𝑡 (𝑠) = = 𝑍𝑇 𝑜𝑝𝑡 (𝑠)𝐴𝑑 (𝑠) ≈ 4
𝑖𝑀 (𝑠) 1 + 𝑠 𝐶𝐿𝑃 2 𝑅𝐿𝑃 𝑠
( + 1)
𝜔𝑝

This means that:


 The DC error introduced by the finite CSA input impedance R is minimized
 The 2nd-second order dynamics introduced by the sensing resistor parasitic inductance Lsh is tamed

The speed of the signal is mainly affected by the CSA bandwidth. As shown in Table 16, the typical settling time
depends on the gain setting G. Figure 30 shows that the CSA bandwidth is capable to settle within 800 ns typically
for the highest gain (lowest bandwidth) setup. In a motor control with 20 kHz PWM, 800 ns represents a duty cycle
of 1.6%. So for applications where very high precision and fast response is needed by the current sensing, it is
suggested to setup the CSA (and design the passives) for the lowest gain possible.

Application note 53 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Current sense amplifier

Figure 30 Frequency and step response of the transfer functions ZT(s) and H(s) with different values
of CLP and the following values: Lsh=1 nH, Rsh=5 mΩ, RLP=10 Ω, G = 60.
The last value, 10 nF, is the suboptimal value that satisfies the 2nd design equation

Application note 54 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Sensor interfaces

12 Sensor interfaces
The TLE987x/6x family offers the option to interface different sensors and communication interfaces to the
device. Depending on the application requirements, one or more of these interfaces can be used by configuring
the corresponding functionality in the relevant device registers. This chapter presents some example interfaces
with relevant pins of the chip which can be used for these interfaces.

12.1 Implementing different interface connections to TLE987x/6x


Using different ports and their alternate select functions, multiple interfaces can be implemented including
TMR sensor (TLE987x-2QX only), Hall sensor, SPI, and UART. Figure 31 and Figure 32 each show two possible
configurations depending on the application requirement. External components which might be needed for
some of the interfaces have not been included, as they depend on the sensors which are used. In case some
interface is not needed, the relevant ports can be used as per application requirement.

P2.0 P0.2 MTSR


XTAL
P2.2 P0.3 SCK SPI
P2.4 P0.4 MRST

RXD P1.1 P1.0


UART2 TLE987x/6x
TXD P2.5

P1.2 Hall_1

P1.3 Hall_2
Hall
RXD P0.1
UART1 Sensor
TXD P1.4 P2.3 Hall_3

P2.0 P1.0 SCK


XTAL
P2.2 P1.1 MTSR SPI
P2.5 MRST
Hall_1 P1.2
P2.4
Hall Hall_2 P1.3 TLE987x/6x
Sensor
Hall_3 P2.3
P0.2 MTSR

RXD P0.1 P0.3 SCK SPI


UART P0.4 MRST
TXD P1.4

Figure 31 Example interfaces for TLE987x/6x

Application note 55 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Sensor interfaces

SIN_P P2.0
P1.0 SCK

SIN_N P2.2
TMR
P1.1 MTSR SPI
COS_P P2.4
P1.2 MRST

COS_N P2.5 P1.3

P2.3
TLE987x-2QX

P0.2 Hall_1

P0.3 Hall_2
Hall
RXD P0.1
UART Sensor
TXD P1.4 P0.4 Hall_3

SIN_P P2.0
P1.0 SCK

SIN_N P2.2
TMR
P1.1 MTSR SPI
COS_P P2.4
P1.2 MRST

COS_N P2.5 P1.3

P2.3
TLE987x-2QX

P0.2 MTSR

RXD P0.1 P0.3 SCK SPI


UART P0.4 MRST
TXD P1.4

Figure 32 Example interfaces for TLE987x-2QX

Application note 56 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
SWD (serial wire debug) interface circuitry

13 SWD (serial wire debug) interface circuitry


The serial wire debug interface (SWD) is used to download code to the MOTIXTM MCU or to debug the chip. This
chapter explains how to implement the circuitry around the chip to achieve a successful SWD connection.

13.1 Description of the SWD interface


The SWD interface provides a debug port for severely pin-limited packages, and as such may be used for small
package microcontrollers but also complex ASICs where limiting the pin count is critical and can be a critical
factor for the device cost.
As SWD interface, the TLE987x/6x uses the pins TMS (data) and P0.0 (clock). In the evaluation boards, the
signals are routed through a 5×2 pin header (SWD connector). The following implementation explains the
connection between embedded power IC and SWD interface.

13.2 Implementing an SWD interface connection to TLE987x/6x


The SWD interface can be directly connected to chips of the TLE987x/6x family. Figure 33 shows the
interconnections between the device and SWD connector.
External pull-up or pull-down resistors are not needed because internal pull-down resistors are present.
The GND for the SWD connector is the digital GND of the TLE987x/6x (pin 19).
A ceramic capacitor from the RESET pin to GND can be placed in order to improve immunity from transients.
The recommended value of the capacitor is 1 nF. If this capacitor is used, a blanking time of 31 μs in the reset
blind time register (CNF_RST_TFB) has to be configured.

PIN 40 VDDP PIN 1

PIN 20 TMS PIN 2

TLE987x/ GND
SWD connector
PIN 3, 5, 9

TLE986x PIN 21 P0.0 PIN 4

PIN 22 RESET PIN 10

Figure 33 SWD connection to the TLE987x/6x device

On the SWD interface of the TLE9879 EvalKit and TLE9869 EvalKit, pin 9 is used to deactivate the onboard
debugging circuit. In a typical implementation, this pin is used as GND. The pinout is shown in Figure 34.

Application note 57 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
SWD (serial wire debug) interface circuitry

Schematic Layout

PIN 1 PIN 2

Figure 34 SWD interface implementation for an application

Application note 58 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Unused pins

14 Unused pins
Table 17 shows the recommendations for the TLE987x/6x pins, in case they are not used in the application.
The GND digital pins are pin 19 and pin 28, while the GND analog is pin 39.

Table 17 Connecting unused pins

Type Pin number Recommendation 1 Recommendation 2


(if unused) (if unused)
CP1L, CP2H, 1, 3, 4, 48 Open –
CP2L, CP1H
VCP 2 Open –
GH3, GH2, GH1, 5, 7, 9, 11, 12, 13 Open –
GL3, GL2, GL1
SH2, SH1, SL, 6, 8, 10, 46 GND –
SH3
MON 14 GND analog/digital Open + configured
internal PU/PD
GPIO 15, 16, 17, 18, 21, 23, GND analog/digital External PU/PD
24, 25, 26, 27, 31, 32, 35 or
Open + configured
internal PU/PD
TMS 20 Open –
RESET 22 Open –
P2.0 / XTAL1 29 GND analog/digital –
P2.2 / XTAL2 30 Open –
VAREF 34 Open (VAREF disabled) –
CSA 36, 37 Open (CSA disabled) –
VDH 44 GND –
VDDEXT 45 Open (VDDEXT disabled) –
VSD 47 GND Connect to VS for
monitoring purpose
LIN 48 Open –

Application note 59 Rev. 1.1


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TLE987x/6x
Hardware design guideline
Layout guidelines

15 Layout guidelines
In this chapter general recommendations are provided regarding PCB layout, as well as some specific hints for
microcontrollers and MOSFET bridge drivers.

15.1 General PCB recommendations


Electromagnetic interference (EMI) is mainly radiated by the PCB and the connected cables. In fact, cables are
very efficient antennas, especially for common-mode currents. Loops on the PCB are regarded as good emitting
antennas. Loops inside an IC are considered to be small compared to the external loops on PCB and cabling.
Therefore, EMI from the IC can be neglected in most cases. Below there are some considerations for an
EMI-aware system/PCB design:
 Signal lines from outside need to be filtered
 Buffer capacitor for supply pins
 Decoupling ceramic capacitors ≤ 100 nF
 Filter and decoupling devices close to disturbance source
 Low-impedance ground plane
 Place filter and storage coils away from sensitive parts
 Pi-filter design with decoupled input/output side, by orthogonally placed components
 PCB format which allows short routing traces
 Multiple vias for filter capacitor GND connections
 GND plane close to component side
 Separate power from control signals
 Fast signals with short connection traces away from PCB border
 Shielding of critical lines by parallel GND lines

Application note 60 Rev. 1.1


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TLE987x/6x
Hardware design guideline
Layout guidelines

15.1.1 Placement of the connectors


Having connectors on both sides of the PCB might cause high emissions. A good PCB design should place all
connectors on the same side.

Figure 35 Placement of the connectors

15.1.2 Floor-planning the PCB


For the placement of components, the following rules should be considered:
 All components from one group should be located together (power, digital, analog, supply, and so on)
 Connectors should all be placed on the same side
 Susceptible parts should be placed away from noisy parts (power, digital, analog)
 Parts that generate noise should be close to a connector
 Route all traces to the components in each zone as if this zone had its own ground plane

For simplicity and clarity reasons, number the components in each zone in the same way (for example,
analog = 100, digital = 200, power = 300, and so on).

Application note 61 Rev. 1.1


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TLE987x/6x
Hardware design guideline
Layout guidelines

15.1.3 Routing the power supply traces


Wiring loops on the PCB should be as small as possible.

Figure 36 Routing the power supply traces

Application note 62 Rev. 1.1


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TLE987x/6x
Hardware design guideline
Layout guidelines

15.1.4 Number of PCB layers


Table 18 Rules for different PCB types
Two-layer PCB  Keep the loop areas that are
(no ground plane) formed by ground and power
supply traces as small as possible
 Route power supply traces always
together (parallel, next to each
other) starting from one central
start point and spreading into
each individual zone
 Do not mix the supplies of
different zones
 Fill free areas with ground
Two-layer PCB  Use a solid ground plane
(solid ground plane)  Components of one zone should
be supplied by only one supply
from a central star point
 Do not mix the supplies of
different zones
 Supply traces cannot have loops;
use a tree structure instead
Multilayer  Keep ground and power supply
configuration layers next to each other. This
(4 layers) provides a good decoupling
capacitor for free
 Avoid slots in ground and power
supply planes (for example, by
routing signal traces within these
planes, vias in a row, through-hole
connectors)
Multilayer  Route critical signals (for example,
configuration high-frequency signals,
(> 4 layers) susceptible signals) in an inner
signal layer that is embedded
between two ground layers
 Give each power supply domain
(for example, 5 V, 3.3 V) a separate
power and ground plane

Application note 63 Rev. 1.1


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TLE987x/6x
Hardware design guideline
Layout guidelines

15.2 Specific PCB design rules for microcontroller with bridge drivers
Some general recommendations are:
 Separate the IC supply (VS and VSD) from VDH, that is, separate voltage sense line from power stage
 For minimal power dissipation, the recommended package for serial resistor at MON is SMD1206
 Placeholder for RC snubber circuit for all bridge MOSFETs should be considered for damping of circuit
resonances during switching (if needed)
 For better filter performance and longer life, low-ESR electrolytic capacitors, rated for higher ripple current,
should be used
 When a shunt resistor is used, the maximum acceptable capacitance between VDH and SL is 30 µF.
Higher values would affect the current sensing too much
 The input capacitor, flying capacitors and tank capacitor should have short traces to reduce radiated
emission and voltage drop across the trace inductances
 The DC-link capacitors should be placed close to the power stage in order to get stray inductance as low
as possible

15.2.1 GND concept


Ground planes should be placed to separate the power MOSFETs’ switching currents and the IC operating
currents as much as possible. Figure 37 shows these currents and the symbols used for their return paths.

VDH

VDH
VCP
VSD
Reverse-
VDH polarity EMI filter
Charge pump protection

HSx
GHx
VBAT
SHx
Motor
VS
phase x
LSx
Logic GLx
PMU
GND SL

Rsh
VDDEXT VDDP GND (pin 39)

VDDC

IC GND PWR GND

PWM switching currents in purple, IC supplies current in orange

Figure 37 GND concept and main current paths

Application note 64 Rev. 1.1


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Hardware design guideline
Layout guidelines

This solution has two beneficial effects:


 The three main GND pins (19, 28, 39) are not influenced by the PWM currents. Voltage differences in the
internal ground connections of the analog and digital circuitry in the IC will be limited
 High-frequency current interactions with the battery ground terminal will be limited

A practical example is shown in Figure 38. The connection between the PWR GND (mid-top) and IC GND (mid-
bottom) planes consists of a slim trace and a via. This connection ensures the IC's current supply, while
rejecting high-frequency currents that could loop from the IC to the battery. Consider these guidelines for the
GND pin routing:
 Pin 39 should have the most solid connection to the IC GND plane. In the layout example this is
accomplished by taking advantage of the exposed pad solid connection through multiple vias. When this is
not feasible, connect the VDDC capacitor's GND pin to IC GND with as many vias as possible
 Pin 19 and 28 can have a weaker connection to IC GND

To minimize the stray inductance, the loop “input cap – bridge MOSFET – shunt resistor” should be as small as
possible
A typical conducted EMI spectrum of an application that follows these rules is shown in Figure 39. This
measurement has been performed on the layout example with the motor-running functions turned off to
highlight the spectral contribution of the AC currents generated by the IC.

Floating PWR GND

VC P

VSD

VS

VD DC

VD DP
Top layer

Mid-top layer

IC GND

Mid-bottom Layer

Figure 38 Example PCB layers

Application note 65 Rev. 1.1


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Hardware design guideline
Layout guidelines

Figure 39 Conducted EMI measurement spectrum related to the layout example

15.2.2 Layout recommendation for 3-phase motor bridge


Figure 40 shows the commutation circuit of one bridge leg. This bridge leg can be a part of a 2-phase or
3-phase bridge.

Figure 40 Layout – one bridge leg with two N-MOSFETs (as part of a 2-phase or 3-phase motor bridge)

During a transition from the low-side to the high-side, the current is commutating from LS switch to HS switch.
The ideal commutation circuit is a loop consisting of CDC, THS and TLS. The inductive part of the real circuit is
considered in the stray inductance Lσ. Overvoltages are induced over Lσ during the switching. These
overvoltages are coupled directly to OUT and VS and will also cause radiated emission. The size of the
commutation circuit has to be as small as possible.
Application note 66 Rev. 1.1
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TLE987x/6x
Hardware design guideline
Layout guidelines

Figure 40 shows an example for a low-impedance layout of one motor bridge leg.
The capacitors C2, CS-H and CS-L are placed as close as possible to the device pins.
Figure 41 shows a recommendation for the commutation circuit of a 3-phase motor bridge.

Figure 41 Layout recommendation – 3-phase motor bridge

Application note 67 Rev. 1.1


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Hardware design guideline
Layout guidelines

15.2.3 Layout recommendation for a current sense shunt


The layout affects the current sensing of the shunt. A low-inductive shunt is no guarantee for a low-noise
measurement signal. The quality of the signal depends on the layout with trace parasitics:
 Use a four-wire sense approach with symmetric sense lines
 Avoid inductive coupling into the sense wires
 Take care of capacitive currents on the leads in presence of high ∆V/∆t (common mode noise)

Figure 42 Layout recommendation – current sense shunt


No magnetic current sensing, pseudo-four-wire technique

Application note 68 Rev. 1.1


2022-04-01
TLE987x/6x
Hardware design guideline
Layout guidelines

Revision history

Document Date Description of changes


revision
1.1 2022-04-01 General:
 Renamed “Embedded Power IC” to “MOTIXTM MCU”
 Added “type: X7R” to the component selections
 Editorial changes
Chapter “3 Clock generation unit (CGU)”
 Added chapter “Ceramic resonator”
Chapter “9 Bridge driver”
 Added “Source resistor at the SHx pin” as an external component

Chapter “10 Charge pump”


 Updated “Charge pump application diagram”
 Switched equations in chapter “Charge pump: how it works”
 Changed voltage ripple time in chapter “Calculation example”

Chapter 11 “Current sense amplifiers”


 Changed Lsh = 1 µH to Lsh = 1 nH

Chapter “14 Unused pins”


 Updated table “Connection of unused pins”
Chapter “15 Layout guidelines”
 Renamed headings, moved chapter “Added considerations for an
EMI-aware system/PBC design”
 Removed chapter “Input filter”, figure “Ground concept and bypass
capacitors, and chapter “Bypass capacitors”
Added chapter “4 General purpose inputs outputs (GPIO)”
Added chapter “7 Analog to digital converters (ADC1)”
Added chapter “8 Sigma-delta analog digital converters (ADC3/4)”
Added chapter “12 Sensor interfaces”
1.0 2020-10-30 Initial creation

Application note 69 Rev. 1.1


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