BLDC - PMSM Control Application Hardware Design Guidelines
BLDC - PMSM Control Application Hardware Design Guidelines
BLDC - PMSM Control Application Hardware Design Guidelines
Z8F80032532
TLE987x/6x
Hardware design guideline
Application note
Intended audience
This application note is addressed to embedded hardware and software developers using the TLE987x/6x
devices to design ECUs (electronic control units) for BLDC/PMSM motor control applications.
*
Arm and Cortex are registered trademarks of Arm Limited, UK
Application note Please read the sections “Important notice” and “Warnings” at the end of this document Rev. 1.1
www.infineon.com 2022-04-01
TLE987x/6x
Hardware design guideline
Table of contents
Table of contents
About this document ......................................................................................................................... 1
Table of contents .............................................................................................................................. 2
1 TLE987x/6x family .................................................................................................................... 4
1.1 TLE987x/6x block diagram ...................................................................................................................... 4
1.2 TLE987x/6x family comparison ............................................................................................................... 5
1.3 Application information .......................................................................................................................... 6
2 Power supply generation unit (PGU) .......................................................................................... 9
2.1 Block diagram.......................................................................................................................................... 9
2.2 Input voltage, VS pre-regulator VPRE, and reference voltage VAREF.................................................. 10
2.3 VDDP voltage regulator 5.0 V ................................................................................................................ 12
2.4 VDDC voltage regulator 1.5 V ................................................................................................................ 12
2.5 VDDEXT voltage regulator 5.0 V ............................................................................................................ 13
3 Clock generation unit (CGU) .....................................................................................................14
3.1 Block diagram........................................................................................................................................ 14
3.2 External Input Clock mode.................................................................................................................... 15
3.3 External Crystal mode ........................................................................................................................... 16
3.3.1 Ceramic resonator............................................................................................................................ 17
3.4 Layout recommendations ..................................................................................................................... 17
4 General purpose inputs outputs (GPIO) .....................................................................................18
4.1 Pull-up and pull-down devices and pin state ....................................................................................... 18
4.2 Software settings and hardware considerations ................................................................................. 19
4.3 Serial resistor for high-speed signals ................................................................................................... 19
5 LIN transceiver ........................................................................................................................21
6 High-voltage monitor input ......................................................................................................22
6.1 Block diagram........................................................................................................................................ 22
6.2 Application hints ................................................................................................................................... 22
7 Analog to digital converters (ADC1) ...........................................................................................23
7.1 Software settings and hardware considerations ................................................................................. 23
7.2 Signals ADC1 .......................................................................................................................................... 23
7.3 ADC1 measuring principle ..................................................................................................................... 23
7.4 ADC1 external components design....................................................................................................... 23
7.4.1 Anti-aliasing filter design ................................................................................................................. 24
8 Sigma-delta analog digital converters (ADC3/4) .........................................................................26
8.1 Software settings and hardware considerations ................................................................................. 26
8.2 ADC3/4 measuring principle ................................................................................................................. 26
8.3 ADC3/4 external components design ................................................................................................... 26
9 Bridge driver (excluding charge pump) .....................................................................................29
9.1 Application diagram .............................................................................................................................. 29
9.2 External components ............................................................................................................................ 30
10 Charge pump ..........................................................................................................................33
10.1 Application diagram .............................................................................................................................. 33
10.2 Charge pump: how it works .................................................................................................................. 33
10.2.1 ICP load current calculation ............................................................................................................ 36
10.3 Charge pump external capacitors design............................................................................................. 41
10.3.1 Calculation example ........................................................................................................................ 42
1 TLE987x/6x family
The TLE987x/6x is a single-chip 3-phase/2-phase motor driver that integrates the industry standard
Arm® Cortex®-M3 core, enabling the implementation of advanced motor control algorithms such as
field-oriented control.
It includes six (TLE987x) or four (TLE986x) fully integrated NFET drivers optimized to drive a 3-phase or 2-phase
motor via external power NFETs, programmable current sources along with slope control for optimized EMC
behavior and an integrated charge pump enabling low-voltage operation. Its peripheral set includes a current
sense amplifier, a successive approximation ADC optionally synchronized with the capture and compare unit
for PWM control, and 16-bit timers. A LIN transceiver to enable communication with the device and several
general-purpose I/O units are also integrated. It includes an on-chip linear voltage regulator to supply external
loads.
Unlike the other members of the TLE987x family, the TLE9879-2QXA40 incorporates two 14-bit sigma-delta
ADCs, which provide a reliable interface for an external GMR/TMR sensor.
In the variants with the sigma-delta ADCs, the XTAL1 and XTAL2 pins for the external oscillator are not available.
LPF ILT
VBAT
CPF ILT1 CPF ILT2
DVS
VDDP VDDC
VS CP1H
CVS 2 CVS 1 CCPS1
CP1L
CP2H CCPS2
CP2L
RMON
IGN VCP
MON RVS D CVCP
CMON
VSD
CVS D
RVDH
VDH
LIN LIN CVDH
CLIN D
GND_LIN RGA TE
G
RGA TE
S
G
D
M
GL2
Temperature TL2
S
SL
ROP AFI LT
OP2 RGA TE
1)
Note: Not connected to board GND.
LPF ILT
VBAT
CPF ILT1 CPF ILT2
DVS
VDDP VDDC
VS CP1H
CVS 2 CVS 1 CCPS1
CP1L
CP2H CCPS2
CP2L
RMON
IGN VCP
MON RVS D CVCP
CMON
VSD
CVS D
RVDH
VDH
LIN LIN CVDH
CLIN D
GND_LIN RGA TE
G
CCOS_P
CVG MR
CSI N_N
CSI N_P
RGA TE
S
G
D
M
GL2
TL2
RGS CGS
D
RGA TE S
P0.3 G
GL3
P0.2 TL3
RGS CGS
P0.1
S
P0.4 SL
ROP AFI LT
P1.4
OP2 RGA TE
P1.3
COP AFI LT RShunt
P1.2
P1.1 OP1 RGA TE
ROP AFI LT
P1.0
RESET
TMS
Debug Connector
P0.0
GND
RTM S
GND
BLDC System
1)
Note: Not connected to board GND.
VS
VPRE
PMU
If data should be saved in the flash memory at power down, the selection of CVS2 should be done in order to
ensure that operations modifying the content of the flash are never interrupted (for example, in case of power
loss). Assuming that at power loss detection all the peripherals are disabled, the power is still consumed by the
MCU and flash erase and write operations. The size of CVS2 can be calculated using the equation:
𝐼×𝑡
𝐶𝑉𝑆2 ≥
∆𝑉
Where:
I is the current consumption at power down
t is the time for which the MCU should stay active after power loss
ΔV is the difference between the voltage at the time when the loss of power is detected and the reset voltage
of the MCU
As reported in the TLE987x/6x product datasheets, the supply voltage in Active mode with reduced
functionality (full MCU and flash operation) has a minimum value of 3 V. For example, assuming 10 mA as the
current consumption during power down, 20 ms as the time needed to save the flash content, and 3 V as ΔV,
then CVS2 must be at least 67 µF.
The voltage pre-regulator VPRE generates an internal voltage of about 7 V from the VS input. The output
voltage of VPRE is used as input for the internal voltage regulators, and it is not accessible externally.
The IPRE current is shared between the VDDP and VDDEXT voltage regulators. The table summarizes the
maximum currents allowed for each voltage regulator.
The voltage VAREF is derived from VPRE and it can be used as 5 V reference voltage for the internal
AD converters. The value of the capacitor CVAREF is in the range of 100 nF up to 1 μF.
Notes
1. The output capacitor CVDDP is necessary for the stability of the output voltage.
2. The values of the CVDDP capacitors are specified in the table below.
3. One single ceramic capacitor can be used, as long as the value is within the recommended range.
4. The CVDDP capacitor should be placed as close as possible to the VDDP pin in the layout.
5. For EMC reasons, a ferrite bead can be placed between the VDDP pin and the CVDDP capacitor.
Notes
1. The output capacitor CVDDC is necessary for the stability of the output voltage.
2. The values of the CVDDC capacitors are specified in the table below.
3. One single ceramic capacitor can be used, as long as the value is within the recommended range.
4. The CVDDC capacitor should be placed as close as possible to the VDDC pin in the layout.
5. It is NOT possible to place a ferrite bead between the VDDC pin and the CVDDC capacitor.
6. For EMI reasons the ground of the VDDC and the ground of the TLE987x/6x can be separated by placing a ferrite
bead between the two ground points.
Notes
1. The output capacitor CVDDEXT is necessary for the stability of the output voltage.
2. The values of the CVDDEXT capacitors are specified in the table below.
3. One single ceramic capacitor can be used, as long as the value is within the recommended limits.
4. The CVDDEXT capacitor should be placed as close as possible to the VDDEXT pin in the layout.
5. In case VDDEXT is not used and disabled, the output capacitor CVDDEXT is not needed. The pin VDDEXT can be
left open.
CGU
OSC_CON PLLCON
CMCON1 SYSCON0
XTAL1 PLL
OSC_HP fPLL
XTAL2
Int
Osc
fOSC_int CCU fSYS
fLP_CLK
LP_CLK
PMU
Phase-locked loop (PLL) module: generates the clock fPLL in different modes:
− Prescaler mode (VCO Bypass mode)
− Normal mode
− Free-running mode
The reference frequency fR can be selected to be taken either from the internal oscillator fINT or from an
external clock source fOSC_INT.
The PLL uses up to three dividers to manipulate the reference frequency in a configurable way. Each of
the three dividers can be bypassed corresponding to the PLL operating mode.
Clock control unit (CCU): enables the selection of the source for fSYS
OSC_HP
XTAL1
fXTAL1 fOSC_int
Not XTAL2
connected
OSC_HP
XTAL1
fOSC_int
fOSC
XTAL2
RXTAL2
CXTAL1 CXTAL2
GND = pin 39 = VSS
The values and the corresponding operating ranges depend on the chosen crystal and have to be determined
and optimized in cooperation with the crystal vendor, using the negative resistance method, which is the most
common test for start-up and oscillation reliability of the oscillator. This method is about the insertion of a test
resistor in series with the quartz crystal and the monitoring of the drive current. Typically, this test does not
result in one set of circuitry values which is the ‘right one’, but it indicates a recommended range. Depending
on further system requirements such as XTAL1 amplitude specification or oscillator frequency, the final
circuitry values of the oscillator are then selected.
More information about the test method can be found in the Infineon application note “Crystal Oscillator
Basics AP56002”.
The oscillator can operate for a specified set of crystals with known ESR and parasitic capacitances CIO and CO
up to a specific value.
Choosing different crystals requires detailed consideration of parasitics, external circuitry, frequency range,
and quality of the intended crystal. Its proper operation has to be verified by testing.
SMD
quartz crystal
VIO is the signal generated by the sending GPIO and VIO2 the signal seen by the receiving GPIO. Each GPIO has a
pin capacitance (P_5.1.19).
The trace capacitance and inductance depend on the traces’ width (W), length (L), thickness (T), PCB layer
thickness (H) (all dimensions in meter), the PCB’s dielectric constant 𝜀𝑅 , and vacuum permittivity 𝜀0 . The used
formula is only valid for surface traces with an adjacent power or ground plane.
𝑊×𝐿
𝐶𝑇𝑟𝑎𝑐𝑒 = 𝜀𝑅 × 𝜀0 × [𝐹]
𝐻
8×𝐻 𝑊
𝐿 𝑇𝑟𝑎𝑐𝑒 = 0.2 × 𝑙𝑛 ( + ) × 𝐿 [𝑛𝐻]
𝑊 4×𝐻
The trace capacitance and inductance are calculated for a standard trace width of 0.2 mm and thickness of
0.04 mm and a PCB layer thickness of 1.6 mm. VIO is 5 V and rises and falls within 1 ns. VIO and VIO2 are plotted for
different trace lengths and serial resistor dimensions in Figure 11.
For traces with a length of 100 mm, a 90 Ω resistor suppresses ringing efficiently. If production spread and
temperature dependency are considered, 220 Ω are sufficient for most applications.
5 LIN transceiver
The LIN module is a transceiver for the local interconnect network (LIN) compliant to the LIN2.2 standard,
backward compatible to LIN1.3, LIN2.0 and LIN2.1. It operates as a bus driver between the protocol controller
and the physical network. The LIN bus is a single-wire, bidirectional bus, which is typically used for in-vehicle
networks, using data rates between 2.4 kBaud and 20 kBaud. Additionally, data rates up to 115.2 kBaud are
supported.
VS
LIN transceiver
RBUS LIN.CTRL_STS
LIN
CTRL
Driver, current TxD_1
limiter, and LIN-FSM from
TSD STATUS UART
GND_LIN
Transmitter STATUS
CTRL
RxD_1 to
Filter UART and
TIMER2,
pin T2EX
(T2EXCON=0,
T2EXIS=0)
Receiver
Filter
LIN_Wake
Sleep comparator
GND_LIN
It is recommended to put a 220 pF capacitor between the LIN and the GND_LIN pins. This complies with the
LIN specification 2.2. The GND_LIN pin has to be connected to a global ground net outside of the chip.
In order to avoid interferences with the SoC’s core voltage, it is recommended to connect GND_LIN to the same
ground net of the power MOSFETs – called power GND. It is strongly advised not to wire GND_LIN to a
connector which leaves the PCB. The global ECU ground level shall be used as a reference for the LIN
connection. To reduce digital ground bounce transmitted via LIN, GND_LIN should not be connected directly to
the GND of the TLE987x/6x. It is better to have a slight decoupling by using few millimeters of trace. The LIN
transceiver can be used also with PWM control. In this case, a pull-up resistor between the LIN input and the
battery input voltage should be placed. The value of the pull-up resistor is ≥ 1 kΩ. In case additional filtering is
needed because of EMC issues, common mode chokes before the LIN pin are not recommended. A ferrite bead
placed at GND_LIN is preferred.
Application note 21 Rev. 1.1
2022-04-01
TLE987x/6x
Hardware design guideline
High-voltage monitor input
VS
MON
+ Filter to internal
circuitry
-
MON
Logic
SFR
VLV
RADC1IN P2.0
CH0
CSA ADC1
CADC1IN CH1
P2.2
ADCCORE
CH2
P2.3
CH3 RAIN S1 S2 D
P2.4 MUX
CH4
Cap array A
P2.5
CAINS
CH5
VDH
CH6
Rin_VDH,measure
NC
CH7
ATTVDH_1
ATTVDH_2
ATTVDH_3
With:
Resulting in a desired time constant for the external anti-aliasing filter of:
1
𝜏𝐴𝐷𝐶1𝐼𝑁 =
(𝑓𝐴𝐷𝐶𝐼 𝑥 𝜋)2 × 𝜏𝐼𝑁
With:
fADCI(min) = 5 MHz and fADCI(max) = 24 MHz (P_9.2.4)
RAIN = 2 kΩ (P_9.2.16)
CAINS = 4 pF (P_9.2.15)
Resulting in:
− ADC1IN(5 MHz) = 507 ns
− ADC1IN(24 MHz) = 22 ns
To improve the accuracy of the sensor interface, the cut-off frequency (fC) for -3 dB attenuation has to be
decreased. This will decrease the RMS output noise (VNoise) of the SDADC for the maximal signal
amplitude (AX/Ydiff).
The original resolution of sensor is given with AX/Ydiff = 2.8 V and VNoise(fC) = 3 mV
𝐴𝑋𝑌𝑑𝑖𝑓𝑓 2.8 𝑉
𝑛 = 𝑙𝑜𝑔2 × ( ) 𝑏𝑖𝑡 = 𝑙𝑜𝑔2 × ( ) 𝑏𝑖𝑡 ≈ 10 𝑏𝑖𝑡
𝑉𝑁𝑜𝑖𝑠𝑒 (𝑓𝐶 ) 3 𝑚𝑉
The cut-off frequency of the SDADC can be changed with an external RC-filter to match the maximum input
frequency of the SDADC (P_10.1.8), gaining resolution in the sensor while sacrificing bandwidth. Since the
sensors RMS noise is pink-noise the spectral noise density is constant for different cut-off frequencies can be
calculated with the formula below. With fnew = 2 × P_10.1.8 = 2 kHz the new RMS noise results in:
𝑓𝑛𝑒𝑤 2 𝑘𝐻𝑧
𝑉𝑁𝑜𝑖𝑠𝑒(𝑓𝑛𝑒𝑤 ) = 𝑉𝑁𝑜𝑖𝑠𝑒 (𝑓𝐶 ) × √ = 3 𝑚𝑉 × √ = 775 µ𝑉
𝑓𝑐 30 𝑘𝐻𝑧
With a dynamic input impedance (P_10.1.15) ZIN = 250 kΩ and the maximum gain error GERR = 0.5% RSINCOS
is given with:
𝑅𝑆𝐼𝑁𝐶𝑂𝑆 (max) = 𝑍𝐼𝑁 × 𝐺𝐸𝑅𝑅 = 250 𝑘𝛺 × 0.5% = 1.25 𝑘𝛺 ≈ 1 𝑘𝛺
from battery
VCP DC link
CPH Ax CPH Bx
RVD H
+ VDH
CVD H
VDS
- High Side
Driver CGD D
RGATE
GHx G CS
THx
VREF
RGGND RGS CGS
RS
S
SHx
IPD D ia g CEM CP x DSH RSH
to motor
Low Side
+ Driver CGD D
RGATE
VDS GLx G
TLx
- RGGND RGS CGS
VREF
SL
to ground
Gate resistor
The optional gate resistor RGATE suppresses potential oscillations between PCB line inductances and MOSFET
capacitances, which build up an LC oscillator that can be stimulated by fast transients during MOSFET
switching. The value of RGATE depends on the PCB layout conditions, MOSFET parasitics, and switching speed,
but should be as small as possible, preferably in the range from 2 Ω to 10 Ω.
Gate-to-source resistor
The gate-to-source resistor RGS terminates the gate of the external MOSFET to its source. It should be placed as
close as possible to the MOSFET to keep it turned off, for example, in the case of electromagnetic interference
(EMI) or broken PCB lines. The recommended value is 100 kΩ.
Gate-to-source capacitor
The optional gate-to-source capacitor CGS linearizes the intrinsic MOSFET gate-to-source capacitors and
reduces the tolerance of the total gate-to-source capacitance seen by the gate driver. The value of CGS should
be large enough to dominate the intrinsic MOSFET gate-to-source capacitance CGS_int.
The recommendation is: CGS ≥ 2 × CGS_int.
Notes:
1. The maximum gate charge Qtot_max per MOSFET including the external gate capacitors must not exceed 100 nC
for VQFN variants and 150 nC for TQFP variants.
2. CGS_int is usually not directly given in MOSFET datasheets, but can be estimated from parameters like Ciss or Qgs.
Gate-to-drain capacitor
The optional gate-to-drain capacitor CGD linearizes the intrinsic MOSFET gate-to-drain capacitor and reduces
the tolerance of the total gate-to-drain capacitance seen by the gate driver. The placement of CGD is
recommended, if it is important for the application to have a well-controlled linear slew rate at the SHx pin:
ΔVSHx / Δt = IGATE / CGD.
Notes:
1. The maximum gate charge Qtot_max per MOSFET including the external gate capacitors must not exceed 100 nC
for VQFN variants and 150 nC for TQFP variants.
2. In order to avoid unintended switch-on of the MOSFET during fast transients, the following condition must be
met: CGD / CGS ≤ 1 / 10.
DC link capacitors
The DC link capacitors CPHAx and CPHBx serve two purposes:
1. CPHAx serves as a buffer capacitor
2. CPHBx suppresses double-digit MHz oscillations on the DC link voltage
The total value of all DC link capacitors CPH_tot = ∑ (CPHAx + CPHBx) depends on the acceptable DC link voltage ripple
caused by PMW operation and on additional application-specific requirements, like having motors operating in
generator mode or the need to buffer the motor energy in the case of an emergency shutdown of the MOSFETs.
Note: CPH_tot must be large enough to always keep all connected input pins (for example, VDH, VSD)
within their absolute maximum ratings.
As a starting point for the value of CPH_tot, a rule of thumb is 230 µF per 10 A motor current. The bigger part of the
capacitance is covered by electrolytic capacitors CPHAx and the rest by ceramic capacitors CPHBx. It is
recommended to choose capacitors with low ESR and low self-inductance and place them close to their
respective high-side MOSFETs, in order to minimize series resistances and inductances in the high-current path.
Snubber
The optional snubber RS and CS reduces voltage peaks and ringing at the motor pin, which can be caused by
PCB parasitics like series inductances. The values for RS and CS depend on the half-bridge power ratings and on
the parasitics of the selected MOSFET.
Starting values for RS and CS can be derived from the following constraints:
RS ≤ VDClink / Imotor in order to keep the voltage across RS always smaller than the DC link voltage
Note: RVDH performs an additional protection role by limiting the current out of the VDH pin in the case of
a reverse-polarity event or other undershoots of the DC link voltage.
10 Charge pump
The charge pump is intended to supply the bridge driver integrated in the TLE987x/6x, as well as the Back-EMF
comparators. The purpose of this chapter is to provide a design method for the external capacitors, depending
on the application requirements.
VDC
CVCP
RVSD
CHARGE PUMP
BDRV
MOSFET
driver
GND
The switches of the charge pump are driven by an internal clock (CLK) with a frequency equal to fSW, derived
from the TLE987x/6x system clock. The following pattern applies (Figure 18):
Clock set to low: the capacitor CCPS1 is charged by VSD, while the energy of CCPS2 is transferred to the
output, boosting the voltage VCP of the capacitor CVCP. Considering VDROP1 as the voltage drop of the
switches of the first stage and ignoring the load current, the average voltage VCPS1 can be expressed as:
Where: VDROP as the is the total voltage drop of the switches of the charge pump.
Clock set to high: the energy is transferred from CCPS1 to CCPS2, while the output voltage VCP is buffered
by the bulk capacitor CVCP. Considering VDROP2 as the voltage drop of the switches of the first and second
stage and ignoring the load current, the average voltages VCPS2 and VCP can be expressed as:
VSD VSD
CLK CLK
nCLK nCLK
CCPS1 CCPS1
VCPS1 VCPS1
nCLK nCLK
CVCP CVCP
CLK CLK
nCLK nCLK
CCPS2 CCPS2
VCPS2 VCPS2
CLK CLK
nCLK nCLK
BDRV BDRV
MOSFET MOSFET
driver VCP driver VCP
Figure 18 Basic scheme of the charge pump (left: clock set to low; right: clock set to high)
Including now the load current in the calculation, the output voltage VCP can be expressed as:
Equation 1:
𝑉𝐶𝑃 = 3 𝑉𝑆𝐷 − 𝑉𝐷𝑅𝑂𝑃 − 𝑅𝑂𝑈𝑇_𝐴𝑉𝐺 × 𝐼𝐶𝑃
Where:
ICP is the average output current, as sum of the bias current of the bridge driver and the total current
needed to drive the MOSFETs gates
ROUT_AVG is the average output resistance of the charge pump, which can be expressed as:
Application note 34 Rev. 1.1
2022-04-01
TLE987x/6x
Hardware design guideline
Charge pump
Equation 2:
2 3
𝑅𝑂𝑈𝑇_𝐴𝑉𝐺 ≈ +
𝑓𝑆𝑊 × 𝐶𝐶𝑃𝑆 4 × 𝑓𝑆𝑊 × 𝐶𝑉𝐶𝑃
Where:
fSW is the switching frequency of the charge pump, and CCPS1 and CCPS2 are both equal to CCPS
Considering:
Equation 3:
𝑉𝐷𝑅𝑂𝑃 = 𝐼𝐶𝑃 × 𝑅𝐸𝑄
Where:
REQ is an average resistance, which takes into account the total voltage drop VDROP in respect to the output
current. A value of REQ fitting to the charge pump implemented in the TLE987x is about 100 Ω.
Figure 19 shows the equivalent circuit as expressed by the Equation 4.
VCP
REQ ROUT_AVG
3VSD ICP
Considering the wide range of the input voltage VSD, the charge pump of the TLE987x limits the output voltage
VCP according to the following relations:
14 𝑉 𝑖𝑓 𝑉𝐶𝑃 − 𝑉𝑆𝐷 ≥ 14 𝑉
𝑉𝐶𝑃 − 𝑉𝑆𝐷 ≅ {
𝑉𝐶𝑃 − 𝑉𝑆𝐷 𝑖𝑓 𝑉𝐶𝑃 − 𝑉𝑆𝐷 < 14 𝑉
Note: Important to note is that the above equations are aiming to provide an equivalent model of the
charge pump considering average values of the electrical parameters, not RMS (root medium
square) values.
For this reason, they should not be used straightforward to calculate the power dissipation of
the charge pump itself.
VSD
CVCP
RVSD
VSD VCP
ICP
VSD
CHARGE ICH HS
GHx
PUMP
VGS IDIS HS
clamp
GND SHx
to the motor
ICH LS
GLx
VGS IDIS LS
clamp
SL
Rsh
Figure 20 Schematic representation of the high-side and low-side MOSFET gate charge (green) and
discharge (blue) currents paths (left). Bias current in red. Each gate driver block is
repeated 3× in the TLE987x, while 2× in TLE986x
The gate charge QMOSFET can be determined from the characteristics of the MOSFET. A typical gate charge graph
of an automotive Infineon MOSFET (IAUA120N04S5N014) is shown in the Figure 21.
In the bridge driver implementation of the TLE987x/6x, the HS and LS gate source voltages VGS are limited by
an internal clamping. In Figure 22 a simplified schematic of the bridge driver is illustrated. It can be assumed
that the MOSFETs ON-resistances and the current sensing resistor Rsh are in the order of magnitude of [mΩ]. As
a consequence the following approximations can be made:
When HSx is ON and LSx is OFF → VPHx ≅ VSD
When LSx is ON and HSx is OFF → VPHx ≅ VSL ≅ GND
Taking this into account, the typical average VGSHS (for the HS) and VGSLS (for the LS) voltages can be
estimated as:
Equation 8:
12.5 𝑉 𝑖𝑓 𝑉𝐶𝑃 − 𝑉𝑆𝐷 ≥ 14 𝑉
𝑉𝐺𝑆𝐻𝑆 ≅ {
𝑉𝐶𝑃 − 𝑉𝑆𝐷 − 1.5 𝑉 𝑖𝑓 𝑉𝐶𝑃 − 𝑉𝑆𝐷 < 14 𝑉
12.5 𝑉 𝑖𝑓 𝑉𝐶𝑃 ≥ 14 𝑉
𝑉𝐺𝑆𝐿𝑆 ≅ {
𝑉𝐶𝑃 − 1.5 𝑉 𝑖𝑓 𝑉𝐶𝑃 < 14 𝑉
VSD
CVCP
RVSD
VSD VCP
ICP
VSD
CHARGE
ICH HS GHx IGSHSx
PUMP HSx
VGS IDIS HS
VGSHSx
clamp CGSext
GND SHx
to the motor
VPHx
ICH LS
GLx IGSLSx
LSx
VGS IDIS LS
VGSLSx
clamp CGSext
VSL
SL
Rsh
Figure 22 Simplified BDRV block diagram with highlight on gate-source voltage clamping. Each gate
driver block is repeated 3× in the TLE987x, while 2× in the TLE986x
A calculation example is provided here below, where no capacitors are connected to the MOSFETs gates and
FOC control with a 3-phase motor is used. For sake of simplicity, we can assume VGS to have the same value for
HS and LS, as well as to be independent from ICP.
Assumptions:
Another calculation example is provided here below, where a capacitor is placed between gate and source, and
no capacitor between gate and drain is connected. The control scheme is always FOC. For sake of simplicity, we
can assume VGS and VGD to have the same value for HS and LS, as well as to be independent from ICP.
Assumptions:
12.5 𝑉
𝑄𝑀 = 60 𝑛𝐶 × + 12.5 𝑉 × 1 𝑛𝐹 ≅ 88 𝑛𝐶
10 𝑉
The current for each gate driver is equal to:
Equation 9:
𝐼𝐶𝑃
𝑉𝑟𝑖𝑝𝑝𝑙𝑒 =
𝑓𝑆𝑊 × 𝐶
Where:
C is the value of the capacitor
The voltage ripple of the output capacitor CVCP is equal to the one of the flying capacitors, but divided by 2.
Dynamic response: the higher the value of the capacitors, the slower will be the start-up time and the
response to load changes. In a typical TLE987x/6x application, this requirement is not critical
Losses due to ESR (equivalent series resistance): the higher the value of the capacitors, the higher will be
the ESR and so the losses. Using ceramic capacitors, the losses can be considered as not relevant in this
application
DC bias voltage: ceramic capacitors exhibit lower capacitance values, when the applied voltage increases.
According to the point of load and the desired capacitance value, the voltage rating should be adequately
selected. For a typical application, 50 V capacitors are recommended
𝑓𝑃𝑊𝑀 = 20 𝑘𝐻𝑧
3. Calculate ICP, considering VGS = 12.5 V, NM = 2, and no external capacitors connected to the gates:
𝐼𝐶𝑃 ≅ 15 𝑚𝐴
4. Calculate preliminary values for CCPS and CVCP, considering a charge pump frequency of 250 kHz and a
voltage ripple of 0.4 V and 0.2 V for CCPS and CVCP respectively:
𝐶𝐶𝑃𝑆 = 150 𝑛𝐹 → +50% → 220 𝑛𝐹
𝐶𝑉𝐶𝑃 = 300 𝑛𝐹 → +50% → 470 𝑛𝐹
5. Calculate ROUT_AVG:
𝑅𝑂𝑈𝑇_𝐴𝑉𝐺 = 43 𝛺
𝐼𝐶𝑃 × 𝑅𝑂𝑈𝑇𝐴𝑉𝐺 ≅ 0.65 𝑉
From the table, the minimum VGS voltage is equal to 12.3 V, so the MOSFETs can be correctly driven in every
condition.
VZERO
CSA CSA->CTRL.VZERO
OP2 Vp GR
0
R
ADC1 - CH1
+ Vo
OPA 1
-
R
Vn
OP1 GR
G
CSA->CTRL.GAIN
Figure 23 CSA block diagram and application schematic for shunt current measurement
11.3 DC characteristics
The differential input voltage is defined as:
𝑉𝑖𝑑 = 𝑂𝑃2 − 𝑂𝑃1 = 𝑉𝑝 − 𝑉𝑛
If, for example, VAREF is generated by the internal reference voltage generator, its nominal value is 5 V. As a
consequence VZERO = 2 V, which allows the ADC1 channel 1 to measure positive and negative values of Vid.
The linear output voltage range of the amplifier is (see P_13.1.4 of the datasheet):
𝑚𝑖𝑛, max{𝑉𝑜 } = 𝑉𝑂𝑈𝑇 = 𝑉𝑍𝐸𝑅𝑂 ± 1.5 𝑉
With the use of the internal VAREF generator, Vo can assume any value between 0.5 V and 3.5 V.
The Vo range limits the differential linear input range, which also depends on the gain setting according to
(see P_13.1.1 of the datasheet):
𝑚𝑖𝑛, max{𝑉𝑖𝑑 } = 𝑉𝐼𝑋 = ±1.5 𝑉 ⁄𝐺
Outside these ranges, the CSA characteristics are not linear and therefore undefined.
Because it is not an ideal circuit, the OPA exhibits an input offset VOS. Because of this, the output voltage can be
expressed by:
𝑉𝑜 = 𝑉𝑍𝐸𝑅𝑂 + 𝐺 (𝑉𝑖𝑑 ± 𝑉𝑂𝑆 )
𝑉𝑖𝑑 = 0 → 𝑉𝑜 = 𝑉𝑍𝐸𝑅𝑂 ± 𝐺 𝑉𝑂𝑆 = 𝑉𝑍𝐸𝑅𝑂 ± 𝑉𝑂𝑂𝑆
This implies that the direct measurement of VZERO by means of CSA->CTRL.VZERO = 1 will differ from the value of
Vo with Vid = 0 with CSA->CTRL.VZERO = 0. This difference equals to the output offset VOOS (see parameter
P_13.1.17). The measurements can be used to calculate this difference in the application software and to
compensate the offset.
The common mode input voltage is defined as:
𝑂𝑃2 + 𝑂𝑃1 𝑉𝑝 + 𝑉𝑛
𝑉𝑖𝑐𝑚 = =
2 2
Considering also the contribution of Vicm and the common mode rejection ratio DC_CMRR (see parameter
P_13.1.8 for grade 1 devices in conjunction with P_13.1.27 for grade 0 devices) the DC characteristics can be
expressed as:
𝑉𝑜 = 𝑉𝑍𝐸𝑅𝑂 ± 𝑉𝑂𝑂𝑆 + 𝐺 (𝑉𝑖𝑑 + 𝑉𝑖𝑐𝑚 ⁄𝐶𝑀𝑅𝑅𝑙𝑖𝑛 )
𝐷𝐶_𝐶𝑀𝑅𝑅
𝐶𝑀𝑅𝑅𝑙𝑖𝑛 = 10 20
Figure 24 shows a graphical representation of the differential DC characteristics and the input/output range.
VOUT
max VOUT
max VOOS
VZERO
min VOOS
G
min VOUT
11.3.1 AC characteristics
The CSA can be modeled as a three-port network with two input ports and one output port, as shown in
Figure 25. The two input ports represent OP2 and OP1, while the output port represents VOUT. Voltages for all
three ports are referred to the ground potential GND.
By considering the specific characteristics of the CSA, the three-port network can be expressed as:
Equation 10:
𝑣𝑜 = 𝐴𝑑 𝑣𝑖𝑑 + 𝐴𝑐𝑚 𝑣𝑖𝑐𝑚
{ 𝑣𝑝 = 𝑍𝑝𝑝 𝑖𝑝 + 𝑍𝑝𝑛 𝑖𝑛
𝑣𝑛 = 𝑍𝑛𝑝 𝑖𝑝 + 𝑍𝑛𝑛 𝑖𝑛
Where:
Equation 11:
𝑣𝑖𝑑 = 𝑣𝑝 − 𝑣𝑛
{ 𝑣𝑝 + 𝑣𝑛
𝑣𝑖𝑐𝑚 =
2
The first equation in Equation 10 represents the output behavior, while the other two represent the input
behavior of the CSA. The nominal value of the input impedances can be expressed as:
𝑣𝑝 𝑣𝑝
𝑍𝑝𝑝 = | = (𝐺 + 1)𝑅 𝑍𝑝𝑛 = | =0
𝑖𝑝 𝑖𝑛 𝑖
𝑖𝑛 =0 𝑝 =0
𝑣𝑛 𝑣𝑛
𝑍𝑛𝑝 = | =𝐺𝑅 𝑍𝑛𝑛 = | =𝑅
𝑖𝑝 𝑖𝑛 𝑖
𝑖𝑛 =0 𝑝 =0
ip
OP2 ip io
vp (G+1)R
io Ad vid
vp
vn
CSA vo Acm vicm
vo
G R ip
OP1 in vn
R
in
Figure 25 shows a schematic representation of the input equations and its impedances. This representation
together with the equations are necessary to design the external current-sensing and filtering network.
The resistors R have nominal values of 1.25 kΩ (see P_13.1.25 of the datasheet) and G changes according the
programmed gain.
The closed-loop nature of the CSA ensures the user that the stability is guaranteed in any application condition.
The open-loop transfer function of the CSA together with its gain and phase margins are designed and fixed
for each G gain configuration. Therefore, only the closed-loop transfer functions are described here.
The DC common mode gain can be derived from the CMRR as:
𝐴𝑑
𝐴𝑐𝑚 =
𝐶𝑀𝑅𝑅
The typical AC differential gain transfer function is shown in Figure 26 and defined as:
𝑣𝑜 (𝑠)
𝐴𝑑 (𝑠) =
𝑣𝑖𝑑 (𝑠)
A simplified analytical expression for each transfer function can be used in order to identify the typical
frequency and time-domain parameters. A dominant-pole approximation of Ad(s) is:
𝑣𝑜 (𝑠) 𝐺
𝐴𝑑 (𝑠) = ≈ 4
𝑣𝑖𝑑 (𝑠) 𝑠
( + 1)
𝜔𝑝
The typical values of ωp for each gain setting are shown in Table 16. Being a 4th-order transfer function, its step
response in the time domain has a fairly complex analytical expression. However, the time constant τp and its
relation to the settling time Ts can be defined as:
1
𝜏𝑝 = 𝑇𝑠 ≈ 9 𝜏𝑝
𝜔𝑝
The settling time Ts is defined as the time between the instant when the step is applied at Vid and the instant in
which Vo remains confined within ±2% of its final value. Table 16 shows the values of the estimated typical Ts
and τp for each gain setting.
IM
RLP
ip vp OP2
io
CSA
Rsh
vsh CLP vo
Lsh
RLP
in vn
OP1
Lst
This equation represents the ideal DC behavior of the CSA, so it is only valid once all the dynamics of the system
are eliminated. However, it is still a valid design equation for the choice of Rsh and G.
Indeed, because of the limited output voltage range of the CSA, one has to consider the behavior under
maximum current:
𝑉𝑜 𝑚𝑎𝑥 = 𝑉𝑍𝐸𝑅𝑂 + 1.5 𝑉 > 𝑉𝑍𝐸𝑅𝑂 + 𝐺 𝑅𝑠ℎ 𝐼𝑀 𝑚𝑎𝑥
This leads to the 1st design equation:
1.5 𝑉
𝑅𝑠ℎ < 𝑅𝑠ℎ 𝑚𝑎𝑥 =
𝐺 𝐼𝑀 𝑚𝑎𝑥
Note: This equation should be used so that Rsh is as close as possible to its maximum limit in order to
take the greatest advantage of the Vo range.
Since the output voltage is eventually measured by the ADC1 channel 1, one has to consider the relation
between the current resolution ΔIM and the ADC1 resolution ΔVo:
𝑉𝐴𝑅𝐸𝐹
∆𝑉𝑜 = < 𝐺 𝑅𝑠ℎ ∆𝐼𝑀 𝑚𝑖𝑛
210 − 1
Using the internal reference leads to ΔVo ≈ 4.5 mV. From this condition, the 2nd design equation derives:
∆𝑉𝑜
𝑅𝑠ℎ > 𝑅𝑠ℎ 𝑚𝑖𝑛 =
𝐺 ∆𝐼𝑀 𝑚𝑖𝑛
Note: This equation should be used so that Rsh is as far as possible to its minimum limit.
𝑃𝐷 𝑠ℎ = 𝑅𝑠ℎ 𝐼𝑀 𝑅𝑀𝑆 2
In order to limit the power dissipation to a certain value PDshmax, the 3rd design equation should be applied:
𝑃𝐷 𝑠ℎ 𝑚𝑎𝑥
𝑅𝑠ℎ < 𝑅𝑠ℎ 𝐷 =
𝐼𝑀 𝑅𝑀𝑆 2
The following considerations are also relevant when selecting a shunt resistor:
1. The higher the gain, the lower the bandwidth, as seen in Figure 26
2. The values of commercial current sensing resistors are discrete and limited
3. More shunt resistors in parallel are possible to increase the total maximum power dissipation
To find the optimal shunt resistance, the best approach is to consider the three design equations for each gain
setting G = {10, 20, 40, 60}:
1. From the 1st design equation:
1.5 𝑉
𝑅𝑠ℎ < 𝑅𝑠ℎ 𝑚𝑎𝑥 = = {15 ; 7.5 ; 3.75 ; 2.5} 𝑚Ω
𝐺 10 𝐴
2. From the 2nd design equation:
4.5 𝑚𝑉
𝑅𝑠ℎ > 𝑅𝑠ℎ 𝑚𝑖𝑛 = = {4.5 ; 2.25 ; 1.225 ; 0.75} 𝑚Ω
𝐺 100 𝑚𝐴
3. From the 3rd design equation:
1𝑊
𝑅𝑠ℎ < 𝑅𝑠ℎ 𝐷 = = 12.5 𝑚Ω
80 𝐴2
Figure 28 shows a graphical representation of the design equations above. It shows that any gain setting can fit
the case, given that Rsh falls in the selection area.
On the base of this analysis and consideration 1. and 2., a suboptimal choice for this use case would be a 7 mΩ
resistor with a gain setting G = 20. This will lead to the following actual values:
𝑉𝑜 𝑚𝑎𝑥 = 2 + 20 × 7 𝑚Ω × 10𝐴 = 3.4 𝑉
4.5 𝑚𝑉
∆𝐼𝑀 = ≈ 32.2 𝑚𝐴
20 × 7 𝑚Ω
𝑃𝐷 𝑠ℎ = 7 𝑚Ω × 80 𝐴2 = 560 𝑚𝑊
Vo as function of IM needs to be expressed. This could be done in the time domain, but the AC analysis in the
frequency domain can simplify the design procedure. The total CSA gain transfer function can be defined as:
𝑣𝑜 (𝑠)
𝐻(𝑠) =
𝑖𝑀 (𝑠)
Further H(s) can be broken down as a function of the CSA differential and common mode gains from the input
pins OP2 and OP1 to the input of the ADC1:
𝑣𝑜 (𝑠) 𝐴𝑑 (𝑠) 𝑣𝑖𝑑 (𝑠) + 𝐴𝑐𝑚 (𝑠) 𝑣𝑖𝑐𝑚 (𝑠) 𝑣𝑖𝑑 (𝑠)
𝐻(𝑠) = = ≈ 𝐴 (𝑠)
𝑖𝑀 (𝑠) 𝑖𝑀 (𝑠) 𝑖𝑀 (𝑠) 𝑑
Note: The above simplification is possible because both common mode input signal and gain are
negligible compared to the differential ones.
In the frequency domain, the goal mentioned above translates into obtaining a response as flat as possible,
ideally a constant response across the whole frequency spectrum. As known, Ad(s) has a flat gain, but within
limited bandwidth (see Figure 26 and Table 16), so the effect of the shunt and filter network has to preserve this
level of fidelity.
IM (G+1)R
RLP ip vp OP2 io
Rsh Ad vid
CLP vid vo
Lsh Acm vicm
R G R ip
RLP in vn
OP1
Figure 29 CSA input filter and graphical representation of the CSA impedances
In conclusion, the best dynamic performances obtainable (without introducing any additional reactive device)
is the one of the CSA. This requires:
𝑣𝑖𝑑 (𝑠)
𝑍𝑇 (𝑠) = = 𝑅𝑠ℎ
𝑖𝑀 (𝑠)
This will be eventually the condition for calculating one of the design equations.
The analytical calculation of ZT(s) from the schematic in Figure 29 leads to:
𝑠 𝐿𝑠ℎ
𝑣𝑖𝑑 (𝑠) 𝐹 (1 + )
𝑅𝑠ℎ
𝑍𝑇 (𝑠) = = 𝑅𝑠ℎ
𝑖𝑀 (𝑠) 𝐿
𝑠 2 𝐶𝐿𝑃 𝐿𝑠ℎ 𝐹 + 𝑠 ( 𝑠ℎ + 𝐶𝐿𝑃 (𝑅𝑠ℎ + 2 𝑅𝐿𝑃 )) 𝐹 + 1
2𝑅
2𝑅
𝐹=
2 𝑅 + 𝑅𝑠ℎ + 2 𝑅𝐿𝑃
For s = 0, which means in DC regime, the transimpedance can be expressed as:
𝑍𝑇 (𝑠)|𝑠=0 = 𝑅𝑠ℎ 𝐹
This means that the factor F introduces a DC error. This factor indeed represents the portion of the DC current IM
that flows through the low pass filter resistors RLP and the input stage of the CSA (because of its non-infinite
input resistance R).
This error can be minimized by considering that Rsh << R and by imposing the 1st design equation:
𝑅
𝑅𝐿𝑃 <
𝑝
This condition leads to a DC gain error of:
𝑅𝑠ℎ − 𝑅𝑠ℎ 𝐹 1
𝐸𝑟𝑟𝑍𝑇 % = %< %
𝑅𝑠ℎ 1+𝑝
For example, for p = 100 the error would be less than 1%. It is therefore good practice to choose a value of RLP
between 1 Ω and 15 Ω.
The following considerations can then be applied:
If p = 100 then F ≈ 1
Rsh << RLP
Lsh / 2R ≈ 0
None of these effects is desirable because the goal is to obtain a flat response (at least within the bandwidth of
the CSA). A third option would be to try to cancel the dynamic of the zero with one of the poles. Partial cancelation
of the zero is indeed possible when:
𝐿𝑠ℎ
𝐶𝐿𝑃 =
2 𝑅𝐿𝑃 𝑅𝑠ℎ
This is the 2nd design equation. The pole/zero cancellation is never perfect in practice, because of the uncertainty
and variation of the passives values. So, this method gives the suboptimal value of CLP that maximizes the
bandwidth of the filter.
This design equation has to be considered as a starting point recommendation for the customer’s design. The
designer shall make use of the analytical tools shown in this chapter to choose the CLP value considering the
design’s specifications.
In Figure 30 the effect of four different CLP values on the normalized transfer functions and step responses can be
observed:
𝐻(𝑠) 𝑍𝑇 (𝑠)
;
𝐺 𝑅𝑠ℎ 𝑅𝑠ℎ
11.4.3 Conclusions
When all the design equations are used to select the current sensing and filter network, the transfer function from
measured current to output of the CSA can be simplified as:
𝑣𝑜 (𝑠) 𝑅𝑠ℎ 𝐺
𝐻𝑜𝑝𝑡 (𝑠) = = 𝑍𝑇 𝑜𝑝𝑡 (𝑠)𝐴𝑑 (𝑠) ≈ 4
𝑖𝑀 (𝑠) 1 + 𝑠 𝐶𝐿𝑃 2 𝑅𝐿𝑃 𝑠
( + 1)
𝜔𝑝
The speed of the signal is mainly affected by the CSA bandwidth. As shown in Table 16, the typical settling time
depends on the gain setting G. Figure 30 shows that the CSA bandwidth is capable to settle within 800 ns typically
for the highest gain (lowest bandwidth) setup. In a motor control with 20 kHz PWM, 800 ns represents a duty cycle
of 1.6%. So for applications where very high precision and fast response is needed by the current sensing, it is
suggested to setup the CSA (and design the passives) for the lowest gain possible.
Figure 30 Frequency and step response of the transfer functions ZT(s) and H(s) with different values
of CLP and the following values: Lsh=1 nH, Rsh=5 mΩ, RLP=10 Ω, G = 60.
The last value, 10 nF, is the suboptimal value that satisfies the 2nd design equation
12 Sensor interfaces
The TLE987x/6x family offers the option to interface different sensors and communication interfaces to the
device. Depending on the application requirements, one or more of these interfaces can be used by configuring
the corresponding functionality in the relevant device registers. This chapter presents some example interfaces
with relevant pins of the chip which can be used for these interfaces.
P1.2 Hall_1
P1.3 Hall_2
Hall
RXD P0.1
UART1 Sensor
TXD P1.4 P2.3 Hall_3
SIN_P P2.0
P1.0 SCK
SIN_N P2.2
TMR
P1.1 MTSR SPI
COS_P P2.4
P1.2 MRST
P2.3
TLE987x-2QX
P0.2 Hall_1
P0.3 Hall_2
Hall
RXD P0.1
UART Sensor
TXD P1.4 P0.4 Hall_3
SIN_P P2.0
P1.0 SCK
SIN_N P2.2
TMR
P1.1 MTSR SPI
COS_P P2.4
P1.2 MRST
P2.3
TLE987x-2QX
P0.2 MTSR
TLE987x/ GND
SWD connector
PIN 3, 5, 9
On the SWD interface of the TLE9879 EvalKit and TLE9869 EvalKit, pin 9 is used to deactivate the onboard
debugging circuit. In a typical implementation, this pin is used as GND. The pinout is shown in Figure 34.
Schematic Layout
PIN 1 PIN 2
14 Unused pins
Table 17 shows the recommendations for the TLE987x/6x pins, in case they are not used in the application.
The GND digital pins are pin 19 and pin 28, while the GND analog is pin 39.
15 Layout guidelines
In this chapter general recommendations are provided regarding PCB layout, as well as some specific hints for
microcontrollers and MOSFET bridge drivers.
For simplicity and clarity reasons, number the components in each zone in the same way (for example,
analog = 100, digital = 200, power = 300, and so on).
15.2 Specific PCB design rules for microcontroller with bridge drivers
Some general recommendations are:
Separate the IC supply (VS and VSD) from VDH, that is, separate voltage sense line from power stage
For minimal power dissipation, the recommended package for serial resistor at MON is SMD1206
Placeholder for RC snubber circuit for all bridge MOSFETs should be considered for damping of circuit
resonances during switching (if needed)
For better filter performance and longer life, low-ESR electrolytic capacitors, rated for higher ripple current,
should be used
When a shunt resistor is used, the maximum acceptable capacitance between VDH and SL is 30 µF.
Higher values would affect the current sensing too much
The input capacitor, flying capacitors and tank capacitor should have short traces to reduce radiated
emission and voltage drop across the trace inductances
The DC-link capacitors should be placed close to the power stage in order to get stray inductance as low
as possible
VDH
VDH
VCP
VSD
Reverse-
VDH polarity EMI filter
Charge pump protection
HSx
GHx
VBAT
SHx
Motor
VS
phase x
LSx
Logic GLx
PMU
GND SL
Rsh
VDDEXT VDDP GND (pin 39)
VDDC
A practical example is shown in Figure 38. The connection between the PWR GND (mid-top) and IC GND (mid-
bottom) planes consists of a slim trace and a via. This connection ensures the IC's current supply, while
rejecting high-frequency currents that could loop from the IC to the battery. Consider these guidelines for the
GND pin routing:
Pin 39 should have the most solid connection to the IC GND plane. In the layout example this is
accomplished by taking advantage of the exposed pad solid connection through multiple vias. When this is
not feasible, connect the VDDC capacitor's GND pin to IC GND with as many vias as possible
Pin 19 and 28 can have a weaker connection to IC GND
To minimize the stray inductance, the loop “input cap – bridge MOSFET – shunt resistor” should be as small as
possible
A typical conducted EMI spectrum of an application that follows these rules is shown in Figure 39. This
measurement has been performed on the layout example with the motor-running functions turned off to
highlight the spectral contribution of the AC currents generated by the IC.
VC P
VSD
VS
VD DC
VD DP
Top layer
Mid-top layer
IC GND
Mid-bottom Layer
Figure 40 Layout – one bridge leg with two N-MOSFETs (as part of a 2-phase or 3-phase motor bridge)
During a transition from the low-side to the high-side, the current is commutating from LS switch to HS switch.
The ideal commutation circuit is a loop consisting of CDC, THS and TLS. The inductive part of the real circuit is
considered in the stray inductance Lσ. Overvoltages are induced over Lσ during the switching. These
overvoltages are coupled directly to OUT and VS and will also cause radiated emission. The size of the
commutation circuit has to be as small as possible.
Application note 66 Rev. 1.1
2022-04-01
TLE987x/6x
Hardware design guideline
Layout guidelines
Figure 40 shows an example for a low-impedance layout of one motor bridge leg.
The capacitors C2, CS-H and CS-L are placed as close as possible to the device pins.
Figure 41 shows a recommendation for the commutation circuit of a 3-phase motor bridge.
Revision history
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