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Basics of Analog Flow A Design-Oriented Approach

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167 views

Basics of Analog Flow A Design-Oriented Approach

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Nguyễn Ngọc Bách

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You are on page 1/ 157

Basics of Analog Flow: A Design-

Oriented Approach
Rapid Adoption Kit (RAK)

Product Version: Virtuoso ICADVM20.1 ISR30, Spectre 21.1 ISR16, PEGASUS 22.20,
Quantus 22.1.0-p089
June 2024
Copyright Statement

© 2024 Cadence Design Systems, Inc. Cadence and the Cadence logo are registered trademarks of
Cadence Design Systems, Inc. All others are the property of their respective holders.

This content is Cadence Confidential and for Cadence customers only. DO NOT DISTRIBUTE.

Learn more at Cadence Learning and Support Portal - https://support.cadence.com

Contents
Purpose.......................................................................................................................... 4
Audience ........................................................................................................................ 4
Terms ............................................................................................................................. 4
Overview ........................................................................................................................ 5
Module 1: Initial Setup ................................................................................................... 6
Generating a cds.lib File for Virtuoso......................................................... 6
Creating a New Library and Cell .............................................................. 13
Module 2: Schematic Design ....................................................................................... 17
Schematic Creation Using Virtuoso Schematic Editor ............................ 17
Symbol Creation ...................................................................................... 24
Module 3: Schematic Testbench ................................................................................. 29
Testbench Creation .................................................................................. 29
Modifying DUT Parameters...................................................................... 41
Module 4: Pre-Layout Simulation ................................................................................ 45
Simulation Setup Using ADE Explorer and Assembler ........................... 45
Waveform Results Analysis ..................................................................... 60
Generating Expressions........................................................................... 74
Design Tuning Using Parameters ............................................................ 82
Backannotation of Tuned Parameters ..................................................... 93
Module 5: Layout ......................................................................................................... 95
Layout XL ................................................................................................. 95
Transistor Abutment ............................................................................... 100
Placement .............................................................................................. 106
Routing ................................................................................................... 115
DRC Tests.............................................................................................. 128
LVS (Layout Versus Schematic) ............................................................ 135
Module 6: Post-Layout Simulation ............................................................................. 141
Using Quantus to Create a DSPF File ................................................... 141
Using Quantus to Create a Smart View ................................................. 143
Creating a Config View Using Virtuoso Hierarchy Editor ...................... 146
Post-Layout Simulations on ADE Assembler ........................................ 151
Support ...................................................................................................................... 157
Feedback ................................................................................................................... 157

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Purpose
This RAK introduces the steps of creating an analog design from initial requirements to
the sign-off stage.

Audience
This RAK is intended for designers who are new to Virtuoso or those who would like an
overview of the complete custom flow using the latest Cadence tools.

For this RAK, you do not require prior knowledge of Cadence tools.

Terms
ADE Analog Design Environment

LMB Left Mouse Button

CIW Command Interpreter Window

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Overview
This workshop highlights the main steps of the analog design flow, focusing on
improved designer productivity by using the latest features available in ICADVM20.1.

For this RAK, you must have ICADVM20.1 (or IC6.1.8), Spectre21.1, PEGASUS 22.20,
and Quantus 22.1 in your path and the necessary licenses for them.

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Module 1: Initial Setup

You need a PDK to create the design. Cadence Generic Process Design Kits (GPDK)
and standard cell reference libraries are provided with Virtuoso and Innovus products.
They are intended to be a representative of the actual semiconductor processes.

For this RAK, you will use the latest version of the 45nm GPDK. You can find this PDK
at https://support.cadence.com. You do not require to download it for this RAK because
it is provided in the database.

Action 1: Unpack the RAK database and cd into the BAF_RAK directory.

$ tar -xzvf BAF_RAK.tar.gz

Action 2: Enter the main directory.

$ cd BAF_RAK

The following two directories will be shown:

• gpdk045_v_6_0: This contains GPDK files.

• solutions: This contains the files representing the completed modules and labs.

To use any of the results from the solutions directory, copy all files inside the desired
Lab and paste them into the BAF_RAK directory by replacing any existing files. For
example, if you want to do Lab 9, copy all files from
BAF_RAK/solutions/Module4/Lab9 and paste them into the BAF_RAK directory,
and you will have all the necessary setup to start the ninth Lab.

Generating a cds.lib File for Virtuoso

The first step in the analog flow is to write a file referencing the libraries required for
your design.

Action 3: Invoke Virtuoso in your xterm.

$ virtuoso &

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The CIW will open.

Action 4: Go to Tools > Library Path Editor from the CIW.

The Library Path Editor opens.

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You will see several libraries already defined. These are the default libraries provided by
Cadence and include generic components for the testbench creation. For the actual
design, you need to include the GPDK with the process-specific (45nm) components.

Action 5: Go to Edit > Add Library.

Action 6: In the Add Library form that opens, click on the pull-down menu and select
the path where you extracted the GPDK.

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Action 7: In the Directory field, double-click on gpdk045_v_6_0, select the gpdk045

library, and click Apply. Repeat this for the assura library. Click OK to close this
window.

This step will add these libraries to your Path Editor form, as shown below.

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Action 8: Select File > Save As. The Save As form will open.

Action 9: In the cds.lib field, erase all data from the field and write “cds.lib”. Then, click
OK and close the Library Path Editor.

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This will create a new cds.lib file in your project directory (where you invoked
Virtuoso).

Action 10: Open the new cds.lib file in a text editor.

As you can see, the cds.lib file is filled with the libraries added in Action 7. It also
includes the default libraries.

Action 11: Close the file without making any changes. You can manually create/edit
the cds.lib file in any editor.

Action 12: In the CIW, go to Tools > Library Manager.

Observe that all the libraries you need for your project are available.

Action 13: In the Library Manager, click on the gpdk045 library.

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These are the basic components you might need for your design. PDK also includes
process constraints, Spectre models, DRC/LVS rules, and QRC extraction decks.

Action 14: Click on the Show Categories checkbox and select the mos category.

The Category column will filter the display of components to show all mos devices.

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Creating a New Library and Cell

The next stage is to create a library for your DUT and testbench.

Action 15: In the Library Manager, go to File > New > Library. The New Library form
will open.

Action 16: Select the path of your project directory and enter MyOpAmp in the Name
field. Then, click OK.

The Technology File for New Library form will open, as shown below.

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Action 17: In the Technology File for New Library form, select the Reference
existing technology libraries option and click OK.

The Reference Existing Technology Libraries form will open.

Action 18: Select the gpdk045 library and click the right arrow icon to include it in the
Reference Technology Libraries list box. Click OK.

This ensures that the newly created library uses the technology of the GPDK. The new
library will then appear in the Library Manager.

Action 19: Click on MyOpAmp in the Library Manager. Then, go to File > New > Cell
View.

This will open the New File form.

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Action 20: In this form, enter OpAmp as the Cell and leave the other entries as-is.
Click OK.

This will create a new cell named “OpAmp” in the MyOpAmp library and a new view of
that cell named schematic. The schematic cellview is automatically opened.

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Action 21: Leave this view open and proceed to the next module.

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Module 2: Schematic Design

In this module, you will create a schematic view of your design. The topology of your
design will be a Two-Stage Operational Amplifier. The final schematic will look like the
one shown below.

Schematic Creation Using Virtuoso Schematic Editor

Action 22: On the schematic canvas, press i to open the Add Instance form. Fill in the
form, as shown below, to place a four-terminal pmos device from the gpdk045 library.
You can type into these fields and use the autocomplete feature.

In the lower part of the form, you will see the default parameters for this component.

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Action 23: Press Hide on the form. Then, place three pmos transistors, as shown
below. Pay attention to the ordering so that you place the middle, then the left, and then
the right-hand components. Press Shift+R to mirror the left-hand instance. Press Esc
after you finish.

Note: The placement of components should match the image shown below.

Action 24: On the schematic canvas, press i to open the Add Instance form. Fill in the
form to place a four-terminal nmos device from the gpdk045 library, as shown below.

Action 25: Press Hide on the form. Then, place the five nmos transistors. Once again,
pay attention to the order in which you place them so that the names match the image
shown below. Press Shift+R to mirror as needed. Press Esc after you finish.

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Now, you have inserted all MOSFET devices. You will now add the capacitor.

Action 26: On the schematic view, press i to open the Add Instance form. Select the
pmoscap2v device from the gpdk045 library.

In the Parameters section, change the Calculated Parameter field to Capacitance

and change both the Length and Finger Width parameters to 6.315u, as shown below.

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By choosing Calculated Parameter as Capacitance, you can edit the capacitor

dimensions and see the resultant capacitance value.

Action 27: After you fill in the form, press Hide. Then, place the capacitor, as shown
below. You can use the Rotate icon ‘ ’ on the form as you place it. Then, press
Esc.

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Action 28: Press W or select Create > Wire to invoke the ‘wiring’ command.

To create connections, click where you want the wire to start. Now, click again in free
space to create an intermediate point OR on a device terminal OR another wire to end
the command. Double-click or press Enter to complete the connection that ends in free
space. You can also click+drag from one terminal and release it on the terminal where
the connection ends.

You can also use the S bindkey to snap to the nearest pin or wire endpoint without
moving the mouse. A yellow diamond will indicate the nearest routing target.

Action 29: Complete the connections as shown below.

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To delete a net or any other component, press Delete and select the component or use
the ‘ ’ icon.

Action 30: After you finish routing, press Esc. Then, press P to add pins. Fill in the
Names field, as shown below, to create pins for this design.

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Action 31: Change the value of the Direction field to input and place the INN and INP
pins. Switch Direction to R to place the OUT pin. Place the last three pins as
inputOutput. Use the Rotation icons on the dialog box to help with the placement.

Press Esc after you finish. The correct pin placement is shown below in the schematic.

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You can drag the name of a pin to make the text more visible if needed.

The schematic is now complete.

Action 32: Select the Check and Save icon ‘ ’. This checks the design against a
number of built-in rules, floating nets, overlapping instances, shorts, and so on. Check >
Rules Setup will show you the complete list of rules.

The following information should appear on your CIW to inform you that everything is
correct:

If there are any issues, a Schematic Check window will open. Markers will appear on
the canvas alerting you of any issues.

Symbol Creation
The last step in this module is to create a symbol for your design. Symbols are used to
construct a hierarchy in designs.

Action 33: In the Schematic Editor, select Create > Cellview > From Cellview. Leave
the form as-is and click OK.

The Symbol Generation Options form will appear. This allows you to specify a
location for placing each pin.

Action 34: Fill in the form as shown below and then click OK.

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The symbol is generated with a rectangular shape. To make it resemble a traditional op-
amp block, you need to edit the shape.

Action 35: Press ‘ ’ and select the green rectangle shape for deleting it. Then, press
Esc.

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Action 36: Drag the nets and pins apart by selecting and dragging them to create more
space between them.

Action 37: Click the Create Polygon icon ‘ ’. Starting on the tip of the INP stub (the
green line), draw a triangle like the one usually seen for an op-amp. Click twice when
done.

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Now, you need to stretch the bottom part of the red rectangle upwards to make the op-
amp symbol selection box more symmetrical.

Action 38: Select the bottom side of the red rectangle together with the VSS stub and
pin and drag them up, as shown below.

The only step left is to extend the stubs for VSS and IBIAS so that they connect to the
triangle. This is an optional step to improve the look of the op-amp symbol.

Action 39: Select the tip of the IBIAS stub and drag it until it touches the triangle.
Repeat the same for the VSS stub.

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Action 40: Adjust the pin-label positions (red text) to make them more legible. To do
this, select and drag them individually.

Action 41: Once the editing is complete, click on the Check and Save icon. If no other
window pops up, the symbol is created correctly.

Action 42: Close the symbol and the OpAmp schematic views and proceed to the next
module.

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Module 3: Schematic Testbench

The next step is to create a schematic view that will be used for testing the op-amp
design.

Testbench Creation
Action 43: Go to the Library Manager. Select MyOpAmp as the Library and go to
File > New > Cell View.

Action 44: On the New File form, enter OpAmp_tran in the Cell field and click OK.

This will generate and open a new schematic view.

Action 45: Press i to invoke the Add Instance form and fill it in, as shown below.

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Action 46: Press Hide and place the instance on the schematic. Then, press Esc.

The next step is to add the necessary DC sources.

Action 47: Press i and populate the Add Instance form, as shown below in the image
on the left. Place the source in the schematic. Repeat twice more, using the other two
images as a guide. Press Esc after it is finished.

It is not necessary to fill in the names of the instances. If the Add Instance form is
hidden behind a window, you can press F3 to show this form.

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The following three DC sources were added:

• One vdc source named VDD_source with DC voltage set to vdd

• One vdc source named VSS_source with DC voltage set to vss
• One idc source named Ibias_source with DC current set to ibias

The DC voltage and DC current field entries are variables. These values will be set
later for the simulation.

The schematic should look as follows:

To test this op-amp, you need to create a simple buffer configuration and use a square
wave for the input. For that, you will need a pulse source.

Action 48: Press i and fill in the form, as shown below. Then, place the instance on the
schematic close to the INP pin.

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This defines a square-wave signal with an amplitude of 700mV to 1.3V.

A load for this testbench is the next step. For example, a capacitor should be a good
load to obtain realistic results of Slew Rate.

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Action 49: Fill in the Add Instance form (as shown below) and place the cap close to
the OUT pin.

The last component to insert is the voltage reference gnd.

Action 50: Fill in the Add Instance form (as shown below) and place the component
thrice: the first below the DC voltage sources, the second below the Vin_pulse source,
and the third below the Cap_Load. Then, exit the Add Instance form by pressing Esc.

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The schematic testbench should look as follows:

Action 51: Press w to invoke the ‘wiring’ command and route the testbench, as shown
below. Press Esc after you finish.

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Note that to avoid crossing wires, sources are not wired to the DUT. Alternatively, you
can connect by name.

Action 52: Click on the Create Wire Name icon ‘ ’ at the top of the toolbar OR
press the l bindkey to invoke this form. Fill it in, as shown below.

Action 53: Press Hide and click on the wires to place each label. Press Esc after you
finish. This schematic testbench is now complete.

Action 54: Press the Check and Save icon ‘ ’. The following information should
appear on your CIW to inform you that everything is correct:

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A testbench is required to analyze the open-loop gain and bandwidth. You must create
a second cellview for that.

Action 55: Go to File > New in the Schematic Editor Window and complete the form,
as shown below. Ensure that the new tab option is selected for Open in. Press OK
when finished.

The new view will open in a new tab.

You can easily create the new testbench by copying the OpAmp_tran components and
making suitable modifications.

Action 56: Go back to the OpAmp_tran tab. Press Ctrl+A to select the entire design,
and then press C and click somewhere in the blank space to copy the design.

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If you move the mouse around after you click, you will see ghosted images of all
objects:

Action 57: Go to the new tab and paste the design by clicking in the free space.

Action 58: Select the Vin_pulse source and press q. Alter the properties to match the
following screenshot:

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Action 59: Press OK when done.

The vsource component is a generic source that can be set to several different sources
such as dc, sine, pulse, and so on, by changing the Source type option.

Action 60: Delete the feedback net connecting INN to OUT and place a resistor in its
place with the settings shown below. As you place it, you can rotate it using the icons on
the form.

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Action 61: Place a capacitor from the INN pin to the ground. Now, add a ground
component for the capacitor.

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The second testbench should look as follows:

Action 62: Check and Save the schematic testbench. No warnings or errors should
appear.

Modifying DUT Parameters

Observe that you have not yet set the width (W) and length (L) values for the NMOS
and PMOS transistors of your op-amp, so they all are set to their default values.

In this section, you will use the Navigator and the Property Editor assistants to set
these values.

Action 63: In the OpAmp_ac schematic testbench, double-click the DUT symbol. In
the Descend dialog box, make sure schematic is selected for View. Choose the edit
option in Open for and click OK.

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The OpAmp schematic is opened. In the left pane, you should see that both the
Navigator and the Property Editor assistants are displayed. If not, invoke them
individually by selecting Window > Assistants from the banner menu.

You will select devices using the Navigator assistant and edit parameters with the
Property Editor assistant. The Navigator also displays nets and pins, making it a
convenient way to locate items in a schematic.

Action 64: In the Navigator assistant, select the Instances category (Object). Select
M0 and M1 using the Ctrl key for multiple selections. Search for Total Width on the
Property Editor and change the value to 465n. Press Enter.

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Note: Do not write “m” for meters because it is automatically set after you press Enter.

Since both transistors (M0 and M1) were selected, width values will be changed for both
at once. Repeat this process for the other MOSFET elements, as shown below:

• M2 Total Width: 10u

• M3 Total Width: 490n

• M4 Total Width: 490n

• M5 Total Width: 1.09u

• M7 Total Width: 1.09u

• M6 Total Width: 6.88u

Note: For all transistors, the value of the Fingers field should be 1.

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Action 65: Select M0, M1, M3, and M4 and change their Multiplier value to 2.

After you finish, your schematic should look as follows:

Your schematic may differ in the labels that are displayed. Just ensure that the w and m
values are correct.

Action 66: Click on Check and Save to save your design. No warnings should be
displayed.

Action 67: Click on the up arrow ‘ ’ on the toolbar in the top-left corner to return to
the top-level testbench. Alternatively, you can right-click on an empty space of the DUT
schematic and select Return (ensure nothing is selected).

The AC schematic testbench view will appear again.

Action 68: Close this view by selecting the ‘x’ icon in the tab. You should still have the
OpAmp_tran/schematic view displayed.

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Module 4: Pre-Layout Simulation

Once the schematic testbenches are completed, you can evaluate the design and its
basic functionality. You will calculate the slew rate, open-loop gain, gain bandwidth, DC
offset, and settling time. The specifications for each of those output measurements are
given below:

• Slew Rate >= 50 MV/s

• DC Open-Loop Gain >= 60 dB (1000V/V)

• Unity-Gain Bandwidth >= 50 MHz

• Output Offset <= 10 mV

• Settling Time <= 50 ns

Simulation Setup Using ADE Explorer and Assembler

Action 69: In the OpAmp_tran schematic, select Launch > ADE Explorer. Select
Create New View and click OK. Change the Cell name in Create new ADE Explorer
view to OpAmp_sim and click OK again.

This will create and open a new maestro view, which is used by the ADE Explorer and
Assembler simulation environments.

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You will first set up PDK model library paths.

Action 70: Go to Setup > Model Libraries. Verify that a path is set like as follows:

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Note: Your exact path will depend on the location where your RAK database is
installed.

Action 71: Change mc to tt in the Section column and click OK.

Action 72: Go to Setup > Save Options and change Simulations Results Directory
Location from ~/simulation to ./simulation, as shown below.

This will save all your simulation data on a directory called “simulation”, created inside
your project directory instead of your home directory. You can set this and other
properties as default by using a .cdsinit file.

Action 73: In your project directory, create a file called “.cdsinit” and insert the text
shown below. Then, save and close the file.

envSetVal("adexl.results" "saveResDir" 'string "./simulation")

Environment variable settings saved in the .cdsinit file get applied when you launch your
Virtuoso session. This way, you will not have to modify this field whenever you invoke
Virtuoso in this project directory.

Action 74: In the Setup assistant docked on the left side of the window, locate the
Analyses section.

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Select Click to add analysis. The following dialog box will appear:

You will specify two analyses: dc and tran.

Action 75: Leaving tran as the analysis, set Stop Time as 100u and click Apply.

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Now, add the dc analysis. The tran information will not be lost if you change the
analysis type.

Action 76: Select dc from the list of Analysis, check the Save DC Operating Point
checkbox, and click OK.

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The Setup assistant shows the Analyses. The next step is to add Design Variables.

Action 77: Go to Variables > Copy From Cellview.

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This scans the schematic view for string parameters and imports them into the Explorer
Setup assistant.

Action 78: Click twice in the Value column of the Design Variables field to set each
value, as shown below. Alternatively, use “Tab” shortcut to go to the next variable, after
selecting the first field.

Next, you will specify the outputs for the simulation.

Action 79: Go to Tools > Calculator.

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Action 80: Click on the vt boolean in the upper-left portion of the calculator.

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This will open the schematic so that you can select a signal.

Action 81: Select the output net (wire) OUT in the schematic. Be careful not to select
the terminals connecting to the wire.

The following expression will appear in the buffer of the calculator:

Action 82: Click the ‘ ’ icon to send this expression to the ADE Outputs pane. Move
the calculator to a side and verify that you see the output added to ADE:

Action 83: In the Name column, double-click and enter Vout_tran. Press Enter.

Action 84: In the Calculator, click again on vt and select the net IN. Click on the ‘ ’
icon again and name the expression Vin_tran.

Action 85: In the Calculator, click on vdc. Select the net OUT again. Send the
expression to the Outputs pane and name it Vout_dc.

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Action 86: In the Calculator, click on vdc. Select the net IN. Send the expression to
the Outputs pane and name it Vin_dc.

For open-loop gain and bandwidth, you will use the AC testbench view. You will add this
second testbench to your setup by using ADE Assembler.

Action 87: Click on the up-arrow icon ‘ ’ on the Setup assistant next to the testbench
name.

This will invoke ADE Assembler, which allows multiple tests to be simulated on the
same environment.

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Action 88: Expand Tests on the Data View assistant. Right-click on the
MyOpAmp:OpAmp_sim:1 test and select Create Test Copy.

Action 89: Change the name of the first test to tran and of the second test to ac. To do
this, select the test name text and then left-click on the name again. Type the new name
in the inline editor.

Your setup should look as follows:

Action 90: Right-click on the ac test and select Design.

Action 91: In the Choose Design form, select OpAmp_ac and press OK.

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This changes the testbench to the OpAmp_ac schematic for the ‘ac’ test.

Action 92: Select all expressions in the Outputs Setup corresponding to the ‘ac’ test
and delete them. Use the Shift key to select multiple items at once, right-click, and
select Delete Output.

Action 93: Expand the ac test tree in the Data View Assistant, expand Analyses, and
delete the two analyses that were copied from the ‘tran’ testbench.

Action 94: Add the following Analysis to the ac test:

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Action 95: Expand the Design Variables field and add the variable vac with a value of
100m.

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Action 96: In the Calculator, select ac as the test.

Action 97: Select the ‘ ’ icon below the buffer to clear the Stack and Buffer.

Action 98: Select vf, which accesses voltage over frequency. Select the net OUT from
the schematic. The following text will appear in the buffer:

Action 99: Click on vf again and select the net IN.

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Action 100: Now, click the ‘/’ button on the left, as shown in the following screenshot.

Action 101: Go to the Function Panel in the lower portion of the calculator. Select All
from the drop-down box (if it is not already selected) and enter db20 in the search field,
as shown below.

Action 102: Select the dB20 function.

This will calculate the gain across the ac frequency sweep, plotting the results in dB.

Action 103: Import this expression to the Outputs pane (as done in the previous
section) and name it Av_ac.

Action 104: Press the green icon ‘ ’ on the top toolbar to start the simulation. You
will see a UI update with a simulation status.

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Waveform Results Analysis

After the simulation is finished, the Results tab will look like as shown below.

Action 105: Go to Options > Plotting/Printing. Deselect the Plot Scalar Expressions
for Multipoint Simulation checkbox and click OK on the form.

Note: If this option is checked and grayed out, change Plotting Option to Auto,
uncheck the Plot Scalar Expressions option, and then change it back to None.

Action 106: To see the waveform results, click on the Plot All icon.

A ViVA XL (Virtuoso Visualizations & Analysis XL) window will appear with results as
follows:

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If the ViVA window is docked to the maestro view, press the ‘ ’ icon.

Two subwindows are displaying the tran test results. The scalar output values for
Vout_dc and Vin_dc are also informed.

Action 107: Right-click on the Vin_tran label on the left side of the waveform and
change the Color to yellow.

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Action 108: Drag and drop Vin_tran in the other subwindow.

If the signals are still not overlaid, press the overlay icon ‘ ’ found in the upper-right
toolbar. Delete the second subwindow by right-clicking on the empty graph and
selecting Delete.

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The op-amp works well as a buffer because the output and the input waves are almost
equal.

In this section, you will use some manual methods for calculating measurements with
signals. This is an introduction to assistants and markers. In a later section, you will
create expressions for these measurements. If you wish to skip this section, move to
Lab 9.

Action 109: Left-click on the Vout_tran legend text to select the signal and go to
Measurements > Transient Measurement.

The Transient Measurement assistant opens, as shown below.

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As you can see in the Measurements section, the first edge (falling) has a Slew Rate
value of 50.8 V/us. You need to find the slowest slew rate value over time.

Action 110: Press the Edge selector up arrow to scroll through the other edges. You
will see that the smallest value is 50.8V/us. Thus, your worst-case Slew Rate is
50.8MV/s.

Action 111: Close the Transient Measurement assistant by selecting the ‘x’ icon in the
toolbar.

To calculate the settling time, consider the time the wave reaches and stays between +/-
1% of its final value compared to the initial value. This is calculated as follows:

• Lower bound = 99%*(1.3V-0.7V) + 0.7V = 1.294V

• Upper bound = 101%*(1.3V-0.7V) + 0.7V = 1.306V

Action 112: Right-click on the x-axis and select Axis Properties.

Action 113: Go to the Scale tab, change Mode to Manual, and set Axis Limits
between 4.98us and 5.04us. After that, click OK.

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This will isolate the edge that you want to analyze.

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Action 114: Click on the eye icon ‘ ’ next to the Vin_tran signal to hide it.

Action 115: Hover your mouse close to the point 5us of Vout_tran and press A to mark
the point, as shown below. You can manually adjust the position of the marker.

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Place a second marker where the signal settles within the bounds calculated above. To
make this placement easier, use horizontal markers for guidance.

Action 116: Press H close to the 1.055V level to place a horizonal marker. Move your
mouse up and place a second one.

Action 117: Double-click on the lower marker to open its properties. Set Y Position to
1.294V. Repeat for the other marker, setting its Y Position to 1.306V.

Action 118: Zoom into the region between the markers. You can do that by holding the
Ctrl key and using the scroll wheel of your mouse.

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Action 119: Hover your mouse over the Vout_tran signal where the voltage value
enters and remains between the horizontal markers (“settling point”). Press B to place
the second marker. Then, press f to see the full signal again.

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Do not worry if your numbers differ slightly from what is shown here. The dx value
reports a Settling Time of about 15.6ns.

Action 120: Go to Marker > Delete All.

Action 121: Repeat this process with the falling edge of the signal. This time, set the x-
axis region between 9.98us and 10.04us. Place a marker at 10us. Place horizontal
markers at 694mV and 706mV.

Again, place a second marker when the signal enters and stays in the region defined by
the horizontal markers.

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As you can see, the dx value is much larger for the falling transition. Therefore,
considering the worst case, you can say that your final Settling Time is about 23.1ns.

One interesting feature ViVA allows is to save plotting templates, in order to easily
access then when using same (or similar) waveforms. Let’s try it now.

Action 122: Go to File -> Create Maestro Plotting Template …, write MyTemplate as
template name and press Create Template button.

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Action 123: Now close the ViVA window. In maestro tab, make sure “MyTemplate” is
selected and press plot button again.

Same results will be plotted:

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Now, move to the DC results.

Action 124: Go to the maestro tab. Do not close ViVA.

As you can see, the output DC value is 998.8mV. Since the input DC value for this
simulation is 1V, the DC Offset is (998.8 - 1000)mV= -1.2mV.

Now, move to the AC results.

Action 125: Go to the ac tab on ViVA.

Action 126: Hover your cursor over the low-frequency portion of the signal.
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Looking at this value, you can say that the DC Open-Loop Gain is about 51.0dB.

Action 127: Move your cursor along the signal until you get to the point where the y
value is around 0dB. Press M to put a simple marker on it.

From this marker, you can say that the Unity-Gain Bandwidth is about 79MHz or
80MHz.

As a review, the measurement specifications are as follows:

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• Slew Rate >= 50MV/s

• DC Open-Loop Gain >= 60dB (1000V/V)

• Unity-Gain Bandwidth >= 50MHz

• Output Offset <= 10mV

• Settling Time <= 50ns

You can see that all measurements meet the specifications, except for the DC Open-
Loop Gain, which is 9dB below the required value. You need to tune your design to
meet this specification.

Action 128: Close the ViVA window and the Calculator.

Generating Expressions
In the last section, you measured waveforms manually to derive expressions. This is
useful, but you can increase productivity by creating reusable expressions.

Action 129: Go to the Outputs Setup pane in ADE Assembler and click on the red
down-facing arrow beside the Add New Output icon ‘ ’. Select tran > Expression to
add an expression to the tran test.

Action 130: Double-click the Details column for the new expression and click on the
Open expression builder icon ‘ ’ to open the Expression Builder.

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Action 131: Type slew, and when the autocompleted string appears in the prompt,
select slewRate.

As you can see, Expression Builder provides helpful prompts for building the
measurement.

Action 132: For the signal, scroll down to the list of measurements and select
Vout_tran. You can also start typing Vout_tran and take advantage of the autocomplete
feature.

Action 133: For initialValue, enter 1.3. Proceed to the next step by pressing the
spacebar.

Action 134: For initialValueType, select nil.

Action 135: For finalValue, enter 0.7.

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Action 136: For finalValueType, select nil.

Action 137: For percentLow, enter 20.

Action 138: For percentHigh, enter 80.

Action 139: For numberOfOccurences, select nil.

Action 140: For sweepName, select time.

Action 141: Press the closing parenthesis and click on the green icon ‘ ’ (OR press
Enter) to insert the expression.

Action 142: Name the expression as Slew Rate.

Action 143: Repeat these steps to add a second expression. This time, you will build an
expression for the settling time.

Action 144: Follow the process defined above to build the following expression:

This expression uses 0us as the initial time and 2us as the final time, so it will measure
the settling time of the first falling edge. Click on the green icon ‘ ’ to insert the
expression.

Action 145: Name the expression Settling Time.

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Action 146: Add another expression to the ‘tran’ testbench. For that, click on the ‘ ’
icon, and the last action performed will be repeated. Enter Vout_dc - Vin_dc in the
Details column and click on the green icon ‘ ’ to insert the expression.

Action 147: Name the expression as Offset.

You will also build an expression to measure dissipated power from the DC analysis.

Action 148: Add another new ‘tran’ testbench expression and bring up the Expression
Builder, as done in the previous steps. Enter 2*.

Action 149: Enter IDC and click on < Select from design >.

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Action 150: Select the top pin of the VDD_source component.

Action 151: Click on the green icon ‘ ’ to insert the expression. Switch to the maestro
tab and name the expression Pdiss.

The value 2 is the total supply voltage range applied on the op-amp. Now, two
expressions are left to add: dc gain and bandwidth. Those will be added to the ac test.

Action 152: Add an expression for the ac test (you will again need to use the
downward-facing arrow ‘ ’ next to the icon) and open the Expression Builder, as
done in previous steps.

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Action 153: Build the following expression:

Action 154: Insert the expression and name it as UGB (Unity-Gain Bandwidth).

Action 155: Enter another expression for ‘ac’ and type value in the Expression
Builder.

Action 156: Build the following expression:

This will measure the Av_ac signal at the initial value (1Hz).

Action 157: Insert the expression and name it as Av0.

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Action 158: Go back to the Results tab of the maestro view. Press ‘ ’ in the toolbar
to reevaluate the output expressions. This feature allows an evaluation of expressions
without rerunning the simulation if all of the required data is available.

The results are shown below.

As you can see, these results are similar to the ones you manually analyzed in the last
section.

Action 159: Since you want absolute values for Slew Rate and Pdiss, insert the abs()
function around both, as shown below. Evaluate again to see the change.

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The next stage is to define specifications for each expression. This means you can see
which expressions are passing or falling at a glance.

Action 160: Return to the Outputs Setup, double-click the Slew Rate Spec column,
select > and insert 50M on the field at its right.

This means you want the slew rate value to be higher than 50MV/s.

Action 161: Add specifications for other measurements, as shown below.

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Action 162: Return to the Results tab and press ‘ ’ to reevaluate. The results are
shown below.

All expressions meet the specifications except Av0. The red colorization is an indication
of the spec failure.

Design Tuning Using Parameters

In this section, you will tune the design to pass the specifications. To tune the circuit,
adjust the length and width of some transistors. Make the lengths and widths
parameters, which will enable you to experiment with these device values without
editing the schematic.

Action 163: On the Data View assistant, expand the Parameters tree and click on the
Click to add parameter text.

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This will open the op-amp schematic and invoke two new assistants: Circuit
Prospector and Variables and Parameters.

Action 164: Go to Window > Assistants > Navigator to reinvoke the Navigator
assistant.

Action 165: Close the Circuit Prospector assistant. Select all instances on the
Navigator except for M2, M5, and M8 (the pmos capacitor). In the Variables and
Parameters assistant, right-click on the Length value of the transistors and select
Create Parameter.

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Action 166: Select all six entries in the lower table of the assistant, right-click and
choose Match Parameters.

This will cause all lengths to vary as you tune the design. Notice that the parameters are
organized in a tree structure with the first parameter as the root.

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Action 167: Select only M3 and M4 (the differential pair) and use similar steps to create
a parameter for Total Width. Select both in the lower table, right-click, and choose
Match so that they track together.

Action 168: Close the schematic view and return to the maestro tab.

Action 169: On the maestro tab, look at the Parameters section on the Data View
assistant and notice the newly created parameters. From here, you can change these
values, avoiding edits to the schematic.

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Action 170: Set M0/l to 500n and M3/w to 1u. Here, it is assumed that M0 and M3 are
the masters of your two parameter sets.

These parameters will be used for both testbenches. Focus first on the ‘ac’ results
tuning.

Action 171: Descend into the ac test by clicking on the down arrow ‘ ’ next to the
testbench name.

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Action 172: Rerun the simulation for this single test using the ‘ ’ icon on the right-
side toolbar.

As you can see, by increasing L and Wdiff, you get much closer to the specifications for
Av0. The yellow colorization indicates that you are within ±10% of the spec.

Action 173: Dismiss the ViVA window. Click on the Real Time Tuning icon.

The schematic testbench appears with the Real Time Tuning assistant docked on the
left.

Action 174: Select Window > Assistants > Outputs to dock the expressions to the
bottom of the window.

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Action 175: Click on the Run icon ‘ ’ under the Tuning panel to initialize the tuner.

Your initial results should look like as shown below. Arrange the schematic and the
waveform so you can see both as you tune.

Action 176: Hover your mouse over the M0/l entry in the tuner and increase its value to
670n. Note a change in the scalar expression and the plotted additional signal.

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Action 177: Tune M3/w to 1.33u.

The specifications are now met.

Action 178: As you need to account for parasitic effects on the simulation, you must
further tune the design. Increase M0/l to 750n and M3/w to 1.5u. This will increase UGB
to about 116MHz and Av0 to about 60.5.

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Action 179: Click the Save back to ADE Explorer icon in the lower portion of the
tuning assistant to save your tuned values to the ADE session.

Action 180: Exit RTT by selecting the same icon that you used to invoke it:

Action 181: Close ViVA and the schematic view and return to the maestro tab. Expand
the Parameters section and notice the updated values:

Action 182: Ascend to ADE Assembler by clicking on the up arrow ‘ ’ next to the ac
testbench name. Rerun the simulation to see how tuning impacts the transient results.

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As you can see, Slew Rate has fallen slightly out of spec. To fix this, increase the bias
current, ibias. As you need to change this value for both tests, make ibias a global
variable.

Action 183: Expand the Design Variables field in the ac test, select ibias, right-click
and select Create/Update Global.

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Expand the Global Variables field and notice that ibias is added. If the variable is
enabled there, you will see it displayed with a strikethrough in the Design Variables
section for each test. This indicates that the global variable will be used rather than a
local variable.

Action 184: Increase the ibias global value to 10.5u and rerun the simulation. Your
results should look as follows:

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Backannotation of Tuned Parameters

In this section, you will replace the width and length values of your op-amp with the
values produced by tuning.

Action 185: In the gray row (just below the Filter widgets in the Results table), right-
click and select Backannotate.

Right-click here

Action 186: In the Warning window that appears, select Only device parameters and
press OK.

Action 187: In the OpAmp_tran tab, descend into the OpAmp block and verify that M0,
M1, M3, M4, M6, and M7 have l=750n. Verify that M3 and M4 have w=1.5u.

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Action 188: Leave all windows open and proceed to the next module.

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Module 5: Layout
In this section, you will build a layout for the op-amp. You will use the capabilities in
Virtuoso to place instances, match critical devices, and route the design.

In the case of a large design, it is advisable to create and use constraints to facilitate the
placement and routing of devices, making this process more automatic. Since this is a
small design, you will not use constraints.

Layout XL
Action 189: From the MyOpAmp/OpAmp/schematic, select Launch > Layout XL.
Specify Create New in the first pop-up window and press OK.

Action 190: In the New File window, accept the default values and select OK.

The design will open in Layout XL.

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Focus first on generating the devices.

Action 191: Go to Connectivity > Generate > All From Source OR press the ‘ ’
icon on the left of the toolbar at the bottom.

Action 192: Ensure the Generate Layout form looks like the image below and click OK.

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Action 193: Select Shift+f to display all layers. Your layout should look as follows:

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The Palette docked on the left of the layout window shows all the layers defined for the
process.

Action 194: Arrange your windows so that the schematic and the layout views are
arranged side by side. Select the M1 instance in the schematic and notice that the
corresponding components are selected in the layout.

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This is because you are working in a connectivity-aware flow.

Action 195: Select the M0 instance in the schematic.

In this first section, you will abut the layout devices corresponding to M0 and M1.

Action 196: Deselect everything in the layout and right-click somewhere inside the
prBoundary where there is a blank space. Select Make PR Boundary Non-Selectable.

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Transistor Abutment
Action 197: In the layout, zoom in on the four components that make up M0 and M1.

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Action 198: Select the leftmost transistor and drag it up a little.

You can also move objects using the M bindkey and selecting the device to move.

Action 199: Zoom in on the space between the two transistors on the left.

The drain (D) of the left member of this pair is next to the source (S) of the right
member, and so, without the abutment functionality, you would need to manually flip
one of them to make the connection correct. You will now see how abutment does that
for you automatically.

Action 200: Drag the left member M1 to the right and down until its drain just touches
the source of the other member, as shown below.

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When the move completes, the source connection for the two transistors will be abutted.

Action 201: Zoom out to see the four components.

There is also an automatic abutment option available when you generate the instances.
You will look at that next.

Action 202: Select the Connectivity > Generate > All From Source command OR
press the ‘ ’ icon on the far left in the bottom toolbar.

Press Yes on the following prompt:

Action 203: On the Generate Layout form, select Chain under Instances.

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Action 204: On the I/O Pins tab, set Layer to Metal2 drawing and click the Apply
button on the right. This will change the Layer for all pins in the lower table.

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Action 205: Click OK on the form. Zoom in on M0 and M1 again.

You will see that M1 and M0 are abutted, along with many other transistors in the
design.

This automatic abutment can save a lot of time when the design is large. To remove an
abutment, drag the transistors apart from one another.

Next, you will look at the alignment capability.

Action 206: Select M2 on the schematic and see that it is also selected in the layout.
You may need to move the capacitor so that it is next to the M2 component, as shown
below.

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Action 207: Press A to invoke the Align command and select the top border of M2 on
the layout.

Action 208: Now, select the top border of the MOSFET capacitor.

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The top edge of M2 will align with the top edge of the capacitor. Again, this is an editing
capability that will streamline your work.

Placement
In this section, you will use some of the manual editing commands in Virtuoso to
optimize the area in your layout before routing.

Action 209: Using the Move command (the m bindkey), place the components as
shown below. For abutted devices, select and move them together. You can use the n
in-command bindkey to change the snap mode during the move.

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Action 210: Select Options > Selection and change the Mode option from Full to
Partial. Then, click OK.

Action 211: Right-click the empty space inside the PR Boundary and select Make PR
Boundary Selectable. Select one of the boundary edges.

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Action 212: Then, press s to invoke the Stretch command. Select and drag the PR
Boundary to just enclose the components. Repeat with the other edges of the
boundary as needed.

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Action 213: To centralize this layout view, select Edit > Advanced > Move Origin.
Then, select the bottom-left corner of the layout PR Boundary rectangle.

Layout design is now better centralized in the design window.

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Action 214: Enable Navigator in the layout if it is not already displayed. Select the six
pins listed in the Navigator assistant to locate them in the Layout view. You may need
to use the left-facing arrow in the Navigator to display the Type filter and select Pins.

The pins are still placed at their original generated location. To improve their placement,
you will use the Pin Placement tool.

Action 215: Go to Place > Pin Placement. The following form will appear:

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The six pins in the design are listed on this form.

Action 216: If the pins are not already selected, use Shift+LMB to select all. Set the
Width and Height to 0.1 and select Apply.

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The dimensions are changed for all pins. Now, set the positions for each pin.

Action 217: Select only the VDD pin in the dialog box. Set Edge as Top and click
Apply.

Action 218: With VDD still selected, select HRail in the Create section.

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This creates a horizontal rail for VDD at the top border of the PR Boundary.

Action 219: Repeat the previous two Actions for VSS, but with Edge selected as
Bottom.

Action 220: Define the following placement for the remaining pins:

• IBIAS, INN, and INP on the left

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Basics of Analog Flow: RAK

• OUT on the right

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After finishing the above, the form should look like as follows:

Action 221: Close the form and save the layout view.

Routing
Action 222: In the layout, change the workspace from Classic to VSR. This will allow
you to see both the Navigator and Palette assistants, which can be helpful for routing.

The Navigator and the Palette assistants are docked and tabbed on the left of the
layout canvas.

Action 223: On the Navigator, display the Nets. Make the assistant wide enough to
display the XL Status column.

The XL Status column shows the number of opens for each net.

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Action 224: Select the net INP.

This highlights the net on the schematic and shows the location where it should be
connected in the layout. One easy way to route this net is by using the autoroute
feature. First, you need to define gate connections for these transistors.

Action 225: Locate the M4 instance in the layout. Select the two fingers and zoom in.

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Action 226: Press q to invoke Edit Instance Properties.

Action 227: Use Shift to select both instances in the list on the left. Select the
Parameter tab.

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Action 228: Set Gate Connection to Top and press OK.

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Gate connections will appear, as shown below.

Action 229: Press f to zoom out. Go back to the Navigator assistant and display the
Nets. Locate INP, right-click, and select Route with Default Lookup. Then, unselect
the created net.

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Your layout should look like the following image:

This routing command used Metal1 for horizontal routes and Metal2 for vertical. The
appropriate ‘via’ is created where they intersect.

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On the Navigator assistant, XL Status will change to reflect the complete route:

Next, you will use the manual routing commands.

Action 230: Press f on the layout to see the full design. Select INN in the Navigator
assistant.

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Action 231: Locate M3 and set the gate connection to Top as was just done for M4.
Then, go to the Palette assistant and select the Metal1 drawing layer.

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Action 232: Press P to start the Create Wire command. Select the right edge of the
leftmost M3 member gate and then the left edge of the rightmost M3 transistor gate,
wiring their gates together.

Action 233: Still in the ‘wiring’ command, zoom in on the M3.1 gate (this is the
component on the left) and select the top edge to start a new wire, as shown below.

You will see that this will start drawing the wire of the same width as the gate. As you do
not want this wire to be that thick, you need to change it from within the command.

Action 234: As you are drawing the wire, right-click and select Use Width > Default
Constraints.

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This will change the wire width, as shown below.

Switch to Metal2 for this vertical route.

Action 235: Return the cursor to the gate (where the route starts) and press the Space
bar to open the Select Via form. Select Metal2. Then, close the form.

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Action 236: Click to place the via and start the Metal2 wire.

Action 237: Press Space bar again and select Metal1. Then, close the form.

Action 238: Zoom out and continue the wire on the left border of the layout.

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Action 239: The INN pin is directly above the wire (if needed, you can move it away
from any components). Continue the route from the horizontal segment by dropping
another via at the endpoint (use the Space bindkey again) and selecting Metal2.
Continue the route to the INN pin. Double-click or press Enter to end the connection,
and then press Esc.

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Action 240: Return to the Navigator assistant.

As you can see, INN is completely routed, with no opens reported.

Action 241: Save the layout and proceed to the next lab.

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DRC Tests
You have made several adjustments to the layout so far, but you still do not know if all
the physical rules are being followed. You will use Design Rule Checking (DRC) in this
lab to check this issue. It is a good practice to do DRC checks after any significant
changes to the design before moving further to avoid propagating mistakes.

If you strictly followed the instructions given in the other labs of this module, DRC tests
should have similar results to the ones shown in this lab. If not, some differences might
appear. In that case, it might be better to copy everything from the
solutions/Module5/Lab15 directory and paste it on the BAF_RAK directory,
replacing repeated files.

Action 242: Go to Pegasus > Run DRC. In the DRC Run Submission Form, enter
DRCrun into the Run Directory field and proceed to the Rules tab (tab controls are on
the left side of the window).

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Action 243: In the Rules tab, press the ‘ ’ button on the Technology mapping file
row and set the path to gpdk045_v_6_0/pvtech.lib.

The pvtech.lib file defines where the required setup information is stored for design
rule checking. The structure is similar to the cds.lib file, mapping a technology name
to the location where the rules are saved.

Action 244: Choose the gpdk045_pvs technology from the drop-down list.

The DRC Run Submission Form should look as shown below.

If there are more rules listed in the Rules pane, delete them.

Action 245: Leave the rest of the setup as-is and press Submit.

The run will start, and a log file will appear. The following results should appear after the
run is finished:

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As you can see, 27 DRC errors are found. Your number may vary depending on how
closely your design matches this reference.

Action 246: Click on the NIMP.SP.1 error. Select the OpAmp/NIMP.SP.1 entry in the
right column.

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Look in the bottom-right section of the Viewer to see details of the selected error. This is
a violation of the N+ Implant spacing.

Action 247: Select the Coordinates link in the error details. This will zoom into the
location of this error in the layout window.

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The location of the error is zoomed in and highlighted with the other objects dimmed.

The error shows that the N+ Implant layers of the transistors are too closely spaced.
You can solve this by joining the N+ Implant layers since they all should connect to the
same body.

Action 248: On the Palette assistant, select the Used checkbox to see only the layers
used in the design.

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Action 249: Select Nimp and click on NV (None Visible) to turn off the visibility for all
other layers.

The V and S checkboxes on the right of each layer set each layer as ‘visible’ and/or
‘selectable’.

To solve the spacing error, draw a rectangle on the Nimp layer.

Action 250: With the Nimp layer selected, press r and draw a rectangle that encloses
the space between the implants, as shown below. Then, press Esc.

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There is no problem if Nimp layers overlap each other.

Action 251: Save the view, go back to the DRC Reports window, and press ReRun.

The NIMP.SP.1 error should disappear. If it does not, repeat the above process to
address the additional spacing violations.

Action 252: Close all windows except for the CIW and Library Manager and proceed to
the next Lab. You can discard changes if prompted.

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LVS (Layout Versus Schematic)

Before running LVS, copy a completed version of the layout into your work area.

Action 253: In the CIW, select Tools > Library Path Editor and go to Edit > Add
Library.

Action 254: In the Add Library form, double-click on the solutions directory and then
select Layout_solution in the Library field. Press OK.

The respective library will be added to your session.

Action 255: Exit the Library Path Editor window and save changes when prompted.

Action 256: Check the Library Manager to make sure that the Layout_solution library
is listed.

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Action 257: Open the Layout_solution/OpAmp/layout design.

Action 258: Go to Pegasus > Run LVS. The following form opens:

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Action 259: Specify Run Directory as LVSrun.

Action 260: On the Rules tab, set Technology mapping file as

gpdk045_v_6_0/pvtech.lib and the technology as gpdk045_pvs. Verify that there is a
single entry in the Rules pane.

Action 261: On the Input tab, change the Convert Pin to option to Geometry+Text
and change the Create CDL option to auCDL, as shown below.

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This will make sure that all pins are correctly identified, even if they are not assigned
using explicit labels.

Action 262: On the Output tab, enable the Create Quantus Input Data checkbox, as
shown below.

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You will use it for the parasitic extraction in the next module.

Action 263: Leave the rest as default and click Apply.

After the LVS run finishes, the following window should appear:

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This means that your LVS is clean, and no errors are found in the comparison between
your layout view and your schematic view.

Action 264: Close the Results Viewer window and close the Pegasus form.

Action 265: Leave the layout view open and proceed to the next module.

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Module 6: Post-Layout Simulation

To be able to simulate with parasitics, you first need to extract parasitics from your
layout. For this RAK, you will use Quantus to create two parasitic formats: a Detailed
Standard Parasitic Format (DSPF) file and Smart View.

DSPF is the most common method of representing parasitics and has been used for
many years. Smart View is a new extracted view that enables you to simulate and
analyze post-layout design seamlessly in ADE without managing external files or
additional translation steps. Smart View has a reduced data size and improved
performance over the original Quantus extracted view. The other advantage of Smart
View is that you can visualize parasitics on the layout. If your Quantus version does not
yet include the Smart View feature, you can skip Lab 19.

Using Quantus to Create a DSPF File

Action 266: On Layout_solution/OpAmp/layout design, go to Quantus > Run
Pegasus - Quantus and fill in the initial form, as shown below.

Action 267: Click OK on the form. On the Quantus (Pegasus) Parasitic Extraction
Run Form, fill in the Setup tab, as shown below.

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Action 268: Scroll down on this tab and change Output to Transistor DSPF. Enable
Extract MOS Diffusion Res and make sure that the Auto Accuracy Downgrade field
is disabled.

Proceed to the Extraction tab and fill it in, as shown below.

Action 269: Click Apply to start the extraction.

When the Quantus Run is completed, the following window should open:

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If you check that path, you should be able to see the DSPF file generated.

Action 270: Click on Close. Leave everything else including the main Quantus window
open and proceed to the next lab.

Using Quantus to Create a Smart View

Action 271: Go back to the Setup tab on Quantus (PVS) Parasitic Extraction Run
Form.

Action 272: Change Output to Smart View. Then, change the View name to
sv_extracted. Enable Extract MOS Diffusion Res and make sure that the Auto
Accuracy Downgrade field is disabled. Leave everything else set to their default
values.

Action 273: Click Apply again.

When the Quantus Run is completed, the following window should open:

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Action 274: Click Close and exit Quantus. Check the Library Manager for the
sv_extracted view.

Action 275: Close the schematic and layout views. The CIW and Library Manager
should still be open.

Let us now place this view on the MyOpAmp library.

Action 276: Right-click the newly created sv_extracted view under Layout_solution >
OpAmp and select Copy. In the To section of the Copy View form, switch the Library
from Layout_solution to MyOpAmp. Your form should look as follows:

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Action 277: Click OK on the dialog box. In the Copy Problems dialog box, select OK.
This will create a copy of the extracted view in your working library.

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Creating a Config View Using Virtuoso Hierarchy Editor

In this lab, you will create a ‘config’ view so that you can use the extracted views for a
post-layout simulation.

Action 278: In the Library Manager, select the MyOpAmp library and the
OpAmp_tran cell. Select File > New > Cell View or use the Crtl+n bindkey. Fill in the
form (as shown below) and click OK.

Virtuoso Hierarchy Editor will open together with the New Configuration window.

Action 279: In the View field on the Top Cell section, select schematic.

Action 280: Press the Use Template button at the bottom of the dialog box and select
spectre as the Name. Click OK on the form.

This populates the View and Stop lists with view names that are used in Spectre
netlisting. These lists will dictate the default traversal behavior as the netlister descends
through the design.

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The New Configuration form should look as follows:

Note that the Library List is used only in text-driven flows, often found in a mixed-signal
design. For now, leave the list as-is.

Action 281: Click OK on the New Configuration dialog box.

The resulting config view should look as follows:

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This editor shows every block/component used in the design. The View Found column
shows the views that will be used during hierarchy traversal and netlisting.

Action 282: Right-click on the OpAmp Cell row and select Set Cell View >
sv_extracted.

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Action 283: Click on the toolbar icon ‘ ’ to update changes. Press OK in the window
that pops up.

Next, create a similar view for the ac test.

Action 284: In the Hierarchy Editor, go to File > Save As and change the cell name to
OpAmp_ac, as shown below. Write config in the View field. Then, press OK.

Now that you made a copy of the config view for the ac test, you just need to change
the top cell since that is the only difference between both views.

Action 285: In the OpAmp_ac config view, select Edit in the Top Cell section and
change the cell name to OpAmp_ac, as shown below. Then, press OK.

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Action 286: Update this config view by pressing the ‘ ’ icon. Press OK on the window
that pops up.

Now, you have successfully created two config views.

Action 287: Close the config view and proceed to the next lab.

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Post-Layout Simulations on ADE Assembler

Action 288: Open the maestro view using MyOpAmp > OpAmp_sim > maestro. The
ADE Assembler window will open.

Action 289: Expand Tests on the Data View assistant, right-click on the tran test, and
select Create Test Copy twice to make two copies of the test.

Action 290: Change the name of the two new tests to tran_SmartView and
tran_DSPF.

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Action 291: Repeat this same process for the ac test so that your maestro view test list
appears as shown below. Drag and rearrange the order of the tests so that all tran and
ac tests appear together.

Action 292: Right-click on the tran_SmartView test and select Design.

Action 293: In the Choose Design dialog box, verify that OpAmp_tran is selected, and
select config as the view. Click OK.

Action 294: Right-click on the tran_DSPF test and select Simulation Files. The
Simulation Files Setup form will open.

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Action 295: Add the OpAmp.dspf file you generated to the Parasitic Files (DSPF)
section.

Action 296: Click OK on the form.

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Action 297: Repeat this process for ac_SmartView and ac_DSPF, changing the
design reference of the ac_Smartview test to use the config of OpAmp_ac and adding
the same DSPF file to Simulation Files for ac_DSPF.

The next step is to run these simulations. Since there are six simulations to be done,
configure ADE to allow parallel runs.

Action 298: Go to Options > Job Setup and set the Max. Jobs field value to 2, as
shown below. Click OK on the form.

This will launch two Spectre jobs simultaneously.

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Action 299: Click the Run Simulation icon ‘ ’.

As the simulations run, you will see two terminal icons in the Run Summary pane,
representing the two parallel simulation jobs. Below that you will see one terminal icon,
representing one job for the netlisting stage. If desired, you can also change the
maximum number of parallel netlisting jobs in the Netlisting tab of the previous form.
The tests statuses will change from ‘pending’ to ‘simulating’ as the jobs begin.

After all the simulations are finished, numerical results will appear for the measurements
and waveform icons for signals.

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Most values should be shaded in green, indicating that the design meets specifications
in all conditions. Some values are shaded in yellow, which indicates an influence of the
parasitic effects on your design.

Additional steps like transistor matching and the use of guard rings during your
layout design might present better post-layout results, but those steps will not be
approached here. Notice that the results from the extracted view tests are identical to
those from the DSPF file tests. This is expected since the parasitics created by
Quantus are precisely the same.

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Support
Cadence Learning and Support Portal provides access to support resources, including
an extensive knowledge base, access to software updates for Cadence products, and
the ability to interact with Cadence Customer Support. Visit
https://support.cadence.com.

Feedback
Email comments, questions, and suggestions to content_feedback@cadence.com.

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