Module 3: Data-Processing Circuits

➢ Syllabus:
o Multiplexers
o Demultiplexers
o 1-of-16 Decoder
o BCD to Decimal Decoder
o Seven Segment Decoders
o Encoders
o Exclusive-or Gates
o Parity Generators and Checkers
o Magnitude Comparator
o Programmable Array Logic
o Programmable Logic Arrays, HDL
o Implementation of Data Processing Circuits

MULTIPLEXERS:
A multiplexer (or data selector, abbreviated as MUX) has a group of data inputs and
a group of control inputs. The control inputs are used to select one of the data inputs
and connect it to the output terminal. The following Figure shows a 2-to-1
multiplexer.

When the control input A is 0, the switch is in the upper position and the MUX output
is Z = I0; when A is 1, the switch is in the lower position and the MUX output is Z =
I1. In other words, a MUX acts like a switch that selects one of the data inputs (I 0 or
I1) and transmits it to the output. The logic equation for the 2-to-1 MUX is therefore:
𝑍 = 𝐴′ 𝐼0 + 𝐴𝐼1

The following Figure shows diagrams for a 4-to-1 multiplexer, 8-to-1 multiplexer,
and 2n-to-1 multiplexer.
The 4-to-1 MUX acts like a four-position switch that transmits one of the four inputs
to the output. Two control inputs (A and B) are needed to select one of the four inputs.
If the control inputs are AB = 00, the output is I0; similarly, the control inputs 01, 10,
and 11 give outputs of I1, I2, and I3, respectively. The 4- to-1 multiplexer is described
by the equation: 𝑍 = 𝐴′ 𝐵′𝐼0 + 𝐴′ 𝐵𝐼1 + 𝐴𝐵′𝐼2 + 𝐴𝐵𝐼3

Similarly, the 8-to-1 MUX selects one of eight data inputs using three control inputs.

It is described by the equation: 𝑍 = 𝐴′ 𝐵′𝐶′𝐼0 + 𝐴′ 𝐵′ 𝐶𝐼1 + 𝐴′𝐵𝐶′𝐼2 + 𝐴′𝐵𝐶𝐼3 + 𝐴𝐵′𝐶′𝐼4

+ 𝐴𝐵′ 𝐶𝐼5 +
𝐴𝐵𝐶′𝐼6 + 𝐴𝐵𝐶𝐼7. Multiplexers can also have an additional input called an enable
input.
If the OR gate in the above Figure is replaced by a NOR gate, then the 8-to-1 MUX
inverts the selected input. To distinguish between these two types of multiplexers,
we will say that the multiplexers without the inversion have active high outputs, and
the multiplexers with the inversion have active low outputs.
 In general, a multiplexer with n control inputs can be used to select any one of 2n
data inputs. The general equation for the output of a MUX with n control inputs and
2n data inputs is:

Where mk is a minterm of the n control variables and Ik is the corresponding data input.

Multiplexers are frequently used in digital system design to select the data which is
to be processed or stored.
The following Figure shows how a quadruple 2-to-1 MUX is used to select one of
two 4-bit data words. If the control A = 0, the values of x0, x1, x2,and x3 will appear
at the z0, z1, z2, and z3 outputs; if A = 1, the values of y0, y1, y2, and y3 will appear
at the outputs.

Multiplexer Logic: A digital design usually begins with a truth table. The problem is to come
up with a logic circuit that has the same truth table. We have two standard methods for
implementing a truth table – the SOP and the POS solution. The third method is the multiplexer
solution.

Problem: Implement Y (A, B, C, D) = ∑m (0, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 15) using 16-to-
1 multiplexer (IC 74150) & 8-to-1 multiplexer.
 Solution: Notice that, output is an active low signal in IC 74150.
8-to-1 MUX
A B C D Y
Data Inputs
0 0 0 0 1
̅
𝐷
0 0 0 1 0
0 0 1 0 1
1
0 0 1 1 1
0 1 0 0 1
1
0 1 0 1 1
0 1 1 0 0
0
0 1 1 1 0
1 0 0 0 1
1
1 0 0 1 1
1 0 1 0 1
1
1 0 1 1 1
1 1 0 0 1
1
1 1 0 1 1
1 1 1 0 0
D We follow a procedure that is similar to the one that
1 1 1 1 1
we adopted in Entered Variable Map method to
implement Y using 8-to-1 MUX.

8-to-1 MUX
A B C
Data Inputs
0 0 0 ̅
𝐷
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 D

Problem: Design a 32-to-1 multiplexer using two 16-to-1 multiplexer and one 2-to-
1 multiplexer. Solution: The circuit diagram is shown in the following Fig. A 32-
to-1 multiplexer required 5 (log2 32) select lines (say, ABCDE). The lower four
select lines (BCDE) chose 16-to-1 multiplexer outputs. The 2- to-1 multiplexer
chooses one of the output of two 16-to-1 multiplexers, depending on the 5th select
line (A).

Problem: Realize 𝑌 = 𝐴̅𝐵 + 𝐵𝐶̅ + 𝐴𝐵𝐶 using an 8-to-1 multiplexer. Also, realize the
same with a 4-to-1 multiplexer.

Solution: Given, 𝑌 = 𝐴̅𝐵 + 𝐵̅ 𝐶̅ + 𝐴𝐵𝐶

𝑌 = 𝐴̅𝐵(𝐶̅ + 𝐶 ) + 𝐵̅ 𝐶̅ (𝐴̅ + 𝐴) + 𝐴𝐵𝐶
𝑌 = 𝐴̅𝐵𝐶̅ + 𝐴̅ 𝐵𝐶 + 𝐴̅𝐵̅ 𝐶̅ + 𝐴𝐵̅ 𝐶̅ + 𝐴𝐵𝐶
Y = ∑m (0, 2, 3, 4, 7).
Hence, to generate the given logic function, using
8-to-1 multiplexer, we find D0 = D2 = D3 = D4 = D7
= 1 and D1 = D5 = D6 = 0.
𝑌 = 𝐴̅𝐵𝐶̅ + 𝐴̅ 𝐵𝐶 + 𝐴̅𝐵̅ 𝐶̅ + 𝐴𝐵̅ 𝐶̅ + 𝐴𝐵𝐶
𝑌 = 𝐴̅𝐵̅ (𝐶̅ ) + 𝐴̅ 𝐵(𝐶̅ ) + 𝐴̅ 𝐵(𝐶) + 𝐴𝐵̅ (𝐶̅ ) + 𝐴𝐵(𝐶)
Hence, for a 4-to-1 multiplexer,
we find D0 = C’, D1 = 1, D2 = C’, and D3 = C generates the given function.
 8:1 MUX 4:1 MUX
A B C
Data Inputs Data Inputs

0 0 0 1 = D0
0 0 1 0 = D1 𝐶̅ = D0
0 1 0 1 = D2
0 1 1 1 = D3 1 = D1
1 0 0 1 = D4
1 0 1 0 = D5 𝐶̅ = D2
1 1 0 0 = D6
1 1 1 1 = D7 C = D3

Demultiplexer:
Demultiplex means one into many. A demultiplexer is a logic circuit with one input and many
outputs. The circuit has 1 input signal, m control or select signals and n output signals where n
<= 2m . Fig (b) shows the circuit diagram of a 1-to-2 demultiplexer. Note the similarity of
multiplexer and demultiplexer circuits in generating different combinations of control variables
through a bank of AND gates. Fig(c) lists some of the commercially available demultiplexer I
Cs. Note that a demultiplexer IC can also behave like a decoder. More about this will be
discussed in next section.

Demultiplexer Working: A demultiplexer obtains in data from one line and directs this to any
of its N outputs depending upon the status of the selected inputs. If the no. of output lines is N
(16), no. of select lines m is specified by 2 m = N that is, 24 = 16. Therefore, the no. of select
lines required for a 1 to 16 demultiplexer is 4. Table illustrates the Truth Table of this
Demultiplexer. The input can be send to any of the 16 outputs, D0 to D15. The input goes to
D0 if DCBA = 0000. The input goes to D1 if DCBA = 0001 and so on.
DECODERS AND ENCODERS:
The decoder is another commonly used type of integrated circuit. The following
Figure shows the diagram and truth table for a 3-to-8 line decoder. This decoder
generates all of them in terms of the three input variables. Exactly one of the output
lines will be 1 for each combination of the values of the input variables.
The following Figure illustrates a 4-to-10 decoder. This decoder has inverted outputs
(indicated by the small circles). For each combination of the values of the inputs,
exactly one of the output lines will be 0. When a binary-coded-decimal digit is used
as an input to this decoder, one of the output lines will go low to indicate which of
the 10 decimal digits is present.

In general, an n-to-2n line decoder generates all 2n minterms (or maxterms) of the n
input variables. The outputs are defined by the equations:
yi = mi, i = 0 to 2n – 1 (non-inverted outputs)
or
 yi = mi’ = Mi, i = 0 to 2n – 1 (inverted outputs)
where mi is a minterm of the n input variables and Mi is a maxterm.
Example: Realize the following functions using a 4-to-10 decoder.
f1 (a, b, c, d) = m1 + m2+ m4 and f2 (a, b, c, d) = m4 + m7 +m9
Solution: An n-input decoder generates all of the minterms of n variables. Hence,
n-variable functions can be realized by ORing together selected minterm outputs from
a decoder.

Rewriting given f1 and f2; we have: f1 = (m1’ m2’m4’)’ and

f2 =
(m4’ m7’m9’)’ Now, f1 and f2 can be generated using NAND gates,
as shown in the following Figure.

Problem: Show how using a 3-to8 decoder and multi-input OR gates following
Boolean expression can be realized simultaneously.

F1 (A, B, C) = ∑m (0, 4, 6) F2 (A, B, C) = ∑m (0, 5) F3 (A, B, C) = ∑m

(1, 2, 3, 7).
Solution: Since, at the decoder output, we get all the min-terms, we use them as
shown in the following Fig, to get the required Boolean expression:
Seven-Segment Decoders: The following Fig shows a seven-segment indicator, i.e. seven
LEDs labeled a through g (actually, eight LEDs labeled through a through h). By forward
biasing the LEDs, we can display the digits 0 through 9. For example, to display the digit 0,
we need to light-up the segments a, b, c, d, e, and f. Similarly, to light-up the digit 5, we need
segments a, c, d, f, and g.

Seven-Segment Indicator: Common Anode Type & Common Cathode Type

Seven-segment indicators may be common-anode type; where all anodes are
connected together (as shown above) or common-cathode type; where all cathodes
are connected together (as shown above).

The 7446 & The 7448: A seven-segment decoder-driver is an IC decoder that can
be used to drive a seven-segment indicator. There are two types of decoder-drivers,
corresponding to common-anode (IC 7446) and common cathode (IC 7448)
indicators. Each decoder driver has 4 input pins (the BCD input) and 7 output pins
(a through h segments), as shown in the following Fig.
7446 Decoder-driver & 7448 Decoder-driver
The logic circuits inside 7446 / 7448 convert the BCD input to the required output.
For Example, if the BCD input is 0111, the internal logic of the 7446 / 7448 will
force segments a, b, and c to conduct. As a result, digit 7 will appear on the seven-
segment indicator.

An encoder (converts an active input signal to a coded output signal) performs the
inverse function of a decoder. The following Figure shows a 8-to-3 priority encoder
with inputs y0 through y7. If input yi is 1 and the other inputs are 0, then the abc
outputs represent a binary number equal to i. For example, if y3 = 1, then abc = 011.

If more than one input is 1 at the same time, the output can be defined using a priority
scheme. The truth table in the above Figure uses the following scheme: If more than
one input is 1, the highest numbered input determines the output. For example, if
inputs y1, y4, and y5 are 1, the output is abc = 101.The X’sin the table are don’t-
cares; for example, if y5 is 1, we do not care what inputs y0 through y4 are. Output
d is 1 if any input is 1, otherwise, d is 0. This signal is needed to distinguish the case
of all 0 inputs from the case where only y0 is 1.
74147
The 74147 Figure a is the pinout diagram for a 74147, a decimal-to-BCD encoder. The
decimal input, X1 to X9, connect to pins 1 to 5, and 10 to 13. The BCD output comes from
pins 14, 6, 7, and 9. Pin 16 is for the supply voltage, and pin 8 is grounded. The label NC on
pin 15 means no connection (the pin is not used).

Figure b shows how to draw a 74147 on a schematic diagram. As usual, the bubbles indicate
active-low inputs and outputs. Table is the truth table ofa 74147. Notice the following. When
allXinputs are high, all outputs are high. When X9 is low, the ABCD output is LHHL (
equivalent to 9 if you complement the bits). When X8 is the only low input, ABCD is LHHH
( equivalent to 8 if the bits are complemented). When X7 is the only low input, ABCD
becomes HLLL (equivalent to 7 if the bits are complemented). Continue like this through
the rest of the truth table and you can see that an active-low decimal input is being converted
to a complemented BCD output.
2 input EXCLUSIVE-OR GATES
The exclusive-OR gate has a high output only when an odd number of inputs is high.

When A and B are low, both AND gates have low outputs; therefore, the final output Y is
low. If A is low and B is high, the upper AND gate has a high output, so the OR gate has
high A B output. Likewise, a high A and a low B result in a final output that is high. If both
inputs are high, both AND gates have low outputs and the final output is low.

4 input EXCLUSIVE-OR GATES

a pair of exclusive-OR gates driving an exclusive-OR gate. If all inputs (A to D) are low, the
input gates have low outputs, so the final gate has a low output. If A to C are low and D is
high, the upper gate has a low output, the lower gate has a high output, and the output gate
has a high output. Analyzing the circuit operation for the remaining input possibilities, we
can work out Table below. Here is an important prope1ty of this truth table. Each ABCD
input with an odd number of ls produces an output I. For instance, the first ABCD entry to
produce an output 1 is 000 l; it has an odd number of 1 s. The next ABCD entry to produce
an output 1 is 001 O; again, an odd number of Is. An output 1 also occurs for these ABCD
inputs: 0100, 0111, 1000, 1011,1101, and 1110, each having an odd number of ls.
Any Number of Inputs

a) There are 3 inputs and l output. If you analyze this circuit, you will find it produces an
output 1 only when the 3-bit input has an odd number of ls.
b) an abbreviated symbol for a 3-input exclusive-OR gate.
c) a circuit with 6 inputs and 1 output. Analysis of the circuit shows that it produces an
output 1 only when the 6-bit input has an odd number of 1 s
d) an abbreviated symbol for a 6-input exclusive-OR gate.
Parity generators and checkers:
o Even parity means an n-bit input has an even number of ls.
▪ For instance, 110011 has even parity because it contains four ls.
▪ 1111 0000 1111 0011 even parity
o Odd parity means an n-bit input has an odd number of ls.
▪ For example, 110001 has odd parity because it contains three ls.
▪ 1111 0000 1111 0111 odd parity
Parity Checker :
Exclusive-OR gates are ideal for checking the parity of a binary number because they
produce an output 1 when the input has an odd number of 1 s. Therefore, an even-parity input
to an exclusive-OR gate produces a low output, while an odd-parity input produces a high
output.
Parity Generation
In a computer, a binary number may represent an instruction that tells the computer to add,
subtract, and so on; or the binary number may represent data to be processed like a number,
letter, etc. In either case, you sometimes will see an extra bit added to the original binary
number to produce a new binary number with even or odd parity.

For instance, Figure shows 8-bit binary number: X7,X6,X5,X4 & X3,X2,X1,X0 Suppose
this number equals 0100 0001. Then, the number has even parity, which means the exclusive-
OR gate produces an output of 0. Because of the inverter, X8= 1 and the final 9-bit output is
‘1’ 01000001. Notice that this has odd parity. Suppose we change the 8-bit input to ‘0’ 110
0001. Now, it has odd parity. In this case, the exclusive-OR gate produces an output 1. But
the inverter produces a 0, so that the final 9-bit output is ‘0’ 0110 0001. Again, the final
output has odd parity. The circuit given is called an odd-parity generator because it always
produces a 9-bit output number with odd parity. If the 8-bit input has even parity, a 1 comes
out of the inverter to produce a final output with odd parity. On the other hand, if the 8-bit
input has odd parity, a O comes out of the inverter, and the final 9-bit output again has odd
parity. (To get an even-parity generator, delete the inverter.)
Practical applications of parity generation and checking-
The transients, noise, and other disturbances cause, 1-bit errors sometimes occur when binary
data is transmitted over telephone,' lines or other communication paths. One way to check
for errors is to use an odd-parity generator at the transmitting end and an odd-parity checker
at the receiving end. If no 1-bit errors occur in transmission, the received data will have odd
parity. But if one of the transmitted bits is changed by noise or any other disturbance, the
received data will have even parity.
Magnitude Comparator
A magnitude digital Comparator is a combinational circuit that compares two digital
or binary numbers in order to find out whether one binary number is equal, less than,
or greater than the other binary number. We logically design a circuit for which we
will have two inputs one for A and the other for B and have three output terminals,
one for A > B condition, one for A = B condition, and one for A < B condition.

1-Bit Magnitude Comparator

A comparator used to compare two bits is called a single-bit comparator. It consists
of two inputs each for two single-bit numbers and three outputs to generate less than,
equal to, and greater than between two binary numbers.

The truth table and logic circuit for a 1-bit comparator is given below.
Example : Show how two IC 7485 can be used to compare magnitude of two 8-bit
numbers.
Solution: The numbers to compare are X: X7,X6,….X0 and Y:Y7,Y6,……Y0. We need
two IC7485s each one comparing 4 bits. The most significant bits (suffix 7 ,6,5,4) are
given higher; priority and the final output is taken from that IC 7485 which compares them.

PROGRAMMABLE LOGIC DEVICES (PLDs):

A programmable logic device (or PLD) is a general name for a digital integrated
circuit capable of being programmed to provide a variety of different logic functions.
PLDs are electronic components, used to build reconfigurable digital circuits.
Programmable Read Only Memory (PROM), Programmable Array Logic (PAL),
and Programmable Logic Array (PLA) are included in the general classification.

Programmable Logic Arrays (PLA):

A PLA with n inputs and m outputs (see the following Figure) can realize m functions
of n variables. In PLA, the product terms of the input variables is realized by an AND
array; and the OR array ORs together the product terms needed to form the output
functions. Hence, a PLA implements a sum-of-products expression.

Example: Realize the following functions using PLA:

F0 = ∑m (0, 1, 4, 6) = A’B’ + AC’ F1 = ∑m (2, 3, 4, 6, 7) = B + AC’
F2 = ∑m (0, 1, 2, 6) = A’B’ + BC’ F3 = ∑m (2, 3, 5, 6, 7) = AC + B
Solution: The following Figure shows a PLA which realizes the said functions.
Product terms are formed in the AND array by connecting switching elements at
appropriate points in the array. For example, to form A’B’, switching elements are
used to connect the first word line with the A’ and B’ lines.

Switching elements are connected in the OR array to select the product terms needed
for the output functions. For example, because F0 = A’B’ + AC’, switching elements
are used to connect the A’B’ and AC’ lines to the F0 line.
The connections in the AND and OR arrays of this PLA make it equivalent to the AND-OR
array shown in the following Figure.

The contents of a PLA can be specified by a PLA table. The following Table specifies
the PLA shown in the above Figure. The input side of the table specifies the product
terms. The symbols 0, l, and – indicate whether a variable is complemented, not

complemented, or not present in the corresponding product term. The output side of
the table specifies which product terms appear in each output function. A 1 or 0
indicates whether a given product term is present or not present in the corresponding
output function. Thus, the first row of Table indicates that the term A’B’ is present in
output functions F0 and F2, and the second row indicates that AC’ is present in F0
and F1.

Example: Realize the following functions using PLA:

𝑓1 = 𝑎′ 𝑏𝑑 + 𝑎𝑏𝑑 + 𝑎𝑏′ 𝑐′ + 𝑏′𝑐
𝑓2 = 𝑐 + 𝑎′𝑏𝑑
Solution: Based on the given expressions, we can construct a PLA table (see Figure (a)),
with one row for each distinct product term. Figure (b) shows the corresponding PLA
structure, which has four inputs, six product terms, and three outputs. A dot at the
intersection of a word line and an input or output line indicates the presence of a
switching element in the array.

NOTE: Mask-programmable and field-programmable PLAs are available. The

mask-programmable type is programmed at the time of manufacture. The field-
programmable logic array (FPLA) has programmable interconnection points that use
electronic charges to store a pattern in the AND and OR arrays.

Problem: Design a PLA to recognize each of the 10 decimal digits represented in

binary form and to correctly drive a 7-segment display.

Solution: The PLA must have 4 inputs, as shown in the following Fig. Four bits are
required to represent the 10 decimal numbers. There must be 7 outputs (abcdefg).

The circuit given in the following Figure shows the links after programming. The
input AND-gate array is programmed such that, each AND gate decodes one of the
decimal numbers. Then, links are removed from the output OR-gate array, such that
proper segments of the indicator are illuminated. For example, when ABCD =
LHLH, segments afgcd are illuminated to display the decimal number 5.

Programmable Array Logic (PAL):

A PAL is a special case of the programmable logic array (PLA) in which the AND
array is programmable and the OR array is fixed. The following Figure represents a
segment of an un-programmed PAL.

Consider the PAL segment of the following Figure (a), used to realize the function
𝐼1𝐼′2 + 𝐼′1𝐼2. The X’sin the following Figure (b) indicate that 𝐼1 𝑎𝑛𝑑 𝐼′2 lines are
 connected to the first AND gate, and the
𝐼′1𝑎𝑛𝑑 𝐼2 lines are connected to the other gate.

Example: Implement Full Adder using PAL. Solution: The logic equations for the full
adder are:
𝑆𝑢𝑚 = 𝑋′ 𝑌′ 𝐶𝑖𝑛 + 𝑋′ 𝑌𝐶′ 𝑖𝑛 + 𝑋𝑌′ 𝐶′ 𝑖𝑛 + 𝑋𝑌𝐶𝑖𝑛
𝐶𝑜𝑢𝑡 = 𝑋𝑌 + 𝑌𝐶𝑖𝑛 + 𝑋𝐶𝑖𝑛
The following Figure shows PAL where each OR gate is driven by four AND gates.
The X’s on the diagram show the connections that are programmed into the PAL to
implement the full adder equations.

Problem: Generate the following Boolean function using PAL.

𝑌3 = 𝐴̅ 𝐵𝐶̅ 𝐷 + 𝐴̅ 𝐵𝐶𝐷
̅ + 𝐴̅𝐵𝐶𝐷 + 𝐴𝐵𝐶𝐷
̅
𝑌2 = 𝐴̅ 𝐵𝐶𝐷
̅ + 𝐴̅𝐵𝐶𝐷 + 𝐴𝐵𝐶𝐷
𝑌1 = 𝐴̅𝐵𝐶̅ + 𝐴̅ 𝐵𝐶 + 𝐴𝐵̅ 𝐶 + 𝐴𝐵𝐶̅
𝑌0 = 𝐴𝐵𝐶𝐷
Solution: Start with first equation. The first desired product is A’BC’D, which is
marked as shown in the following Figure. The fixed OR connections on the output
side imply that the first OR gate produces an output of first equation.
Implementation of Data Processing Circuits
2:1 MUX Data Flow

2:1 MUX Behavioral

4:1 MUX

1:4 DMUX
module demuxlto4(S,D,Y);
input (1:0J S;
input D;
output [3 : 0] Y;
reg [3:0] Y;
always @ (S or D)
case ( { D,S}}
3'b100 : Y= 4'b0001;
3'b101 : Y= 4'b0010;
3'b110 : Y=4’b0100;;
3'b111 : Y= 4'b1000;
default: Y= 4'b0000;
endcase
endmodule

module arithmetic_operators;
reg signed [4:0] a, b, res;
reg signed [6:0] mul_res;
real a1;
real div_res;

initial begin
a = 5'd5;
b = 5'd9;
a1 = 5;

res = a + b;
$display("%0d + %0d = %0d", a, b, res);

res = a - b;
$display("%0d - %0d = %0d", a, b, res);

mul_res = a * b;
$display("%0d * %0d = %0d", a, b, mul_res);

res = a / b;
$display("%0d / %0d = %0d (in integer)", a,
b, res);

div_res = a / b; // This will output

integer value as both the operands are integer
div_res = a1 / b; // This will output real
value as one of the operands (a1 is real)
$display("%0d / %0d = %f (in real)", a, b,
div_res);
 $display("%0d / %0d = %f (in real)", a1, b,
div_res);

res = b % a;
$display("%0d %% %0d = %0d", b, a, res);
end
endmodule

module alu(
input [7:0] A,B, // ALU 8-bit Inputs
input [3:0] ALU_Sel,// ALU Selection
output [7:0] ALU_Out, // ALU 8-bit Output
output CarryOut // Carry Out Flag
);
reg [7:0] ALU_Result;
wire [8:0] tmp;
assign ALU_Out = ALU_Result; // ALU out
assign tmp = {1'b0,A} + {1'b0,B};
assign CarryOut = tmp[8]; // Carryout flag
always @(*)
begin
case(ALU_Sel)
4'b0000: // Addition
ALU_Result = A + B ;
4'b0001: // Subtraction
ALU_Result = A - B ;
4'b0010: // Multiplication
ALU_Result = A * B;
4'b0011: // Division
ALU_Result = A/B;
4'b0100: // Logical shift left
ALU_Result = A<<1;
4'b0101: // Logical shift right
ALU_Result = A>>1;
4'b0110: // Rotate left
ALU_Result = {A[6:0],A[7]};
4'b0111: // Rotate right
ALU_Result = {A[0],A[7:1]};
4'b1000: // Logical and
ALU_Result = A & B;
 4'b1001: // Logical or
ALU_Result = A | B;
4'b1010: // Logical xor
ALU_Result = A ^ B;
4'b1011: // Logical nor
ALU_Result = ~(A | B);
4'b1100: // Logical nand
ALU_Result = ~(A & B);
4'b1101: // Logical xnor
ALU_Result = ~(A ^ B);
4'b1110: // Greater comparison
ALU_Result = (A>B)?8'd1:8'd0 ;
4'b1111: // Equal comparison
ALU_Result = (A==B)?8'd1:8'd0 ;
default: ALU_Result = A + B ;
endcase
end

endmodule

testbench module

`timescale 1ns / 1ps

module tb_alu;
//Inputs
reg[7:0] A,B;
reg[3:0] ALU_Sel;

//Outputs
wire[7:0] ALU_Out;
wire CarryOut;
// Verilog code for ALU
integer i;
alu test_unit(
A,B, // ALU 8-bit Inputs
ALU_Sel,// ALU Selection
ALU_Out, // ALU 8-bit Output
CarryOut // Carry Out Flag
);
 initial begin
// hold reset state for 100 ns.
A = 8'h0A;
B = 4'h02;
ALU_Sel = 4'h0;

for (i=0;i<=15;i=i+1)
begin
ALU_Sel = ALU_Sel + 8'h01;
#10;
end;

A = 8'hF6;
B = 8'h0A;

end
endmodule