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Matrices and Calculus Numerical Methods -
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- MA3151 MA3251
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4th Semester
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Signals and Systems - Circuits - EC3451

Engineering Physics - Engineering Graphics
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Systems - EC3491
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GE3151 Digital Systems Design Sustainability -
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Wireless
Communication -
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VLSI and Chip Design
5th Semester

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and Machine Learning
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 All ECE Engg Subjects - [ B.E., M.E., ] (Click on Subjects to enter)
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Processes Differential Equations Engineering
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Problem Solving and Python Object Oriented Programming Environmental Science
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Principles of Management Technical English Total Quality
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Engineering II
4931_Grace College of Engineering, Thoothukudi

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING

B.E. Electronics and Communication Engineering

Anna University Regulation: 2021

EC3552 – VLSI and Chip Design

III Year / V Semester

Hand Written Notes

Unit – V
ASIC Design and Testing
Prepared by,
Mrs. S. Pricilla Mary, AP/ECE

EC3552_VLSI and Chip Design

Page 1 of 16 www.BrainKart.com
 ONIT- V
4931_Grace College of Engineering, Thoothukudi

DESIG N ANO TE STI N G

Toroductoh: Applícatron Sperítre Tntoqratod

deaiqned
1oted elcuit (7)
cícuît
funciton fo a specific
to provm a specitie
applicaton.
Aevels Oß Tnteqvatton
inteqsaffon ar o
The levels oß
Small Scale Iotoqratict
Medium Scale înte qrafton
MST -

-
Scale
ntegsoiror
Scale Toteq iatron
VhST -

Very Arge
scale Inteqratfen
Implenentato dechnotoq4
Transis tos Transísto
kogic
- Fmi tten Coupled kogie
Somí conductoy (Nos,
Meral Ox(de
CK)os)
gpes o$ AstC
ot low s.
The AslCs are ctassit'ed ar
() Fall cachD ASICs

ASiCs CeBiC)
* Standand colt Based
(MP6r4)
Gato Avy aq
EC3552_VLSI and Chip Design d) Channeled Gate Aiva
(b) chonnet
Page 2 of 16 (os Grate Anaq
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 Array
sthuctured erat
(c)
4931_Grace College of Engineering, Thoothukudi

Programnable
ASIC9
Devic s
Programnable kog'
(h tormplex Arro
1ammable iate
() Fold. Prcg
Pooq (FPGA)

Full ugtom ASIO

engineor can desiqn

* Tn yut! Custom sIt,
ASIC,

so thníq4e
knoen as Faf! cushom ASIC

Engine usuSes mixed analoq and digial

d chniq ce to manufacturo I(. Al me
ASC.
Cetls QT0 Spec«fYco ley de:tqned for one
Use c§ bipolar chnotogy:
componente
auach ts ttcs cß bipola
* The ch
Same IC r natched Very

maBched oetf.
díkßerernt 1C Qre not
Use o CMOS:

thls is twidel used

manugactare 10

of analog and diqitat functen

aechnctoqy sutr:
sufts uetl.
Oesignes S qive ipos tance to pe jeunm
When Jaqe vo lume is
oveall cost wtl b Qducod
manufactucd
EC3552_VLSI and Chip Design

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 quatity
quarry importart So bis
sis impoytant
ouDe3
4931_GraceSupe
conpureT,
College of Engineering, Thoothukudi
implemented
design is fna fall custom ASIC
Al! nask lagere
Out alt ce ts by hand
he designer laqs
Generally, ement and routtng may be
autvmatC þlaC
&omo
laid out
are usualiy
d one
críffcal t tirni ng) parhs
conopletetyg by hand hiqhest pergostnance
Pe
he
custordeaiqn ofters
Full -custom

Cost Bo a qiver dexiqn.

and lowest past
the dísadvantaqes
increa Sod
des ign
expense, and highest oisk
castorm,but
complexfty des ign exclusivelq tu ll
IO Semícuso m
Nicoop90cessot8
qre inc QQAingl UTning
as we (l.
designeos in uhís
ae a
ASIC techniques
ASC's
Seni CUetom

Cell based deaign ANOgare,

() Standad eBeed to
gtandad cells ae etc.
NOR

9ate,muttiplexea
OR be used w?rs 2arqe
Shandad cetls can
prede ined cetls. le ve)
design
approa ch Standaidixes
This
at eogíc qate genenatcd
e1a tod a uforma fYalf
Adesign is
ianguage

EC3552_VLSI and Chip Design

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 In sianhud ool
is (reote d
4931_Grace doyout
x ThenCollege
dayout
of Engineering, Thoothukudi

Cells a0 píared in 200S,

outng channei
konhtal boghte
byass ove in
tetle in
Al tetle in ibra vantod Jb OCotnodoto
con be

yor vanio tton s fn complexits borooon e

a300 is alotted
*A SubstanHal 10ctot cf

ignor eutng overh00d ir

ínimixaton ct îptor cchneth
* The Standaxd cell porement
most inpotant qoa
ng tools It is dono b
dittorort
By using tood rough rdl, cel ls in
ows Can be Conhectod veHcal 0utng
deng ct cuine is Teduced by tocd
collg

CBIC'

Cett Based ASICs

mirod.
X At! he mask iayere of eBic ae Custo
* T a(loos mnog a colls (SRA M, MPFG, decodes ete)

to be placed
(addo, qas etc)
Mega colls ar0 supplioa by AsiC Corpany
cata path Jogic neans ahe 1ogc that opats
o mulple uiqnals a data bas

prorido
data patfh compiler cohich autbrnattca llcq qeneyato
data pot dcgic
EC3552_VLSI and Chip Design

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 Dota path Pibia4 Contane rotle Piko addor d
4931_Grace College of Engineering, Thoothukudi

mulkplex e3, Siple ALUs

tobuch
1ibn4 Covpang oovdo data trok
ASie
deciptron
has tuncitcna
’Colls

’ RouHng chonne
Cofls
Fed thaough
functtonalmodulo

( RAM,

Feature:
basod
ASC (CB1e - "sea-bick")
Cell
JE fs a standad Cotl ig
Standaud cells.
It has
elemornts used CMo technotogfunchorns, tull cUstorn
bocH s,
cells ,mega Co0c
PRes ibly mega (sMs *eO bocks,
ma CyDs
Qustorm- lorel Blaks CESB
c)
vansistTe and
Stardaid
Funcfo)al customiged -
* All )ask doyers
30u irg.
intercohnoct placement Qnd
aizing,
Auormated bu8fea
* be ennbedded
blocks can
And cus torn
Cellein

Cel!

Fixod
block s

boomm
EC3552_VLSI and Chip Design

Page 6 of 16 www.BrainKart.com
Gate Annag
4931_Grace CollegeBas
Based ASICe
of Engineering, Thoothukudi

In GA tyarnaistors aye
based ASiC, Ibo
thÍ sttccon waße?.
Base oy: the predszone d pattern ot trg
qate is known as bage a00y JYonsishr
eplica ted t mako uthe base is knoon
base cell Cor) primitrvo cell
Toterconncct is do fin ed
Oy uingtop tow Jayess f metal.
* This type ot qate
orag
maska gafe aroy
ie provide d by Asic

tompany
the choose

Tho s e

known
's game fo Qa ch

But inrerc on oct s

GrBßused array
TA g also calle Gas PPe-
becaus e he Tansistors ave digtused at rst
Proqiammable Gate
Types Arsays
Channded Giato Avvoy
Channel test Gore Aooag
Structuned Gato
EC3552_VLSI and Chip Design Avra4
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Page 7 of 16
 ta) channeled Giate
ATva
4931_Grace College of Engineering, Thoothukudi
is similar CBIC (Coll based ASI C)
Tt

* Sn the bo t) ype,
chonnele. Thege channels an usod
sepasared by tor

oß cetle is kxed in a
Space
But paco betweorn 0wS of
a?004
cha nnelod qate
cetts mag be
adjusrod

Foatuses
customdxo d
V only pa ces
otorcon nect uses pre dot tned
The
baue Cells
between

Manufactuinq
and

lsasecel|

Ro cws
basical/

Channel Gate Avay

EC3552_VLSI and Chip Design

Page 8 of 16 www.BrainKart.com
 Channa tess Grgte Ara04
4931_Grace College of Engineering, Thoothukudi

channel flee GA
T is aleo called as

bottwe ern
Top gew
inteconnect ConecHons

devices

Achtevo ble toqe derai i higher

tDan

foo channeled gat anays

* Each Joqre in a gore ar1ay
Hred
pedtsigned using base cel/
known

base J

base cbtis
(not a
Shan)

Channoled and channeless gare arsay s may

eirhe ate soia hcrn (or )Oxide igcfat on,
Tsotato Jhe nanaisos on a
gate avay
anotte Rithen corth uhick tretd oxrdo oy byusing
otfe .rtansiciots fhat ane wi0d Pernanenrty of
EC3552_VLSI and Chip Design

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Page 9 of 16
 shuctured
(O 4931_Grace Grate Araq
College of Engineering, Thoothukudi
calod as

embe cided gare oo

înnge gare. of (Be
TH Combnos somO o the ea tues
(N2GA).
and Oshed gare aia
is usod or
erobedood
nnonta Hon ct pecia tly deatqned
irpple
bl oc k diß8erent
Can cottatn a
SEpbedde d aTea efrhe
suttable tor building
base cetl is moso eincuit block,
a (ormple to
meme amicocontoollo
Quch as

Spece'a l eaares
ue
enly Can bo embedded
doad fme is
anugaciutng

is increased

Pßorman co is inereaspd cw?rh doo cast

Disadv.
ermbedded kunctton is tixe d,
The
3Qbit morDo rU
for ex: ? pmb ddod block har

But e custorn0 necds onlq

mernor cwarte
Gnbdded
bloc

EC3552_VLSI and Chip Design aot:

Page 10 of 16 www.BrainKart.com
 flow / tytle
4931_Grace College of Engineering, Thoothukudi

hardcae

iet aiphon donsquage

cchemalt ont4
syniesie Produtes a ntisl
(8Agie Cellg andthelg connedtfCht

(6 system p tironig bivide adaqe sytton, a

ino AsI( - sizo d piece:

Paciaqcut

fiociplanning
o the
Anange
netlot cn the chip
blocke

6) Placenucnt Oecicde the tocatto)s oß

(ells n q block

Rautng Cetls and blocks

Connechons betweon

ExtacHcn: Deteine tie esistane and

Capacitance os the inteTConnect

Post ayout 3igutaten - check to Ser ihe

deaign ghll uorK
Qoads oß the nter conne ct

EC3552_VLSI and Chip Design

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Page 11 of 16
 4931_Grace College of Engineering, Thoothukudi
Stast

eirulatto

loqie
synthess

3ystern

flooy
PBt foyout| plonning
siruidron

PlatenMent

Circui r
vouhing
extachu
qinish

ls ute Key part cß AS |C

the cett trbrar9

design For a proqrarmMable AgLC the FPGA Company

Supp lie9 a doqi

desiqn
Kit
have thee chofco
For MGAS and tcs you
CIBICS

EC3552_VLSI and Chip Design

Page 12 of 16 www.BrainKart.com
 ASIC Ytndoy will supp
4931_Grace College of Engineering, Thoothukudi

qeu can buy

buy a cen ibra14 grcm a mir
ponty atbaq endoy.you Can buid
yog

Tho ist cheite ng an AsiC

aibiass. eqgines
tools opprcved by
yeu vendo
the ASiC
Dte
and
timulate yeu desiq:
SOme ASLC ven dos Suppls tcolg thot
supply
have cde veloped inen house

vendon aibrany is noTma lly

phantm uibray rte cell! Q70 empty þoxes
phantoms, but (ontain
ehouq h ingormahon tor
dayout
A{fe you tomplete Jayout ou hácl ot

The sec cnd and shird chci cog 00Cuise

makí ng a buy to) build decicicn
AStC

tett sibiar4 ehat yeu bought, qou aso

tsed to sk manua Ctux
ASIC This is called custorney ownod

tool nq

EC3552_VLSI and Chip Design

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Page 13 of 16
 yound cnly pooví des manugactuni nq,
4931_Grace College of Engineering, Thoothukudi

deaign holp T8 ho retl Qibrarg mets tne

goundy speifitatrions, o toll is a qualigied
cell aibrasy
The od choire is o develop a

in hotuse Mang lage compute v and electotri

companies makes Ris chotco

COvtains
Each aib vavy may co
(6 APmysicoal layeutmode t
behavioual
A
VHOL mode|
(íto A veíloq
fming model s
(ív) Oe tailec
() Aresr strare9
schena(ie
(V) A cícuiF

load mode
( Vis) A wrse
(wí) A r0UH

M'cro chip ces t'g rocesr.

the Tequi'temotr
Specitaiter) In ths staqe,
and ihe mi'c ochip ave dettned.

work closety
Ctosely with &takehotdos&
&

uhderstand he applicatto ang Petoman (e

EC3552_VLSI and Chip Design

Page 14 of 16 www.BrainKart.com
Achi te chune Detgn
4931_Grace College of Engineering, Thoothukudi

architeckuno ?.
chighlevet
The chip':
ctevetepe d. inluding a0d oveall Ryttern
(omponeote,
deffring
do he chip:
0 srgn. his stoqt (cuses cD
difteent cormponenr wiy
guncttenality and hcuw
intenatt

The Rrgisren Tans to o

kevel (ATL)
desigo
using
is C72atod degin ing rte chtp's behavi our
haidwau daxriplion language Aike Veri logo)
RTL kRsigo yorms the bavit
yor at
Sraqes
Functi oDal verit(ca tt'orn!
Thp RT Ceaign ie xtens ively testecd to

ensuTp it be haves as intonded .,Vaíous

vei fícaton techni quer, Such CUs simulato,
Ronal vertgtcatton and hasdwoue emuloHo
employed o Carch duign bugu and
issues

aunthexis and rhystet dugn

the Rru code co yn hes'od info a
lovel noHrst, whrch Tep0sentg mo chip's gaie
iropleme otat'on The
Phguta phyicat deaigr phan
involves tlos plonning placement, outrng.
Qnd opimixat'c)
EC3552_VLSI and Chip Design tD eet minq and nrea
consha?nfs
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Page 15 of 16
 College Testabîttq
4931_GraceBer
Cesigo (or
of Engineering, Thoothukudi

toch n'cques iko SCan choins,

Choios buitf in golt
are addod
Test guctuses, and and bound ouy
to make he chip testo ble duinq manutachaing
and

NNanugactun ng
a sormiconducho r
Sorrt
The gnal dean is
înrolOs

goundry OD tabi cort oh

This pI0CeSs

and orbes stops to Cr0are

pheo.aiho gapy
actual giticon chíp

Tesing and &ualf

Agres manugacfurínq. e chips undeoqo
Vasious estnq merhodotog ie o
ensu rO mey
speciícafan and ase 8oee
dezted
rom defects

EC3552_VLSI and Chip Design

Page 16 of 16 www.BrainKart.com
 Click on Subject/Paper under Semester to enter.
Random Process and Electromagnetic
Professional English Linear Algebra -
Professional English - - II - HS3252 Fields - EC3452
MA3355
I - HS3152
C Programming and Networks and
Statistics and
Data Structures - Security - EC3401
Matrices and Calculus Numerical Methods -
CS3353
- MA3151 MA3251
1st Semester

3rd Semester

Linear Integrated

4th Semester
2nd Semester

Signals and Systems - Circuits - EC3451

Engineering Physics - Engineering Graphics
- GE3251 EC3354
PH3151 Digital Signal
Processing - EC3492
Physics for Electronic Devices and
Engineering Chemistry Electronics Engg - Circuits - EC3353
- CY3151 PH3254 Communication
Systems - EC3491
Control Systems -
Basic Electrical & EC3351
Problem Solving and Instru Engg - BE3254 Environmental
Python Programming - Sciences and
GE3151 Digital Systems Design Sustainability -
Circuit Analysis - - EC3352 GE3451
EC3251

Wireless
Communication -
EC3501 Embedded Systems
and IOT Design -
ET3491
VLSI and Chip Design
5th Semester

- EC3552 Human Values and

7th Semester

8th Semester
6th Semester

Artificial Intelligence Ethics - GE3791

and Machine Learning
Transmission Lines and - CS3491
RF Systems - EC3551 Open Elective 2 Project Work /
Intership
Open Elective-1 Open Elective 3
Elective 1
Elective-4
Open Elective 4
Elective 2
Elective-5
Elective 3
Elective-6
 All ECE Engg Subjects - [ B.E., M.E., ] (Click on Subjects to enter)
Circuit Analysis Digital Electronics Communication Theory
Basic Electrical and Electrical Engineering and Principles of Digital
Instrumentation Engineering Instrumentation Signal Processing
Electronic Devices Linear Integrated Circuits Signals and Systems
Electronic Circuits I Electronic Circuits II Digital Communication
Transmission Lines and Wave Control System Engineering Microprocessors and
Guides Microcontrollers
Computer Architecture Computer Networks Operating Systems
RF and Microwave Engineering Medical Electronics VLSI Design
Optical Communication and Embedded and Real Time Cryptography and
Networks Systems Network Security
Probability and Random Transforms and Partial Physics for Electronics
Processes Differential Equations Engineering
Engineering Physics Engineering Chemistry Engineering Graphics
Problem Solving and Python Object Oriented Programming Environmental Science
Programming and Data Structures and Engineering
Principles of Management Technical English Total Quality
Management
Professional Ethics in Engineering Mathematics I Engineering Mathematics
Engineering II