Presented by: Dr. Mohd Hana Ahmad Hijazi FKI, Slides,UMS with minor modi cations, taken from William StallingsthComputer Organization and Architecture, 10 Edition + Chapter 5 Internal Memo – Pa 1 + Memo Cell Operation Semiconductor Memo Types
Table 5.1 Semiconductor Memo Types
+ Dynamic RAM (DRAM) RAM technology is divided into two technologies: Dynamic RAM (DRAM) Static RAM (SRAM) DRAM Made with capacitors cells that store data as charge on Presence interpreted or absence as a bina of 1charge (full in witha capacitor electrons) is or 0 (empty) Requires periodic charge storage through transistor refreshing to maintain data e term charge to dynamic leak away,refers even to tendency with power of the stored continuously Images by applied -Eric Schrader from San Francisco, CA, United States - 12739s, CC BY-SA 2.0, https: //commons.wikimedia.org/w/index.php?curid=37625896 -Transisto at English Wikipedia - Own work, CC BY-SA 3.0, ttps://commons.wikimedia.org/w/index.php? + Dynamic RAM Structure
Figure 5.2a Typical Memo Cell Structures + Static RAM (SRAM) Digital device that uses the same logic elements used in the
processor Bina values are stored using traditional ip- op logic gate
con gurations Will hold its data as long as power is supplied to it + Static RAM Structure
Figure 5.2b Typical Memo Cell Structures SRAM versus DRAM SRAM Both volatile Power must be continuously supplied to the memo to prese e the bit values
Dynamic cell DRAM Simpler to build, smaller More dense (smaller cells = more cells per unit area) Less expensive Requires the suppo ing refresh circuit Tend to be favored for large memo requirements +
Used for main memo
Static Faster Used for cache memo (both on and o chip) + Read Only Memo (ROM) Contains a permanent pattern of data that cannot be changed or added to
No power source is required to maintain the bit values in
memo
Data or program is permanently in main memo and never
needs to be loaded from a seconda storage device
Data is actually wired into the chip as pa of the fabrication
process
Disadvantages of this: No room for error, if one bit is wrong the whole batch of ROMs must be thrown out
Data inse ion step includes a relatively large xed cost
+ Programmable ROM (PROM) Less expensive alternative Nonvolatile and may be written into only once Writing process is pe ormed electrically and may be pe ormed by supplier or customer at a time later than the
original chip fabrication
Special equipment is required for the writing process Provides exibility and convenience Attractive for high volume production runs Read-Mostly Memo Flash EPROM EEPROM Memo Electrically erasable Intermediate between Erasable programmable read programmable read-only EPROM and EEPROM in both -only memo memo cost and functionality Can be written into at any time without erasing prior contents Uses an electrical erasing Erasure process can be technology, does not provide pe ormed repeatedly Combines the advantage of byte-level erasure non-volatility with the exibility of being updatable in place More expensive than PROM Microchip is organized so but it has the advantage of that a section of memo the multiple update More expensive than EPROM cells are erased in a single capability action or “ ash” Typical 16 Mb DRAM (4M x 4) Chip Packaging Figure 5.5
memo bank Each bank is independently able to se ice a memo read or write request Krequests banks can se ice K simultaneously, increasing memo read or write rates by a factor of K If consecutive words of memo are stored in di erent banks, the transfer of a block of memo is speeded up Advanced DRAM Organization SDRAM One of the most critical system bottlenecks when using high-pe ormance processors is the inte ace to main DDR-DRAM
internal memo e traditional DRAM chip is constrained both by its internal architecture and by its inte ace to the
processor’s memo bus
A number of enhancements to the basic DRAM architecture have been explored: RDRAM +
Table 5.3 Pe ormance Comparison of Some DRAM Alternatives
Synchronous DRAM (SDRAM) One of the most widely used forms of DRAM
RDRAM chips and is rated competitor to SDRAM at 1.6 GBps
Chips are ve ical packages
with all pins on one side • Exchanges data with the processor over 28 wires no more than 12 centimeters long + RDRAM Structure Data lines cycling twice the clock rate, at the rising and following edge of each clock signal + Double Data Rate SDRAM (DDR SDRAM) SDRAM can only send data once per bus clock cycle Double-data-rate SDRAM can send data twice per clock cycle, once on the rising edge of the clock pulse and once on the
falling edge Developed by the JEDEC Solid State Technology Association (Electronic Industries Alliance’s semiconductor-engineering-
Developed by Mitsubishi Integrates a small SRAM cache onto a generic DRAM chip SRAM on the CDRAM can be used in two ways: It can be used as a true cache consisting of a number of 64-bit lines
Cache mode of the CDRAM is e ective for ordina random
access to memo
Can also be used as a bu er to suppo the serial access of a
