UNIT-III

ARITHMATIC LOGIC CIRCUITS

Combinational Logic Design

Logic circuits for digital systems may be combinational or sequential. The output of a
combinational circuit depends on its present inputs only .Combinational circuit processing
operation fully specified logically by a set of Boolean functions .A combinational circuit consists
of input variables, logic gates and output variables.Both input and output data are represented by
signals, i.e., they exists in two possible values. One is logic –1 and the other logic 0.

For n input variables,there are 2n possible combinations of binary input variables .For
each possible input Combination ,there is one and only one possible output combination.A
combinational circuit can be described by m Boolean functions one for each output
variables.Usually the input s comes from flip-flops and outputs goto flip-flops.

Design Procedure:

1.The problem is stated

2. The number of available input variables and required output variables is determined.
3.The input and output variables are assigned letter symbols.
4.The truth table that defines the required relationship between inputs and outputs is derived.
5.The simplified Boolean function for each output is obtained.
6.The logic diagram is drawn.
Adders:

Digital computers perform variety of information processing tasks,the one is arithmetic

operations.And the most basic arithmetic operation is the addition of two binary digits.i.e, 4 basic
possible operations are:

0+0=0,0+1=1,1+0=1,1+1=10

The first three operations produce a sum whose length is one digit, but when augends and addend
bits are equal to 1,the binary sum consists of two digits.The higher significant bit of this result is
called a carry.A combinational circuit that performs the addition of two bits is called a half-
adder. One that performs the addition of 3 bits (two significant bits & previous carry) is called a
full adder.& 2 half adder can employ as a full-adder.

The Half Adder: A Half Adder is a combinational circuit with two binary inputs (augends and
addend bits and two binary outputs (sum and carry bits.) It adds the two inputs (A and B) and
produces the sum (S) and the carry (C) bits. It is an arithmetic operation of addition of two single
bit words.

The Sum(S) bit and the carry (C) bit, according to the rules of binary addition, the sum (S) is the
X-OR of A and B ( It represents the LSB of the sum). Therefore,

S=A𝐵+𝐴B=

The carry (C) is the AND of A and B (it is 0 unless both the inputs are 1).Therefore,

C=AB

A half-adder can be realized by using one X-OR gate and one AND gate a

Logic diagrams of half-adder

NAND LOGIC:

NOR Logic:

The Full Adder:

A Full-adder is a combinational circuit that adds two bits and a carry and outputs a sum
bit and a carry bit. To add two binary numbers, each having two or more bits, the LSBs can be
added by using a half-adder. The carry resulted from the addition of the LSBs is carried over to
the next significant column and added to the two bits in that column. So, in the second and
higher columns, the two data bits of that column and the carry bit generated from the addition in
the previous column need to be added.

The full-adder adds the bits A and B and the carry from the previous column called the
carry-in Cin and outputs the sum bit S and the carry bit called the carry-out Cout . The variable S
gives the value of the least significant bit of the sum. The variable Cout gives the output carry.The
eight rows under the input variables designate all possible combinations of 1s and 0s that these
variables may have. The 1s and 0s for the output variables are determined from the arithmetic
sum of the input bits. When all the bits are 0s , the output is 0. The S output is equal to 1 when
only 1 input is equal to 1 or when all the inputs are equal to 1. The C out has a carry of 1 if two or
three inputs are equal to 1.

From the truth table, a circuit that will produce the correct sum and carry bits in response to
every possible combination of A,B and Cin is described by

S  A B Cin  A BC in  AB C in  ABC in
Cout  A BCin  AB Cin  ABC in  ABC in

and
S  A  B  Cin
Cout  ACin  BCin  AB

The sum term of the full-adder is the X-OR of A,B, and Cin, i.e, the sum bit the modulo
sum of the data bits in that column and the carry from the previous column. The logic diagram
of the full-adder using two X-OR gates and two AND gates (i.e, Two half adders) and one OR
gate is
Even though a full-adder can be constructed using two half-adders, the disadvantage is that the
bits must propagate through several gates in accession, which makes the total propagation delay
greater than that of the full-adder circuit using AOI logic.

The Full-adder neither can also be realized using universal logic, i.e., either only NAND gates or
only NOR gates as

NAND Logic:
NOR Logic:

Subtractors:

The subtraction of two binary numbers may be accomplished by taking the complement
of the subtrahend and adding it to the minuend. By this, the subtraction operation becomes an
addition operation and instead of having a separate circuit for subtraction, the adder itself can be
used to perform subtraction. This results in reduction of hardware. In subtraction, each
subtrahend bit of the number is subtracted from its corresponding significant minuend bit to form
a difference bit. If the minuend bit is smaller than the subtrahend bit, a 1 is borrowed from the
next significant position., that has been borrowed must be conveyed to the next higher pair of
bits by means of a signal coming out (output) of a given stage and going into (input) the next
higher stage.

The Half-Subtractor:

A Half-subtractor is a combinational circuit that subtracts one bit from the other and
produces the difference. It also has an output to specify if a 1 has been borrowed. . It is used to
subtract the LSB of the subtrahend from the LSB of the minuend when one binary number is
subtracted from the other.

A Half-subtractor is a combinational circuit with two inputs A and B and two

outputs d and b. d indicates the difference and b is the output signal generated that informs the
next stage that a 1 has been borrowed. When a bit B is subtracted from another bit A, a
difference bit (d) and a borrow bit (b) result according to the rules given as
The output borrow b is a 0 as long as A≥B. It is a 1 for A=0 and B=1. The d output is the result
of the arithmetic operation 2b+A-B.

A circuit that produces the correct difference and borrow bits in response to every possible
combination of the two 1-bit numbers is , therefore ,

d=A𝐵+𝐴B= and b=𝐴B

That is, the difference bit is obtained by X-OR ing the two inputs, and the borrow bit is obtained
by ANDing the complement of the minuend with the subtrahend.Note that logic for this exactly
the same as the logic for output S in the half-adder.

A half-substractor can also be realized using universal logic either using only NAND gates or
using NOR gates as:

NAND Logic:

NOR Logic:
The Full-Subtractor:

The half-subtractor can be only for LSB subtraction. IF there is a borrow

during the subtraction of the LSBs, it affects the subtraction in the next higher column; the
subtrahend bit is subtracted from the minuend bit, considering the borrow from that column used
for the subtraction in the preceding column. Such a subtraction is performed by a full-subtractor.
It subtracts one bit (B) from another bit (A) , when already there is a borrow b i from this column
for the subtraction in the preceding column, and outputs the difference bit (d) and the borrow
bit(b) required from the next d and b. The two outputs present the difference and output borrow.
The 1s and 0s for the output variables are determined from the subtraction of A-B-bi.

From the truth table, a circuit that will produce the correct difference and borrow bits in response
to every possiblecombinations of A,B and bi is

A full-subtractor can be realized using X-OR gates and AOI gates as

The full subtractor can also be realized using universal logic either using only NAND gates or
using NOR gates as:

NAND Logic:

NOR Logic:
Binary Parallel Adder:

A binary parallel adder is a digital circuit that adds two binary numbers in parallel form
and produces the arithmetic sum of those numbers in parallel form. It consists of full adders
connected in a chain , with the output carry from each full-adder connected to the input carry of
the next full-adder in the chain.

The interconnection of four full-adder (FA) circuits to provide a 4-bit parallel adder. The
augends bits of A and addend bits of B are designated by subscript numbers from right to left,
with subscript 1 denoting the lower –order bit. The carries are connected in a chain through the
full-adders. The input carry to the adder is Cin and the output carry is C4. The S output generates
the required sum bits. When the 4-bit full-adder circuit is enclosed within an IC package, it has
four terminals for the augends bits, four terminals for the addend bits, four terminals for the sum
bits, and two terminals for the input and output carries. AN n-bit parallel adder requires n-full
adders. It can be constructed from 4-bit, 2-bit and 1-bit full adder ICs by cascading several
packages. The output carry from one package must be connected to the input carry of the one
with the next higher –order bits. The 4-bit full adder is a typical example of an MSI function.

Ripple carry adder:

In the parallel adder, the carry –out of each stage is connected to the carry-in of
the next stage. The sum and carry-out bits of any stage cannot be produced, until sometime after
the carry-in of that stage occurs. This is due to the propagation delays in the logic circuitry,
which lead to a time delay in the addition process. The carry propagation delay for each full-
adder is the time between the application of the carry-in and the occurrence of the carry-out.

The 4-bit parallel adder, the sum (S1) and carry-out (C1) bits given by FA1 are not valid, until
after the propagation delay of FA1. Similarly, the sum S2 and carry-out (C2) bits given by FA2 are
not valid until after the cumulative propagation delay of two full adders (FA1 and FA2) , and so
on. At each stage ,the sum bit is not valid until after the carry bits in all the preceding stages are
valid. Carry bits must propagate or ripple through all stages before the most significant sum bit is
valid. Thus, the total sum (the parallel output) is not valid until after the cumulative delay of all
the adders.

The parallel adder in which the carry-out of each full-adder is the carry-in to the next most
significant adder is called a ripple carry adder.. The greater the number of bits that a ripple carry
adder must add, the greater the time required for it to perform a valid addition. If two numbers
are added such that no carries occur between stages, then the add time is simply the propagation
time through a single full-adder.

4-Bit Parallel Subtractor:

The subtraction of binary numbers can be carried out most conveniently by means of
complements , the subtraction A-B can be done by taking the 2‘s complement of B and adding
it to A . The 2‘s complement can be obtained by taking the 1‘s complement and adding 1 to the
least significant pair of bits. The 1‘s complement can be implemented with inverters as

Binary-Adder Subtractor:

A 4-bit adder-subtractor, the addition and subtraction operations are combined into
one circuit with one common binary adder. This is done by including an X-OR gate with each
full-adder. The mode input M controls the operation. When M=0, the circuit is an adder, and
when M=1, the circuit becomes a subtractor. Each X-OR gate receives input M and one of the
inputs of B. When M=0, .The full-adder receives the value of B , the input carry is 0
and the circuit performs A+B. when M=1, and C1 =1. The B inputs are complemented
and a 1 is through the input carry. The circuit performs the operation A plus the 2‘s complement
of B.

The Look-Ahead –Carry Adder:

In parallel-adder,the speed with which an addition can be performed is governed by

the time required for the carries to propagate or ripple through all of the stages of the adder. The
look-ahead carry adder speeds up the process by eliminating this ripple carry delay. It examines
all the input bits simultaneously and also generates the carry-in bits for all the stages
simultaneously.

The method of speeding up the addition process is based on the two additional
functions of the full-adder, called the carry generate and carry propagate functions.

Consider one full adder stage; say the nth stage of a parallel adder as shown in fig.
we know that is made by two half adders and that the half adder contains an X-OR gate to
produce the sum and an AND gate to produce the carry. If both the bits A n and Bn are 1s, a carry
has to be generated in this stage regardless of whether the input carry Cin is a 0 or a 1. This is
called generated carry, expressed as Gn= An.Bn which has to appear at the output through the OR
gate as shown in fig.

Thereis another possibility of producing a carry out. X-OR gate inside the half-adder

at the input produces an intermediary sum bit- call it Pn –which is expressed as .

Next Pn and Cn are added using the X-OR gate inside the second half adder to produce the final
sum bit and and output carryC0= Pn.Cn=( )Cn which
becomes carry for the (n+1) th stage.

Consider the case of both Pn and Cn being 1. The input carry Cn has to be propagated
to the output only if Pn is 1. If Pn is 0, even if Cn is 1, the and gate in the second half-adder will
inhibit Cn . the carry out of the nth stage is 1 when either G n=1 or Pn.Cn =1 or both Gn and Pn.Cn
are equal to 1.

For the final sum and carry outputs of the nth stage, we get the following Boolean
expressions.

Observe the recursive nature of the expression for the output carry
at the nth stage which becomes the input carry for the (n+1)st stage .it is possible to express the
output carry of a higher significant stage is the carry-out of the previous stage.

Based on these , the expression for the carry-outs of various full adders are as follows,

Observe that the final output carry is expressed as a function of

the input variables in SOP form. Which is two level AND-OR or equivalent NAND-NAND
form. Observe that the full look-ahead scheme requires the use of OR gate with (n+1) inputs and
AND gates with number of inputs varying from 2 to (n+1).
2’s complement Addition and Subtraction using Parallel Adders:

Most modern computers use the 2‘s complement system to represent negative numbers
and to perform subtraction operations of signed numbers can be performed using only the
addition operation ,if we use the 2‘s complement form to represent negative numbers.

The circuit shown can perform both addition and subtraction in the 2‘s complement. This
adder/subtractor circuit is controlled by the control signal ADD/SUB‘. When the ADD/SUB‘
level is HIGH, the circuit performs the addition of the numbers stored in registers A and B.
When the ADD/Sub‘ level is LOW, the circuit subtract the number in register B from the number
in register A. The operation is:

When ADD/SUB‘ is a 1:

1. AND gates 1,3,5 and 7 are enabled , allowing B 0,B1,B2and B3 to pass to the OR gates
9,10,11,12 . AND gates 2,4,6 and 8 are disabled , blocking B0 ‘,B1‘,B2‘, and B3‘ from
reaching the OR gates 9,10,11 and 12.

2. The two levels B0 to B3 pass through the OR gates to the 4-bit parallel adder, to be added
to the bits A0 to A3. The sum appears at the output S0 to S3

3. Add/SUB‘ =1 causes no carry into the adder.

When ADD/SUB‘ is a 0:

1. AND gates 1,3,5 and 7 are disabled , allowing B0,B1,B2and B3 from reaching the OR
gates 9,10,11,12 . AND gates 2,4,6 and 8 are enabled , blocking B0‘,B1‘,B2‘, and B3 ‘
from reaching the OR gates.
 2. The two levels B0‘ to B3‘ pass through the OR gates to the 4-bit parallel adder, to be
added to the bits A0 to A3.The C0 is now 1.thus the number in register B is converted to
its 2‘s complement form.

3. The difference appears at the output S0 to S3.

Adders/Subtractors used for adding and subtracting signed binary numbers. In computers , the
output is transferred into the register A (accumulator) so that the result of the addition or
subtraction always end up stored in the register A This is accomplished by applying a transfer
pulse to the CLK inputs of register A.

BCD Adder:

The BCD addition process:

1. Add the 4-bit BCD code groups for each decimal digit position using ordinary binary
addition.

2. For those positions where the sum is 9 or less, the sum is in proper BCD form and no
correction is needed.

3. When the sum of two digits is greater than 9, a correction of 0110 should be added to
that sum, to produce the proper BCD result. This will produce a carry to be added to
the next decimal position.

A BCD adder circuit must be able to operate in accordance with the above steps. In other words,
the circuit must be able to do the following:

1. Add two 4-bit BCD code groups, using straight binary addition.
 2. Determine, if the sum of this addition is greater than 1101 (decimal 9); if it is , add 0110
(decimal 6) to this sum and generate a carry to the next decimal position.

The first requirement is easily met by using a 4- bit binary parallel adder such as the 74LS83
IC .For example , if the two BCD code groups A3 A2 A1A0and B3B2B1B0 are applied to a 4-bit
parallel adder, the adder will output S4S3S2S1S0 , where S4 is actually C4 , the carry –out of the
MSB bits.

The sum outputs S4S3S2S1S0 can range anywhere from 00000 to 100109when both the
BCD code groups are 1001=9). The circuitry for a BCD adder must include the logic needed to
detect whenever the sum is greater than 01001, so that the correction can be added in. Those
cases , where the sum is greater than 1001 are listed as:

Let us define a logic output X that will go HIGH only when the sum is greater than 01001
(i.e, for the cases in table). If examine these cases ,see that X will be HIGH for either of the
following conditions:

1. Whenever S4 =1(sum greater than 15)

2. Whenever S3 =1 and either S2 or S1 or both are 1 (sum 10 to 15)

This condition can be expressed as

X=S4+S3(S2+S1)

Whenever X=1, it is necessary to add the correction factor 0110 to the sum bits, and to
generate a carry. The circuit consists of three basic parts. The two BCD code groups A3A2 A1 A0
and B3B2B1B0 are added together in the upper 4-bit adder, to produce the sum S4S3S2S1S0. The
logic gates shown implement the expression for X. The lower 4-bit adder will add the correction
0110 to the sum bits, only when X=1, producing the final BCD sum output represented by
∑3∑2∑1∑0. The X is also the carry-out that is produced when the sum is greater than 01001.
When X=0, there is no carry and no addition of 0110. In such cases, ∑ 3∑2∑1∑0= S3S2S1S0.
 Two or more BCD adders can be connected in cascade when two or more digit decimal
numbers are to be added. The carry-out of the first BCD adder is connected as the carry-in of the
second BCD adder, the carry-out of the second BCD adder is connected as the carry-in of the
third BCD adder and so on.

EXCESS-3(XS-3) ADDER:

To perform Excess-3 additions,

1. Add two xs-3 code groups
2. If carry=1, add 0011(3) to the sum of those two code groups
If carry =0, subtract 0011(3) i.e., add 1101 (13 in decimal) to the sum of those two code
groups.
Ex: Add 9 and 5
1100 9 in Xs-3
+1000 5 in xs-3
_____________

1 0100 there is a carry

+0011 0011 add 3 to each group
---------- ----------
0100 0111 14 in xs-3
(1) (4)

EX:

Implementation of xs-3 adder using 4-bit binary adders is shown. The augend (A3
A2A1 A0) and addend (B3B2B1B0) in xs-3 are added using the 4-bit parallel adder. If the carry is a
1, then 0011(3) is added to the sum bits S 3S2S1S0 of the upper adder in the lower 4-bit parallel
adder. If the carry is a 0, then 1101(3) is added to the sum bits (This is equivalent to subtracting
0011(3) from the sum bits. The correct sum in xs-3 is obtained

Excess-3 (XS-3) Subtractor:

To perform Excess-3 subtraction,
1. Complement the subtrahend
2. Add the complemented subtrahend to the minuend.
3. If carry =1, result is positive. Add 3 and end around carry to the result . If carry=0, the
result is negative. Subtract 3, i.e, and take the 1‘s complement of the result.

Ex: Perform 9-4

1100 9 in xs-3
+1000 Complement of 4 n Xs-3
--------
(1) 0100 There is a carry
+0011 Add 0011(3)
------------
0111
1 End around carry
------------
1000 5 in xs-3

The minuend and the 1‘s complement of the subtrahend in xs-3 are added in the upper 4-
bit parallel adder. If the carry-out from the upper adder is a 0, then 1101 is added to the sum bits
of the upper adder in the lower adder and the sum bits of the lower adder are complemented to
get the result. If the carry-out from the upper adder is a 1, then 3=0011 is added to the sum bits
of the lower adder and the sum bits of the lower adder give the result.

Code converters:

The availability of a large variety of codes for the same discrete elements of
information results in the use of different codes by different digital systems. It is sometimes
necessary to use the output of one system as the input to another. A conversion circuit must be
inserted between the two systems if each uses different codes for the same information. Thus a
code converter is a logic circuit whose inputs are bit patterns representing numbers (or
character) in one cod and whose outputs are the corresponding representation in a different
code. Code converters are usually multiple output circuits.
To convert from binary code A to binary code B, the input lines must supply the bit
combination of elements as specified by code A and the output lines must generate the
corresponding bit combination of code B. A combinational circuit performs this transformation
by means of logic gates.
For example, a binary –to-gray code converter has four binary input lines B4, B3,B2,B1 and four
gray code output lines G4,G3,G2,G1. When the input is 0010, for instance, the output should be
0011 and so forth. To design a code converter, we use a code table treating it as a truth table to
express each output as a Boolean algebraic function of all the inputs.
In this example, of binary –to-gray code conversion, we can treat the binary to the
gray code table as four truth tables to derive expressions for G 4, G3, G2, and G1. Each of these
four expressions would, in general, contain all the four input variables B 4, B3,B2,and B1.
Thus,this code converter is actually equivalent to four logic circuits, one for each of the truth
tables.
The logic expression derived for the code converter can be simplified using the usual
techniques, including ‗don‘t cares‘ if present. Even if the input is an unweighted code, the same
cell numbering method which we used earlier can be used, but the cell numbers --must
correspond to the input combinations as if they were an 8-4-2-1 weighted code. s
Design of a 4-bit binary to gray code converter:
Design of a 4-bit gray to Binary code converter:
Design of a 4-bit BCD to XS-3 code converter:
Design of a BCD to gray code converter:

Design of a SOP circuit to Detect the Decimal numbers 5 through 12 in a 4-bit gray code
Input:

Design of a SOP circuit to detect the decimal numbers 0,2,4,6,8 in a 4-bit 5211 BCD code
input:
Design of a Combinational circuit to produce the 2’s complement of a 4-bit binary number:

Comparators:
1. Magnitude Comparator:

1- bit Magnitude Comparator:

4-Bit Magnitude Comparator:
 IC Comparator:

ENCODERS:

Octal to Binary Encoder:

Decimal to BCD Encoder:

Tristate bus system:

In digital electronicsthree-state, tri-state, or 3-statelogic allows an output port to assume a high

impedance state in addition to the 0 and 1 logic levels, effectively removing the output from the
circuit.

This allows multiple circuits to share the same output line or lines (such as a bus which cannot
listen to more than one device at a time).

Three-state outputs are implemented in many registers, bus drivers, and flip-flops in the 7400
and 4000 series as well as in other types, but also internally in many integrated circuits. Other
typical uses are internal and external buses in microprocessors, computer memory, and
peripherals. Many devices are controlled by an active-low input called OE (Output Enable)
which dictates whether the outputs should be held in a high-impedance state or drive their
respective loads (to either 0- or 1-level).
Multiplexers
A digital multiplexer (MUX) is a combinational circuits that selects one input out of
several inputs and direct it to a single output. The particular input selection is controlled by
a set of select inputs. Fig. 4.19 shows block diagram of a digital multiplexer with n inputs
lines and single output line.
For selecting one out of n input, a set of m select
inputs is required where
n = 2m
On the basis of digital (binary) code applied at the select
inputs, one output of n data sources is selected. Usually, an
enable (or strobe) input (E) is built-in for cascading purpose.
Enable input is generally active-low, i.e., it performs its in-
tended operation when it is low (logic).
Note. 16:1 are the largest available ICs, therefore for Fig. 4.19 Block diagram of the
larger input requirements there should be provision for digital multiplexer
expansion. This is achieved through enable/stroble input
(multiplexer stacks or trees are designed).
A circuit diagram for a possible 4-line to 1-line data selector/multiplexer (abbreviated as
MUX for multiplexer) is shown in Fig. 4.20. Here, the output Y is equal to the input I0, I1,
I2, I3 depending on whether the select lines S1 and S0 have values 00, 01, 10, 11 for S1 and
S0 respectively. That is, the output Y is selected to be equal to the input of the line given by
the binary value of the select lines S1S0.
The logic equation for the circuit shown in Fig. 4.20 is:
Y = I0 . S1 . S0 + I1 . S1 . S0 + I2 . S1 . S0 + I3 .S1 .S0
This device can be used simply as a data selector/multiplexer, or it can be used to
perform logic functions. Its simplest application is to implement a truth table directly, e.g.,

with a 4 line to 1 line MUX, it is possible to implement any 2-variable function directly, simply
by connecting I0, I1, I2, I3 to logic 1 in logic 0, as dictated by a truth table. In this way, a
MUX can be used as a simple look-up table for switching functions. This facility makes the
MUX a very general purpose logic device.

I0 I1 I2 I3
S1

S0

Fig 4.20 A four-line to 1-line multiplexer

Example 1. Use a 4 line to 1 line MUX to implement the function shown in the following
truth table (Y = A.B + A.B) .

A B Y 1 I0
0 0 1 = I0 0 I1
0 1 0 = I1 0 I2 Y
1 0 0 = I2 1 I3
1 1 1 = I3 S1 S0

A B

Fig. 4.21 A 4-line to 1-line MUX implementation of a function of 2 variables

 Simply connecting I0 = 1, I1 = 0, I2 = 0, I3 = 1, and the inputs A and B to the S1 and S0
selector inputs of the 4-line to 1-line MUX implement this truth table, as shown in Fig. 4.21.
The 4-line to 1-line MUX can also be used to implement any function of three logical
variables, as well. To see this, we need note only that the only possible functions of one
variable C, are C, C, and the constants 0 or 1. (i.e., C, C , C + C = 1, and 0). We need only
connect the appropriate value, C, C , 0 or 1, to I0, I1, I2, I3 to obtain a function of 3 variables.
The MUX still behaves as a table lookup device; it is now simply looking up values of another
variable.
Example 2. Implement the function

Y (A, B, C) = A.B.C + A.B. C + A. B. C + A.B.C

Using a 4-line to 1-line MUX.
Here, again, we use the A and B variables as data select inputs. We can use the above
equation to construct the table shown in Fig. 4.22. The residues are what is “left over” in each
minterm when the “address” variables are taken away. To implement this circuit, we connect
I0 and I3 to C, and I1 and I2 to C , as shown in Fig. 4.22.

Input “Address” Other variables

(residues) C I0
I0 A.B C C I1
C I2 Y
I1 A.B C
I2 A.B C C I3
S1 S0
I3 A.B C
A B
Fig. 4.22 A 4-line to 1-line MUX implementation of a function of 3 variables

In general a 4 input MUX can give any function of 3 inputs, an 8 input MUX can give
any functional of 4 variables, and a 16 input MUX, any function of 5 variables.
Example 3. Use an 8 input MUX to implement the following equation:
Y = A.B. C.D + A.B.C.D + A.B. C.D + A.B. C.D + A.B. C.D + A.B.C.D
+ A.B. C.D + A.B. C.D
Again, we will use A, B, C as data select inputs, or address inputs, connected to S2, S1
and S0, respectively.

Input “Address” Residues

D I0
I0 A.B.C D D I1
I1 A.B.C D 1 I2
I2 A.B.C D+D=1 0 I3
I3 A.B.C D I4 Y
I4 A.B.C D D I5
I5 A.B.C D 1 I6
I6 A.B.C D+D=1 0 I7
I7 A.B.C S2 S1 S0

A B C

Fig. 4.23 An 8-line to 1-line MUX implementation of a function of 4 variables

Values of the address set A, B, C with no residues corresponding to the address in the
above table must have logic value 0 connected to the corresponding data input. The select
variables A, B, C must be connected to S2, S1 and S0 respectively. A circuit which implements
this function is shown in Fig. 4.23.
 This use of a MUX as a “table look up” device can be extended to functions of a larger
number of variables; the MUX effectively removes the terms involving the variables assigned
to its select inputs from the logic expression. This can sometimes be an effective way to
reduce the complexity of implementation of a function. For complex functions, however, there
are often better implementations, as we use PLDs (see chapter 5).
Although it is obvious how the function shown in Fig. 4.20 can be extended a 2n line
to 1 line MUX, for any n, in practice, about the largest devices available are only to 16 line
to 1 line functions. It is possible to use a “tree” of smaller MUX’s to make arbitrarily large
MUX’s. Fig. 4.24 shows an implementation of a 16 line to 1 line MUX using five 4 line to
1 line MUX’s.

Fig. 4.24 A 16-line to 1-line MUX made from five 4-line to 1-line MUX’s

Demultiplexers
Another commonly used MSI device is the decoder. Decoders, in general, transform a set
of inputs into a different set of outputs, which are coded in a particular manner; e.g., certain
decoders are designed to decode binary or BCD coded numbers and produce the correct output
to display a digit on a 7 segment (calculator type) display. Decoders are also available to
convert numbers from binary to BCD, from binary to hexadecimal, etc.
Normally, however, the term “decoder” implies a device which performs, in a sense, the
inverse operation of a multiplexer. A decoder accepts an n digit number as its n “select” inputs
and produces an output (usually a logic 0) at one of its 2n possible outputs. Decoders are usually
referred to as n line to 2n line decoders; e.g. a 3 line to 8 line decoder. This type of decoder
is really a binary to unary number system decoder. Most decoders have inverted outputs, so
the selected output is set to logic 0, while all the other outputs remain at logic 1. As well, most
decoders have an “enable” input E , which “enables” the operation of the decoder—when the E
input is set to 0, the device behaves as a decoder and selects the output determined by the
select inputs; when the E input is set to 1, the outputs of the decoder are all set to 1. (The
bar over the E indicates that it is an “active low” input; that is, a logic 0 enables the function).
 The enable input also allows decoders to be con-
nected together in a treelike fashion, much as we saw for
MUX’s, so large decoders can be easily constructed from
smaller devices. The enable input also allows the decoder
to perform the inverse operation of a MUX; a MUX se-
lects as output one of 2n inputs, the decoder can be used
to present an input to one of 2n outputs, simply by con-
necting the input signal to the E input; the signal at the
selected output will then be the same as the input at E —
this application is called “demultiplexing.” The demulti-
plexer (DEMUX) performs the reverse operation of
a multiplexer. A demultiplexer is a circuit that accepts Fig. 4.25 Block diagram of the
demultiplexer/decoder
single input and transmit it over several (one of 2n
possible) outputs.
In the block diagram (Fig. 4.25) a demultiplexer, the number of output lines is n and the
number of select lines is m, where n = 2m.
One the basis of select input code, to which output the data will be transmitted is
determined. There is an active-low (low-logic) enable/data input. The output for these devices
are also active-low.
Note. 4-line to 16-line decoders are the largest available circuits in ICs.
A typical 3 line to 8 line decoder with an enable input behaves according to the following
truth table, and has a circuit symbol as shown in Fig. 4.26.

E S2 S1 S0 O0 O1 O2 O3 O4 O5 O6 O7 E
1 x x x 1 1 1 1 1 1 1 1 O0
0 0 0 0 0 1 1 1 1 1 1 1 O1
0 0 0 1 1 0 1 1 1 1 1 1 S0 O2
0 0 1 0 1 1 0 1 1 1 1 1 O3
S1
0 0 1 1 1 1 1 0 1 1 1 1 O4
0 1 0 0 1 1 1 1 0 1 1 1 S2 O5
0 1 0 1 1 1 1 1 1 0 1 1 O6
0 1 1 0 1 1 1 1 1 1 0 1 O7
0 1 1 1 1 1 1 1 1 1 1 0

Fig. 4.26 An 3-line to 8-line decoder

Note that, when the E input is enabled, an output of 0 is produced corresponding to each
minterm of S2, S1, S0. These minterm can be combined together using other logic gates to
form any required logic function of the input variables. In fact, several functions can be
produced at the same time. If the selected output was a logic 1, then the required minterms
could simply be ORed together to implement a switching function directly from its minterm
form. Using de Morgans theorem, we can see that when the outputs are inverted, as is
normally the case, then the minterm form of the function can be obtained by NANDing the
required terms together.
Example 1. An implementation the functions defined by the following truth table using
a decoder and NAND gates is shown in Fig. 4.27.
 A B C Y1 Y2
O0
0 0 0 0 1
O1
0 0 1 1 1 Y2
C S0 O2
0 1 0 1 0
O3
0 1 1 0 0 B S1
O4
1 0 0 1 0
A S2 O5
1 0 1 0 1
O6 Y1
1 1 0 0 1
O7
1 1 1 0 0

Fig. 4.27

IMPLEMENTATION EXAMPLES OF COMBINATIONAL LOGIC DESIGN USING

MUX/DEMUX
We have already seen how to implement combinational circuits using MUX/DEMUX. The
standard ICs available for multiplexers are 2:1, 4:1, 8:1 and 16:1. The different digital ICs are
given in appendix B, but for sake of convenience some of the MUX/DEMUX ICs are given
here in Tables A and B.
Table A: Standard multiplexer ICs
IC No. Description Output

74157 Quad. 2:1 Multiplexer Same as input

74158 Quad 2:1 MUX Inverted input
74153 Dual 4:1 MUX Same as input
74352 Dual 4:1 MUX Inverted input
74151A 8:1 MUX Complementary outputs
74152 8:1 MUX Inverted input
74150 16:1 MUX Inverted input

Table B: Standard Demultiplexer/Decoder ICs

IC No. Description Output

74139 Dual 1:4 Demultiplexer Inverted input

(2-line-to-4-line decoder)
74155 Dual 1:4 Demultiplexer 1Y-Inverted I/P
(2-line-to-4-line decoder) 2Y-Same as I/P
74138 1:8 Demultiplexer Inverted I/P
(3-line-to-8-line decoder)
74154 1:16 Demultiplexer Same as input
(4-line-to-16-line decoder)

When using the multiplexer as a logic element either the truth table or one of the
standard forms of logic expression must be available. The design procedure for combinational
circuits using MUX are as follows:
 STEP 1: Identify the decimal number correspond-
ing to each minterm in the expression. The input lines Logic 1 Logic 0
corresponding to these numbers are to be connected to
logic 1 (high). 0
STEP 2 : All other input lines except that used in 1
2
step 1 are to be connected to logic 0 (low). 3
STEP 3 : The control inputs are to be applied to 4
5
select inputs. 6
Example 2. Implement the following function with 7
8 16 : 1
multiplexer. Y
MUX
9
Y = F (A, B, C, D) = Σm (0, 1, 3, 4, 8, 9, 15) 10
11
Solution. STEP 1 : The input lines correspond- 12
ing to each minterms (decimal number) are to be con- 13
nected to logic 1. 14
15
Therefore input lines 0, 1, 3, 4, 8, 9, 15 have to S3 S2 S1 S0
E
be connected to logic 1.
A B C D
STEP 2 : All other input lines except 0, 1, 3, 4, 8, (MSB) (LSB)
9, 15 are to be connected to logic 0.
STEP 3 : The control inputs A, B, C, D are to be applied to select inputs.
Note: Although the given procedure is simple to implement but the 16 to 1 multiplexers are
the largest available ICs, therefore to meet the larger input needs there should be provision for
expansion. This is achieved with the help of enable/stroke inputs and multiplexer stacks or trees are
designed.
Example 3. Implement the following function with a 4×1 multiplexer.
Y = F (A, B, C) = Σm (1, 3, 5, 6)
Solution. Given Y = F (A, B, C) = Σm (1, 3, 5, 6)
= A BC + ABC + ABC + ABC
We use the A and B variables as data select inputs. We can use the above equation to
construct the table shown in Fig. 4.28. The residues are what is “left over” in each minterm
when the “address” variables are taken away.
Input “Address” Other variables
(residues) C I0
I0 AB C 1 I1
C I2 Y
I1 AB C
C I3
I2 AB C S1 S0
I3 AB C A B
Fig. 4.28 A 4-line to 1-line MUX implementation of a function of 3 variables

To implement this circuit, we connect I0, I1 and I2 to C and I3 to C as shown in Fig. 4.28.
Example 4. Using four-input multiplexer, implement the following function
Y = F (A, B, C) = Σm (0, 2, 3, 5, 7)
Control variables A, B.
 Solution. Given Y = F (A, B, C) = Σm (0, 2, 3, 5, 7)
= AB C + ABC + ABC + ABC + ABC
We can use the above equation to construct the table shown in Fig. 4.29. The residues
are what is “left over” in each minterm when the “address/control” variables are taken away.
Input “Address” Other variables
(residues) C I0
I0 AB C I1
C 4:1
C I2 MUX Y
I1 AB C+C =1 I3
C
I2 AB C S1 S0
I3 AB C A B
Fig. 4.29 A 4-line to 1-line MUX implementation of a function of 3 variables

To implement this function, we connect I0 to C , I1 to 1 and I2 and I3 to C, as shown

in Fig. 4.29.
Example 5. Design a full adder using 8:1 multiplexer.
Solution. The truth table of a full adder is given as
A B C S CF
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
S (A, B, C) = A BC + ABC + AB C + ABC = Σ m (1, 2, 4, 7)

CF (A, B, C) = ABC + ABC + ABC + ABC = Σm (3, 5, 6, 7)

The implementation for summation expression is
Step 1: The input lines corresponding to 1, 2, 4, 7 are to be connected to logic 1.
Step 2: Other input lines are to be connected to logic 0.
Step 3: Control inputs A, B, C are to be applied to select inputs. Fig. 4.30 A.
Similarly for carry expression.
Step 1: The input lines corresponding to 3, 5, 6, 7 are to be connected to logic 1.
Step 2: Other input lines are to be connected to logic 0.
Step 3: Control inputs A, B, C are to be applied to select inputs. Fig. 4.30 B.
 Logic 1 Logic 0 Logic 1 Logic 0

0 0
1 1
2 2
3 3
4 8:1 4 8:1
S CF
5 MUX 5 MUX
6 6
7 7
S2 S1 S0 S2 S1 S0

A B C A B C
(A) (B)

Fig. 4.30 Full adder implementation using 8:1 multiplexer

Example 6. Implement a full adder with a decoder and two OR-gates.

Solution. From the previous example we note that expression for summation is
given by
S (A, B, C) = Σm (1, 2, 4, 7)
and expression for carry is given by
CF (A, B, C) = Σm (3, 5, 6, 7)
The combinational logic of full adder can be implemented with due help of 3-line to 8-
line decoder/1:8 demultiplexer as shown in Fig. 4.31.

0
C LSB 1
2 S
3×8 3
B
decoder 4
5
A MSB 6
7

Fig. 4.31 Full adder implementation using 3 × 8 decoder

Example 7. A combinational circuit is defined by the following Boolean functions. Design

circuit with a decoder and external gates.
Solution. Y1 = F1(A, B, C) = A B C + AC

Y2 = F2(A, B, C) = ABC + AC

Given Y1 = A B C + AC
First we have to write the expression in minterms, if the expression is not in the form
of minterms by using (x + x = 1)
 Fig. 4.32 Function implementation using 3×8 decoder

Therefore, Y1 = A B C + AC
Y1 = A B C + AC (B + B)
Y1 = A B C + ABC + ABC
Y1 = Σm (0, 5, 7)
Y2 = ABC + AC
Y2 = ABC + AC (B + B)
Y2 = ABC + ABC + A BC
Y2 = Σm (1, 3, 5)
The combinational logic for the boolean function can be implemented with the help of
3-line to 8-line decoder as shown in Fig 4.32.
Example 8. Realise the given function using a multiplexer
Y(A, B, C, D) = ΠM (0, 3, 5, 9, 11, 12, 13, 15)
Solution. To implement the given function, first we have to express the function in
terms of sum of product. i.e.,
Y (A, B, C, D) = Σm (1, 2, 4, 6, 7, 8, 10, 14)
Now the given function in this form can be realized as
Step 1: Input lines corresponding to 1, 2, 4, 6, 7, 8, 10, 14 are to be connected to logic 1.

Fig. 4.33 A 16-line to 1-line MUX implementation

 Step 2: Other input lines are to be connected to logic 0.
Step 3: Control inputs A, B, C, D are to be applied to select inputs.
Example 9. Realize the following boolean expression using 4:1 MUX(S) only.
Z = ABC D + ABCD + ABCD + ABCD + ABC D + ABCD
Solution. Given Z = Σm (0, 6, 8, 10, 11, 15)
To implement the given boolean expression we must have 16 input and 4 selection
inputs.
Since 4:1 mux has 4 input lines and two selection lines. Therefore we can use 4, 4:1 MUX
with their select lines connected together. This is followed by a 4:1 MUX to select one of the
four outputs. The select lines of the 4:1 MUX (final) are driven from inputs A, B. The complete
circuit is shown in Fig. 4.34.
Logic 0 Logic 1

0
1 4:1
2 MUX

C D

4
I0
5 4:1 I1 4:1
6 MUX Z
I2 MUX
7
I3
S1 S0
C D

A B
8
9 4:1
10 MUX
11

C D

12
13 4 : 1
14 MUX
15

C D

Fig. 4.34 A 4-line to 1-line MUX implementation of a function of 4 variable

 Encoders
The encoder is another example of
combinational circuit that performs the inverse m n
Encoder
operation of a decoder. It is disigned to generate Inputs Inputs
a diffrent output code for each input which becomes
active. In general, the encoder is a circuit with m
input lines (m ≤ 2n ) * (* m < 2n → If unused input Fig. 4.35 Block diagram of an encoder
combinations occur.) and n output lines that
converts an active input signal into a coded output signal. In an encoder, the number of outputs
is less than the number of inputs. The block diagram of an encoder is shown in Fig. 4.35.
An example of an encoder is an octal to binary encoder. An octal to binary encoder accept
eight inputs and produces a 3-bit output code corresponding to the activated input. The truth
table for the octal to binary encoder is shown below in table.
Inputs Outputs
O0 O1 O2 O3 O4 O5 O6 O7 Y2 Y1 Y0
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
It has eight inputs, one for each octal digit and three outputs that generate the corre-
sponding binary number.
The truth table shows that Y0 must be 1 whenever the input O1 or O3 or O5 or O7 is
high. Thus,
Y0 = O1 + O3 + O5 + O7
Similarly Y1 = O2 + O3 + O6 + O7 and
Y2 = O4 + O5 + O6 + O7.
Using these three expressions, the circuit can be implemented using three 4-input OR
gates as shown in Fig. 4.36.
O0 O1 O2 O3 O4 O5 O6 O7

Y0

Y1

Y2

Fig. 4.36 Octal to binary encoder

The encoder has two limitations:

1. Only one input can be active at any given time. If two or more inputs are equal
to 1 at the same time, the O/P is undefined. For example if O2 and O5 are active
similtaneously, the o/p of encoder will be 111 that is equal to binary 7. This does
not represent binary 2 or 5.
2. The output with all 0’s is generated when all inputs are ‘0’, and is also true when
O0 = ‘1’.
 The first problem is taken care by a circuit, called as ‘priority encoder’. It establishes a
priority to ensure that only one input is active (High) at a given time.
The second problem is taken care by an extra line in the encoder output, called ‘valid
output indicator’ that specifies the condition that none of the inputs are active.

Priority Encoder
A priority encoder is an encoder that includes priority function. If two or more inputs are
equal to 1 at the same time, the input having the highest priority will take precedence. To
understand priority encoder, consider a 4 to 2 line encoder which gives priority to higher
subscript number input than lower subscript number. The truth table is given below.
Truth Table of 4 to 2 line priority encoder:
Inputs Outputs
D0 D1 D2 D3 Y1 Y2 V
0 0 0 0 x x 0
1 0 0 0 0 0 1
x 1 0 0 0 1 1
x x 1 0 1 0 1
x x x 1 1 1 1
The X’s are don’t care conditions. Input D3 has the highest priority, so regardless of
values of other inputs, when this input is 1, the output Y1 Y2 = 11. D2 has next priority level.
The o/p is 10 if D2 is 1, provided D3 = 0, irrespective of the values of the other two lower-
priority inputs. The o/p is 01 if D1 is 1, provided both D2 and D3 are 0, irrespective of the
value of lower-priority input D0. The o/p is 00 if D0 = 1, provided all other inputs are 0.
A valid output indicator, V is set to 1, only when one or more of the inputs are equal
to 1. If all the inputs are 0, V is equal to 0 and the other two outputs of the circuit are not
used.
Now, simplifying using k-map the outputs can be written as :
Y 1 = D 2 + D3
Y2 = D3 + D1 D2'
V = D0 + D1 + D2 + D3.
The logic diagram for a 4 to 2 line priority encoder with ‘valid output indicator’ is shown
below in Fig. 4.37.

D0 D1 D2 D3

Y1

Y2

Fig. 4.37
Error – Detecting codes:When binary data is transmitted & processed,it is susceptible to noise
that can alter or distort its contents. The 1‘s may get changed to 0‘s & 1‘s .because digital
systems must be accurate to the digit, error can pose a problem. Several schemes have been
devised to detect the occurrence of a single bit error in a binary word, so that whenever such an
error occurs the concerned binary word can be corrected & retransmitted.

Parity:The simplest techniques for detecting errors is that of adding an extra bit known as parity
bit to each word being transmitted.Two types of parity: Oddparity, evenparity forodd parity, the
parity bit is set to a ‗0‘ or a ‗1‘ at the transmitter such that the total no. of 1 bit in the word
including the parity bit is an odd no.For even parity, the parity bit is set to a ‗0‘ or a ‗1‘ at the
transmitter such that the parity bit is an even no.

Decimal 8421 code Odd parity Even parity

0 0000 1 0
1 0001 0 1
2 0010 0 1
3 0011 1 0
4 0100 0 1
5 0100 1 0
6 0110 1 0
7 0111 0 1
8 1000 0 1
9 1001 1 0
When the digit data is received . a parity checking circuit generates an error signal if the
total no of 1‘s is even in an odd parity system or odd in an even parity system. This parity check
can always detect a single bit error but cannot detect 2 or more errors with in the same word.Odd
parity is used more often than even parity does not detect the situation. Where all 0‘s are created
by a short ckt or some other fault condition.

Ex: Even parity scheme

(a) 10101010 (b) 11110110 (c)10111001
Ans:
(a) No. of 1‘s in the word is even is 4 so there is no error
(b) No. of 1‘s in the word is even is 6 so there is no error
(c) No. of 1‘s in the word is odd is 5 so there is error

Ex: odd parity

(a)10110111 (b) 10011010 (c)11101010
Ans:
(a) No. of 1‘s in the word is even is 6 so word has error
(b) No. of 1‘s in the word is even is 4 so word has error
(c) No. of 1‘s in the word is odd is 5 so there is no error
Checksums:

Simple parity can‘t detect two errors within the same word. To overcome this, use a sort
of 2 dimensional parity. As each word is transmitted, it is added to the sum of the previously
transmitted words, and the sum retained at the transmitter end. At the end of transmission, the
sum called the check sum. Up to that time sent to the receiver. The receiver can check its sum
with the transmitted sum. If the two sums are the same, then no errors were detected at the
receiver end. If there is an error, the receiving location can ask for retransmission of the entire
data, used in teleprocessing systems.

Block parity:

Block of data shown is create the row & column parity bits for the data using odd parity.
The parity bit 0 or 1 is added column wise & row wise such that the total no. of 1‘s in each
column & row including the data bits & parity bit is odd as

Data Parity bit data

10110 0 10110
10001 1 10001
10101 0 10101
00010 0 00010
11000 1 11000
00000 1 00000
11010 0 11010

Error –Correcting Codes:

A code is said to be an error –correcting code, if the code word can always be deduced
from an erroneous word. For a code to be a single bit error correcting code, the minimum
distance of that code must be three. The minimum distance of that code is the smallest no. of bits
by which any two code words must differ. A code with minimum distance of 3 can‘t only correct
single bit errors but also detect ( can‘t correct) two bit errors, The key to error correction is that
it must be possible to detect & locate erroneous that it must be possible to detect & locate
erroneous digits. If the location of an error has been determined. Then by complementing the
erroneous digit, the message can be corrected , error correcting , code is the Hamming code , In
this , to each group of m information or message or data bits, K parity checking bits denoted by
P1,P2,----------pk located at positions 2 k-1 from left are added to form an (m+k) bit code word.
To correct the error, k parity checks are performed on selected digits of each code word, & the
position of the error bit is located by forming an error word, & the error bit is then
complemented. The k bit error word is generated by putting a 0 or a 1 in the 2 k-1th position
depending upon whether the check for parity involving the parity bit P k is satisfied or not.Error
positions & their corresponding values :
 Error Position For 15 bit code For 12 bit code For 7 bit code
C4 C3 C2 C1 C4 C3 C2 C1 C3 C2 C1
0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1 0 0 1
2 0 0 1 0 0 0 1 0 0 1 0
3 0 0 1 1 0 0 1 1 0 1 1
4 0 1 0 0 0 1 0 0 1 0 0
5 0 1 0 1 0 1 0 1 1 0 1
6 0 1 1 0 0 1 1 0 1 1 0
7 0 1 1 1 0 1 1 1 1 1 1
8 1 0 0 0 1 0 0 0
9 1 0 0 1 1 0 0 1
10 1 0 1 0 1 0 1 0
11 1 0 1 1 1 0 1 1
12 1 1 0 0 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1

7-bit Hamming code:

To transmit four data bits, 3 parity bits located at positions 20 21&22 from left are
added to make a 7 bit codeword which is then transmitted.

The word format

P1 P2 D3 P4 D5 D6 D7
D—Data bits
P—Parity bits

Decimal Digit For BCD

P1P2D3P4D5D6D7
0 0 0 0 0 0 0 0
1 1 1 0 1 0 0 1
2 0 1 0 1 0 1 1
3 1 0 0 0 0 1 1
4 1 0 0 1 1 0 0
5 0 1 0 0 1 0 1
6 1 1 0 0 1 1 0
7 0 0 0 1 1 1 1
8 1 1 1 0 0 0 0
9 0 0 1 1 0 0 1
Ex: Encode the data bits 1101 into the 7 bit even parity Hamming Code

The bit pattern is

P1P2D3P4D5D6D7

1 1 0 1

Bits 1,3,5,7 (P1 111) must have even parity, so P1 =1

Bits 2, 3, 6, 7(P2 101) must have even parity, so P2 =0

Bits 4,5,6,7 (P4 101)must have even parity, so P4 =0

The final code is 1010101

EX: Code word is 1001001

Bits 1,3,5,7 (C1 1001) →no error →put a 0 in the 1‘s position→C1=0

Bits 2, 3, 6, 7(C2 0001)) → error →put a 1 in the 2‘s position→C2=1

Bits 4,5,6,7 (C4 1001)) →no error →put a 0 in the 4‘s position→C3=0

15-bit Hamming Code: It transmit 11 data bits, 4 parity bits located 20 21 22 23

Word format is

P1 P2 D3 P4 D5 D6 D7 P8 D9 D10 D11 D12 D13 D14 D15

12-Bit Hamming Code:It transmit 8 data bits, 4 parity bits located at position 20 21 22 23

Word format is

P1 P2 D3 P4 D5 D6 D7 P8 D9 D10 D11 D12

Alphanumeric Codes:

These codes are used to encode the characteristics of alphabet in addition to the decimal
digits. It is used for transmitting data between computers & its I/O device such as printers,
keyboards & video display terminals.Popular modern alphanumeric codes are ASCII code &
EBCDIC code.