Unit 7: Memory

Organization

Reference : Chapter 12 Computer System Architecture by Morris Mano

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Memory Hierarchy
• What is Memory?

• Why different types of memory? (Main Memory, Auxiliary Memory)

• Volatile, Large Storage, Speed

• Main Memory: memory unit that communicates directly with the CPU
• RAM, ROM

• Auxiliary Memory: provide backup storage

• Magnetic disk

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Memory Organization and Relation
Magnetic
Disk

I/O Processor

Magnetic
Tapes
Main Memory CPU

Cache
Memory
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Memory Hierarchy

Smaller
Faster Registers
Costlier
(per byte storage) Cache
(SRAM)

Main memory
(DRAM)

Larger Local secondary storage

Slower (local disks)
Cheaper
(per byte storage) Remote secondary storage
(tapes, distribute file systems, web servers)

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Multiprogramming
• Concept used in OS which enable the CPU to Process a number of
independent programs concurrently.

• Keep CPU busy by working with several programs in sequence.

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Main Memory
• Relatively large and fast memory used to store programs and data
during the computer operation.

• RAM(Random Access Memory)

• Static and Dynamic

• ROM(Read Only Memory)

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RAM (Random Access Memory)
• Volatile
• Can perform Read and Write operation

1. SRAM (Static RAM)

• consist of internal flip-flops that store the binary information.
 Cache Memory

2. DRAM(Dynamic RAM)
• Stores the Binary information in the form of electric charges that are applied
to capacitors
• Refreshing is required
• Reduced power consumption and Larger storage capacity
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ROM (Read Only Memory)
• Non volatile

• Can perform Read operation only

• Store programs and data that are permanently reside in the computer
that do not change in value.
• Store Bootstrap Loader

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Bootstrap Loader
• It is a program whose function is to start the computer software
operating when power is turned on.

• When power is turned on, the hardware of the computer sets the
program counter to the first address of the bootstrap loader.

• The bootstrap program loads a portion of the operating system from

disk to main memory and control is then transferred to the OS, which
prepares the computer for general use.

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RAM Chip Block Diagram

Chip Select 1 CS1

Chip Select 2 CS2
128 × 8
Read RD 8-bit Data Bus
RAM
Write WR

7-bit Address AD7

Function Table
CS1 CS2 RD WR Memory Function State of the Data Bus
0 0 × Inhibit High Impedance
×
0 1 × × Inhibit High Impedance
1 1 × × Inhibit High Impedance
1 0 0 0 Inhibit High Impedance
1 0 0 1 Write Input data to RAM
1 0 1 × Read Output data from RAM
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ROM Chip

Block Diagram

Chip Select 1 CS1

Chip Select 2 CS2

512 × 8
8-bit Data Bus
ROM

9-bit Address AD9

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Memory Connection to the CPU
• Require Memory: 512 Bytes of RAM and 512 Bytes of ROM

• Available chip
• RAM: 128 × 8
• ROM: 512 × 8

• No of RAM and ROM Chip required

• 4 RAM Chip
• 1 ROM Chip

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 CPU
Data bus

8 bit data
128 × 8 128 × 8 128 × 8 128 × 8 512 × 8
RAM 1 RAM 2 RAM 3 RAM 4 ROM

CS1 CS2 RD WR AD7 CS1 CS2 RD WR AD7 CS1 CS2 RD WR AD7 CS1 CS2 RD WR AD7 CS1 CS2 AD
9
WR
RD
1
1-7 8 9

1-7

0
8
1
Decoder
Address bus

2
9
3

10
11-16

Address : 0 0 0 0 0 0 00 1 1 0 0 1 0 1 0 © Ronak Patel, Computer Engineering Department , CSPIT, CHARUSAT

 Memory Address Map
Note: Bits 11 to 16 are all zero
Starting Address Ending Address

Component
Binary Hexa Binary Hexa
Decimal Decimal
10 9 8 7 6 5 4 3 2 1 10 9 8 7 6 5 4 3 2 1

0 0 0 0 0 0 0 0 0 0 0000 0 0 0 1 1 1 1 1 1 1 007F
RAM-1
0 0 1 0 0 0 0 0 0 0 0080 0 0 1 1 1 1 1 1 1 1 00FF
RAM-2
0 1 0 0 0 0 0 0 0 0 0100 0 1 0 1 1 1 1 1 1 1 017F
RAM-3
0 1 1 0 0 0 0 0 0 0 0180 0 1 1 1 1 1 1 1 1 1 01FF
RAM-4
1 0 0 0 0 0 0 0 0 0 0200 1 1 1 1 1 1 1 1 1 1 03FF
ROM

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Associative Memory
• A memory unit accessed by content is called an associative memory or content
addressable memory(CAM).

• Time required to find an item stored in memory can be reduced.

• Can be accessed simultaneously.

• The memory is capable of finding an empty unused location to store the word.

• When a word is to be read from the memory, the content of the word, or part of the word,
is specified.

• The memory locates all words which match the specified content and marks them for
reading.

• Expensive
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Cache Memory
• Locality of reference: few localized areas of memory are repeatedly
referred.

• If the active program and data are placed in a fast small memory, the
average memory access time can be reduced, thus reducing total
execution time of the program. Such a fast small memory is referred
to as a cache memory.

• Less access time than main memory.

• What happens when CPU access memory?

• CPU-----> Cache Memory ----->Main Memory
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Performance of Cache Memory
• Hit ratio =

• TC = Cache Memory Access Time

• Tm = Main Memory Access Time
• Tavg= Average Memory Access Time
• H = Hit ratio

• Tavg = H × TC + (1 - H) × (TC + Tm)

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Addressing Mapping
• Decide which block of main memory has to be placed where in the
cache memory.

• Three types of Mapping process:

1. Direct Mapping
2. Associative Mapping
3. Set – Associative Mapping

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 Direct Mapping
Kth Block of main memory is placed in (Kth mod N)th block of cache memory.
32 words in Main Memory Physical Address= 5 bits 0 0 mod 4 = 0
16 words in Cache Memory
Block size= 4 words 1

0
2 2 mod 4 = 2
3
Tag 1
2
4 4 mod 4 = 0
5
3 1 Bit of Tag is required
Cache Memory 01 6
No of Block(N)=4 7
MM Blocks That Can be Placed in Block 0 of CM are {0,4} Main Memory
MM Blocks That Can be Placed in Block 1 of CM are {1,5} No of Block(M)=8
MM Blocks That Can be Placed in Block 2 of CM are {2,6}
MM Blocks That Can be Placed in Block 3 of CM are {3,7}
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 Direct Mapping
1 bit 2 bits 2 bits
TAG Physical
Cache Blockaddress
Offset Word Offset
0 1 0 0 1
0 0 mod 4 = 0
Compare
1
01 0
2 2 mod 4 = 2
3
Tag 1
0 2
4 4 mod 4 = 0
1 5
3
Tag bits are same. Cache Memory 6
So word is present. No of Block(N)=4
It is at location 1.
7 7 mod 4 = 3
Check word no 9 is present in cache or not? Main Memory
No of Block(M)=8
Physical Address 0 1 0 0 1
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Example
• MM= 512 words
• CM = 64 words
• Block size= 16 words
1. How many Bits for Physical Address?
2. How many TAG Bits are required?
3. How many Bits are required for cache offset?
4. How many Bits are required for word offset?
5. If MM blocks 16, 9, 26, 7 are present in CM than show Tag of each
cache.
6. Now Check on above cache representation that word 237 and 400 is
Present? and How?
© Ronak Patel, Computer Engineering Department , CSPIT, CHARUSAT
 Direct Mapping
3 bit 2 bits 4 bits
PA= 9 Bits TAG Physical
Cache Blockaddress
Offset Word Offset

1
10000 16
100 2
00 16
01001 9
010 3
Tag 01 9
11010 26 4
110 26
10 00111
001 7 :
11 7
30
Cache Memory
No of Block(N)=4 31
Check word is present in cache or not?
word no 237 word no 400 word no 145
PA: 010 01 0001 Main Memory
PA: 011 10 1101 PA: 110 01 0000 No of Block(M)=32
TAG is Different in 10 TAG is Different in 01 TAG is same in 01 word is at 0001 in that block
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Limitation of Direct Mapping

• Conflict penalties:
• Present of one block abstracting the incoming block inspite of the cache is
free
• MM Block ref: 0, 4, 0, 4, 8, 0, 4, 12, 4, 12

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Associative Mapping
Any Block of main memory can be placed any where in the cache
TAG Physical address Word Offset
3 bits 2 bits

1
000 2
0
010 3
Tag 1
111 4
2
5
3
Cache Memory 6
No of Block(N)=4 7
Main Memory
No of Block(M)=8
© Ronak Patel, Computer Engineering Department , CSPIT, CHARUSAT
Example
• MM= 512 words
• CM = 64 words
• Block size= 16 words
1. How many Bits for Physical Address?
2. How many TAG Bits are required?
3. How many Bits are required for cache offset?
4. How many Bits are required for word offset?
5. If MM blocks 16, 9, 26, 7 are present in CM than show Tag of each
cache.
6. Now Check on above cache representation that word 237 and 400 is
Present? and How?
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Set Associative Mapping
• Advantage of Direct Mapping and Associative Mapping.

• Total number of sets in k-way set associative is:

S=

• Jth Block of MM has to be placed in ( Jth mod S )th Set. Within the set it
can be placed anywhere.

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2 Way Set Associative Mapping
Sets

TAG Physical
Set Offsetaddress Word Offset
2 bits 1 bit 2 bits 0 0 mod 2 = 0
1
00 0
2 2 mod 2 = 0
01 3
1
11 4
2
5
3
Cache Memory 6
No of Block(N)=4 7 7 mod 2 = 1
Main Memory
No of Block(M)=8
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Example
• MM= 512 words
• CM = 64 words
• Block size= 16 words
• 2-way Set Associative
1. How many Bits for Physical Address?
2. How many TAG Bits are required?
3. How many Bits are required for set offset?
4. How many Bits are required for word offset?
5. If MM blocks 16, 9, 26, 7 are present in CM than show Tag of each cache.
6. Now Check on above cache representation that word 237 and 400 is
Present? and How?
© Ronak Patel, Computer Engineering Department , CSPIT, CHARUSAT
Question
• Consider 1MB cache and 4 GB MM are partitioned into 64KB blocks.

1. How many bits are required for Physical address if word size is 1B?

2. How many block are there in MM and CM?

3. How many TAG bits are required for

1. Direct Mapping
2. Associate Mapping
3. 8-Way set Associative Mapping

4. How many TAG memory in Bytes are required for each case?

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 Answer

32 bits Physical address TAG Comparator TAG Memory

Direct Mapping: TAG CB Offset Word Offset 1 – 12 bits 16 × 12 = 192 bits = 24 B

12 bits 4 bits 16 bits

Associative Mapping: TAG Word Offset 16 – 16 bits 16 × 16 = 256 bits = 32 B

16 bits 16 bits

8-Way Set Associative: TAG Set Offset Word Offset 8 – 15 bits 16 × 15 = 240 bits = 30 B
15 bits 1 bit 16 bits

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Observation

• What about 1 way set associative?

• It is similar to direct mapping.
• Because each set contains 1 block. To select set we use modulo operation. So, It
will tell you in which set you have to go and there is one block only in that,
which is similar to direct mapping.

• What about N-way set associative?

• It is similar to Associative Mapping.
• As set size is equal to total number of cache block, there is only 1 set.
• In set you can put your block any where which is similar to associative mapping.

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Writing to main memory
• Write-through
• Useful in Direct memory access transfer

• Write-back

Cache Initialization
• Valid bit

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Virtual Memory
• What is it?

• Why it is required?

• Paging overview

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 Any
Questions

?
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