Procedural Statements

and Routines
 Introduction
• As you verify your design, you need to
write a great deal of code, most of which is
in tasks and functions.
• System Verilog introduces many
incremental improvements to make this
easier by making the language look more
like C, especially around argument passing.
Procedural Statements
New procedural statements and operators
Procedural Statements (cont)
Using break and continue while reading a file

Two new statements help with loops. First, if you are in a

loop, but want to skip over rest of the statements and do
the next iteration, use continue. If you want to leave the
loop immediately, use break.
 Procedural Statements (cont)
• SystemVerilog expands the case statement so that you no
longer have to give every possible value.
• We can give a range values as shown in Sample Example
shown below .
• This is a version of the inside operator in system Verilog.
 Tasks and Functions in Verilog
• Tasks and Functions are subroutines or subprograms used in
Verilog.
• Tasks and Functions provide subroutine mechanism of reusing
the same section of code at different places in a module.
• Tasks and Functions help to make module definition more
readable by breaking it up into manageable subunits.
• Tasks and Functions are included in the design hierarchy and
can be addressed by hierarchical name referencing.

8
 Tasks
• Tasks are declared with keywords task and endtask.
• Tasks must be used if any one of the following conditions is
true for the procedure.
 There are delay, timing, or event control constructs in the procedure.
 The procedure has zero or more than one output arguments
 The procedure has no input arguments.

• Tasks have input, output, and inout arguments.

• I/O arguments in a task are used to pass values to and from the
task.
• Sequential statements within the task can use the different time
control constructs.
• Task calling is inside the always or initial statement.
9
10
FA using two HA’s

11
 FA using two HA’s
• Verilog Full Adder Using Task
• module Full_add (x, y, cin, sum, cout);
• //The full adder is built from two half adders
• input x, y, cin;
• output sum, cout;
• reg sum, sum1, c1, c2, cout;
• always @ (x, y, cin)
• begin
•
• Haddr (sum1, c1, y, cin);
• Haddr (sum, c2, sum1, x);
• //The above two statements are calls to the task Haddr.
• cout = c1 | c2;
• end
•
•
12
 FA using two HA’s
• task Haddr;
• //This task describes the half adder
• output sh, ch;
• input ah, bh;
• begin
• sh = ah ^ bh;
• ch = ah & bh;
• end
• endtask
• endmodule 13
 Verilog N-Bit Ripple Carry Adder Using Task
• module adder_ripple (x, y, cin, sum, cout);
• parameter N = 3;
• input [N:0] x, y;
• input cin;
• output [N:0] sum;
• output cout;
• reg [N+1:0] cint;
• reg [N:0] sum;
• reg cout;
• integer i;
• always @ (x, y, cin)
• begin
• cint[0] = cin;
• for (i = 0; i <= N; i = i + 1)
• begin
• Faddr (sum[i], cint[i+1], x[i], y[i], cint[i]);
• cout = cint[N+1];
• end
14
•
•
 TASK FULL ADDER
• task Faddr;
• //The task describes a full adder
• output sf, cof;
• input af, bf, cinf;
• begin
• sf = af ^ bf ^ cinf;
• cof = (af & bf) | (af & cinf) | (bf & cinf);
• end
• endtask
•
• endmodule

15
 Functions
• Functions are declared with keywords function and
endfunction.
• Functions are used if all of the following conditions are true
for the procedure.
 There are no delay, timing, or event control constructs in the
procedure.
 The procedure returns a single value.
 There is at least one input arguments.

• A register with the name as the function name is declared

implicitly when a function is declared.
• The return value of the function is passed back in this register.
• At least one input argument must be defined for a function.

16
17
 Verilog Function That Calculates exp = a XOR b
• module Func_exm (a1, b1, d1);
• input a1, b1;
• output d1;
• reg d1;
• always @ (a1, b1)
• begin
• /*The following statement calls the function exp
• and stores the output in d1.*/
• d1 = exp (a1, b1);
• end
• function exp ;
• input a, b;
• begin
• exp = a ^ b;
• end
• endfunction
• endmodule

18
 Verilog Function to Find the Greater of Two Signed Numbers
• module greater_2 (x, y, z);
• input signed [3:0] x;
• input signed [3:0] y;
• output signed [3:0] z;
• reg signed [3:0] z;
• always @ (x, y)
• begin
• z = grt (x, y); //This is a function call.
• end
• function [3:0] grt;
• input signed [3:0] a, b;
• begin
• if (a>= b)
• grt = a;
• else
• grt = b;
• end
• endfunction
• endmodule 19
Differences between Tasks and Functions

20
Tasks, Functions, and Void Functions
Tasks, Functions, and Void Functions
Routine Arguments
Routine Arguments
 Argument Direction

The arguments a and b are input logic, 1 bit wide. The

arguments u and v are 16-bit output bit types.
Advanced Argument Types
Advanced Argument
Default value for Arguments
Default value for Arguments
Default value for Arguments(Cont)
Passing Arguments by name
Returning from a Routine
Returning from a Routine
Local Data Storage
Local Data Storage (cont)
Variable initialization
Variable initialization
Variable initialization - solution
Local Data Storage Exercise
Time units and Precision
Time Literals
Time and Variables
$time vs $realtime
Time Exercise
 Connecting the Testbench and
Design
•Interfaces
•Clocking blocks
•Program blocks
•The end of simulation
•Top level scope
•Assertions
Connecting the Testbench and
Design
 Connecting the Testbench and
Design
• Test bench wraps around the design, sending in stimulus
and capturing the design’s response. The testbench forms
the “real world” around the design, mimicking the entire
environment.
• For example, a processor model needs to connect to
various busses and devices, which are modeled in the test
bench as bus functional models.
• A networking device connects to multiple input and output
data streams that are modeled based on standard protocols.
• video chip connects to buses that send in commands, and
then forms images that are written into memory models.
• The key concept is that the testbench simulates everything
not in the design under test.
 Separating the Test bench and Design
• As designs grow in complexity, the connections between
the blocks increase.
• Two RTL blocks may share dozens of signals, which must
be listed in the correct order for them to communicate
properly.
• One mismatched or misplaced connection and the design
will not work.
• The solution is the interface, the System Verilog construct
that represents a bundle of wires, with intelligence such as
synchronization, and functional code.
• An interface can be instantiated like a module but also
connected to ports like a signal.
Separating the Testbench and Design
 Communication between the test
bench and DUT
• The following diagram shows how the test bench
connected to an arbiter, using individual signals and again
using interfaces.
• Here is a diagram of the top level design including a test
bench, arbiter, clock generator, and the signals that connect
them.
• This is a trivial design, so we can concentrate on the
System Verilog concepts and not get bogged down in the
design.
Communication between the test bench
and DUT

Fig.Testbench – Arbiter without interfaces

 Communication with ports
• In SystemVerilog the classic reg type so that you can use it
like a wire to connect blocks.

• In recognition of its new capabilities, the reg type has the

new name of logic.

• The only place where you cannot use a logic variable is a

net with multiple drivers, where you must use a net such as
wire.
Example : Arbiter model using ports
Testbench using ports
 Top-level netlist without an interface
• In Example, the netlists are simple, but real designs with
hundreds of pins require pages of signal and port
declarations.
• All these connections can be error prone. As a signal
moves through several layers of hierarchy, it has to be
declared and connected over and over.
• Worst of all, if you just want to add a new signal, it has to
be declared and connected in multiple files.
• SystemVerilog interfaces can help in each of these cases.
Top-level netlist without an interface
 The Interface Construct
• Designs are so complex that even the communication
between them may need to be separated out into separate
entities.

• To model this, SystemVerilog uses the interface construct

that you can think of as an intelligent bundle of wires.

• They contain the connectivity, synchronization, and

optionally, the functionality of the communication between
two or more blocks.

• They connect design blocks and/or testbenches.

.
The Interface Construct

The simplest interface is just a

bundle of nondirectional signals.
Use logic so you can drive the
signals from procedural
statements.
Using an Interface to Simplify
Connectivity.
 Connecting Interfaces and Ports

We have a legacy design

with ports that cannot be
changed to use an interface,
you can just connect the
interfaces’s signals to the
individual ports.
 Group Signals in I/F using Modport

The modport construct in an interface lets you group

signals and specify directions
Group Signals in I/F using Modport

* The MONITOR modport allows you to connect a monitor

module. It is optional.
Functions in an Interface
Mixing interface and ordinary ports
RTL functions in Interface
Synthesis in SystemVerilog
Interface trade-offs
Interface Exercise
Interface Exercise
 Stimulus Timing
• The timing between the testbench and the design must be
carefully orchestrated.

• At a cycle level, you need to drive and receive the

synchronous signals at the proper time in relation to the
clock.

• Mixing design and testbench events can cause a race

condition, such as when a signal is both read and written at
the same time.

• SystemVerilog has several constructs to help you control

the timing of the communication.
Stimulus Timing
Control Timing with a clocking block
Interface clocking block
Timing of stimulus/checker
The program block and timing regions
 The program block and timing regions
• In SystemVerilog, several new regions were introduced.
First to execute during a time slot is the Prepone region.
which samples signals before any design activity.
• These samples are used by the testbench. Next is the
Active region, where design events run.
• These include your RTL and gate code plus the clock
generator.
• The third region is the Observed region, where assertions
are evaluated.
• Following that is the Reactive region where the testbench
executes.
• Note that time does not strictly flow forwards — events in
the Observed and Reactive regions can trigger further
design events in the Active region in the current cycle.
The program block and timing regions
Specifying delays in clocking blocks
Input and Output Skew Example
Clocking Block Summary
Using a Clocking block
The end of simulation
 Connecting It All Together
 The design is described in a module, a testbench in a program
block, and interfaces that connect them together.

 The top-level module that instantiates and connects all the

pieces
Connecting it all Together
Top-Level Scope
Top-Level Scope -$root
Top-Level Scope -$root
 Assertions in systemverilog

Assertions are primarily used to validate the behavior of a

design
 Benefits of Assertions
• Improves observability of the design
• Improves debugging of the design
• Improves the documentation of the Design
• Assertion can be used to provide functional coverage
Functional coverage is provided by cover property
• Can use these assertions in formal analysis
Assertions in systemverilog
Why can’t VERILOG
System verilog assertions
System verilog assertions
 Immediate Assertions
• Immediate assertions = instructions to a simulator
• Follows simulations event semantics
• Appears as a procedural statement, executed like a statement in a procedural
block
• Syntax: assert (expression) pass_statement [else fail_statement]
• The statement is non-temporal and treated as a condition in if statement
• The else block is optional, however it allows registering severity of assertion
failure
• Severity System tasks:
• $fatal : run time fatal, terminates simulation
• $error : run time error (default)
• $warning : run time warning, can be suppressed by command-line option
• $info : failure carries no specific severity, can be suppressed
Immediate Assertion check
 Immediate Assertions
Example:
always @ (posedge clk)
Begin //checkResults
assert ( output == expected ) okCount++;
else
begin
$error(“Output is incorrect”); errCount++; end
 Concurrent Assertions
• Concurrent assertions = instructions to verification tools
• Based on clock semantics. Evaluated on the clock edge
• Values of the variables used in evaluation are the sampled values
• Detects behavior over a period of time
• Ability to specify behavior over time. So these are called temporal
expressions
• Assertions occur both in procedural block and a module
• Example:
assert property
( @(posedge clk) a ##1 b |-> d ##1 e );
 Layers of Concurrent Assertion
• Make the sequence
• Evaluate the sequence
• Define a property for sequence with pass fail
• Property asserted with a specific block
( eg: Illegal sequence, measuring coverage … )