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lab1

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tranquocan1708
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7 views

lab1

Uploaded by

tranquocan1708
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Bài 1

START: LDI R16, 0x00


OUT DDRA, R16 / /PORTA - INPUT -- DIP SW LDI R16, OxFF
OUT PORTA, R16
//DIEN TRO KEO LEN
OUT DDRB, R16 //PORTB -OUTPUT - - BAR LED OUT PORTB, R16
MAIN: IN R17, PINA //PINA = 0 --> ON - - LED SANG - -> PB = 1
COM R17
//PB = NOT (PINA)
OUT PORTB, R17
RIMP MAIN
//TIEP TUC DOC PIN A

Bài 2
Bai 2a
•cseg .org 0x00
START: LDI R16, 0x00
OUT DDRA, R16 / /PORTA - INPUT - - DIP SW LDI R16, OxFF
OUT PORTA, R16 / /DIEN TRO KEO LEN OUT DDRB, R16 / /PORTB -OUTPUT - - BAR LED
OUT PORTB, R16
MAIN: IN R17, PINA / / R17 < - - PINA(DIPSW)
LDI R16, OxOF //R16 < - - 00001111
AND R16, R17 / /R16 < - - NIBBLE THAP LDI R18, OxF0 / / R16 < - - 11110000
AND R18, R17 / / R18 < - - NIBBLE CAO (BYTE CAO) SWAP R18 / /CHUYEN VE BYTE
THAP
MUL R18, R16 / / R1:RO < - - NIBBLE CAO × NIBBLE THAP (KO DAU) OUT PORTB, RO
//PB (BARLED) < - - R0 (BYTE THAP) RIMP MAIN
;Bai 26 .cseg
. org 0x00
START: LDI R16, 0x00
OUT DDRA, R16 / /PORTA - INPUT - - DIP SW LDI R16, OxFF
OUT PORTA, R16 //DIEN TRO KEO LEN OUT DDRB, R16 / /PORTB -OUTPUT - - BAR LED
OUT PORT, R16
MAIN: IN R17, PINA / / R17 < - - PINA(DIPSW)
LDI R16, 0x0F //R16 < -- 00001111
AND R16, R17 / /R16 < - - NIBBLE THAP SBRC R16, 3 //MO RONG BIT NEU LA SO AM ORI
R16, OxFO
LDI R18, OxF0 / /R16 < - - 11110000
AND R18, R17 / /R18 < - - NIBBLE CAO(BYTE CAO) SWAP R18 / /CHUYEN VE BYTE THAP
SBRC R18, 3 / /MO RONG BIT NEU LA SO AM ORI R18, OxFO
MULS R18, R16 // RI:RO <- - NIBBLE CAO X NIBBLE THAP (CO DAU) OUT PORTB, RO //
PB (BARLED) < - - RO (BYTE THAP) RIMP MAIN
Bài 3

{T (4x250-1)+41×8-1 +1 +4 (CALL) +4(RET) = 8032 MC sai so 32MC


;{L (4x249-1)+4]x8-1 +1 +4 (CALL) +4 (RET) = 8000 MC sai so OMC
DELAYIMS:
LDI R16, 8
LP1:
;1MC
LDI R17, 249;1MC
LP2:
DEC R17
;1MC
NOP
BRNE LP2
DEC R16
BRNE LP1
RET
:2 /1MC
- jIMC
;AMC
DELAY1OMS: LDI R18, 10 LP3:
CALL DELAYIMS
DEC R18
BRNE LP3
RET
DELAY100MS: LDI R18, 100 LP4:
CALL DELAYIMS
DEC R18
BRNE LP4
RET
;1000 = 4×250
;{ (8002x250-1)+4×4 -1 +1 +4(CALL) +4(RET) = 8002020 MC sai so 2020MC DELAYIS:
LDI R18, 4 ;1MC
LP5:
LDI R19, 250 ;1MC
LP6:
RCALL DELAYIMS; 7999MC DEC R19
;1MC
BRNE LP6
;2/1MC
DEC R18
BRNE LP5
RET
;AMC
; INPUT: R16 Thoi gian delay = R16.100us
------ -
DELAY US:
MOV R15, R16 ;1MC n?p data cho R15
LDI R16,200 ;1MC s? d?ng R16
L1: MOV R14, R16 ;1MC n?p data cho R14 L2: DEC R14 ;1MC NOP ;1MC BRNE L2;2/1MC DEC
R15 ;1MC BRNE L1 ; 2/1MC RET ;4MC

Bài 4

.include "m324padef.inc" ; Include Atmega324pa definitions


•DEF DATAR = R20 ;KHAI BÁO THANH GHI CHÚA DATA CÂN DICH
• EQU SPORT = PORTA; KHAI BAO PORTA DIEU KHIEN
.EQU SRDDR = DDRA
•EQU SDI = 0 ; PAO
.EOU LACK = 1
.EQU CLK = 2
.EQU MR = 3 ;MR NHÄN 0 = XOÁ MAIN:
RCALL INITPORT
RCALL XOADATA
LOOP:
RCALL DELAY500MS
LDI DATAR, 0B10000000 RCALL SANGDAN LDI DATAR, 0B11111111 RCALL TATDAN
RJMP LOOP
INITPORT:
LDI R16, OXOF; BAT 4 CHAN DIEU KHIEN LA OUTPUT OUT SRDDR, R16 RET
XOADATA:
CBI SPORT, MR RCALL DELAY500MS SBI SPORT, MR
TATDAN:
LDI R19, 9 ;DEM HIEN THI 8 LAN LOOPLACK:
LDI R18, 8; DÊM DICH 8 BIT
MOV R15, DATAR ; THANH GHI CAC TRANG THAI HIEN THI LSR DATAR; THAY DÖI
CHIEU
LOOPCLK:
SBRC R15, 7 ;KIEM TRA BIT 7(0) THANH GHI DATA SBI SPORT, SDI
SBI SPORT, CLK ; DICH BIT CBI SPORT, CLK
LSL R15 ;DICH TRAI (PHAI)THAN GHI TRANG THAI CBI SPORT, SDI DEC R18
BRNE LOOPCLK
SBI SPORT, LACK ;HIEN THI RA BAR CBI SPORT, LACK RCALL DELAY500MS DEC R19
BRNE LOOPLACK RET
SANGDAN:
LDI R19, 8 ;DÊM HIEN THI 8 LAN LOOPLACK2:
LDI R18, 8; DEM DICH 8 BIT
MOV R15, DATAR ;THANH GHI CAC TRANG THAI HIEN THI ASR DATAR; THAY DÖI
CHIEU
LOOPCLK2:
SBRC R15, 7 ;KIEM TRA BIT 7(0) THANH GHI DATA SBI SPORT, SDI
SBI SPORT, CLK; DICH BIT CBI SPORT, CLK
LSL R15 ;DICH TRAI(PHAI)THANH GHI TRANG THAI CBI SPORT, SDI DEC R18
BRNE LOOPCLK2
SBI SPORT, LACK ;HIEN THI RA BAR CBI SPORT, LACK RCALL DELAY500MS DEC R19
BRNE LOOPLACK2
RET
§{I (4×250-1)+4]×8-1 +1 +4 (CALL) +4(RET) = 8032 MC sai so 32MC ;{[ (4×249-1)+4]x8-1 +1 +4
(CALL) +4(RET) = 8000 MC sai so OMC DELAYIMS:
PUSH R16
PUSH R17
LDI R16, 8 ;1MC LP1:
LDI R17, 249;1MC
LP2:
DEC R17
;1MC
NOP
BRNE LP2
DEC R16
;1MC
BRNE LP1
;2/1MC
POP R17
POP R16
RET
;AMC
DELAY500MS:
PUSH R18
PUSH R19
;AMC
LDI R18, 2
LP5:
LDI R19, 250;1MC
LP6:
RCALL DELAYIMS; 7999MC DEC R19
BRNE LP6
DEC R18
BRNE LP5
;1MC
:211MC HAC
;1MC 2/1MC
POP R19
POP R18
RET
;AMC

DELAY500MS:
PUSH R18
PUSH R19
;AMC
LDI R18, 2
LP5:
LDI R19, 250;1MC
LP6:
RCALL DELAYIMS; 7999MC DEC R19
BRNE LP6
DEC R18
BRNE LP5
;1MC
:211MC HAC
;1MC 2/1MC
POP R19
POP R18
RET
;AMC
OUT_LCD4:
OUT LCDPORT.R17
SBI LCDPORT, EN CBI LCDPORT, EN RET
OUT_LCD:
LDI R16,1 ;chò 100us
RCALL DELAY US
IN R16, LCDPORT ;doc PORT LCD ANDI R16, (1<<RS) ;loc bit R$ PUSH R16 ;cât R16
PUSH R17 ;cât R17
ANDI R17,$FO ;lay 4 bit cao OR R17, R16 ;ghép bit RS RCALL OUT LCD4 ;ghi ra LCD LDI
R16,1 ;chò 100us
RCALL DELAY US
POP R17 ;phuc hôi R17, r16
POP R16
SWAP R17 ;dao byte thäp lênh lên
ANDI R17,$FO ;l?y 4 bit th?p chuy?n thänh cao OR R17,R16 ;ghép bit RS RCALL
OUT_LCD4 ;ghi ra LCD RET
Bài 5
RCALL DELAY_ US ;ctc delay 100usxR16
LDI R16,250 ;delay 25ms
RCALL DELAY US
LDI R16, OXFF ;SET OUTPUT CHO PORTLCD OUT LCDDDR, R16
CBI LCDPORT, RS ;RS=0 ghi I?nh
LDI R17,$30 ;mã lênh=$30 lân 1
RCALL OUT LCD4
LDI R16,42 ;delay 4.2ms
RCALL DELAY US CBI LCDPORT, R$
LDI R17,$30 ;ma lênh=$30 lân 2
CALL OUT LCD4
LDI R16,2 ;delay 200us
RCALL DELAY US CBI LCDPORT, RS
LDI R17, $20 ;mã lênh=$20
RCALL OUT LCD4
RET
INIT LCD4:
CBI LCDPORT, RS ;RS=0 ghi 1?nh
LDI R17, $28 ;Function set - giao tiep 4 bit, 1 döng, font 5×8
RCALL OUT LCD
CBI LCDPORT, RS ;RS=0 ghi I?nh
LDI R17,$01 ;Clear display
RCALL OUT LCD
LDI R16,20 ;ch? 2ms sau 1?nh Clear display
CALL DELAY US
CBI LCDPORT, RS ;RS=0 ghi I?nh
LDI R17,$OC ;hiên man hinh, tat con tro
RCALL OUT LCD
CBI LCDPORT, RS ;RS=0 ghi 1?nh
LDI R17, $06 ;con tró dich phái sau moi lân doc/ghi
CALL OUT LCD
RET
Xuât so BCD 2 nibble trong

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