STP14NF10

N-channel 100 V - 0.115 Ω - 15 A - TO-220

low gate charge STripFET™ II Power MOSFET

Features
Type VDSS RDS(on) max ID
STP14NF10 100 V < 0.13 Ω 15 A

■ Exceptional dv/dt capability

■ 100% avalanche tested 2
3
1
■ Application oriented characterization
TO-220

Application
■ Switching applications

Description
This Power MOSFET series realized with Figure 1. Internal schematic diagram
STMicroelectronics unique STripFET™ process
has specifically been designed to minimize input
capacitance and gate charge. It is therefore
suitable as primary switch in advanced high-
efficiency, high-frequency isolated DC-DC
converters for telecom and computer applications.
It is also intended for any applications with low
gate drive requirements.

Table 1. Device summary

Order code Marking Package Packaging

STP14NF10 P14NF10 TO-220 Tube

April 2008 Rev 4 1/12

www.st.com 12
Contents STP14NF10

Contents

1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) ............................. 6

3 Test circuits .............................................. 8

4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

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STP14NF10 Electrical ratings

1 Electrical ratings

Table 2. Absolute maximum ratings

Symbol Parameter Value Unit

VDS Drain-source voltage (VGS = 0) 100 V

VGS Gate- source voltage ± 20 V
ID Drain current (continuous) at TC = 25 °C 15 A
ID Drain current (continuous) at TC = 100 °C 10 A
(1)
IDM Drain current (pulsed) 60 A
Ptot Total dissipation at TC = 25 °C 60 W
Derating factor 0.4 W/°C
dv/dt (2) Peak diode recovery voltage slope 9 V/ns
EAS (3) Single pulse avalanche energy 70 mJ
Tstg Storage temperature -55 to 175 °C
Tj Max. operating junction temperature 175 °C
1. Pulse width limited by safe operating area.
2. ISD ≤ 14A, di/dt ≤ 300A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX
3. Starting Tj = 25 °C, ID = 15A, VDD = 50V

Table 3. Thermal data

Symbol Parameter Value Unit

Rthj-case Thermal resistance junction-case max 2.5 °C/W

Rthj-amb Thermal resistance junction-ambient max 62.5 °C/W
TJ Maximum lead temperature for soldering purpose 300 °C

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Electrical characteristics STP14NF10

2 Electrical characteristics

(TCASE=25 °C unless otherwise specified)

Table 4. On/off states

Symbol Parameter Test conditions Min. Typ. Max. Unit

Drain-source
V(BR)DSS ID = 250 µA, VGS =0 100 V
breakdown voltage
VDS = max ratings
Zero gate voltage 1 µA
IDSS VDS = max ratings,
drain current (VGS = 0) 10 µA
TC = 125 °C
Gate-body leakage
IGSS VGS = ± 20 V ±100 nA
current (VDS = 0)
VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 2 3 4 V
Static drain-source on
RDS(on) VGS = 10 V, ID = 7 A 0.115 0.13 Ω
resistance

Table 5. Dynamic
Symbol Parameter Test conditions Min. Typ. Max. Unit

Forward
gfs (1) VDS = 15 V, ID = 7 A 20 S
transconductance
Input capacitance
Ciss 460 pF
Output capacitance VDS = 25 V, f = 1 MHz,
Coss 70 pF
Reverse transfer VGS = 0
Crss 30 pF
capacitance
td(on) Turn-on delay time 16 ns
VDD = 50 V, ID = 7 A
tr Rise time 25 ns
RG = 4.7 Ω VGS = 10 V
td(off) Turn-off delay time 32 ns
(see Figure 14)
tf Fall time 8 ns
Qg Total gate charge VDD = 80 V, ID = 12 A, 15.5 21 nC
Qgs Gate-source charge VGS = 10 V 3.7 nC
Qgd Gate-drain charge (see Figure 15) 4.7 nC
1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%.

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STP14NF10 Electrical characteristics

Table 6. Source drain diode

Symbol Parameter Test conditions Min. Typ. Max. Unit

Source-drain current
ISD 15 A
Source-drain current
ISDM (1) 60 A
(pulsed)
VSD (2) Forward on voltage ISD = 14 A, VGS = 0 1.5 V
ISD = 14 A,
trr Reverse recovery time 90 ns
di/dt = 100 A/µs,
Qrr Reverse recovery charge 230 nC
VDD = 50 V, Tj = 150 °C
IRRM Reverse recovery current 5 A
(see Figure 16)
1. Pulse width limited by safe operating area.
2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%

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Electrical characteristics STP14NF10

2.1 Electrical characteristics (curves)

Figure 2. Safe operating area Figure 3. Thermal impedance

Figure 4. Output characteristics Figure 5. Transfer characteristics

Figure 6. Transconductance Figure 7. Static drain-source on resistance

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STP14NF10 Electrical characteristics

Figure 8. Gate charge vs gate-source voltage Figure 9. Capacitance variations

Figure 10. Normalized gate threshold voltage Figure 11. Normalized on resistance vs
vs temperature temperature

Figure 12. Source-drain diode forward Figure 13. Normalized BVDSS vs temperature
characteristics

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Test circuits STP14NF10

3 Test circuits

Figure 14. Switching times test circuit for Figure 15. Gate charge test circuit
resistive load

Figure 16. Test circuit for inductive load Figure 17. Unclamped Inductive load test
switching and diode recovery times circuit

Figure 18. Unclamped inductive waveform Figure 19. Switching time waveform

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STP14NF10 Package mechanical data

4 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK®

packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com

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Package mechanical data STP14NF10

TO-220 mechanical data

mm inch
Dim
Min Typ Max Min Typ Max
A 4.40 4.60 0.173 0.181
b 0.61 0.88 0.024 0.034
b1 1.14 1.70 0.044 0.066
c 0.48 0.70 0.019 0.027
D 15.25 15.75 0.6 0.62
D1 1.27 0.050
E 10 10.40 0.393 0.409
e 2.40 2.70 0.094 0.106
e1 4.95 5.15 0.194 0.202
F 1.23 1.32 0.048 0.051
H1 6.20 6.60 0.244 0.256
J1 2.40 2.72 0.094 0.107
L 13 14 0.511 0.551
L1 3.50 3.93 0.137 0.154
L20 16.40 0.645
L30 28.90 1.137
∅P 3.75 3.85 0.147 0.151
Q 2.65 2.95 0.104 0.116

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STP14NF10 Revision history

5 Revision history

Table 7. Document revision history

Date Revision Changes

05-Feb-2004 1 First version

21-Jun-2004 2 Preliminary version
19-Jun-2006 3 New template, no content change
20-Mar-2008 4 Removed packages: D²PAK and TO-220FP

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 STP14NF10

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