MC9S08DZ60

MC9S08DZ60 MC9S08DZ48 MC9S08DZ32 MC9S08DZ16
Data Sheet
HCS08 Microcontrollers
MC9S08DZ60 Rev. 4 6/2008
freescale.com
MC9S08DZ60 Series Features

8-Bit HCS08 Central Processor Unit (CPU)
40-MHz HCS08 CPU (20-MHz bus) HC08 instruction set with added BGND instruction Support for up to 32 interrupt/reset sources
Peripherals
ADC 24-channel, 12-bit resolution, 2.5 s conversion time, automatic compare function, temperature sensor, internal bandgap reference channel ACMPx Two analog comparators with selectable interrupt on rising, falling, or either edge of comparator output; compare option to xed internal bandgap reference voltage MSCAN CAN protocol - Version 2.0 A, B; standard and extended data frames; Support for remote frames; Five receive buffers with FIFO storage scheme; Flexible identier acceptance lters programmable as: 2 x 32-bit, 4 x 16-bit, or 8 x 8-bit SCIx Two SCIs supporting LIN 2.0 Protocol and SAE J2602 protocols; Full duplex non-return to zero (NRZ); Master extended break generation; Slave extended break detection; Wakeup on active edge SPI Full-duplex or single-wire bidirectional; Double-buffered transmit and receive; Master or Slave mode; MSB-rst or LSB-rst shifting IIC Up to 100 kbps with maximum bus loading; Multi-master operation; Programmable slave address; General Call Address; Interrupt driven byte-by-byte data transfer TPMx One 6-channel (TPM1) and one 2-channel (TPM2); Selectable input capture, output compare, or buffered edge-aligned PWM on each channel RTC (Real-time counter) 8-bit modulus counter with binary or decimal based prescaler; Real-time clock capabilities using external crystal and RTC for precise time base, time-of-day, calendar or task scheduling functions; Free running on-chip low power oscillator (1 kHz) for cyclic wake-up without external components
On-Chip Memory
Flash read/program/erase over full operating voltage and temperature MC9S08DZ60 = 60K MC9S08DZ48 = 48K MC9S08DZ32 = 32K MC9S08DZ16 = 16K Up to 2K EEPROM in-circuit programmable memory; 8-byte single-page or 4-byte dual-page erase sector; Program and Erase while executing Flash; Erase abort Up to 4K random-access memory (RAM)
Power-Saving Modes
Two very low power stop modes Reduced power wait mode Very low power real time interrupt for use in run, wait, and stop
Clock Source Options

Oscillator (XOSC) Loop-control Pierce oscillator; Crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz Multi-purpose Clock Generator (MCG) PLL and FLL modes (FLL capable of 1.5% deviation using internal temperature compensation); Internal reference clock with trim adjustment (trimmed at factory, with trim value stored in ash); External reference with oscillator/resonator options
Input/Output
53 general-purpose input/output (I/O) pins and 1 input-only pin 24 interrupt pins with selectable polarity on each pin Hysteresis and congurable pull device on all input pins. Congurable slew rate and drive strength on all output pins.
System Protection
Watchdog computer operating properly (COP) reset with option to run from backup dedicated 1-kHz internal clock source or bus clock Low-voltage detection with reset or interrupt; selectable trip points Illegal opcode detection with reset Illegal address detection with reset Flash block protect Loss-of-lock protection
Package Options
64-pin low-prole quad at-pack (LQFP) 10x10 mm 48-pin low-prole quad at-pack (LQFP) 7x7 mm 32-pin low-prole quad at-pack (LQFP) 7x7 mm
Development Support
Single-wire background debug interface On-chip, in-circuit emulation (ICE) with real-time bus capture
MC9S08DZ60 Data Sheet

Covers MC9S08DZ60 MC9S08DZ48 MC9S08DZ32 MC9S08DZ16
MC9S08DZ60 Rev. 4 6/2008
Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. Freescale Semiconductor, Inc., 2007-2008. All rights reserved.
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/
The following revision history table summarizes changes contained in this document.
Revision Number
1 2
Revision Date
6/2006 9/2007
Description of Changes
Advance Information for alpha samples customers Product Launch. Removed the 64-pin QFN package. Changed from standard to extended mode for MSCAN registers in register summary. Corrected Block diagrams for SCI. Updated the latest Temp Sensor information. Made FTSTMOD reserved. Updated device to use the ADC 12-bit module. Revised the MCG module. Updated the CPU Instruction Set table. Updated the TPM block module to version 3. Added the TPM block module version 2 as an appendix for devices using 3M05C (or earlier) mask sets. Heavily revised the Electricals appendix. Removed two tables that were inadvertently included in the MC9S08DZ60 version of the book. Sustaining update. Incorporated PS Issues # 2765, 3177, 3236, 3292, 3311, 3312, 3326, 3335, 3345, 3382, 2795, 3382 and 3386 PLL Jitter Spec update. Also, added internal reference clock trim adjustment statement to Features page. Updated the TPM module to the latest version. Adjusted values in Table A-13 Control Timing row 2 and in Table A-6 DC Characteristics row 24 so that it references 5.0 V instead of 3.0 V.
3 4
10/2007 6/2008
Freescale Semiconductor, Inc., 2007-2008. All rights reserved. This product incorporates SuperFlash Technology licensed from SST.
MC9S08DZ60 Series Data Sheet, Rev. 4 6 Freescale Semiconductor
List of Chapters
Chapter Title Page
Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12 Chapter 13 Chapter 14 Chapter 15 Chapter 16 Chapter 17 Appendix A Appendix B Appendix C
Device Overview .............................................................................. 21 Pins and Connections ..................................................................... 27 Modes of Operation ......................................................................... 35 Memory ............................................................................................. 41 Resets, Interrupts, and General System Control.......................... 69 Parallel Input/Output Control.......................................................... 85 Central Processor Unit (S08CPUV3) ............................................ 115 Multi-Purpose Clock Generator (S08MCGV1) ............................. 135 Analog Comparator (S08ACMPV3) .............................................. 167 Analog-to-Digital Converter (S08ADC12V1)................................ 173 Inter-Integrated Circuit (S08IICV2) ............................................... 199 Freescale Controller Area Network (S08MSCANV1) .................. 219 Serial Peripheral Interface (S08SPIV3) ........................................ 273 Serial Communications Interface (S08SCIV4)............................. 289 Real-Time Counter (S08RTCV1) ................................................... 309 Timer Pulse-Width Modulator (S08TPMV3) ................................. 319 Development Support ................................................................... 347 Electrical Characteristics.............................................................. 369 Timer Pulse-Width Modulator (TPMV2) ....................................... 391 Ordering Information and Mechanical Drawings........................ 405
MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 7
Contents
Section Number Title Page
Chapter 1 Device Overview

1.1 1.2 1.3 Devices in the MC9S08DZ60 Series................................................................................................21 MCU Block Diagram .......................................................................................................................22 System Clock Distribution ...............................................................................................................24
Chapter 2 Pins and Connections

2.1 2.2 Device Pin Assignment ....................................................................................................................27 Recommended System Connections ................................................................................................30 2.2.1 Power ................................................................................................................................31 2.2.2 Oscillator ...........................................................................................................................31 2.2.3 RESET ..............................................................................................................................31 2.2.4 Background / Mode Select (BKGD/MS) ..........................................................................32 2.2.5 ADC Reference Pins (VREFH, VREFL) ..............................................................................32 2.2.6 General-Purpose I/O and Peripheral Ports ........................................................................32
Chapter 3 Modes of Operation

3.1 3.2 3.3 3.4 3.5 3.6 Introduction ......................................................................................................................................35 Features ............................................................................................................................................35 Run Mode.........................................................................................................................................35 Active Background Mode.................................................................................................................35 Wait Mode ........................................................................................................................................36 Stop Modes.......................................................................................................................................37 3.6.1 Stop3 Mode .......................................................................................................................37 3.6.2 Stop2 Mode .......................................................................................................................38 3.6.3 On-Chip Peripheral Modules in Stop Modes ....................................................................39
Chapter 4 Memory
4.1 4.2 4.3 4.4 4.5 MC9S08DZ60 Series Memory Map ................................................................................................41 Reset and Interrupt Vector Assignments ..........................................................................................42 Register Addresses and Bit Assignments.........................................................................................44 RAM.................................................................................................................................................52 Flash and EEPROM .........................................................................................................................52 4.5.1 Features .............................................................................................................................52
Section Number
4.5.2 4.5.3 4.5.4 4.5.5 4.5.6 4.5.7 4.5.8 4.5.9 4.5.10 4.5.11
Title
Page
Program and Erase Times .................................................................................................53 Program and Erase Command Execution .........................................................................53 Burst Program Execution ..................................................................................................55 Sector Erase Abort ............................................................................................................57 Access Errors ....................................................................................................................58 Block Protection ................................................................................................................59 Vector Redirection ............................................................................................................59 Security .............................................................................................................................59 EEPROM Mapping ...........................................................................................................61 Flash and EEPROM Registers and Control Bits ...............................................................61
Chapter 5 Resets, Interrupts, and General System Control

5.1 5.2 5.3 5.4 5.5 Introduction ......................................................................................................................................69 Features ............................................................................................................................................69 MCU Reset.......................................................................................................................................69 Computer Operating Properly (COP) Watchdog..............................................................................70 Interrupts ..........................................................................................................................................71 5.5.1 Interrupt Stack Frame .......................................................................................................72 5.5.2 External Interrupt Request (IRQ) Pin ...............................................................................72 5.5.3 Interrupt Vectors, Sources, and Local Masks ....................................................................73 Low-Voltage Detect (LVD) System .................................................................................................75 5.6.1 Power-On Reset Operation ...............................................................................................75 5.6.2 Low-Voltage Detection (LVD) Reset Operation ...............................................................75 5.6.3 Low-Voltage Warning (LVW) Interrupt Operation ...........................................................75 MCLK Output ..................................................................................................................................75 Reset, Interrupt, and System Control Registers and Control Bits ....................................................76 5.8.1 Interrupt Pin Request Status and Control Register (IRQSC) ............................................77 5.8.2 System Reset Status Register (SRS) .................................................................................78 5.8.3 System Background Debug Force Reset Register (SBDFR) ............................................79 5.8.4 System Options Register 1 (SOPT1) ................................................................................80 5.8.5 System Options Register 2 (SOPT2) ................................................................................81 5.8.6 System Device Identication Register (SDIDH, SDIDL) ................................................82 5.8.7 System Power Management Status and Control 1 Register (SPMSC1) ...........................83 5.8.8 System Power Management Status and Control 2 Register (SPMSC2) ...........................84
5.6
5.7 5.8
Chapter 6 Parallel Input/Output Control

6.1 6.2 6.3 Port Data and Data Direction ...........................................................................................................85 Pull-up, Slew Rate, and Drive Strength............................................................................................86 Pin Interrupts ....................................................................................................................................87 6.3.1 Edge Only Sensitivity .......................................................................................................87
Section Number
Title
Page
6.4 6.5
6.3.2 Edge and Level Sensitivity ................................................................................................88 6.3.3 Pull-up/Pull-down Resistors .............................................................................................88 6.3.4 Pin Interrupt Initialization .................................................................................................88 Pin Behavior in Stop Modes.............................................................................................................88 Parallel I/O and Pin Control Registers .............................................................................................89 6.5.1 Port A Registers ................................................................................................................90 6.5.2 Port B Registers ................................................................................................................94 6.5.3 Port C Registers ................................................................................................................98 6.5.4 Port D Registers ..............................................................................................................101 6.5.5 Port E Registers ...............................................................................................................105 6.5.6 Port F Registers ...............................................................................................................108 6.5.7 Port G Registers ..............................................................................................................111
Chapter 7 Central Processor Unit (S08CPUV3)

7.1 7.2 Introduction ....................................................................................................................................115 7.1.1 Features ...........................................................................................................................115 Programmers Model and CPU Registers ......................................................................................116 7.2.1 Accumulator (A) .............................................................................................................116 7.2.2 Index Register (H:X) .......................................................................................................116 7.2.3 Stack Pointer (SP) ...........................................................................................................117 7.2.4 Program Counter (PC) ....................................................................................................117 7.2.5 Condition Code Register (CCR) .....................................................................................117 Addressing Modes..........................................................................................................................119 7.3.1 Inherent Addressing Mode (INH) ...................................................................................119 7.3.2 Relative Addressing Mode (REL) ...................................................................................119 7.3.3 Immediate Addressing Mode (IMM) ..............................................................................119 7.3.4 Direct Addressing Mode (DIR) ......................................................................................119 7.3.5 Extended Addressing Mode (EXT) ................................................................................120 7.3.6 Indexed Addressing Mode ..............................................................................................120 Special Operations..........................................................................................................................121 7.4.1 Reset Sequence ...............................................................................................................121 7.4.2 Interrupt Sequence ..........................................................................................................121 7.4.3 Wait Mode Operation ......................................................................................................122 7.4.4 Stop Mode Operation ......................................................................................................122 7.4.5 BGND Instruction ...........................................................................................................123 HCS08 Instruction Set Summary ...................................................................................................124
7.3
7.4
7.5
Chapter 8 Multi-Purpose Clock Generator (S08MCGV1)

8.1 Introduction ....................................................................................................................................135 8.1.1 Features ...........................................................................................................................137
Section Number
8.2 8.3
Title
Page
8.4
8.5
8.1.2 Modes of Operation ........................................................................................................139 External Signal Description ...........................................................................................................139 Register Denition .........................................................................................................................140 8.3.1 MCG Control Register 1 (MCGC1) ...............................................................................140 8.3.2 MCG Control Register 2 (MCGC2) ...............................................................................141 8.3.3 MCG Trim Register (MCGTRM) ...................................................................................142 8.3.4 MCG Status and Control Register (MCGSC) .................................................................143 8.3.5 MCG Control Register 3 (MCGC3) ...............................................................................144 Functional Description ...................................................................................................................146 8.4.1 Operational Modes ..........................................................................................................146 8.4.2 Mode Switching ..............................................................................................................150 8.4.3 Bus Frequency Divider ...................................................................................................151 8.4.4 Low Power Bit Usage .....................................................................................................151 8.4.5 Internal Reference Clock ................................................................................................151 8.4.6 External Reference Clock ...............................................................................................151 8.4.7 Fixed Frequency Clock ...................................................................................................152 Initialization / Application Information .........................................................................................152 8.5.1 MCG Module Initialization Sequence ............................................................................152 8.5.2 MCG Mode Switching ....................................................................................................153 8.5.3 Calibrating the Internal Reference Clock (IRC) .............................................................164
Chapter 9 Analog Comparator (S08ACMPV3)

9.1 Introduction ....................................................................................................................................167 9.1.1 ACMP Conguration Information ..................................................................................167 9.1.2 Features ...........................................................................................................................169 9.1.3 Modes of Operation ........................................................................................................169 9.1.4 Block Diagram ................................................................................................................170 External Signal Description ...........................................................................................................170 Memory Map/Register Denition ..................................................................................................171 9.3.1 ACMPx Status and Control Register (ACMPxSC) .........................................................171 Functional Description ...................................................................................................................172
9.2 9.3 9.4
Chapter 10 Analog-to-Digital Converter (S08ADC12V1)

10.1 Introduction ....................................................................................................................................173 10.1.1 Analog Power and Ground Signal Names ......................................................................173 10.1.2 Channel Assignments ......................................................................................................173 10.1.3 Alternate Clock ...............................................................................................................174 10.1.4 Hardware Trigger ............................................................................................................174 10.1.5 Temperature Sensor ........................................................................................................175 10.1.6 Features ...........................................................................................................................177
Section Number
Title
Page
10.1.7 ADC Module Block Diagram .........................................................................................177 10.2 External Signal Description ...........................................................................................................178 10.2.1 Analog Power (VDDAD) ..................................................................................................179 10.2.2 Analog Ground (VSSAD) .................................................................................................179 10.2.3 Voltage Reference High (VREFH) ...................................................................................179 10.2.4 Voltage Reference Low (VREFL) .....................................................................................179 10.2.5 Analog Channel Inputs (ADx) ........................................................................................179 10.3 Register Denition .........................................................................................................................179 10.3.1 Status and Control Register 1 (ADCSC1) ......................................................................179 10.3.2 Status and Control Register 2 (ADCSC2) ......................................................................181 10.3.3 Data Result High Register (ADCRH) .............................................................................181 10.3.4 Data Result Low Register (ADCRL) ..............................................................................182 10.3.5 Compare Value High Register (ADCCVH) ....................................................................182 10.3.6 Compare Value Low Register (ADCCVL) .....................................................................183 10.3.7 Conguration Register (ADCCFG) ................................................................................183 10.3.8 Pin Control 1 Register (APCTL1) ..................................................................................184 10.3.9 Pin Control 2 Register (APCTL2) ..................................................................................185 10.3.10Pin Control 3 Register (APCTL3) ..................................................................................186 10.4 Functional Description ...................................................................................................................187 10.4.1 Clock Select and Divide Control ....................................................................................188 10.4.2 Input Select and Pin Control ...........................................................................................188 10.4.3 Hardware Trigger ............................................................................................................188 10.4.4 Conversion Control .........................................................................................................188 10.4.5 Automatic Compare Function .........................................................................................191 10.4.6 MCU Wait Mode Operation ............................................................................................191 10.4.7 MCU Stop3 Mode Operation ..........................................................................................192 10.4.8 MCU Stop2 Mode Operation ..........................................................................................192 10.5 Initialization Information ...............................................................................................................193 10.5.1 ADC Module Initialization Example .............................................................................193 10.6 Application Information.................................................................................................................195 10.6.1 External Pins and Routing ..............................................................................................195 10.6.2 Sources of Error ..............................................................................................................196
Chapter 11 Inter-Integrated Circuit (S08IICV2)

11.1 Introduction ....................................................................................................................................199 11.1.1 Features ...........................................................................................................................201 11.1.2 Modes of Operation ........................................................................................................201 11.1.3 Block Diagram ................................................................................................................202 11.2 External Signal Description ...........................................................................................................202 11.2.1 SCL Serial Clock Line ...............................................................................................202 11.2.2 SDA Serial Data Line ................................................................................................202
Section Number
Title
Page
11.3 Register Denition .........................................................................................................................202 11.3.1 IIC Address Register (IICA) ...........................................................................................203 11.3.2 IIC Frequency Divider Register (IICF) ...........................................................................203 11.3.3 IIC Control Register (IICC1) ..........................................................................................206 11.3.4 IIC Status Register (IICS) ...............................................................................................207 11.3.5 IIC Data I/O Register (IICD) ..........................................................................................208 11.3.6 IIC Control Register 2 (IICC2) .......................................................................................208 11.4 Functional Description ...................................................................................................................209 11.4.1 IIC Protocol .....................................................................................................................209 11.4.2 10-bit Address .................................................................................................................213 11.4.3 General Call Address ......................................................................................................214 11.5 Resets .............................................................................................................................................214 11.6 Interrupts ........................................................................................................................................214 11.6.1 Byte Transfer Interrupt ....................................................................................................214 11.6.2 Address Detect Interrupt .................................................................................................214 11.6.3 Arbitration Lost Interrupt ................................................................................................214 11.7 Initialization/Application Information ...........................................................................................216
Chapter 12 Freescale Controller Area Network (S08MSCANV1)

12.1 Introduction ....................................................................................................................................219 12.1.1 Features ...........................................................................................................................221 12.1.2 Modes of Operation ........................................................................................................221 12.1.3 Block Diagram ................................................................................................................222 12.2 External Signal Description ...........................................................................................................222 12.2.1 RXCAN CAN Receiver Input Pin .............................................................................222 12.2.2 TXCAN CAN Transmitter Output Pin .....................................................................222 12.2.3 CAN System ...................................................................................................................222 12.3 Register Denition .........................................................................................................................223 12.3.1 MSCAN Control Register 0 (CANCTL0) ......................................................................223 12.3.2 MSCAN Control Register 1 (CANCTL1) ......................................................................226 12.3.3 MSCAN Bus Timing Register 0 (CANBTR0) ...............................................................227 12.3.4 MSCAN Bus Timing Register 1 (CANBTR1) ...............................................................228 12.3.5 MSCAN Receiver Interrupt Enable Register (CANRIER) .............................................231 12.3.6 MSCAN Transmitter Flag Register (CANTFLG) ..........................................................232 12.3.7 MSCAN Transmitter Interrupt Enable Register (CANTIER) ........................................233 12.3.8 MSCAN Transmitter Message Abort Request Register (CANTARQ) ...........................234 12.3.9 MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK) .................235 12.3.10MSCAN Transmit Buffer Selection Register (CANTBSEL) .........................................235 12.3.11MSCAN Identier Acceptance Control Register (CANIDAC) ......................................236 12.3.12MSCAN Miscellaneous Register (CANMISC) ..............................................................237 12.3.13MSCAN Receive Error Counter (CANRXERR) ............................................................238
Section Number
Title
Page
12.3.14MSCAN Transmit Error Counter (CANTXERR) ..........................................................239 12.3.15MSCAN Identier Acceptance Registers (CANIDAR0-7) ............................................239 12.3.16MSCAN Identier Mask Registers (CANIDMR0CANIDMR7) .................................240 12.4 Programmers Model of Message Storage .....................................................................................241 12.4.1 Identier Registers (IDR0IDR3) ...................................................................................244 12.4.2 IDR0IDR3 for Standard Identier Mapping .................................................................246 12.4.3 Data Segment Registers (DSR0-7) .................................................................................247 12.4.4 Data Length Register (DLR) ...........................................................................................248 12.4.5 Transmit Buffer Priority Register (TBPR) ......................................................................249 12.4.6 Time Stamp Register (TSRHTSRL) .............................................................................249 12.5 Functional Description ...................................................................................................................250 12.5.1 General ............................................................................................................................250 12.5.2 Message Storage .............................................................................................................251 12.5.3 Identier Acceptance Filter .............................................................................................254 12.5.4 Modes of Operation ........................................................................................................261 12.5.5 Low-Power Options ........................................................................................................262 12.5.6 Reset Initialization ..........................................................................................................268 12.5.7 Interrupts .........................................................................................................................268 12.6 Initialization/Application Information ...........................................................................................270 12.6.1 MSCAN initialization .....................................................................................................270 12.6.2 Bus-Off Recovery ...........................................................................................................271
Chapter 13 Serial Peripheral Interface (S08SPIV3)

13.1 Introduction ....................................................................................................................................273 13.1.1 Features ...........................................................................................................................275 13.1.2 Block Diagrams ..............................................................................................................275 13.1.3 SPI Baud Rate Generation ..............................................................................................277 13.2 External Signal Description ...........................................................................................................278 13.2.1 SPSCK SPI Serial Clock ............................................................................................278 13.2.2 MOSI Master Data Out, Slave Data In ......................................................................278 13.2.3 MISO Master Data In, Slave Data Out ......................................................................278 13.2.4 SS Slave Select ...........................................................................................................278 13.3 Modes of Operation........................................................................................................................279 13.3.1 SPI in Stop Modes ..........................................................................................................279 13.4 Register Denition .........................................................................................................................279 13.4.1 SPI Control Register 1 (SPIC1) ......................................................................................279 13.4.2 SPI Control Register 2 (SPIC2) ......................................................................................280 13.4.3 SPI Baud Rate Register (SPIBR) ....................................................................................281 13.4.4 SPI Status Register (SPIS) ..............................................................................................282 13.4.5 SPI Data Register (SPID) ................................................................................................283 13.5 Functional Description ...................................................................................................................284
Section Number
Title
Page
13.5.1 SPI Clock Formats ..........................................................................................................284 13.5.2 SPI Interrupts ..................................................................................................................287 13.5.3 Mode Fault Detection .....................................................................................................287
Chapter 14 Serial Communications Interface (S08SCIV4)

14.1 Introduction ....................................................................................................................................289 14.1.1 SCI2 Conguration Information .....................................................................................289 14.1.2 Features ...........................................................................................................................291 14.1.3 Modes of Operation ........................................................................................................291 14.1.4 Block Diagram ................................................................................................................292 14.2 Register Denition .........................................................................................................................294 14.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBDL) ..........................................................294 14.2.2 SCI Control Register 1 (SCIxC1) ...................................................................................295 14.2.3 SCI Control Register 2 (SCIxC2) ...................................................................................296 14.2.4 SCI Status Register 1 (SCIxS1) ......................................................................................297 14.2.5 SCI Status Register 2 (SCIxS2) ......................................................................................299 14.2.6 SCI Control Register 3 (SCIxC3) ...................................................................................300 14.2.7 SCI Data Register (SCIxD) .............................................................................................301 14.3 Functional Description ...................................................................................................................301 14.3.1 Baud Rate Generation .....................................................................................................301 14.3.2 Transmitter Functional Description ................................................................................302 14.3.3 Receiver Functional Description .....................................................................................303 14.3.4 Interrupts and Status Flags ..............................................................................................305 14.3.5 Additional SCI Functions ...............................................................................................306
Chapter 15 Real-Time Counter (S08RTCV1)

15.1 Introduction ....................................................................................................................................309 15.1.1 RTC Clock Signal Names ...............................................................................................309 15.1.2 Features ...........................................................................................................................311 15.1.3 Modes of Operation ........................................................................................................311 15.1.4 Block Diagram ................................................................................................................312 15.2 External Signal Description ...........................................................................................................312 15.3 Register Denition .........................................................................................................................312 15.3.1 RTC Status and Control Register (RTCSC) ....................................................................313 15.3.2 RTC Counter Register (RTCCNT) ..................................................................................314 15.3.3 RTC Modulo Register (RTCMOD) ................................................................................314 15.4 Functional Description ...................................................................................................................314 15.4.1 RTC Operation Example .................................................................................................315 15.5 Initialization/Application Information ...........................................................................................316
Section Number
Title Chapter 16 Timer Pulse-Width Modulator (S08TPMV3)
Page
16.1 Introduction ....................................................................................................................................319 16.1.1 Features ...........................................................................................................................321 16.1.2 Modes of Operation ........................................................................................................321 16.1.3 Block Diagram ................................................................................................................322 16.2 Signal Description ..........................................................................................................................324 16.2.1 Detailed Signal Descriptions ...........................................................................................324 16.3 Register Denition .........................................................................................................................328 16.3.1 TPM Status and Control Register (TPMxSC) ................................................................328 16.3.2 TPM-Counter Registers (TPMxCNTH:TPMxCNTL) ....................................................329 16.3.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL) ....................................330 16.3.4 TPM Channel n Status and Control Register (TPMxCnSC) ..........................................331 16.3.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) ..........................................333 16.4 Functional Description ...................................................................................................................334 16.4.1 Counter ............................................................................................................................335 16.4.2 Channel Mode Selection .................................................................................................337 16.5 Reset Overview ..............................................................................................................................340 16.5.1 General ............................................................................................................................340 16.5.2 Description of Reset Operation .......................................................................................340 16.6 Interrupts ........................................................................................................................................340 16.6.1 General ............................................................................................................................340 16.6.2 Description of Interrupt Operation ..................................................................................341 16.7 The Differences from TPM v2 to TPM v3.....................................................................................342
Chapter 17 Development Support

17.1 Introduction ....................................................................................................................................347 17.1.1 Forcing Active Background ............................................................................................347 17.1.2 Features ...........................................................................................................................348 17.2 Background Debug Controller (BDC) ...........................................................................................348 17.2.1 BKGD Pin Description ...................................................................................................349 17.2.2 Communication Details ..................................................................................................350 17.2.3 BDC Commands .............................................................................................................354 17.2.4 BDC Hardware Breakpoint .............................................................................................356 17.3 On-Chip Debug System (DBG) .....................................................................................................357 17.3.1 Comparators A and B ......................................................................................................357 17.3.2 Bus Capture Information and FIFO Operation ...............................................................357 17.3.3 Change-of-Flow Information ..........................................................................................358 17.3.4 Tag vs. Force Breakpoints and Triggers .........................................................................358 17.3.5 Trigger Modes .................................................................................................................359 17.3.6 Hardware Breakpoints ....................................................................................................361
Section Number
Title
Page
17.4 Register Denition .........................................................................................................................361 17.4.1 BDC Registers and Control Bits .....................................................................................361 17.4.2 System Background Debug Force Reset Register (SBDFR) ..........................................363 17.4.3 DBG Registers and Control Bits .....................................................................................364
Appendix A Electrical Characteristics

A.1 A.2 A.3 A.4 A.5 A.6 A.7 A.8 A.9 A.10 A.11 A.12 Introduction ...................................................................................................................................369 Parameter Classification ................................................................................................................369 Absolute Maximum Ratings ..........................................................................................................369 Thermal Characteristics .................................................................................................................370 ESD Protection and Latch-Up Immunity ......................................................................................372 DC Characteristics .........................................................................................................................373 Supply Current Characteristics ......................................................................................................375 Analog Comparator (ACMP) Electricals ......................................................................................376 ADC Characteristics ......................................................................................................................376 External Oscillator (XOSC) Characteristics .................................................................................380 MCG Specifications ......................................................................................................................381 AC Characteristics .........................................................................................................................383 A.12.1 Control Timing ...............................................................................................................383 A.12.2 Timer/PWM ....................................................................................................................384 A.12.3 MSCAN ..........................................................................................................................385 A.12.4 SPI ...................................................................................................................................386 A.13 Flash and EEPROM ......................................................................................................................389 A.14 EMC Performance .........................................................................................................................390 A.14.1 Radiated Emissions .........................................................................................................390
Appendix B Timer Pulse-Width Modulator (TPMV2)

B.0.1 Features ...........................................................................................................................391 B.0.2 Block Diagram ................................................................................................................391 B.1 External Signal Description ...........................................................................................................393 B.1.1 External TPM Clock Sources ..........................................................................................393 B.1.2 TPMxCHn TPMx Channel n I/O Pins .......................................................................393 B.2 Register Denition .........................................................................................................................393 B.2.1 Timer Status and Control Register (TPMxSC) ...............................................................394 B.2.2 Timer Counter Registers (TPMxCNTH:TPMxCNTL) ...................................................395 B.2.3 Timer Counter Modulo Registers (TPMxMODH:TPMxMODL) ..................................396 B.2.4 Timer Channel n Status and Control Register (TPMxCnSC) .........................................397 B.2.5 Timer Channel Value Registers (TPMxCnVH:TPMxCnVL) .........................................398 B.3 Functional Description ...................................................................................................................399 B.3.1 Counter ............................................................................................................................399
Section Number
Title
Page
B.3.2 Channel Mode Selection .................................................................................................400 B.3.3 Center-Aligned PWM Mode ...........................................................................................402 B.4 TPM Interrupts ...............................................................................................................................403 B.4.1 Clearing Timer Interrupt Flags .......................................................................................403 B.4.2 Timer Overow Interrupt Description ............................................................................403 B.4.3 Channel Event Interrupt Description ..............................................................................404 B.4.4 PWM End-of-Duty-Cycle Events ...................................................................................404
Appendix C Ordering Information and Mechanical Drawings

C.1 Ordering Information ....................................................................................................................405 C.1.1 MC9S08DZ60 Series Devices ........................................................................................405 C.2 Mechanical Drawings ....................................................................................................................405

MC9S08DZ60 Series devices provide signicant value to customers looking to combine Controller Area Network (CAN) and embedded EEPROM in their applications. This combination will provide lower costs, enhanced performance, and higher quality.
1.1
Devices in the MC9S08DZ60 Series
This data sheet covers members of the MC9S08DZ60 Series of MCUs: MC9S08DZ60 MC9S08DZ48 MC9S08DZ32 MC9S08DZ16 Table 1-1 summarizes the feature set available in the MC9S08DZ60 Series.
Table 1-1. MC9S08DZ60 Series Features by MCU and Pin Count

Feature Flash size (bytes) RAM size (bytes) EEPROM size (bytes) Pin quantity ACMP1 ACMP2 ADC channels DBG IIC IRQ MCG MSCAN RTC SCI1 SCI2 SPI TPM1 channels TPM2 channels XOSC COP Watchdog
1
MC9S08DZ60 60032 4096 2048 64 yes 24 48 yes

1
MC9S08DZ48 49152 3072 1536 32 no 10 64 yes 24 48 yes1 16 32 yes no 10 yes yes yes yes yes yes yes yes yes yes 24 64
MC9S08DZ32 33792 2048 1024 48 yes1 16 32 no 10
MC9S08DZ16 16896 1024 512 48 yes1 16 32 no 10
16
4 2 yes yes
ACMP2O is not available.
1.2
MCU Block Diagram
Figure 1-1 is the MC9S08DZ60 Series system-level block diagram.
HCS08 CORE PORT A CPU BKGD/MS ANALOG COMPARATOR (ACMP1) ACMP1O ACMP1ACMP1+
BDC
BKP
PTA7/PIA7/ADP7/IRQ PTA6/PIA6/ADP6 PTA5/PIA5/ADP5 PTA4/PIA4/ADP4 PTA3/PIA3/ADP3/ACMP1O PTA2/PIA2/ADP2/ACMP1PTA1/PIA1/ADP1/ACMP1+ PTA0/PIA0/ADP0/MCLK PTB7/PIB7/ADP15 PTB6/PIB6/ADP14 PTB5/PIB5/ADP13 PTB4/PIB4/ADP12 PTB3/PIB3/ADP11 PTB2/PIB2/ADP10 PTB1/PIB1/ADP9 PTB0/PIB0/ADP8 PTC7/ADP23 PTC6/ADP22 PTC5/ADP21 PTC4/ADP20 PTC3/ADP19 PTC2/ADP18 PTC1/ADP17 PTC0/ADP16 PTD7/PID7/TPM1CH5 PTD6/PID6/TPM1CH4 PTD5/PID5/TPM1CH3 PTD4/PID4/TPM1CH2 PTD3/PID3/TPM1CH1 PTD2/PID2/TPM1CH0 PTD1/PID1/TPM2CH1 PTD0/PID0/TPM2CH0 PTE7/RxD2/RXCAN PTE6/TxD2/TXCAN PTE5/SDA/MISO PTE4/SCL/MOSI PTE3/SPSCK PTE2/SS PTE1/RxD1 PTE0/TxD1 PTF7 PTF6/ACMP2O PTF5/ACMP2PTF4/ACMP2+ PTF3/TPM2CLK/SDA PTF2/TPM1CLK/SCL PTF1/RxD2 PTF0/TxD2 PTG5 PTG4 PTG3 PTG2 PTG1/XTAL PTG0/EXTAL
HCS08 SYSTEM CONTROL RESET RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT COP INT VREFH VREFL VDDA VSSA LVD IRQ 24-CHANNEL,12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) 8 IRQ ADP7-ADP0 ADP15-ADP8 ADP23-ADP16 PORT C 2-CHANNEL TIMER/PWM MODULE (TPM2) USER EEPROM MC9S08DZ60 = 2K CONTROLLER AREA NETWORK (MSCAN) SERIAL PERIPHERAL INTERFACE MODULE (SPI) SERIAL COMMUNICATIONS INTERFACE (SCI1) ANALOG COMPARATOR (ACMP2) IIC MODULE (IIC) SERIAL COMMUNICATIONS INTERFACE (SCI2) MULTI-PURPOSE CLOCK GENERATOR (MCG) OSCILLATOR (XOSC) - VREFH/VREFL internally connected to VDDA/VSSA in 48-pin and 32-pin packages - VDD and VSS pins are each internally connected to two pads in 32-pin package XTAL EXTAL TPM2CH1, TPM2CH0 TPM2CLK RxCAN TXCAN MISO MOSI SPSCK SS RxD1 TxD1 ACMP2O ACMP2ACMP2+ SDA SCL RxD2 TxD2 DEBUG MODULE (DBG) REAL-TIME COUNTER (RTC) VDD VDD VSS VSS VOLTAGE REGULATOR
- Pin not connected in 48-pin and 32-pin packages - Pin not connected in 32-pin package
Figure 1-1. MC9S08DZ60 Block Diagram
PORT G
PORT F
PORT E
USER RAM MC9S08DZ60 = 4K
PORT D
USER Flash MC9S08DZ60 = 60K MC9S08DZ48 = 48K MC9S08DZ32 = 32K MC9S08DZ16 = 16K
6-CHANNEL TIMER/PWM MODULE (TPM1)
TPM1CH5 TPM1CH0 6 TPM1CLK
PORT B
Table 1-2 provides the functional version of the on-chip modules.

Table 1-2. Module Versions
Module Central Processor Unit Multi-Purpose Clock Generator Analog Comparator Analog-to-Digital Converter Inter-Integrated Circuit Freescales CAN Serial Peripheral Interface Serial Communications Interface Real-Time Counter Timer Pulse Width Modulator Debug Module
1
Version (CPU) (MCG) (ACMP) (ADC) (IIC) (MSCAN) (SPI) (SCI) (RTC) (TPM) (DBG) 3 1 3 1 2 1 3 4 1 31 2
3M05C and older masks have TPM version 2.
1.3
System Clock Distribution
Figure 1-2 shows a simplied clock connection diagram. Some modules in the MCU have selectable clock inputs as shown. The clock inputs to the modules indicate the clock(s) that are used to drive the module function. The following are the clocks used in this MCU: BUSCLK The frequency of the bus is always half of MCGOUT. LPO Independent 1-kHz clock that can be selected as the source for the COP and RTC modules. MCGOUT Primary output of the MCG and is twice the bus frequency. MCGLCLK Development tools can select this clock source to speed up BDC communications in systems where BUSCLK is congured to run at a very slow frequency. MCGERCLK External reference clock can be selected as the RTC clock source. It can also be used as the alternate clock for the ADC and MSCAN. MCGIRCLK Internal reference clock can be selected as the RTC clock source. MCGFFCLK Fixed frequency clock can be selected as clock source for the TPM1 and TPM2. TPM1CLK External input clock source for TPM1. TPM2CLK External input clock source for TPM2.
Chapter 1 Device Overview TPM1CLK 1 kHZ LPO MCGERCLK MCGIRCLK TPM1 TPM2CLK TPM2 IIC SCI1 SCI2 SPI
RTC
COP
MCGFFCLKVALID MCG MCGFFCLK
2 2
BUSCLK
1 0
FFCLK*
MCGOUT MCGLCLK XOSC CPU
BDC
ADC
MSCAN
FLASH
EEPROM
EXTAL
XTAL
* The xed frequency clock (FFCLK) is internally synchronized to the bus clock and must not exceed one half of the bus clock frequency.
ADC has min and max frequency requirements.See the ADC chapter and electricals appendix for details.
Flash and EEPROM have frequency requirements for program and erase operation. See the electricals appendix for details.
Figure 1-2. MC9S08DZ60 System Clock Distribution Diagram

This section describes signals that connect to package pins. It includes pinout diagrams, recommended system connections, and detailed discussions of signals.
2.1
Device Pin Assignment
This section shows the pin assignments for MC9S08DZ60 Series MCUs in the available packages.
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PTA6/PIA6/ADP6 PTB5/PIB5/ADP13 PTA5/PIA5/ADP5 PTC4/ADP20 PTB4/PIB4/ADP12 PTA4/PIA4/ADP4 VDDA VREFH VREFL VSSA PTA3/PIA3/ADP3/ACMP1O PTB3/PIB3/ADP11 PTC3/ADP19 PTA2/PIA2/ADP2/ACMP1PTB2/PIB2/ADP10 PTA1/PIA1/ADP1/ACMP1+ 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
PTE2/SS PTE3/SPSCK PTE4/SCL/MOSI PTE5/SDA/MISO PTG2 PTG3 PTF0/TxD2 PTF1/RxD2 PTF2/TPM1CLK/SCL PTF3/TPM2CLK/SDA PTG4 PTG5 PTE6/TxD2/TXCAN PTE7/RxD2/RXCAN PTD0/PID0/TPM2CH0 PTD1/PID1/TPM2CH1
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PTB6/PIB6/ADP14 PTC5/ADP21 PTA7/PIA7/ADP7/IRQ PTC6/ADP22 PTB7/PIB7/ADP15 PTC7/ADP23 VDD VSS PTG0/EXTAL PTG1/XTAL RESET PTF4/ACMP2+ PTF5/ACMP2PTF6/ACMP2O PTE0/TxD1 PTE1/RxD1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
64-Pin LQFP
PTB1/PIB1/ADP9 PTC2/ADP18 PTA0/PIA0/ADP0/MCLK PTC1/ADP17 PTB0/PIB0/ADP8 PTC0/ADP16 BKGD/MS PTD7/PID7/TPM1CH5 PTD6/PID6/TPM1CH4 VDD VSS PTF7 PTD5/PID5/TPM1CH3 PTD4/PID4/TPM1CH2 PTD3/PID3/TPM1CH1 PTD2/PID2/TPM1CH0
Figure 2-1. 64-Pin LQFP
48 47 46 45 44 43 42 41 40 39 38 37
PTA6/PIA6/ADP6 PTB5/PIB5/ADP13 PTA5/PIA5/ADP5 PTB4/PIB4/ADP12 PTA4/PIA4/ADP4 VDDA/VREFH VSSA/VREFL PTA3/PIA3/ADP3/ACMP1O PTB3/PIB3/ADP11 PTA2/PIA2/ADP2/ACMP1PTB2/PIB2/ADP10 PTA1/PIA1/ADP1/ACMP1+ PTB6/PIB6/ADP14 PTA7/PIA7/ADP7/IRQ PTB7/PIB7/ADP15 VDD VSS PTG0/EXTAL PTG1/XTAL RESET PTF4/ACMP2+ PTF5/ACMP2PTE0/TxD1 PTE1/RxD1 36 35 34 33 32 31 30 29 28 27 26 25
VREFH and VREFL are internally connected to VDDA and VSSA, respectively.
PTE2/SS PTE3/SPSCK PTE4/SCL/MOSI PTE5/SDA/MISO PTF0/TxD2 PTF1/RxD2 PTF2/TPM1CLK/SCL PTF3/TPM2CLK/SDA PTE6/TxD2/TXCAN PTE7/RxD2/RXCAN PTD0/PID0/TPM2CH0 PTD1/PID1/TPM2CH1
13 14 15 16 17 18 19 20 21 22 23 24
1 2 3 4 5 6 7 8 9 10 11 12
48-Pin LQFP
PTB1/PIB1/ADP9 PTA0/PIA0/ADP0/MCLK PTB0/PIB0/ADP8 BKGD/MS PTD7/PID7/TPM1CH5 PTD6/PID6/TPM1CH4 VDD VSS PTD5/PID5/TPM1CH3 PTD4/PID4/TPM1CH2 PTD3/PID3/TPM1CH1 PTD2/PID2/TPM1CH0
PTA3/ADP3/ACMPO
PTA5/PIA5/ADP5
PTA4/PIA4/ADP4
VDDA/VREFH
VSSA/VREFL
32 PTA7/PIA7/ADP7/IRQ 1 VDD VSS PTG0/EXTAL PTG1/XTAL RESET PTE0/TxD1 PTE1/RxD1 8 10 9 PTE6/TxD2/TXCAN PTD0/PID0/TPM2CH0 PTE7/RxD2/RXCAN PTE5/SDA/MISO PTE4/SCL/MOSI PTE3/SPSCK PTE2/SS 11 12 13 14 15 2 3 4 5 6 7 31 30 29 28 27 26
25 24 PTB1/PIB1/ADP9 23 22 21 PTA0/PIA0/ADP0/MCLK PTB0/PIB0/ADP8 BKGD/MS PTD5/PID5/TPM1CH3 PTD4/PID4/TPM1CH2 PTD3/PID3/TPM1CH1 17 PTD2/PID2/TPM1CH0 16 PTD1/PID1/TPM2CH1
32-Pin LQFP
20 19 18
VREFH and VREFL are internally connected to VDDA and VSSA, respectively.
PTA1/ADP1/ACMP+
PTA2/ADP2/ACMP-
PTA6/PIA6/ADP6
2.2
Recommended System Connections
Figure 2-4 shows pin connections that are common to MC9S08DZ60 Series application systems.
MC9S08DZ60 VDD + 5V CBLK + 10 F CBY 0.1 F VSS SYSTEM POWER VDDA VREFH VREFL VSSA IRQ PORT A PTA0/PIA0/ADP0/MCLK PTA1/PIA1/ADP1/ACMP1+ PTA2/PIA2/ADP2/ACMP1PTA3/PIA3/ADP3/ACMP1O PTA4/PIA4/ADP4 PTA5/PIA5/ADP5 PTA6/PIA6/ADP6 PTA7/PIA7/ADP7/IRQ PTB0/PIB0/ADP8 BACKGROUND HEADER VDD VDD 4.7 k10 k RESET PORT B PTB1/PIB1/ADP9 PTB2/PIB2/ADP10 PTB3/PIB3/ADP11 PTB4/PIB4/ADP12 PTB5/PIB5/ADP13 PTB6/PIB6/ADP14 PTB7/PIB7/ADP15 PTC0/ADP16 PTC1/ADP17 PTC2/ADP18 PTC3/ADP19 PTC4/ADP20 PTC5/ADP21 PTC6/ADP22 PTC7/ADP23
CBY 0.1 F
BKGD/MS
OPTIONAL MANUAL RESET
0.1 F PORT C
RF C1 C2
RS PTD0/PID0/TPM2CH0 PTD1/PID1/TPM2CH1 PTG0/EXTAL PTG1/XTAL PTG2 PTG3 PTG4 PTG5 PTF0/TxD2 PTF1/RxD2 PTF2/TPM1CLK/SCL PTF3/TPM2CLK/SDA PTF4/ACMP2+ PTF5/ACMP2 PTF6/ACMP2O PTF7 PTD2/PID2/TPM1CH0 PORT G PORT D PTD3/PID3/TPM1CH1 PTD4/PID4/TPM1CH2 PTD5/PID5/TPM1CH3 PTD6/PID6/TPM1CH4 PTD7/PID7/TPM1CH5 PTE0/TxD1 PTE1/RxD1 PTE2/SS PTE3/SPSCK PTE4/SCL/MOSI PTE5/SDA/MISO PTE6/TxD2/TXCAN PTE7/RxD2/RXCAN
X1
NOTES: 1. External crystal circuit not required if using the internal clock option. 2. RESET pin can only be used to reset into user mode, you can not enter BDM using RESET pin. BDM can be entered by holding MS low during POR or writing a 1 to BDFR in SBDFR with MS low after issuing BDM command. 3. RC filter on RESET pin recommended for noisy environments. 4. For 32-pin and 48-pin packages: VDDA and VSSA are double bonded to VREFH and VREFL respectively.
PORT F
PORT E
Figure 2-4. Basic System Connections (Shown in 64-Pin Package)

2.2.1
Power
VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides regulated lower-voltage source to the CPU and other internal circuitry of the MCU. Typically, application systems have two separate capacitors across the power pins. In this case, there should be a bulk electrolytic capacitor, such as a 10-F tantalum capacitor, to provide bulk charge storage for the overall system and a 0.1-F ceramic bypass capacitor located as near to the MCU power pins as practical to suppress high-frequency noise. The MC9S08DZ60 Series has two VDD pins except on the 32-pin package. Each pin must have a bypass capacitor for best noise suppression. VDDA and VSSA are the analog power supply pins for the MCU. This voltage source supplies power to the ADC module. A 0.1-F ceramic bypass capacitor should be located as near to the MCU power pins as practical to suppress high-frequency noise.
2.2.2
Oscillator
Immediately after reset, the MCU uses an internally generated clock provided by the multi-purpose clock generator (MCG) module. For more information on the MCG, see Chapter 8, Multi-Purpose Clock Generator (S08MCGV1). The oscillator (XOSC) in this MCU is a Pierce oscillator that can accommodate a crystal or ceramic resonator. Rather than a crystal or ceramic resonator, an external oscillator can be connected to the EXTAL input pin. Refer to Figure 2-4 for the following discussion. RS (when used) and RF should be low-inductance resistors such as carbon composition resistors. Wire-wound resistors and some metal lm resistors have too much inductance. C1 and C2 normally should be high-quality ceramic capacitors that are specically designed for high-frequency applications. RF is used to provide a bias path to keep the EXTAL input in its linear range during crystal startup; its value is not generally critical. Typical systems use 1 M to 10 M. Higher values are sensitive to humidity, and lower values reduce gain and (in extreme cases) could prevent startup. C1 and C2 are typically in the 5-pF to 25-pF range and are chosen to match the requirements of a specic crystal or resonator. Be sure to take into account printed circuit board (PCB) capacitance and MCU pin capacitance when selecting C1 and C2. The crystal manufacturer typically species a load capacitance which is the series combination of C1 and C2 (which are usually the same size). As a rst-order approximation, use 10 pF as an estimate of combined pin and PCB capacitance for each oscillator pin (EXTAL and XTAL).
2.2.3
RESET
RESET is a dedicated pin with a pull-up device built in. It has input hysteresis, a high current output driver, and no output slew rate control. Internal power-on reset and low-voltage reset circuitry typically make external reset circuitry unnecessary. This pin is normally connected to the standard 6-pin background debug connector so a development system can directly reset the MCU system. If desired, a manual external reset can be added by supplying a simple switch to ground (pull reset pin low to force a reset).
Whenever any reset is initiated (whether from an external signal or from an internal system), the RESET pin is driven low for about 34 bus cycles. The reset circuitry decodes the cause of reset and records it by setting a corresponding bit in the system reset status register (SRS).
2.2.4
Background / Mode Select (BKGD/MS)
While in reset, the BKGD/MS pin functions as a mode select pin. Immediately after reset rises, the pin functions as the background pin and can be used for background debug communication. While functioning as a background or mode select pin, the pin includes an internal pull-up device, input hysteresis, a standard output driver, and no output slew rate control. If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of reset. If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD low during the rising edge of reset which forces the MCU to active background mode. The BKGD/MS pin is used primarily for background debug controller (BDC) communications using a custom protocol that uses 16 clock cycles of the target MCUs BDC clock per bit time. The target MCUs BDC clock could be as fast as the bus clock rate, so there should never be any signicant capacitance connected to the BKGD/MS pin that could interfere with background serial communications. Although the BKGD/MS pin is a pseudo open-drain pin, the background debug communication protocol provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from cables and the absolute value of the internal pull-up device play almost no role in determining rise and fall times on the BKGD/MS pin.
2.2.5
ADC Reference Pins (VREFH, VREFL)
The VREFH and VREFL pins are the voltage reference high and voltage reference low inputs, respectively, for the ADC module.
2.2.6
General-Purpose I/O and Peripheral Ports
The MC9S08DZ60 Series series of MCUs support up to 53 general-purpose I/O pins and 1 input-only pin, which are shared with on-chip peripheral functions (timers, serial I/O, ADC, MSCAN, etc.). When a port pin is congured as a general-purpose output or a peripheral uses the port pin as an output, software can select one of two drive strengths and enable or disable slew rate control. When a port pin is congured as a general-purpose input or a peripheral uses the port pin as an input, software can enable a pull-up device. Immediately after reset, all of these pins are congured as high-impedance general-purpose inputs with internal pull-up devices disabled. When an on-chip peripheral system is controlling a pin, data direction control bits still determine what is read from port data registers even though the peripheral module controls the pin direction by controlling the enable for the pins output buffer. For information about controlling these pins as general-purpose I/O pins, see Chapter 6, Parallel Input/Output Control.
NOTE To avoid extra current drain from oating input pins, the reset initialization routine in the application program should either enable on-chip pull-up devices or change the direction of unused or non-bonded pins to outputs so they do not oat.
Table 2-1. Pin Availability by Package Pin-Count

3
Pin Number 64 48 32 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9
<-- Lowest Port Pin/Interrupt PIB6 PIA7 PIB7
Priority Alt 1 ADP14 ADP21 ADP7 ADP22 ADP15 ADP23
--> Highest Alt 2
Pin Number 64 48 32
<-- Lowest Port Pin/Interrupt PID2 PID3 PID4 PID5
Priority Alt 1
--> Highest Alt 2 TPM1CH0 TPM1CH1 TPM1CH2 TPM1CH3 VSS VDD
PTB6 1 PTA7 PTB7 2 3 4 PTG0 5 PTG1 6 PTF4
33 25 17 PTD2 34 26 18 PTD3 IRQ 35 27 19 PTD4 36 28 20 PTD5 37 PTF7 38 29 VDD VSS 39 30 40 31 PTD6 41 32 PTD7 42 33 21 RESET ACMP2+ ACMP2ACMP2O 43 PTC0 44 34 22 PTB0 45 PTC1 46 35 23 PTA0 47 PTC2 48 36 24 PTB1 SS SPSCK 49 37 25 PTA1 50 38 PTB2 51 39 26 PTA2 52 PTC3 53 40 PTB3 54 41 27 PTA3 TxD2
4
PTC5 PTC6 PTC7
PID6 PID7 BKGD ADP16 PIB0 PIA0 PIB1 PIA1 PIB2 PIA2 PIB3 PIA3 ADP8 ADP17 ADP0 ADP18 ADP9 ADP11 ADP10 ADP21 ADP19 ADP11 ADP3
TPM1CH4 TPM1CH5 MS
EXTAL XTAL
13 10 PTF5 14 PTF6 15 11 16 12 17 13 7 PTE0 8 PTE12 9 PTE2 SCL

3
MCLK
TxD1 RxD12
ACMP1+1 ACMP1-1
18 14 10 PTE3 19 15 11 PTE4 20 16 12 PTE5 21 PTG2 22 PTG3 23 17 PTF0 24 18 PTF1 25 19 PTF2 26 20 PTF3 27 PTG4 28 PTG5 29 21 13 PTE6 30 22 14 PTE7 31 23 15 PTD0 32 24 16 PTD1 PID0 PID1 TxD2
4
MOSI MISO
SDA3
ACMP1O VSSA VREFL VREFH VDDA
55 56 57 58
RxD24 TPM1CLK SCL3 TPM2CLK SDA3
42 28 43 29 PIA4 PIB4 PIA5 PIB5 PIA6 ADP4 ADP12 ADP20 ADP5 ADP13 ADP6
59 44 30 PTA4 60 45 PTB4 TXCAN RxCAN TPM2CH0 TPM2CH1 61 PTC4 62 46 31 PTA5 63 47 PTB5 64 48 32 PTA6 RxD24
1. If both of these analog modules are enabled, they both will have access to the pin. 2. Pin does not contain a clamp diode to VDD and should not be driven above VDD. The voltage measured on this pin when internal pull-up is enabled may be as low as VDD 0.7 V. The internal gates connected to this pin are pulled to VDD. 3. The IIC module pins can be repositioned using IICPS bit in the SOPT1 register. The default reset locations are on PTF2 and PTF3. 4. The SCI2 module pins can be repositioned using SCI2PS bit in the SOPT1 register. The default reset locations are on PTF0 and PTF1. MC9S08DZ60 Series Data Sheet, Rev. 4 34 Freescale Semiconductor

3.1 Introduction
The operating modes of the MC9S08DZ60 Series are described in this chapter. Entry into each mode, exit from each mode, and functionality while in each of the modes are described.
3.2

Features
Active background mode for code development Wait mode CPU shuts down to conserve power; system clocks are running and full regulation is maintained Stop modes System clocks are stopped and voltage regulator is in standby Stop3 All internal circuits are powered for fast recovery Stop2 Partial power down of internal circuits; RAM content is retained
3.3
Run Mode
This is the normal operating mode for the MC9S08DZ60 Series. This mode is selected when the BKGD/MS pin is high at the rising edge of reset. In this mode, the CPU executes code from internal memory with execution beginning at the address fetched from memory at 0xFFFE0xFFFF after reset.
3.4
Active Background Mode
The active background mode functions are managed through the background debug controller (BDC) in the HCS08 core. The BDC, together with the on-chip debug module (DBG), provide the means for analyzing MCU operation during software development. Active background mode is entered in any of ve ways: When the BKGD/MS pin is low at the rising edge of reset When a BACKGROUND command is received through the BKGD/MS pin When a BGND instruction is executed When encountering a BDC breakpoint When encountering a DBG breakpoint After entering active background mode, the CPU is held in a suspended state waiting for serial background commands rather than executing instructions from the user application program.
Background commands are of two types: Non-intrusive commands, dened as commands that can be issued while the user program is running. Non-intrusive commands can be issued through the BKGD/MS pin while the MCU is in run mode; non-intrusive commands can also be executed when the MCU is in the active background mode. Non-intrusive commands include: Memory access commands Memory-access-with-status commands BDC register access commands The BACKGROUND command Active background commands, which can only be executed while the MCU is in active background mode. Active background commands include commands to: Read or write CPU registers Trace one user program instruction at a time Leave active background mode to return to the user application program (GO) The active background mode is used to program a bootloader or user application program into the Flash program memory before the MCU is operated in run mode for the rst time. When the MC9S08DZ60 Series is shipped from the Freescale Semiconductor factory, the Flash program memory is erased by default unless specically noted so there is no program that could be executed in run mode until the Flash memory is initially programmed. The active background mode can also be used to erase and reprogram the Flash memory after it has been previously programmed. For additional information about the active background mode, refer to the Development Support chapter.
3.5
Wait Mode
Wait mode is entered by executing a WAIT instruction. Upon execution of the WAIT instruction, the CPU enters a low-power state in which it is not clocked. The I bit in CCR is cleared when the CPU enters the wait mode, enabling interrupts. When an interrupt request occurs, the CPU exits the wait mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine. While the MCU is in wait mode, there are some restrictions on which background debug commands can be used. Only the BACKGROUND command and memory-access-with-status commands are available when the MCU is in wait mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from wait mode and enter active background mode.
3.6
Stop Modes
One of two stop modes is entered upon execution of a STOP instruction when the STOPE bit in SOPT1 register is set. In both stop modes, all internal clocks are halted. The MCG module can be congured to leave the reference clocks running. See Chapter 8, Multi-Purpose Clock Generator (S08MCGV1), for more information. Table 3-1 shows all of the control bits that affect stop mode selection and the mode selected under various conditions. The selected mode is entered following the execution of a STOP instruction.
Table 3-1. Stop Mode Selection
STOPE 0 1 1 1 1
1
ENBDM 1 x 1 0 0 0
LVDE x x
LVDSE
PPDC x x x 0 1
Stop Mode Stop modes disabled; illegal opcode reset if STOP instruction executed Stop3 with BDM enabled 2 Stop3 with voltage regulator active Stop3 Stop2
Both bits must be 1 Either bit a 0 Either bit a 0
ENBDM is located in the BDCSCR, which is only accessible through BDC commands, see Section 17.4.1.1, BDC Status and Control Register (BDCSCR). 2 When in Stop3 mode with BDM enabled, The S IDD will be near RIDD levels because internal clocks are enabled.
3.6.1
Stop3 Mode
Stop3 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. The states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained. Exit from stop3 is done by asserting RESET or an asynchronous interrupt pin. The asynchronous interrupt pins are IRQ, PIA0PIA7, PIB0PIB7, and PID0PID7. Exit from stop3 can also be done by the low-voltage detect (LVD) reset, low-voltage warning (LVW) interrupt, ADC conversion complete interrupt, real-time clock (RTC) interrupt, MSCAN wake-up interrupt, or SCI receiver interrupt. If stop3 is exited by means of the RESET pin, the MCU will be reset and operation will resume after fetching the reset vector. Exit by means of an interrupt will result in the MCU fetching the appropriate interrupt vector.
3.6.1.1
LVD Enabled in Stop3 Mode
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below the LVD voltage. If the LVD is enabled in stop (LVDE and LVDSE bits in SPMSC1 both set) at the time the CPU executes a STOP instruction, then the voltage regulator remains active during stop mode. For the ADC to operate the LVD must be left enabled when entering stop3.
3.6.1.2
Active BDM Enabled in Stop3 Mode
Entry into the active background mode from run mode is enabled if ENBDM in BDCSCR is set. This register is described in Chapter 17, Development Support. If ENBDM is set when the CPU executes a STOP instruction, the system clocks to the background debug logic remain active when the MCU enters stop mode. Because of this, background debug communication remains possible. In addition, the voltage regulator does not enter its low-power standby state but maintains full internal regulation. Most background commands are not available in stop mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from stop and enter active background mode if the ENBDM bit is set. After entering background debug mode, all background commands are available.
3.6.2
Stop2 Mode
Stop2 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. Most of the internal circuitry of the MCU is powered off in stop2 with the exception of the RAM. Upon entering stop2, all I/O pin control signals are latched so that the pins retain their states during stop2. Exit from stop2 is performed by asserting RESET. On 3M05C or older masksets only, exit from stop2 can also be performed by asserting PTA7/ADP7/IRQ.
NOTE On 3M05C or older masksets only, PTA7/ADP7/IRQ is an active low wake-up and must be congured as an input prior to executing a STOP instruction to avoid an immediate exit from stop2. PTA7/ADP7/IRQ can be disabled as a wake-up if it is congured as a high driven output. For lowest power consumption in stop2, this pin should not be left open when congured as input (enable the internal pullup; or tie an external pullup/down device; or set pin as output). In addition, the real-time counter (RTC) can wake the MCU from stop2, if enabled. Upon wake-up from stop2 mode, the MCU starts up as from a power-on reset (POR): All module control and status registers are reset The LVD reset function is enabled and the MCU remains in the reset state if VDD is below the LVD trip point (low trip point selected due to POR) The CPU takes the reset vector In addition to the above, upon waking up from stop2, the PPDF bit in SPMSC2 is set. This ag is used to direct user code to go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched until a 1 is written to PPDACK in SPMSC2.
To maintain I/O states for pins that were congured as general-purpose I/O before entering stop2, the user must restore the contents of the I/O port registers, which have been saved in RAM, to the port registers before writing to the PPDACK bit. If the port registers are not restored from RAM before writing to PPDACK, then the pins will switch to their reset states when PPDACK is written. For pins that were congured as peripheral I/O, the user must recongure the peripheral module that interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O latches are opened.
3.6.3
On-Chip Peripheral Modules in Stop Modes
When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate, clocks to the peripheral systems are halted to reduce power consumption. Refer to Section 3.6.2, Stop2 Mode and Section 3.6.1, Stop3 Mode for specic information on system behavior in stop modes.
Table 3-2. Stop Mode Behavior
Mode Peripheral Stop2 CPU RAM Flash/EEPROM Parallel Port Registers ACMP ADC IIC MCG MSCAN RTC SCI SPI TPM Voltage Regulator XOSC I/O Pins BDM LVD/LVW
1 2
Stop3 Standby Standby Standby Standby Off Optionally On1 Standby Optionally On2 Standby On3 Optionally On3 Standby Standby Standby Optionally On4 Optionally On5 States Held Optionally On Optionally On
Off Standby Off Off Off Off Off Off Off Optionally Off Off Off Off Off States Held Off Off
6 7
Requires the asynchronous ADC clock and LVD to be enabled, else in standby. IRCLKEN and IREFSTEN set in MCGC1, else in standby. 3 Requires the RTC to be enabled, else in standby. 4 Requires the LVD or BDC to be enabled.

5
ERCLKEN and EREFSTEN set in MCGC2 for, else in standby. For high frequency range (RANGE in MCGC2 set) requires the LVD to also be enabled in stop3. 6 If ENBDM is set when entering stop2, the MCU will actually enter stop3. 7 If LVDSE is set when entering stop2, the MCU will actually enter stop3.
Chapter 4 Memory
4.1 MC9S08DZ60 Series Memory Map
On-chip memory in the MC9S08DZ60 Series consists of RAM, EEPROM, and Flash program memory for nonvolatile data storage, and I/O and control/status registers. The registers are divided into three groups: Direct-page registers (0x0000 through 0x007F) High-page registers (0x1800 through 0x18FF) Nonvolatile registers (0xFFB0 through 0xFFBF)
Chapter 4 Memory
0x0000 DIRECT PAGE REGISTERS 128 BYTES 0x007F 0x0080 RAM 4096 BYTES
0x0000 DIRECT PAGE REGISTERS 128 BYTES 0x007F 0x0080 RAM 3072 BYTES 0x0C7F 0x0C80
0x0000 DIRECT PAGE REGISTERS 128 BYTES 0x007F 0x0080 RAM 2048 BYTES 0x087F 0x0880
0x0000 DIRECT PAGE REGISTERS 128 BYTES 0x007F 0x0080 RAM 1024 BYTES 0x047F 0x0480
0x107F 0x1080 0x13FF 0x1400 FLASH 896 BYTES
UNIMPLEMENTED 2176 BYTES 0x14FF 0x1500 EEPROM1 2 x 768 BYTES
UNIMPLEMENTED 3456 BYTES 0x15FF 0x1600
UNIMPLEMENTED 4736 BYTES 0x16FF 0x1700 EEPROM1 0x17FF 2 x 256 BYTES 0x1800 HIGH PAGE REGISTERS 256 BYTES 0x18FF 0x1900
0x17FF 0x1800 HIGH PAGE REGISTERS 256 BYTES 0x18FF 0x1900
2 x 1024 BYTES
EEPROM1
EEPROM1 2 x 512 BYTES
UNIMPLEMENTED 9984 BYTES 0x3FFF 0x4000
UNIMPLEMENTED 25,344 BYTES
UNIMPLEMENTED 42,240 BYTES
0x7BFF 0x7C00 0xBDFF 0xBE00 FLASH 59136 BYTES FLASH 49152 BYTES FLASH 33792 BYTES 0xFFFF MC9S08DZ32 MC9S08DZ16 FLASH 16896 BYTES
0xFFFF MC9S08DZ60
1
0xFFFF MC9S08DZ48
0xFFFF
EEPROM address range shows half the total EEPROM. See Section 4.5.10, EEPROM Mapping for more details.
Figure 4-1. MC9S08DZ60 Memory Map
4.2
Reset and Interrupt Vector Assignments
Table 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table are the labels used in the MC9S08DZ60 Series equate file provided by Freescale Semiconductor.
Table 4-1. Reset and Interrupt Vectors
Address (High/Low) 0xFFC0:0xFFC1 0xFFC2:0xFFC3 0xFFC4:0xFFC5 0xFFC6:0xFFC7 0xFFC8:0xFFC9 0xFFCA:0xFFCB Vector ACMP2 ACMP1 MSCAN Transmit MSCAN Receive MSCAN errors MSCAN wake up Vector Name Vacmp2 Vacmp1 Vcantx Vcanrx Vcanerr Vcanwu
Chapter 4 Memory
Table 4-1. Reset and Interrupt Vectors

Address (High/Low) 0xFFCC:0xFFCD 0xFFCE:0xFFCF 0xFFD0:0xFFD1 0xFFD2:0xFFD3 0xFFD4:0xFFD5 0xFFD6:0xFFD7 0xFFD8:0xFFD9 0xFFDA:0xFFDB 0xFFDC:0xFFDD 0xFFDE:0xFFDF 0xFFE0:0xFFE1 0xFFE2:0xFFE3 0xFFE4:0xFFE5 0xFFE6:0xFFE7 0xFFE8:0xFFE9 0xFFEA:0xFFEB 0xFFEC:0xFFED 0xFFEE:0xFFEF 0xFFF0:0xFFF1 0xFFF2:0xFFF3 0xFFF4:0xFFF5 0xFFF6:0xFFF7 0xFFF8:0xFFF9 0xFFFA:0xFFFB 0xFFFC:0xFFFD 0xFFFE:0xFFFF Vector RTC IIC ADC Conversion Port A, Port B, Port D SCI2 Transmit SCI2 Receive SCI2 Error SCI1 Transmit SCI1 Receive SCI1 Error SPI TPM2 Overow TPM2 Channel 1 TPM2 Channel 0 TPM1 Overow TPM1 Channel 5 TPM1 Channel 4 TPM1 Channel 3 TPM1 Channel 2 TPM1 Channel 1 TPM1 Channel 0 MCG Loss of lock Low-Voltage Detect IRQ SWI Reset Vector Name Vrtc Viic Vadc Vport Vsci2tx Vsci2rx Vsci2err Vsci1tx Vsci1rx Vsci1err Vspi Vtpm2ovf Vtpm2ch1 Vtpm2ch0 Vtpm1ovf Vtpm1ch5 Vtpm1ch4 Vtpm1ch3 Vtpm1ch2 Vtpm1ch1 Vtpm1ch0 Vlol Vlvd Virq Vswi Vreset
Chapter 4 Memory
4.3
Register Addresses and Bit Assignments
The registers in the MC9S08DZ60 Series are divided into these groups: Direct-page registers are located in the rst 128 locations in the memory map; these are accessible with efcient direct addressing mode instructions. High-page registers are used much less often, so they are located above 0x1800 in the memory map. This leaves more room in the direct page for more frequently used registers and RAM. The nonvolatile register area consists of a block of 16 locations in Flash memory at 0xFFB00xFFBF. Nonvolatile register locations include: NVPROT and NVOPT are loaded into working registers at reset An 8-byte backdoor comparison key that optionally allows a user to gain controlled access to secure memory Because the nonvolatile register locations are Flash memory, they must be erased and programmed like other Flash memory locations. Direct-page registers can be accessed with efcient direct addressing mode instructions. Bit manipulation instructions can be used to access any bit in any direct-page register. Table 4-2 is a summary of all user-accessible direct-page registers and control bits. The direct page registers in Table 4-2 can use the more efcient direct addressing mode, which requires only the lower byte of the address. Because of this, the lower byte of the address in column one is shown in bold text. In Table 4-3 and Table 4-5, the whole address in column one is shown in bold. In Table 4-2, Table 4-3, and Table 4-5, the register names in column two are shown in bold to set them apart from the bit names to the right. Cells that are not associated with named bits are shaded. A shaded cell with a 0 indicates this unused bit always reads as a 0. Shaded cells with dashes indicate unused or reserved bit locations that could read as 1s or 0s.
Chapter 4 Memory
Table 4-2. Direct-Page Register Summary (Sheet 1 of 3)

Address Register Name Bit 7 PTAD7 PTADD7 PTBD7 PTBDD7 PTCD7 PTCDD7 PTDD7 PTDDD7 PTED7 PTEDD7 PTFD7 PTFDD7 0 0 ACME ACME COCO ADACT 0 ADR7 0 ADCV7 ADLPC ADPC7 ADPC15 ADPC23 0 TOF Bit 15 Bit 7 Bit 15 Bit 7 CH0F Bit 15 Bit 7 ADPC6 ADPC14 ADPC22 IRQPDD TOIE 14 6 14 6 CH0IE 14 6 6 PTAD6 PTADD6 PTBD6 PTBDD6 PTCD6 PTCDD6 PTDD6 PTDDD6 PTED6 PTEDD6 PTFD6 PTFDD6 0 0 ACBGS ACBGS AIEN ADTRG 0 ADR6 0 ADCV6 ADIV ADPC5 ADPC13 ADPC21 IRQEDG CPWMS 13 5 13 5 MS0B 13 5 5 PTAD5 PTADD5 PTBD5 PTBDD5 PTCD5 PTCDD5 PTDD5 PTDDD5 PTED5 PTEDD5 PTFD5 PTFDD5 PTGD5 PTGDD5 ACF ACF ADCO ACFE 0 ADR5 0 ADCV5 ACFGT 0 ADR4 0 ADCV4 ADLSMP ADPC4 ADPC12 ADPC20 IRQPE CLKSB 12 4 12 4 MS0A 12 4 0 ADR11 ADR3 ADCV11 ADCV3 ADPC3 ADPC11 ADPC19 IRQF CLKSA 11 3 11 3 ELS0B 11 3 4 PTAD4 PTADD4 PTBD4 PTBDD4 PTCD4 PTCDD4 PTDD4 PTDDD4 PTED4 PTEDD4 PTFD4 PTFDD4 PTGD4 PTGDD4 ACIE ACIE 3 PTAD3 PTADD3 PTBD3 PTBDD3 PTCD3 PTCDD3 PTDD3 PTDDD3 PTED3 PTEDD3 PTFD3 PTFDD3 PTGD3 PTGDD3 ACO ACO 2 PTAD2 PTADD2 PTBD2 PTBDD2 PTCD2 PTCDD2 PTDD2 PTDDD2 PTED2 PTEDD2 PTFD2 PTFDD2 PTGD2 PTGDD2 ACOPE ACOPE ADCH 0 ADR10 ADR2 ADCV10 ADCV2 ADPC2 ADPC10 ADPC18 IRQACK PS2 10 2 10 2 ELS0A 10 2 ADR9 ADR1 ADCV9 ADCV1 ADPC1 ADPC9 ADPC17 IRQIE PS1 9 1 9 1 0 9 1 ADR8 ADR0 ADCV8 ADCV0 ADPC0 ADPC8 ADPC16 IRQMOD PS0 Bit 8 Bit 0 Bit 8 Bit 0 0 Bit 8 Bit 0 1 PTAD1 PTADD1 PTBD1 PTBDD1 PTCD1 PTCDD1 PTDD1 PTDDD1 PTED1 PTEDD1 PTFD1 PTFDD1 PTGD1 PTGDD1 ACMOD1 ACMOD1 Bit 0 PTAD0 PTADD0 PTBD0 PTBDD0 PTCD0 PTCDD0 PTDD0 PTDDD0 PTED0 PTEDD0 PTFD0 PTFDD0 PTGD0 PTGDD0 ACMOD0 ACMOD0
0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 0x0018 0x0019 0x001A 0x001B 0x001C 0x001D 0x001F 0x0020 0x0021 0x0022 0x0023 0x0024 0x0025 0x0026 0x0027
PTAD PTADD PTBD PTBDD PTCD PTCDD PTDD PTDDD PTED PTEDD PTFD PTFDD PTGD PTGDD ACMP1SC ACMP2SC ADCSC1 ADCSC2 ADCRH ADCRL ADCCVH ADCCVL ADCCFG APCTL1 APCTL2 APCTL3 Reserved IRQSC Reserved TPM1SC TPM1CNTH TPM1CNTL TPM1MODH TPM1MODL TPM1C0SC TPM1C0VH TPM1C0VL
MODE
ADICLK
Chapter 4 Memory

Address Register Name Bit 7 CH1F Bit 15 Bit 7 CH2F Bit 15 Bit 7 CH3F Bit 15 Bit 7 CH4F Bit 15 Bit 7 CH5F Bit 15 Bit 7 LBKDIE SBR7 LOOPS TIE TDRE LBKDIF R8 Bit 7 LBKDIE SBR7 LOOPS TIE TDRE LBKDIF R8 Bit 7 CLKS BDIV LOLS LOLIE LOCK PLLS RANGE PLLST CME 6 CH1IE 14 6 CH2IE 14 6 CH3IE 14 6 CH4IE 14 6 CH5IE 14 6 RXEDGIE SBR6 SCISWAI TCIE TC RXEDGIF T8 6 RXEDGIE SBR6 SCISWAI TCIE TC RXEDGIF T8 6 5 MS1B 13 5 MS2B 13 5 MS3B 13 5 MS4B 13 5 MS5B 13 5 0 SBR5 RSRC RIE RDRF 0 TXDIR 5 0 SBR5 RSRC RIE RDRF 0 TXDIR 5 4 MS1A 12 4 MS2A 12 4 MS3A 12 4 MS4A 12 4 MS5A 12 4 SBR12 SBR4 M ILIE IDLE RXINV TXINV 4 SBR12 SBR4 M ILIE IDLE RXINV TXINV 4 RDIV HGO TRIM IREFST 0 CLKST OSCINIT VDIV FTRIM LP 3 ELS1B 11 3 ELS2B 11 3 ELS3B 11 3 ELS4B 11 3 ELS5B 11 3 SBR11 SBR3 WAKE TE OR RWUID ORIE 3 SBR11 SBR3 WAKE TE OR RWUID ORIE 3 2 ELS1A 10 2 ELS2A 10 2 ELS3A 10 2 ELS4A 10 2 ELS5A 10 2 SBR10 SBR2 ILT RE NF BRK13 NEIE 2 SBR10 SBR2 ILT RE NF BRK13 NEIE 2 IREFS EREFS 1 0 9 1 0 9 1 0 9 1 0 9 1 0 9 1 SBR9 SBR1 PE RWU FE LBKDE FEIE 1 SBR9 SBR1 PE RWU FE LBKDE FEIE 1 IRCLKEN Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 SBR8 SBR0 PT SBK PF RAF PEIE Bit 0 SBR8 SBR0 PT SBK PF RAF PEIE Bit 0 IREFSTEN
0x0028 0x0029 0x002A 0x002B 0x002C 0x002D 0x002E 0x002F 0x0030 0x0031 0x0032 0x0033 0x0034 0x0035 0x0036 0x0037 0x0038 0x0039 0x003A 0x003B 0x003C 0x003D 0x003E 0x003F 0x0040 0x0041 0x0042 0x0043 0x0044 0x0045 0x0046 0x0047 0x0048 0x0049 0x004A 0x004B 0x004C 0x004D 0x004F
TPM1C1SC TPM1C1VH TPM1C1VL TPM1C2SC TPM1C2VH TPM1C2VL TPM1C3SC TPM1C3VH TPM1C3VL TPM1C4SC TPM1C4VH TPM1C4VL TPM1C5SC TPM1C5VH TPM1C5VL Reserved SCI1BDH SCI1BDL SCI1C1 SCI1C2 SCI1S1 SCI1S2 SCI1C3 SCI1D SCI2BDH SCI2BDL SCI2C1 SCI2C2 SCI2S1 SCI2S2 SCI2C3 SCI2D MCGC1 MCGC2 MCGTRM MCGSC MCGC3 Reserved
ERCLKEN EREFSTEN
Chapter 4 Memory

Address Register Name Bit 7 SPIE 0 0 SPRF 0 Bit 7 AD7 MULT IICEN TCF GCAEN TOF Bit 15 Bit 7 Bit 15 Bit 7 CH0F Bit 15 Bit 7 CH1F Bit 15 Bit 7 RTIF IICIE IAAS ADEXT TOIE 14 6 14 6 CH0IE 14 6 CH1IE 14 6 RTCLKS MST BUSY 0 CPWMS 13 5 13 5 MS0B 13 5 MS1B 13 5 TX ARBL DATA 0 CLKSB 12 4 12 4 MS0A 12 4 MS1A 12 4 RTIE RTCCNT RTCMOD 0 CLKSA 11 3 11 3 ELS0B 11 3 ELS1B 11 3 AD10 PS2 10 2 10 2 ELS0A 10 2 ELS1A 10 2 RTCPS AD9 PS1 9 1 9 1 0 9 1 0 9 1 AD8 PS0 Bit 8 Bit 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 TXAK 0 6 SPE 0 SPPR2 0 0 6 AD6 5 SPTIE 0 SPPR1 SPTEF 0 5 AD5 4 MSTR MODFEN SPPR0 MODF 0 4 AD4 3 CPOL BIDIROE 0 0 0 3 AD3 ICR RSTA SRW 0 IICIF 0 RXAK 2 CPHA 0 SPR2 0 0 2 AD2 1 SSOE SPISWAI SPR1 0 0 1 AD1 Bit 0 LSBFE SPC0 SPR0 0 0 Bit 0 0
0x0050 0x0051 0x0052 0x0053 0x0054 0x0055 0x0056 0x0057 0x0058 0x0059 0x005A 0x005B 0x005C 0x005D 0x005E 0x005F 0x0060 0x0061 0x0062 0x0063 0x0064 0x0065 0x0066 0x0067 0x0068 0x0069 0x006A 0x006B 0x006C 0x006D 0x006E 0x006F 0x0070 0x007F
SPIC1 SPIC2 SPIBR SPIS Reserved SPID Reserved IICA IICF IICC1 IICS IICD IICC2 Reserved TPM2SC TPM2CNTH TPM2CNTL TPM2MODH TPM2MODL TPM2C0SC TPM2C0VH TPM2C0VL TPM2C1SC TPM2C1VH TPM2C1VL Reserved RTCSC RTCCNT RTCMOD Reserved Reserved
High-page registers, shown in Table 4-3, are accessed much less often than other I/O and control registers so they have been located outside the direct addressable memory space, starting at 0x1800.
Chapter 4 Memory
Table 4-3. High-Page Register Summary (Sheet 1 of 3)

Address Register Name Bit 7 POR 0 COPT COPCLKS ID7 LVWF 0 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 DBGEN TRGSEL AF DIVLD KEYEN 0 FCBEF PTAPE7 PTASE7 PTADS7 0 PTAPS7 PTAES7 EPS FCCF PTAPE6 PTASE6 PTADS6 0 PTAPS6 PTAES6 FPVIOL PTAPE5 PTASE5 PTADS5 0 PTAPS5 PTAES5 FACCERR FCMD PTAPE4 PTASE4 PTADS4 0 PTAPS4 PTAES4 PTAPE3 PTASE3 PTADS3 PTAIF PTAPS3 PTAES3 PTAPE2 PTASE2 PTADS2 PTAACK PTAPS2 PTAES2 PTAPE1 PTASE1 PTADS1 PTAIE PTAPS1 PTAES1 PTAPE0 PTASE0 PTADS0 PTAMOD PTAPS0 PTAES0 0 COPW ID6 LVWACK 0 14 6 14 6 14 6 ARM BEGIN BF PRDIV8 FNORED EPGSEL EPGMOD KEYACC 0 Reserved1 0 0 FPS FBLANK 0 0 6 PIN 0 5 COP 0 STOPE 0 ID5 LVWIE LVDV 13 5 13 5 13 5 TAG 0 ARMF 4 ILOP 0 SCI2PS ADHTS ID4 LVDRE LVWV 12 4 12 4 12 4 BRKEN 0 0 3 ILAD 0 IICPS 0 ID11 ID3 LVDSE PPDF 11 3 11 3 11 3 RWA TRG3 CNT3 DIV 0 0 0 SEC 1 ID10 ID2 LVDE PPDACK 10 2 10 2 10 2 RWAEN TRG2 CNT2 2 LOCS 0 0 1 LVD 0 0 MCSEL ID9 ID1 0 0 9 1 9 1 9 1 RWB TRG1 CNT1 ID8 ID0 BGBE PPDC Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 RWBEN TRG0 CNT0 Bit 0 0 BDFR 0
0x1800 0x1801 0x1802 0x1803 0x1804 0x1805 0x1806 0x1807 0x1808 0x1809 0x180A 0x180B 0x180F 0x1810 0x1811 0x1812 0x1813 0x1814 0x1815 0x1816 0x1817 0x1818 0x1819 0x181F 0x1820 0x1821 0x1822 0x1823 0x1824 0x1825 0x1826 0x1827 0x183F 0x1840 0x1841 0x1842 0x1843 0x1844 0x1845 0x1846
SRS SBDFR SOPT1 SOPT2 Reserved SDIDH SDIDL Reserved SPMSC1 SPMSC2 Reserved DBGCAH DBGCAL DBGCBH DBGCBL DBGFH DBGFL DBGC DBGT DBGS Reserved FCDIV FOPT Reserved FCNFG FPROT FSTAT FCMD Reserved PTAPE PTASE PTADS Reserved PTASC PTAPS PTAES
Chapter 4 Memory

Address Register Name Bit 7 PTBPE7 PTBSE7 PTBDS7 0 PTBPS7 PTBES7 PTCPE7 PTCSE7 PTCDS7 PTDPE7 PTDSE7 PTDDS7 0 PTDPS7 PTDES7 PTEPE7 PTESE7 PTEDS7 PTFPE7 PTFSE7 PTFDS7 0 0 0 RXFRM CANE SJW1 6 PTBPE6 PTBSE6 PTBDS6 0 PTBPS6 PTBES6 PTCPE6 PTCSE6 PTCDS6 PTDPE6 PTDSE6 PTDDS6 0 PTDPS6 PTDES6 PTEPE6 PTESE6 PTEDS6 PTFPE6 PTFSE6 PTFDS6 0 0 0 RXACT CLKSRC SJW0 5 PTBPE5 PTBSE5 PTBDS5 0 PTBPS5 PTBES5 PTCPE5 PTCSE5 PTCDS5 PTDPE5 PTDSE5 PTDDS5 0 PTDPS5 PTDES5 PTEPE5 PTESE5 PTEDS5 PTFPE5 PTFSE5 PTFDS5 PTGPE5 PTGSE5 PTGDS5 CSWAI LOOPB BRP5 4 PTBPE4 PTBSE4 PTBDS4 0 PTBPS4 PTBES4 PTCPE4 PTCSE4 PTCDS4 PTDPE4 PTDSE4 PTDDS4 0 PTDPS4 PTDES4 PTEPE4 PTESE4 PTEDS4 PTFPE4 PTFSE4 PTFDS4 PTGPE4 PTGSE4 PTGDS4 SYNCH LISTEN BRP4 3 PTBPE3 PTBSE3 PTBDS3 PTBIF PTBPS3 PTBES3 PTCPE3 PTCSE3 PTCDS3 PTDPE3 PTDSE3 PTDDS3 PTDIF PTDPS3 PTDES3 PTEPE3 PTESE3 PTEDS3 PTFPE3 PTFSE3 PTFDS3 PTGPE3 PTGSE3 PTGDS3 TIME BORM BRP3 2 PTBPE2 PTBSE2 PTBDS2 PTBACK PTBPS2 PTBES2 PTCPE2 PTCSE2 PTCDS2 PTDPE2 PTDSE2 PTDDS2 PTDACK PTDPS2 PTDES2 PTEPE2 PTESE2 PTEDS2 PTFPE2 PTFSE2 PTFDS2 PTGPE2 PTGSE2 PTGDS2 WUPE WUPM BRP2 1 PTBPE1 PTBSE1 PTBDS1 PTBIE PTBPS1 PTBES1 PTCPE1 PTCSE1 PTCDS1 PTDPE1 PTDSE1 PTDDS1 PTDIE PTDPS1 PTDES1 PTEPE1 PTESE1 PTEDS1 PTFPE1 PTFSE1 PTFDS1 PTGPE1 PTGSE1 PTGDS1 SLPRQ SLPAK BRP1 Bit 0 PTBPE0 PTBSE0 PTBDS0 PTBMOD PTBPS0 PTBES0 PTCPE0 PTCSE0 PTCDS0 PTDPE0 PTDSE0 PTDDS0 PTDMOD PTDPS0 PTDES0 PTEPE0 PTESE0 PTEDS0 PTFPE0 PTFSE0 PTFDS0 PTGPE0 PTGSE0 PTGDS0 INITRQ INITAK BRP0
0x1847 0x1848 0x1849 0x184A 0x184B 0x184C 0x184D 0x184E 0x184F 0x1850 0x1851 0x1852 0x1853 0x1857 0x1858 0x1859 0x185A 0x185B 0x185C 0x185D 0x185E 0x185F 0x1860 0x1861 0x1862 0x1863 0x1867 0x1868 0x1869 0x186A 0x186B 0x186F 0x1870 0x1871 0x1872 0x1873 0x187F 0x1880 0x1881 0x1882
Reserved PTBPE PTBSE PTBDS Reserved PTBSC PTBPS PTBES Reserved PTCPE PTCSE PTCDS Reserved PTDPE PTDSE PTDDS Reserved PTDSC PTDPS PTDES Reserved PTEPE PTESE PTEDS Reserved PTFPE PTFSE PTFDS Reserved PTGPE PTGSE PTGDS Reserved CANCTL0 CANCTL1 CANBTR0
Chapter 4 Memory

Address Register Name Bit 7 SAMP WUPIF WUPIE 0 0 0 0 0 0 0 0 RXERR7 TXERR7 AC7 AM7 AC7 AM7 TSR15 TSR7 6 TSEG22 CSCIF CSCIE 0 0 0 0 0 0 0 0 RXERR6 TXERR6 AC6 AM6 AC6 AM6 TSR14 TSR6 5 TSEG21 RSTAT1 RSTATE1 0 0 0 0 0 IDAM1 0 0 RXERR5 TXERR5 AC5 AM5 AC5 AM5 TSR13 TSR5 4 TSEG20 RSTAT0 RSTATE0 0 0 0 0 0 IDAM0 0 0 RXERR4 TXERR4 AC4 AM4 AC4 AM4 TSR12 TSR4 3 TSEG13 TSTAT1 TSTATE1 0 0 0 0 0 0 0 0 RXERR3 TXERR3 AC3 AM3 AC3 AM3 TSR11 TSR3 2 TSEG12 TSTAT0 TSTATE0 TXE2 TXEIE2 ABTRQ2 ABTAK2 TX2 IDHIT2 0 0 RXERR2 TXERR2 AC2 AM2 AC2 AM2 TSR10 TSR2 1 TSEG11 OVRIF OVRIE TXE1 TXEIE1 ABTRQ1 ABTAK1 TX1 IDHIT1 0 0 RXERR1 TXERR1 AC1 AM1 AC1 AM1 TSR9 TSR1 Bit 0 TSEG10 RXF RXFIE TXE0 TXEIE0 ABTRQ0 ABTAK0 TX0 IDHIT0 0 BOHOLD RXERR0 TXERR0 AC0 AM0 AC0 AM0 TSR8 TSR0
0x1883 0x1884 0x1885 0x1886 0x1887 0x1888 0x1889 0x188A 0x188B 0x188C 0x188D 0x188E 0x188F 0x1890 0x1893 0x1894 0x1897 0x1898 0x189B 0x189C 0x189F 0x18BE 0x18BF 0x18C0 0x18FF
1
CANBTR1 CANRFLG CANRIER CANTFLG CANTIER CANTARQ CANTAAK CANTBSEL CANIDAC Reserved CANMISC CANRXERR CANTXERR CANIDAR0 CANIDAR3 CANIDMR0 CANIDMR3 CANIDAR4 CANIDAR7 CANIDMR4 CANIDMR7 CANTTSRH CANTTSRL Reserved
This bit is reserved. User must write a 1 to this bit. Failing to do so may result in unexpected behavior.
Figure 4-4 shows the structure of receive and transmit buffers for extended identier mapping. These registers vary depending on whether standard or extended mapping is selected. See Chapter 12, Freescale Controller Area Network (S08MSCANV1), for details on extended and standard identier mapping.
Table 4-4. MSCAN Foreground Receive and Transmit Buffer Layouts Extended Mapping Shown 0x18A0 0x18A1 0x18A2 0x18A3 0x18A4 0x18AB 0x18AC 0x18AD 0x18AE CANRIDR0 CANRIDR1 CANRIDR2 CANRIDR3 CANRDSR0 CANRDSR7 CANRDLR Reserved CANRTSRH
ID28 ID20 ID14 ID6 DB7 TSR15 ID27 ID19 ID13 ID5 DB6 TSR14 ID26 ID18 ID12 ID4 DB5 TSR13 ID25 SRR(1) ID11 ID3 DB4 TSR12 ID24 IDE(1) ID10 ID2 DB3 DLC3 TSR11 ID23 ID17 ID9 ID1 DB2 DLC2 TSR10 ID22 ID16 ID8 ID0 DB1 DLC1 TSR9 ID21 ID15 ID7 RTR2 DB0 DLC0 TSR8
Chapter 4 Memory
Table 4-4. MSCAN Foreground Receive and Transmit Buffer Layouts Extended Mapping Shown 0x18AF 0x18B0 0x18B1 0x18B2 0x18B3 0x18B4 0x18BB 0x18BC 0x18BD
1 2
CANRTSRL CANTIDR0 CANTIDR1 CANTIDR2 CANTIDR3 CANTDSR0 CANTDSR7 CANTDLR CANTTBPR
TSR7 ID10 ID2 DB7 PRIO7
TSR4 ID7 RTR DB4 PRIO4
TSR3 ID6 IDE DB3 DLC3 PRIO3
TSR2 ID5 DB2 DLC2 PRIO2
SRR and IDE are both 1s. The position of RTR differs between extended and standard identier mapping.
Nonvolatile Flash registers, shown in Table 4-5, are located in the Flash memory. These registers include an 8-byte backdoor key, NVBACKKEY, which can be used to gain access to secure memory resources. During reset events, the contents of NVPROT and NVOPT in the nonvolatile register area of the Flash memory are transferred into corresponding FPROT and FOPT working registers in the high-page registers to control security and block protection options.
Table 4-5. Nonvolatile Register Summary
Address Register Name Reserved for storage of FTRIM Res. for storage of MCGTRM Bit 7 0 6 0 5 0 4 0 TRIM 8-Byte Comparison Key EPS KEYEN FNORED EPGMOD 0 0 FPS 0 SEC 3 0 2 0 1 0 Bit 0 FTRIM
0xFFAE 0xFFAF 0xFFB0 0xFFB7 0xFFB8 0xFFBC 0xFFBD 0xFFBE 0xFFBF
NVBACKKEY Reserved NVPROT Reserved NVOPT
Provided the key enable (KEYEN) bit is 1, the 8-byte comparison key can be used to temporarily disengage memory security. This key mechanism can be accessed only through user code running in secure memory. (A security key cannot be entered directly through background debug commands.) This security key can be disabled completely by programming the KEYEN bit to 0. If the security key is disabled, the only way to disengage security is by mass erasing the Flash if needed (normally through the background debug interface) and verifying that Flash is blank. To avoid returning to secure mode after the next reset, program the security bits (SEC) to the unsecured state (1:0).
Chapter 4 Memory
4.4
RAM
The MC9S08DZ60 Series includes static RAM. The locations in RAM below 0x0100 can be accessed using the more efcient direct addressing mode, and any single bit in this area can be accessed with the bit manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed program variables in this area of RAM is preferred. The RAM retains data while the MCU is in low-power wait, stop2, or stop3 mode. At power-on the contents of RAM are uninitialized. RAM data is unaffected by any reset if the supply voltage does not drop below the minimum value for RAM retention (VRAM). For compatibility with M68HC05 MCUs, the HCS08 resets the stack pointer to 0x00FF. In the MC9S08DZ60 Series, it is usually best to reinitialize the stack pointer to the top of the RAM so the direct page RAM can be used for frequently accessed RAM variables and bit-addressable program variables. Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated to the highest address of the RAM in the Freescale Semiconductor equate le).
LDHX TXS #RamLast+1 ;point one past RAM ;SP<-(H:X-1)
When security is enabled, the RAM is considered a secure memory resource and is not accessible through BDM or code executing from non-secure memory. See Section 4.5.9, Security, for a detailed description of the security feature.
4.5
Flash and EEPROM
MC9S08DZ60 Series devices include Flash and EEPROM memory intended primarily for program and data storage. In-circuit programming allows the operating program and data to be loaded into Flash and EEPROM, respectively, after nal assembly of the application product. It is possible to program the arrays through the single-wire background debug interface. Because no special voltages are needed for erase and programming operations, in-application programming is also possible through other software-controlled communication paths. For a more detailed discussion of in-circuit and in-application programming, refer to the HCS08 Family Reference Manual, Volume I, Freescale Semiconductor document order number HCS08RMv1.
4.5.1
Features
Features of the Flash and EEPROM memory include: Array size (see Table 1-1 for exact array sizes) Flash sector size: 768 bytes EEPROM sector size: selectable 4-byte or 8-byte sector mapping operation Single power supply program and erase Command interface for fast program and erase operation Up to 100,000 program/erase cycles at typical voltage and temperature Flexible block protection and vector redirection Security feature for Flash, EEPROM, and RAM
Chapter 4 Memory
Burst programming capability Sector erase abort
4.5.2
Program and Erase Times
Before any program or erase command can be accepted, the Flash and EEPROM clock divider register (FCDIV) must be written to set the internal clock for the Flash and EEPROM module to a frequency (fFCLK) between 150 kHz and 200 kHz (see Section 4.5.11.1, Flash and EEPROM Clock Divider Register (FCDIV)). This register can be written only once, so normally this write is performed during reset initialization. The user must ensure that FACCERR is not set before writing to the FCDIV register. One period of the resulting clock (1/fFCLK) is used by the command processor to time program and erase pulses. An integer number of these timing pulses is used by the command processor to complete a program or erase command. Table 4-6 shows program and erase times. The bus clock frequency and FCDIV determine the frequency of FCLK (fFCLK). The time for one cycle of FCLK is tFCLK = 1/fFCLK. The times are shown as a number of cycles of FCLK and as an absolute time for the case where tFCLK = 5 s. Program and erase times shown include overhead for the command state machine and enabling and disabling of program and erase voltages.
Table 4-6. Program and Erase Times
Parameter Byte program Burst program Sector erase Mass erase Sector erase abort
1
Cycles of FCLK 9 4 4000 20,000 4
Time if FCLK = 200 kHz 45 s 20 s1 20 ms 100 ms 20 s1
Excluding start/end overhead
4.5.3
Program and Erase Command Execution
The FCDIV register must be initialized after any reset and any error ag is cleared before beginning command execution. The command execution steps are: 1. Write a data value to an address in the Flash or EEPROM array. The address and data information from this write is latched into the Flash and EEPROM interface. This write is a required rst step in any command sequence. For erase and blank check commands, the value of the data is not important. For sector erase commands, the address can be any address in the sector of Flash or EEPROM to be erased. For mass erase and blank check commands, the address can be any address in the Flash or EEPROM memory. Flash and EEPROM erase independently of each other.
Chapter 4 Memory
NOTE Before programming a particular byte in the Flash or EEPROM, the sector in which that particular byte resides must be erased by a mass or sector erase operation. Reprogramming bits in an already programmed byte without rst performing an erase operation may disturb data stored in the Flash or EEPROM memory. 2. Write the command code for the desired command to FCMD. The six valid commands are blank check (0x05), byte program (0x20), burst program (0x25), sector erase (0x40), mass erase1 (0x41), and sector erase abort (0x47). The command code is latched into the command buffer. 3. Write a 1 to the FCBEF bit in FSTAT to clear FCBEF and launch the command (including its address and data information). A partial command sequence can be aborted manually by writing a 0 to FCBEF any time after the write to the memory array and before writing the 1 that clears FCBEF and launches the complete command. Aborting a command in this way sets the FACCERR access error ag which must be cleared before starting a new command. A strictly monitored procedure must be obeyed or the command will not be accepted. This minimizes the possibility of any unintended changes to the memory contents. The command complete ag (FCCF) indicates when a command is complete. The command sequence must be completed by clearing FCBEF to launch the command. Figure 4-2 is a owchart for executing all of the commands except for burst programming and sector erase abort. 4. Wait until the FCCF bit in FSTAT is set. As soon as FCCF= 1, the operation has completed successfully.
1. A mass erase is possible only when the Flash block is fully unprotected. MC9S08DZ60 Series Data Sheet, Rev. 4 54 Freescale Semiconductor
Chapter 4 Memory
WRITE TO FCDIV(1)
(1) Required only once
after reset.
PROGRAM AND ERASE FLOW
START 0 FACCERR?
CLEAR ERROR
WRITE TO FLASH OR EEPROM TO BUFFER ADDRESS AND DATA
WRITE COMMAND TO FCMD
WRITE 1 TO FCBEF TO LAUNCH COMMAND AND CLEAR FCBEF (2) YES
(2)
Wait at least four bus cycles before checking FCBEF or FCCF.
FPVIOL OR FACCERR? NO 0 FCCF? 1 DONE
ERROR EXIT
Figure 4-2. Program and Erase Flowchart
4.5.4
Burst Program Execution
The burst program command is used to program sequential bytes of data in less time than would be required using the standard program command. This is possible because the high voltage to the Flash array does not need to be disabled between program operations. Ordinarily, when a program or erase command is issued, an internal charge pump associated with the Flash memory must be enabled to supply high voltage to the array. Upon completion of the command, the charge pump is turned off. When a burst program command is issued, the charge pump is enabled and remains enabled after completion of the burst program operation if these two conditions are met: The next burst program command sequence has begun before the FCCF bit is set. The next sequential address selects a byte on the same burst block as the current byte being programmed. A burst block in this Flash memory consists of 32 bytes. A new burst block begins at each 32-byte address boundary. The rst byte of a series of sequential bytes being programmed in burst mode will take the same amount of time to program as a byte programmed in standard mode. Subsequent bytes will program in the burst
Chapter 4 Memory
program time provided that the conditions above are met. If the next sequential address is the beginning of a new row, the program time for that byte will be the standard time instead of the burst time. This is because the high voltage to the array must be disabled and then enabled again. If a new burst command has not been queued before the current command completes, then the charge pump will be disabled and high voltage removed from the array. A flowchart to execute the burst program operation is shown in Figure 4-3.
WRITE TO FCDIV(1)
(1) Required only once
after reset.
BURST PROGRAM FLOW
START 0 FACCERR? 1 CLEAR ERROR
FCBEF? 1 WRITE TO Flash TO BUFFER ADDRESS AND DATA
WRITE COMMAND TO FCMD
WRITE 1 TO FCBEF TO LAUNCH COMMAND AND CLEAR FCBEF (2) YES
(2)
Wait at least four bus cycles before checking FCBEF or FCCF.
FPVIOL OR FACCERR? YES NO NEW BURST COMMAND? NO 0 FCCF? 1 DONE
ERROR EXIT
Figure 4-3. Burst Program Flowchart
Chapter 4 Memory
4.5.5
Sector Erase Abort
The sector erase abort operation will terminate the active sector erase operation so that other sectors are available for read and program operations without waiting for the sector erase operation to complete. The sector erase abort command write sequence is as follows: 1. Write to any Flash or EEPROM address to start the command write sequence for the sector erase abort command. The address and data written are ignored. 2. Write the sector erase abort command, 0x47, to the FCMD register. 3. Clear the FCBEF ag in the FSTAT register by writing a 1 to FCBEF to launch the sector erase abort command. If the sector erase abort command is launched resulting in the early termination of an active sector erase operation, the FACCERR flag will set once the operation completes as indicated by the FCCF flag being set. The FACCERR flag sets to inform the user that the Flash sector may not be fully erased and a new sector erase command must be launched before programming any location in that specific sector. If the sector erase abort command is launched but the active sector erase operation completes normally, the FACCERR flag will not set upon completion of the operation as indicated by the FCCF flag being set. Therefore, if the FACCERR flag is not set after the sector erase abort command has completed, a sector being erased when the abort command was launched will be fully erased. A flowchart to execute the sector erase abort operation is shown in Figure 4-4.
SECTOR ERASE ABORT FLOW
1 FCCF? 0 WRITE TO Flash TO BUFFER ADDRESS AND DATA START
WRITE 0x47 TO FCMD
WRITE 1 TO FCBEF TO LAUNCH COMMAND AND CLEAR FCBEF (2)
(2) Wait at least four bus cycles
before checking FCBEF or FCCF.
0 FCCF? 1 SECTOR ERASE COMPLETED 0 FACCERR? 1 SECTOR ERASE ABORTED
Figure 4-4. Sector Erase Abort Flowchart
Chapter 4 Memory
NOTE The FCBEF ag will not set after launching the sector erase abort command. If an attempt is made to start a new command write sequence with a sector erase abort operation active, the FACCERR ag in the FSTAT register will be set. A new command write sequence may be started after clearing the ACCERR ag, if set. NOTE The sector erase abort command should be used sparingly since a sector erase operation that is aborted counts as a complete program/erase cycle.
4.5.6
Access Errors
An access error occurs whenever the command execution protocol is violated. Any of the following specic actions will cause the access error ag (FACCERR) in FSTAT to be set. FACCERR must be cleared by writing a 1 to FACCERR in FSTAT before any command can be processed. Writing to a Flash address before the internal Flash and EEPROM clock frequency has been set by writing to the FCDIV register. Writing to a Flash address while FCBEF is not set. (A new command cannot be started until the command buffer is empty.) Writing a second time to a Flash address before launching the previous command. (There is only one write to Flash for every command.) Writing a second time to FCMD before launching the previous command. (There is only one write to FCMD for every command.) Writing to any Flash control register other than FCMD after writing to a Flash address. Writing any command code other than the six allowed codes (0x05, 0x20, 0x25, 0x40, 0x41, or 0x47) to FCMD. Writing any Flash control register other than to write to FSTAT (to clear FCBEF and launch the command) after writing the command to FCMD. The MCU enters stop mode while a program or erase command is in progress. (The command is aborted.) Writing the byte program, burst program, sector erase or sector erase abort command code (0x20, 0x25, 0x40, or 0x47) with a background debug command while the MCU is secured. (The background debug controller can do blank check and mass erase commands only when the MCU is secure.) Writing 0 to FCBEF to cancel a partial command.
Chapter 4 Memory
4.5.7
Block Protection
The block protection feature prevents the protected region of Flash or EEPROM from program or erase changes. Block protection is controlled through the Flash and EEPROM protection register (FPROT). The EPS bits determine the protected region of EEPROM and the FPS bits determine the protected region of Flash. See Section 4.5.11.4, Flash and EEPROM Protection Register (FPROT and NVPROT). After exit from reset, FPROT is loaded with the contents of the NVPROT location, which is in the nonvolatile register block of the Flash memory. Any FPROT write that attempts to decrease the size of the protected region will be ignored. Because NVPROT is within the last sector of Flash, if any amount of memory is protected, NVPROT is itself protected and cannot be unprotected (intentionally or unintentionally) by the application software. FPROT can be written through background debug commands, which provides a way to erase and reprogram protected Flash memory. One use for block protection is to block protect an area of Flash memory for a bootloader program. this bootloader program can call a routine outside of Flash that can be used to sector erase the rest of the Flash memory and reprogram it. The bootloader is protected even if MCU power is lost during an erase and reprogram operation.
4.5.8
Vector Redirection
While any Flash is block protected, the reset and interrupt vectors will be protected. Vector redirection allows users to modify interrupt vector information without unprotecting bootloader and reset vector space. Vector redirection is enabled by programming the FNORED bit in the NVOPT register located at address 0xFFBF to 0. For redirection to occur, at least some portion of the Flash memory must be block protected by programming the NVPROT register located at address 0xFFBD. All interrupt vectors (memory locations 0xFFC00xFFFD) are redirected, though the reset vector (0xFFFE:0xFFFF) is not. For example, if 1536 bytes of Flash are protected, the protected address region is from 0xFA00 through 0xFFFF. The interrupt vectors (0xFFC00xFFFD) are redirected to the locations 0xF9C00xF9FD. If vector redirection is enabled and an interrupt occurs, the values in the locations 0xF9E0:0xF9E1 are used for the vector instead of the values in the locations 0xFFE0:0xFFE1. This allows the user to reprogram the unprotected portion of the Flash with new program code including new interrupt vector values while leaving the protected area, which includes the default vector locations, unchanged.
4.5.9
Security
The MC9S08DZ60 Series includes circuitry to prevent unauthorized access to the contents of Flash, EEPROM, and RAM memory. When security is engaged, Flash, EEPROM, and RAM are considered secure resources. Direct-page registers, high-page registers, and the background debug controller are considered unsecured resources. Programs executing within secure memory have normal access to any MCU memory locations and resources. Attempts to access a secure memory location with a program executing from an unsecured memory space or through the background debug interface are blocked (writes are ignored and reads return all 0s). Security is engaged or disengaged based on the state of two register bits (SEC[1:0]) in the FOPT register. During reset, the contents of the nonvolatile location NVOPT are copied from Flash into the working FOPT register in high-page register space. A user engages security by programming the NVOPT location,
Chapter 4 Memory
which can be performed at the same time the Flash memory is programmed. The 1:0 state disengages security; the other three combinations engage security. Notice the erased state (1:1) makes the MCU secure. During development, whenever the Flash is erased, it is good practice to immediately program the SEC0 bit to 0 in NVOPT so SEC = 1:0. This would allow the MCU to remain unsecured after a subsequent reset. The on-chip debug module cannot be enabled while the MCU is secure. The separate background debug controller can be used for background memory access commands, but the MCU cannot enter active background mode except by holding BKGD low at the rising edge of reset. A user can choose to allow or disallow a security unlocking mechanism through an 8-byte backdoor security key. If the nonvolatile KEYEN bit in NVOPT/FOPT is 0, the backdoor key is disabled and there is no way to disengage security without completely erasing all Flash locations. If KEYEN is 1, a secure user program can temporarily disengage security by: 1. Writing 1 to KEYACC in the FCNFG register. This makes the Flash module interpret writes to the backdoor comparison key locations (NVBACKKEY through NVBACKKEY+7) as values to be compared against the key rather than as the rst step in a Flash program or erase command. 2. Writing the user-entered key values to the NVBACKKEY through NVBACKKEY+7 locations. These writes must be performed in order starting with the value for NVBACKKEY and ending with NVBACKKEY+7. STHX must not be used for these writes because these writes cannot be performed on adjacent bus cycles. User software normally would get the key codes from outside the MCU system through a communication interface such as a serial I/O. 3. Writing 0 to KEYACC in the FCNFG register. If the 8-byte key that was written matches the key stored in the Flash locations, SEC bits are automatically changed to 1:0 and security will be disengaged until the next reset. The security key can be written only from secure memory (either RAM, EEPROM, or Flash), so it cannot be entered through background commands without the cooperation of a secure user program. The backdoor comparison key (NVBACKKEY through NVBACKKEY+7) is located in Flash memory locations in the nonvolatile register space so users can program these locations exactly as they would program any other Flash memory location. The nonvolatile registers are in the same 768-byte block of Flash as the reset and interrupt vectors, so block protecting that space also block protects the backdoor comparison key. Block protects cannot be changed from user application programs, so if the vector space is block protected, the backdoor security key mechanism cannot permanently change the block protect, security settings, or the backdoor key. Security can always be disengaged through the background debug interface by taking these steps: 1. Disable any block protections by writing FPROT. FPROT can be written only with background debug commands, not from application software. 2. Mass erase Flash if necessary. 3. Blank check Flash. Provided Flash is completely erased, security is disengaged until the next reset. To avoid returning to secure mode after the next reset, program NVOPT so SEC = 1:0.
Chapter 4 Memory
4.5.10
EEPROM Mapping
Only half of the EEPROM is in the memory map. The EPGSEL bit in FCNFG register selects which half of the array can be accessed in foreground while the other half can not be accessed in background. There are two mapping mode options that can be selected to congure the 8-byte EEPROM sectors: 4-byte mode and 8-byte mode. Each mode is selected by the EPGMOD bit in the FOPT register. In 4-byte sector mode (EPGMOD = 0), each 8-byte sector splits four bytes on foreground and four bytes on background but on the same addresses. The EPGSEL bit selects which four bytes can be accessed. During a sector erase, the entire 8-byte sector (four bytes in foreground and four bytes in background) is erased. In 8-byte sector mode (EPGMOD = 1), each entire 8-byte sector is in a single page. The EPGSEL bit selects which sectors are on background. During a sector erase, the entire 8-byte sector in foreground is erased.
4.5.11
Flash and EEPROM Registers and Control Bits
The Flash and EEPROM modules have seven 8-bit registers in the high-page register space and three locations in the nonvolatile register space in Flash memory. Two of those locations are copied into two corresponding high-page control registers at reset. There is also an 8-byte comparison key in Flash memory. Refer to Table 4-3 and Table 4-5 for the absolute address assignments for all Flash and EEPROM registers. This section refers to registers and control bits only by their names. A Freescale Semiconductor-provided equate or header le normally is used to translate these names into the appropriate absolute addresses.
4.5.11.1
Flash and EEPROM Clock Divider Register (FCDIV)
Bit 7 of this register is a read-only ag. Bits 6:0 may be read at any time but can be written only one time. Before any erase or programming operations are possible, write to this register to set the frequency of the clock for the nonvolatile memory system within acceptable limits.
7 6 5 4 3 2 1 0
R W Reset
DIVLD PRDIV8 0 0 0 0 0 DIV 0 0 0
= Unimplemented or Reserved
Figure 4-5. Flash and EEPROM Clock Divider Register (FCDIV)
Chapter 4 Memory
Table 4-7. FCDIV Register Field Descriptions

Field 7 DIVLD Description Divisor Loaded Status Flag When set, this read-only status ag indicates that the FCDIV register has been written since reset. Reset clears this bit and the rst write to this register causes this bit to become set regardless of the data written. 0 FCDIV has not been written since reset; erase and program operations disabled for Flash and EEPROM. 1 FCDIV has been written since reset; erase and program operations enabled for Flash and EEPROM. Prescale (Divide) Flash and EEPROM Clock by 8 (This bit is write once.) 0 Clock input to the Flash and EEPROM clock divider is the bus rate clock. 1 Clock input to the Flash and EEPROM clock divider is the bus rate clock divided by 8. Divisor for Flash and EEPROM Clock Divider These bits are write once. The Flash and EEPROM clock divider divides the bus rate clock (or the bus rate clock divided by 8 if PRDIV8 = 1) by the value in the 6-bit DIV eld plus one. The resulting frequency of the internal Flash and EEPROM clock must fall within the range of 200 kHz to 150 kHz for proper Flash and EEPROM operations. Program/Erase timing pulses are one cycle of this internal Flash and EEPROM clock which corresponds to a range of 5 s to 6.7 s. The automated programming logic uses an integer number of these pulses to complete an erase or program operation. See Equation 4-1 and Equation 4-2.
6 PRDIV8 5:0 DIV
if PRDIV8 = 0 fFCLK = fBus (DIV + 1) if PRDIV8 = 1 fFCLK = fBus (8 (DIV + 1))
Eqn. 4-1 Eqn. 4-2
Table 4-8 shows the appropriate values for PRDIV8 and DIV for selected bus frequencies.
Table 4-8. Flash and EEPROM Clock Divider Settings
fBus 20 MHz 10 MHz 8 MHz 4 MHz 2 MHz 1 MHz 200 kHz 150 kHz PRDIV8 (Binary) 1 0 0 0 0 0 0 0 DIV (Decimal) 12 49 39 19 9 4 0 0 fFCLK 192.3 kHz 200 kHz 200 kHz 200 kHz 200 kHz 200 kHz 200 kHz 150 kHz Program/Erase Timing Pulse (5 s Min, 6.7 s Max) 5.2 s 5 s 5 s 5 s 5 s 5 s 5 s 6.7 s
4.5.11.2
Flash and EEPROM Options Register (FOPT and NVOPT)
During reset, the contents of the nonvolatile location NVOPT are copied from Flash into FOPT. To change the value in this register, erase and reprogram the NVOPT location in Flash memory as usual and then issue a new MCU reset.
Chapter 4 Memory
R W Reset
KEYEN
FNORED
EPGMOD
SEC
F = loaded from nonvolatile location NVOPT during reset
Figure 4-6. Flash and EEPROM Options Register (FOPT) Table 4-9. FOPT Register Field Descriptions
Field 7 KEYEN Description Backdoor Key Mechanism Enable When this bit is 0, the backdoor key mechanism cannot be used to disengage security. The backdoor key mechanism is accessible only from user (secured) rmware. BDM commands cannot be used to write key comparison values that would unlock the backdoor key. For more detailed information about the backdoor key mechanism, refer to Section 4.5.9, Security. 0 No backdoor key access allowed. 1 If user rmware writes an 8-byte value that matches the nonvolatile backdoor key (NVBACKKEY through NVBACKKEY+7 in that order), security is temporarily disengaged until the next MCU reset. Vector Redirection Disable When this bit is 1, then vector redirection is disabled. 0 Vector redirection enabled. 1 Vector redirection disabled. EEPROM Sector Mode When this bit is 0, each sector is split into two pages (4-byte mode). When this bit is 1, each sector is in a single page (8-byte mode). 0 Half of each EEPROM sector is in Page 0 and the other half is in Page 1. 1 Each sector is in a single page. Security State Code This 2-bit eld determines the security state of the MCU as shown in Table 4-10. When the MCU is secure, the contents of RAM, EEPROM and Flash memory cannot be accessed by instructions from any unsecured source including the background debug interface. SEC changes to 1:0 after successful backdoor key entry or a successful blank check of Flash. For more detailed information about security, refer to Section 4.5.9, Security.
6 FNORED 5 EPGMOD
1:0 SEC
Table 4-10. Security States1

SEC[1:0] 0:0 0:1 1:0 1:1
1
Description secure secure unsecured secure
SEC changes to 1:0 after successful backdoor key entry or a successful blank check of Flash.
Chapter 4 Memory
4.5.11.3
Flash and EEPROM Conguration Register (FCNFG)

7 6 5 4 3 2 1 0
R W Reset
0 EPGSEL 0 0 KEYACC 0
Reserved1 1
Figure 4-7. Flash Conguration Register (FCNFG)

1
User must write a 1 to this bit. Failing to do so may result in unexpected behavior.
Table 4-11. FCNFG Register Field Descriptions

Field 6 EPGSEL 5 KEYACC Description EEPROM Page Select This bit selects which EEPROM page is accessed in the memory map. 0 Page 0 is in foreground of memory map. Page 1 is in background and can not be accessed. 1 Page 1 is in foreground of memory map. Page 0 is in background and can not be accessed. Enable Writing of Access Key This bit enables writing of the backdoor comparison key. For more detailed information about the backdoor key mechanism, refer to Section 4.5.9, Security. 0 Writes to 0xFFB00xFFB7 are interpreted as the start of a Flash programming or erase command. 1 Writes to NVBACKKEY (0xFFB00xFFB7) are interpreted as comparison key writes.
4.5.11.4
Flash and EEPROM Protection Register (FPROT and NVPROT)
The FPROT register denes which Flash and EEPROM sectors are protected against program and erase operations. During the reset sequence, the FPROT register is loaded from the nonvolatile location NVPROT. To change the protection that will be loaded during the reset sequence, the sector containing NVPROT must be unprotected and erased, then NVPROT can be reprogrammed. FPROT bits are readable at any time and writable as long as the size of the protected region is being increased. Any write to FPROT that attempts to decrease the size of the protected memory will be ignored. Trying to alter data in any protected area will result in a protection violation error and the FPVIOL ag will be set in the FSTAT register. Mass erase is not possible if any one of the sectors is protected.
7 6 5 4 3 2 1 0
R W Reset
1
EPS1
FPS1 This register is loaded from nonvolatile location NVPROT during reset.
Background commands can be used to change the contents of these bits in FPROT.
Figure 4-8. Flash and EEPROM Protection Register (FPROT)
Chapter 4 Memory
Table 4-12. FPROT Register Field Descriptions

Field 7:6 EPS 5:0 FPS Description EEPROM Protect Select Bits This 2-bit eld determines the protected EEPROM locations that cannot be erased or programmed. See Table 4-13. Flash Protect Select Bits This 6-bit eld determines the protected Flash locations that cannot be erased or programmed. SeeTable 4-14.
Table 4-13. EEPROM Block Protection

EPS 0x3 0x2 0x1 0x0 Address Area Protected N/A 0x17F0 - 0x17FF 0x17E0 - 0x17FF 0x17C00x17FF Memory Size Protected (bytes) 0 32 64 128 Number of Sectors Protected 0 4 8 16
Table 4-14. Flash Block Protection

FPS 0x3F 0x3E 0x3D 0x3C 0x3B ... 0x37 0x36 0x35 0x34 ... 0x2C 0x2B 0x2A 0x29 ... 0x22 0x21 0x20 0x1F ... Address Area Protected N/A 0xFA000xFFFF 0xF4000xFFFF 0xEE000xFFFF 0xE8000xFFFF ... 0xD0000xFFFF 0xCA000xFFFF 0xC4000xFFFF 0xBE000xFFFF ... 0x8E000xFFFF 0x88000xFFFF 0x82000xFFFF 0x7C000xFFFF ... 0x52000xFFFF 0x4C000xFFFF 0x46000xFFFF 0x40000xFFFF ... Memory Size Protected (bytes) 0 1.5K 3K 4.5K 6K ... 12K 13.5K 15K 16.5K ... 28.5K 30K 31.5K 33K ... 43.5K 45K 46.5K 48K ... Number of Sectors Protected 0 2 4 6 8 ... 16 18 20 22 ... 38 40 42 44 ... 58 60 62 64 ...
Chapter 4 Memory
Table 4-14. Flash Block Protection (continued)

FPS 0x1B 0x1A 0x19 0x180x00 Address Area Protected 0x28000xFFFF 0x22000xFFFF 0x1C000xFFFF 0x00000xFFFF Memory Size Protected (bytes) 54K 55.5K 57K 64K Number of Sectors Protected 72 74 76 86
4.5.11.5
R
Flash and EEPROM Status Register (FSTAT)

7 6 5 4 3 2 1 0
FCCF FCBEF FPVIOL 1 0 FACCERR 0
FBLANK
W Reset 1 0 0 0 0
Figure 4-9. Flash and EEPROM Status Register (FSTAT) Table 4-15. FSTAT Register Field Descriptions
Field 7 FCBEF Description Command Buffer Empty Flag The FCBEF bit is used to launch commands. It also indicates that the command buffer is empty so that a new command sequence can be executed when performing burst programming. The FCBEF bit is cleared by writing a 1 to it or when a burst program command is transferred to the array for programming. Only burst program commands can be buffered. 0 Command buffer is full (not ready for additional commands). 1 A new burst program command can be written to the command buffer. Command Complete Flag FCCF is set automatically when the command buffer is empty and no command is being processed. FCCF is cleared automatically when a new command is started (by writing 1 to FCBEF to register a command). Writing to FCCF has no meaning or effect. 0 Command in progress 1 All commands complete Protection Violation Flag FPVIOL is set automatically when a command that attempts to erase or program a location in a protected block is launched (the erroneous command is ignored). FPVIOL is cleared by writing a 1 to FPVIOL. 0 No protection violation. 1 An attempt was made to erase or program a protected location.
6 FCCF
5 FPVIOL
Chapter 4 Memory
Table 4-15. FSTAT Register Field Descriptions (continued)

Field 4 FACCERR Description Access Error Flag FACCERR is set automatically when the proper command sequence is not obeyed exactly (the erroneous command is ignored), if a program or erase operation is attempted before the FCDIV register has been initialized, or if the MCU enters stop while a command was in progress. For a more detailed discussion of the exact actions that are considered access errors, see Section 4.5.6, Access Errors. FACCERR is cleared by writing a 1 to FACCERR. Writing a 0 to FACCERR has no meaning or effect. 0 No access error. 1 An access error has occurred. Veried as All Blank (erased) Flag FBLANK is set automatically at the conclusion of a blank check command if the entire Flash or EEPROM array was veried to be erased. FBLANK is cleared by clearing FCBEF to write a new valid command. Writing to FBLANK has no meaning or effect. 0 After a blank check command is completed and FCCF = 1, FBLANK = 0 indicates the Flash or EEPROM array is not completely erased. 1 After a blank check command is completed and FCCF = 1, FBLANK = 1 indicates the Flash or EEPROM array is completely erased (all 0xFFFF).
2 FBLANK
4.5.11.6
Flash and EEPROM Command Register (FCMD)
Only six command codes are recognized in normal user modes, as shown in Table 4-16. All other command codes are illegal and generate an access error. Refer to Section 4.5.3, Program and Erase Command Execution, for a detailed discussion of Flash and EEPROM programming and erase operations.
7 6 5 4 3 2 1 0
R W Reset
0 FCMD
Figure 4-10. Flash and EEPROM Command Register (FCMD) Table 4-16. Flash and EEPROM Commands
Command Blank check Byte program Burst program Sector erase Mass erase Sector erase abort FCMD 0x05 0x20 0x25 0x40 0x41 0x47 Equate File Label mBlank mByteProg mBurstProg mSectorErase mMassErase mEraseAbort
It is not necessary to perform a blank check command after a mass erase operation. Only blank check is required as part of the security unlocking mechanism.
Chapter 4 Memory

5.1 Introduction
This section discusses basic reset and interrupt mechanisms and their various sources in the MC9S08DZ60 Series. Some interrupt sources from peripheral modules are discussed in greater detail within other sections of this data sheet. This section gathers basic information about all reset and interrupt sources in one place for easy reference. A few reset and interrupt sources, including the computer operating properly (COP) watchdog, are not part of on-chip peripheral systems with their own chapters.
5.2
Features
Reset and interrupt features include: Multiple sources of reset for exible system conguration and reliable operation Reset status register (SRS) to indicate source of most recent reset Separate interrupt vector for each module (reduces polling overhead); see Table 5-1
5.3
MCU Reset
Resetting the MCU provides a way to start processing from a known set of initial conditions. During reset, most control and status registers are forced to initial values and the program counter is loaded from the reset vector (0xFFFE:0xFFFF). On-chip peripheral modules are disabled and I/O pins are initially congured as general-purpose high-impedance inputs with pull-up devices disabled. The I bit in the condition code register (CCR) is set to block maskable interrupts so the user program has a chance to initialize the stack pointer (SP) and system control settings. (See the CPU chapter for information on the Interrupt (I) bit.) SP is forced to 0x00FF at reset. The MC9S08DZ60 Series has eight sources for reset: Power-on reset (POR) External pin reset (PIN) Computer operating properly (COP) timer Illegal opcode detect (ILOP) Illegal address detect (ILAD) Low-voltage detect (LVD) Loss of clock (LOC) Background debug forced reset (BDFR) Each of these sources, with the exception of the background debug forced reset, has an associated bit in the system reset status register (SRS).
5.4
Computer Operating Properly (COP) Watchdog
The COP watchdog is intended to force a system reset when the application software fails to execute as expected. To prevent a system reset from the COP timer (when it is enabled), application software must reset the COP counter periodically. If the application program gets lost and fails to reset the COP counter before it times out, a system reset is generated to force the system back to a known starting point. After any reset, the COP watchdog is enabled (see Section 5.8.4, System Options Register 1 (SOPT1), for additional information). If the COP watchdog is not used in an application, it can be disabled by clearing COPT bits in SOPT1. The COP counter is reset by writing 0x55 and 0xAA (in this order) to the address of SRS during the selected timeout period. Writes do not affect the data in the read-only SRS. As soon as the write sequence is done, the COP timeout period is restarted. If the program fails to do this during the time-out period, the MCU will reset. Also, if any value other than 0x55 or 0xAA is written to SRS, the MCU is immediately reset. The COPCLKS bit in SOPT2 (see Section 5.8.5, System Options Register 2 (SOPT2), for additional information) selects the clock source used for the COP timer. The clock source options are either the bus clock or an internal 1-kHz clock source. With each clock source, there are three associated time-outs controlled by the COPT bits in SOPT1. Table 5-6 summaries the control functions of the COPCLKS and COPT bits. The COP watchdog defaults to operation from the 1-kHz clock source and the longest time-out (210 cycles). When the bus clock source is selected, windowed COP operation is available by setting COPW in the SOPT2 register. In this mode, writes to the SRS register to clear the COP timer must occur in the last 25% of the selected timeout period. A premature write immediately resets the MCU. When the 1-kHz clock source is selected, windowed COP operation is not available. The COP counter is initialized by the rst writes to the SOPT1 and SOPT2 registers and after any system reset. Subsequent writes to SOPT1 and SOPT2 have no effect on COP operation. Even if the application will use the reset default settings of COPT, COPCLKS, and COPW bits, the user should write to the write-once SOPT1 and SOPT2 registers during reset initialization to lock in the settings. This will prevent accidental changes if the application program gets lost. The write to SRS that services (clears) the COP counter should not be placed in an interrupt service routine (ISR) because the ISR could continue to be executed periodically even if the main application program fails. If the bus clock source is selected, the COP counter does not increment while the MCU is in background debug mode or while the system is in stop mode. The COP counter resumes when the MCU exits background debug mode or stop mode. If the 1-kHz clock source is selected, the COP counter is re-initialized to zero upon entry to either background debug mode or stop mode and begins from zero upon exit from background debug mode or stop mode.
5.5
Interrupts
Interrupts provide a way to save the current CPU status and registers, execute an interrupt service routine (ISR), and then restore the CPU status so processing resumes where it left off before the interrupt. Other than the software interrupt (SWI), which is a program instruction, interrupts are caused by hardware events such as an edge on the IRQ pin or a timer-overow event. The debug module can also generate an SWI under certain circumstances. If an event occurs in an enabled interrupt source, an associated read-only status ag will become set. The CPU will not respond unless the local interrupt enable is a 1 to enable the interrupt and the I bit in the CCR is 0 to allow interrupts. The global interrupt mask (I bit) in the CCR is initially set after reset which prevents all maskable interrupt sources. The user program initializes the stack pointer and performs other system setup before clearing the I bit to allow the CPU to respond to interrupts. When the CPU receives a qualied interrupt request, it completes the current instruction before responding to the interrupt. The interrupt sequence obeys the same cycle-by-cycle sequence as the SWI instruction and consists of: Saving the CPU registers on the stack Setting the I bit in the CCR to mask further interrupts Fetching the interrupt vector for the highest-priority interrupt that is currently pending Filling the instruction queue with the rst three bytes of program information starting from the address fetched from the interrupt vector locations
While the CPU is responding to the interrupt, the I bit is automatically set to avoid the possibility of another interrupt interrupting the ISR itself (this is called nesting of interrupts). Normally, the I bit is restored to 0 when the CCR is restored from the value stacked on entry to the ISR. In rare cases, the I bit can be cleared inside an ISR (after clearing the status ag that generated the interrupt) so that other interrupts can be serviced without waiting for the rst service routine to nish. This practice is not recommended for anyone other than the most experienced programmers because it can lead to subtle program errors that are difcult to debug. The interrupt service routine ends with a return-from-interrupt (RTI) instruction which restores the CCR, A, X, and PC registers to their pre-interrupt values by reading the previously saved information from the stack. NOTE For compatibility with M68HC08 devices, the H register is not automatically saved and restored. It is good programming practice to push H onto the stack at the start of the interrupt service routine (ISR) and restore it immediately before the RTI that is used to return from the ISR. If more than one interrupt is pending when the I bit is cleared, the highest priority source is serviced rst (see Table 5-1).
5.5.1
Interrupt Stack Frame
Figure 5-1 shows the contents and organization of a stack frame. Before the interrupt, the stack pointer (SP) points at the next available byte location on the stack. The current values of CPU registers are stored on the stack starting with the low-order byte of the program counter (PCL) and ending with the CCR. After stacking, the SP points at the next available location on the stack which is the address that is one less than the address where the CCR was saved. The PC value that is stacked is the address of the instruction in the main program that would have executed next if the interrupt had not occurred.
UNSTACKING ORDER 7 5 4 3 2 1 1 2 3 4 5 TOWARD LOWER ADDRESSES 0 SP AFTER INTERRUPT STACKING CONDITION CODE REGISTER ACCUMULATOR INDEX REGISTER (LOW BYTE X)* PROGRAM COUNTER HIGH PROGRAM COUNTER LOW SP BEFORE THE INTERRUPT
STACKING ORDER
TOWARD HIGHER ADDRESSES * High byte (H) of index register is not automatically stacked.
Figure 5-1. Interrupt Stack Frame
When an RTI instruction is executed, these values are recovered from the stack in reverse order. As part of the RTI sequence, the CPU lls the instruction pipeline by reading three bytes of program information, starting from the PC address recovered from the stack. The status ag corresponding to the interrupt source must be acknowledged (cleared) before returning from the ISR. Typically, the ag is cleared at the beginning of the ISR so that if another interrupt is generated by this same source, it will be registered so it can be serviced after completion of the current ISR.
5.5.2
External Interrupt Request (IRQ) Pin
External interrupts are managed by the IRQ status and control register, IRQSC. When the IRQ function is enabled, synchronous logic monitors the pin for edge-only or edge-and-level events. When the MCU is in stop mode and system clocks are shut down, a separate asynchronous path is used so the IRQ (if enabled) can wake the MCU.
5.5.2.1
Pin Conguration Options
The IRQ pin enable (IRQPE) control bit in IRQSC must be 1 in order for the IRQ pin to act as the interrupt request (IRQ) input. As an IRQ input, the user can choose the polarity of edges or levels detected (IRQEDG), whether the pin detects edges-only or edges and levels (IRQMOD), and whether an event causes an interrupt or only sets the IRQF ag which can be polled by software.
The IRQ pin, when enabled, defaults to use an internal pull device (IRQPDD = 0), the device is a pull-up or pull-down depending on the polarity chosen. If the user desires to use an external pull-up or pull-down, the IRQPDD can be written to a 1 to turn off the internal device. BIH and BIL instructions may be used to detect the level on the IRQ pin when the pin is congured to act as the IRQ input.
5.5.2.2
Edge and Level Sensitivity
The IRQMOD control bit recongures the detection logic so it detects edge events and pin levels. In the edge and level detection mode, the IRQF status ag becomes set when an edge is detected (when the IRQ pin changes from the deasserted to the asserted level), but the ag is continuously set (and cannot be cleared) as long as the IRQ pin remains at the asserted level.
5.5.3
Interrupt Vectors, Sources, and Local Masks
Table 5-1 provides a summary of all interrupt sources. Higher-priority sources are located toward the bottom of the table. The high-order byte of the address for the interrupt service routine is located at the rst address in the vector address column, and the low-order byte of the address for the interrupt service routine is located at the next higher address. When an interrupt condition occurs, an associated ag bit becomes set. If the associated local interrupt enable is 1, an interrupt request is sent to the CPU. Within the CPU, if the global interrupt mask (I bit in the CCR) is 0, the CPU will nish the current instruction; stack the PCL, PCH, X, A, and CCR CPU registers; set the I bit; and then fetch the interrupt vector for the highest priority pending interrupt. Processing then continues in the interrupt service routine.
Table 5-1. Vector Summary1

Vector No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address (High/Low) 0xFFC0/0xFFC1 0xFFC2/0xFFC3 0xFFC4/0xFFC5 0xFFC6/0xFFC7 0xFFC8/0xFFC9 0xFFCA/0xFFCB 0xFFCC/0xFFCD 0xFFCE/0xFFCF 0xFFD0/0xFFD1 0xFFD2/0xFFD3 0xFFD4/0xFFD5 0xFFD6/0xFFD7 0xFFD8/0xFFD9 0xFFDA/0xFFDB 0xFFDC/0xFFDD 0xFFDE/0xFFDF 0xFFE0/0xFFE1 0xFFE2/0xFFE3 0xFFE4/0xFFE5 0xFFE6/0xFFE7 0xFFE8/0xFFE9 0xFFEA/0xFFEB 0xFFEC/0xFFED 0xFFEE/0xFFEF 0xFFF0/0xFFF1 0xFFF2/0xFFF3 0xFFF4/0xFFF5 0xFFF6/0xFFF7 0xFFF8/0xFFF9 0xFFFA/0xFFFB 0xFFFC/0xFFFD 0xFFFE/0xFFFF Vector Name Vacmp2 Vacmp1 Vcantx Vcanrx Vcanerr Vcanwu Vrtc Viic Vadc Vport Vsci2tx Vsci2rx Vsci2err Vsci1tx Vsci1rx Vsci1err Vspi Vtpm2ovf Vtpm2ch1 Vtpm2ch0 Vtpm1ovf Vtpm1ch5 Vtpm1ch4 Vtpm1ch3 Vtpm1ch2 Vtpm1ch1 Vtpm1ch0 Vlol Vlvd Virq Vswi Vreset Module ACMP2 ACMP1 MSCAN MSCAN MSCAN MSCAN RTC IIC ADC Port A,B,D SCI2 SCI2 SCI2 SCI1 SCI1 SCI1 SPI TPM2 TPM2 TPM2 TPM1 TPM1 TPM1 TPM1 TPM1 TPM1 TPM1 MCG System control IRQ Core System control Source Enable Description Analog comparator 2 Analog comparator 1 CAN transmit CAN receive CAN errors CAN wake-up Real-time interrupt IIC control ADC Port Pins SCI2 transmit SCI2 receive SCI2 error SCI1 transmit SCI1 receive SCI1 error SPI TPM2 overow TPM2 channel 1 TPM2 channel 0 TPM1 overow TPM1 channel 5 TPM1 channel 4 TPM1 channel 3 TPM1 channel 2 TPM1 channel 1 TPM1 channel 0 MCG loss of lock Low-voltage warning IRQ pin Software interrupt Watchdog timer Loss-of-clock Low-voltage detect External pin Illegal opcode Illegal address Power-on-reset BDM-forced reset
ACF ACIE ACF ACIE TXE[2:0] TXEIE[2:0] RXF RXFIE CSCIF, OVRIF CSCIE, OVRIE WUPIF WUPIE RTIF RTIE IICIS IICIE COCO AIEN PTAIF, PTBIF, PTAIE, PTBIE, PTDIE PTDIF TDRE, TC TIE, TCIE IDLE, LBKDIF, ILIE, LBKDIE, RIE, RDRF, RXEDGIF RXEDGIE OR, NF ORIE, NFIE, FE, PF FEIE, PFIE TDRE, TC TIE, TCIE IDLE, LBKDIF, ILIE, LBKDIE, RIE, RDRF, RXEDGIF RXEDGIE OR, NF, ORIE, NFIE, FE, PF FEIE, PFIE SPIF, MODF, SPIE, SPIE, SPTIE SPTEF TOF TOIE CH1F CH1IE CH0F CH0IE TOF TOIE CH5F CH5IE CH4F CH4IE CH3F CH3IE CH2F CH2IE CH1F CH1IE CH0F CH0IE LOLS LOLIE LVWF LVWIE IRQF SWI Instruction COP, LOC, LVD, RESET, ILOP, ILAD, POR, BDFR IRQIE COPE CME LVDRE
Vector priority is shown from lowest (rst row) to highest (last row). For example, Vreset is the highest priority vector.
5.6
Low-Voltage Detect (LVD) System
The MC9S08DZ60 Series includes a system to protect against low-voltage conditions in order to protect memory contents and control MCU system states during supply voltage variations. The system is comprised of a power-on reset (POR) circuit and a LVD circuit with trip voltages for warning and detection. The LVD circuit is enabled when LVDE in SPMSC1 is set to 1. The LVD is disabled upon entering any of the stop modes unless LVDSE is set in SPMSC1. If LVDSE and LVDE are both set, then the MCU cannot enter stop2 (it will enter stop3 instead), and the current consumption in stop3 with the LVD enabled will be higher.
5.6.1
Power-On Reset Operation
When power is initially applied to the MCU, or when the supply voltage drops below the power-on reset rearm voltage level, VPOR, the POR circuit will cause a reset condition. As the supply voltage rises, the LVD circuit will hold the MCU in reset until the supply has risen above the low-voltage detection low threshold, VLVDL. Both the POR bit and the LVD bit in SRS are set following a POR.
5.6.2
Low-Voltage Detection (LVD) Reset Operation
The LVD can be congured to generate a reset upon detection of a low-voltage condition by setting LVDRE to 1. The low-voltage detection threshold is determined by the LVDV bit. After an LVD reset has occurred, the LVD system will hold the MCU in reset until the supply voltage has risen above the low-voltage detection threshold. The LVD bit in the SRS register is set following either an LVD reset or POR.
5.6.3
Low-Voltage Warning (LVW) Interrupt Operation
The LVD system has a low-voltage warning ag to indicate to the user that the supply voltage is approaching the low-voltage condition. When a low-voltage warning condition is detected and is congured for interrupt operation (LVWIE set to 1), LVWF in SPMSC1 will be set and an LVW interrupt request will occur.
5.7
MCLK Output
The PTA0 pin is shared with the MCLK clock output. If the MCSEL bits are all zeroes, the MCLK clock is disabled. Setting any of the MCSEL bits causes the PTA0 pin to output a divided version of the internal MCU bus clock regardless of the state of the port data direction control bit for the pin. The divide ratio is determined by the MCSEL bits. The slew rate and drive strength for the pin are controlled by PTASE0 and PTADS0, respectively. The maximum clock output frequency is limited if slew rate control is enabled, see the electrical specications for the maximum frequency under different conditions.
5.8
Reset, Interrupt, and System Control Registers and Control Bits
One 8-bit register in the direct page register space and eight 8-bit registers in the high-page register space are related to reset and interrupt systems. Refer to Table 4-2 and Table 4-3 in Chapter 4, Memory, of this data sheet for the absolute address assignments for all registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header le is used to translate these names into the appropriate absolute addresses. Some control bits in the SOPT1 and SPMSC2 registers are related to modes of operation. Although brief descriptions of these bits are provided here, the related functions are discussed in greater detail in Chapter 3, Modes of Operation.
5.8.1
Interrupt Pin Request Status and Control Register (IRQSC)
This direct page register includes status and control bits which are used to congure the IRQ function, report status, and acknowledge IRQ events.
7 6 5 4 3 2 1 0
R W Reset
0 IRQPDD 0 0 IRQEDG 0 IRQPE
IRQF
0 IRQIE IRQACK IRQMOD 0
Figure 5-2. Interrupt Request Status and Control Register (IRQSC) Table 5-2. IRQSC Register Field Descriptions
Field 6 IRQPDD Description Interrupt Request (IRQ) Pull Device Disable This read/write control bit is used to disable the internal pull-up/pull-down device when the IRQ pin is enabled (IRQPE = 1) allowing for an external device to be used. 0 IRQ pull device enabled if IRQPE = 1. 1 IRQ pull device disabled if IRQPE = 1. Interrupt Request (IRQ) Edge Select This read/write control bit is used to select the polarity of edges or levels on the IRQ pin that cause IRQF to be set. The IRQMOD control bit determines whether the IRQ pin is sensitive to both edges and levels or only edges. When the IRQ pin is enabled as the IRQ input and is congured to detect rising edges, it has a pull-down. When the IRQ pin is enabled as the IRQ input and is congured to detect falling edges, it has a pull-up. 0 IRQ is falling edge or falling edge/low-level sensitive. 1 IRQ is rising edge or rising edge/high-level sensitive. IRQ Pin Enable This read/write control bit enables the IRQ pin function. When this bit is set the IRQ pin can be used as an interrupt request. 0 IRQ pin function is disabled. 1 IRQ pin function is enabled. IRQ Flag This read-only status bit indicates when an interrupt request event has occurred. 0 No IRQ request. 1 IRQ event detected. IRQ Acknowledge This write-only bit is used to acknowledge interrupt request events (write 1 to clear IRQF). Writing 0 has no meaning or effect. Reads always return 0. If edge-and-level detection is selected (IRQMOD = 1), IRQF cannot be cleared while the IRQ pin remains at its asserted level. IRQ Interrupt Enable This read/write control bit determines whether IRQ events generate an interrupt request. 0 Interrupt request when IRQF set is disabled (use polling). 1 Interrupt requested whenever IRQF = 1. IRQ Detection Mode This read/write control bit selects either edge-only detection or edge-and-level detection. The IRQEDG control bit determines the polarity of edges and levels that are detected as interrupt request events. See Section 5.5.2.2, Edge and Level Sensitivity for more details. 0 IRQ event on falling edges or rising edges only. 1 IRQ event on falling edges and low levels or on rising edges and high levels.
5 IRQEDG
4 IRQPE
3 IRQF 2 IRQACK 1 IRQIE
0 IRQMOD
5.8.2
System Reset Status Register (SRS)
This high page register includes read-only status ags to indicate the source of the most recent reset. When a debug host forces reset by writing 1 to BDFR in the SBDFR register, none of the status bits in SRS will be set. Writing any value to this register address causes a COP reset when the COP is enabled except the values 0x55 and 0xAA. Writing a 0x55-0xAA sequence to this address clears the COP watchdog timer without affecting the contents of this register. The reset state of these bits depends on what caused the MCU to reset.
7 6 5 4 3 2 1 0
R W
POR: LVD: Any other reset:
1
POR
PIN
COP
ILOP
ILAD
LOC
LVD
Writing 0x55, 0xAA to SRS address clears COP watchdog timer. 1 u 0 0 0 Note(1) 0 0 Note(1) 0 0 Note(1) 0 0 Note(1) 0 0 0 1 1 0 0 0 0
Any of these reset sources that are active at the time of reset entry will cause the corresponding bit(s) to be set; bits corresponding to sources that are not active at the time of reset entry will be cleared.
Figure 5-3. System Reset Status (SRS) Table 5-3. SRS Register Field Descriptions
Field 7 POR Description Power-On Reset Reset was caused by the power-on detection logic. Because the internal supply voltage was ramping up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the reset occurred while the internal supply was below the LVD threshold. 0 Reset not caused by POR. 1 POR caused reset. External Reset Pin Reset was caused by an active-low level on the external reset pin. 0 Reset not caused by external reset pin. 1 Reset came from external reset pin. Computer Operating Properly (COP) Watchdog Reset was caused by the COP watchdog timer timing out. This reset source can be blocked by COPE = 0. 0 Reset not caused by COP timeout. 1 Reset caused by COP timeout. Illegal Opcode Reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP instruction is considered illegal if stop is disabled by STOPE = 0 in the SOPT register. The BGND instruction is considered illegal if active background mode is disabled by ENBDM = 0 in the BDCSC register. 0 Reset not caused by an illegal opcode. 1 Reset caused by an illegal opcode. Illegal Address Reset was caused by an attempt to access either data or an instruction at an unimplemented memory address. 0 Reset not caused by an illegal address. 1 Reset caused by an illegal address.
6 PIN 5 COP
4 ILOP
3 ILAD
Table 5-3. SRS Register Field Descriptions

Field 2 LOC 1 LVD Description Loss of Clock Reset was caused by a loss of external clock. 0 Reset not caused by loss of external clock 1 Reset caused by loss of external clock Low-Voltage Detect If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset will occur. This bit is also set by POR. 0 Reset not caused by LVD trip or POR. 1 Reset caused by LVD trip or POR.
5.8.3
System Background Debug Force Reset Register (SBDFR)
This high page register contains a single write-only control bit. A serial background command such as WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are ignored. Reads always return 0x00.
7 6 5 4 3 2 1 0
R W Reset:
0 BDFR1
1
BDFR is writable only through serial background debug commands, not from user programs.
Figure 5-4. System Background Debug Force Reset Register (SBDFR) Table 5-4. SBDFR Register Field Descriptions
Field 0 BDFR Description Background Debug Force Reset A serial background command such as WRITE_BYTE can be used to allow an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from a user program.
5.8.4
System Options Register 1 (SOPT1)
This high page register is a write-once register so only the rst write after reset is honored. It can be read at any time. Any subsequent attempt to write to SOPT1 (intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings. This register should be written during the users reset initialization program to set the desired controls even if the desired settings are the same as the reset settings.
7 6 5 4 3 2 1 0
R COPT W Reset: 1 1 0 0 0 STOPE SCI2PS IICPS
Figure 5-5. System Options Register 1 (SOPT1) Table 5-5. SOPT1 Register Field Descriptions
Field 7:6 COPT[1:0] 5 STOPE Description COP Watchdog Timeout These write-once bits select the timeout period of the COP. COPT along with COPCLKS in SOPT2 denes the COP timeout period. See Table 5-6. Stop Mode Enable This write-once bit is used to enable stop mode. If stop mode is disabled and a user program attempts to execute a STOP instruction, an illegal opcode reset is forced. 0 Stop mode disabled. 1 Stop mode enabled. SCI2 Pin Select This write-once bit selects the location of the RxD2 and TxD2 pins of the SCI2 module. 0 TxD2 on PTF0, RxD2 on PTF1. 1 TxD2 on PTE6, RxD2 on PTE7. IIC Pin Select This write-once bit selects the location of the SCL and SDA pins of the IIC module. 0 SCL on PTF2, SDA on PTF3. 1 SCL on PTE4, SDA on PTE5.
4 SCI2PS 3 IICPS
Table 5-6. COP Conguration Options

Control Bits Clock Source COPCLKS N/A 0 0 0 1 1 1
1
COPT[1:0] 0:0 0:1 1:0 1:1 0:1 1:0 1:1 N/A 1 kHz 1 kHz 1 kHz Bus Bus Bus
COP Window1 Opens (COPW = 1) N/A N/A N/A N/A 6144 cycles 49,152 cycles 196,608 cycles
COP Overow Count COP is disabled 25 cycles (32 ms2) 28 cycles (256 ms1) 210 cycles (1.024 s1) 213 cycles 216 cycles 218 cycles
Windowed COP operation requires the user to clear the COP timer in the last 25% of the selected timeout period. This column displays the minimum number of clock counts required before the COP timer can be reset when in windowed COP mode (COPW = 1). 2 Values shown in milliseconds based on t LPO = 1 ms. See tLPO in the appendix Section A.12.1, Control Timing, for the tolerance of this value.
5.8.5
System Options Register 2 (SOPT2)
This high page register contains bits to congure MCU specic features on the MC9S08DZ60 Series devices.
7 6 5 4 3 2 1 0
R W Reset:
COPCLKS1 0
COPW1 0
0 ADHTS 0 0
0 MCSEL 0 0 0 0
Figure 5-6. System Options Register 2 (SOPT2)

1
This bit can be written only one time after reset. Additional writes are ignored.
Table 5-7. SOPT2 Register Field Descriptions

Field 7 COPCLKS Description COP Watchdog Clock Select This write-once bit selects the clock source of the COP watchdog. See Table 5-6 for details. 0 Internal 1-kHz clock is source to COP. 1 Bus clock is source to COP. COP Window This write-once bit selects the COP operation mode. When set, the 0x55-0xAA write sequence to the SRS register must occur in the last 25% of the selected period. Any write to the SRS register during the rst 75% of the selected period will reset the MCU. 0 Normal COP operation. 1 Window COP operation. ADC Hardware Trigger Select This bit selects which hardware trigger initiates conversion for the analog to digital converter when the ADC hardware trigger is enabled (ADCTRG is set in ADCSC2 register). 0 Real Time Counter (RTC) overow. 1 External Interrupt Request (IRQ) pin. MCLK Divide Select These bits enable the MCLK output on PTA0 pin and select the divide ratio for the MCLK output according to the formula below when the MCSEL bits are not equal to all zeroes. In case that the MCSEL bits are all zeroes, the MCLK output is disabled.
6 COPW
4 ADHTS
2:0 MCSEL
MCLK frequency = Bus Clock frequency (2 * MCSEL)
5.8.6
System Device Identication Register (SDIDH, SDIDL)
These high page read-only registers are included so host development systems can identify the HCS08 derivative and revision number. This allows the development software to recognize where specic memory blocks, registers, and control bits are located in a target MCU.
7 6 5 4 3 2 1 0
R W Reset: 01 01
Reserved
ID11
ID10
ID9
ID8
01
01
1
The revision number that is hard coded into these bits reects the current silicon revision level.
Figure 5-7. System Device Identication Register High (SDIDH) Table 5-8. SDIDH Register Field Descriptions
Field 3:0 ID[11:8] Description Part Identication Number MC9S08DZ60 Series MCUs are hard-coded to the value 0x00E. See also ID bits in Table 5-9.
R W Reset:
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
Figure 5-8. System Device Identication Register Low (SDIDL) Table 5-9. SDIDL Register Field Descriptions
Field 7:0 ID[7:0] Description Part Identication Number MC9S08DZ60 Series MCUs are hard-coded to the value 0x00E. See also ID bits in Table 5-8.
5.8.7
System Power Management Status and Control 1 Register (SPMSC1)
This high page register contains status and control bits to support the low-voltage detect function, and to enable the bandgap voltage reference for use by the ADC and ACMP modules. This register should be written during the users reset initialization program to set the desired controls even if the desired settings are the same as the reset settings.
7 6 1 5 4 3 2 1 0
R W Reset:
LVWF
0 LVWIE LVWACK
LVDRE2 1
LVDSE 1
LVDE2 1
0 BGBE 0 0
1 2
LVWF will be set in the case when VSupply transitions below the trip point or after reset and VSupply is already below VLVW. This bit can be written only one time after reset. Additional writes are ignored.
Figure 5-9. System Power Management Status and Control 1 Register (SPMSC1) Table 5-10. SPMSC1 Register Field Descriptions
Field 7 LVWF 6 LVWACK 5 LVWIE 4 LVDRE Description Low-Voltage Warning Flag The LVWF bit indicates the low-voltage warning status. 0 low-voltage warning is not present. 1 low-voltage warning is present or was present. Low-Voltage Warning Acknowledge If LVWF = 1, a low-voltage condition has occurred. To acknowledge this low-voltage warning, write 1 to LVWACK, which will automatically clear LVWF to 0 if the low-voltage warning is no longer present. Low-Voltage Warning Interrupt Enable This bit enables hardware interrupt requests for LVWF. 0 Hardware interrupt disabled (use polling). 1 Request a hardware interrupt when LVWF = 1. Low-Voltage Detect Reset Enable This write-once bit enables LVD events to generate a hardware reset (provided LVDE = 1). 0 LVD events do not generate hardware resets. 1 Force an MCU reset when an enabled low-voltage detect event occurs. Low-Voltage Detect Stop Enable Provided LVDE = 1, this read/write bit determines whether the low-voltage detect function operates when the MCU is in stop mode. 0 Low-voltage detect disabled during stop mode. 1 Low-voltage detect enabled during stop mode. Low-Voltage Detect Enable This write-once bit enables low-voltage detect logic and qualies the operation of other bits in this register. 0 LVD logic disabled. 1 LVD logic enabled. Bandgap Buffer Enable This bit enables an internal buffer for the bandgap voltage reference for use by the ADC and ACMP modules on one of its internal channels. 0 Bandgap buffer disabled. 1 Bandgap buffer enabled.
3 LVDSE
2 LVDE
0 BGBE
5.8.8
System Power Management Status and Control 2 Register (SPMSC2)
This register is used to report the status of the low-voltage warning function, and to congure the stop mode behavior of the MCU. This register should be written during the users reset initialization program to set the desired controls even if the desired settings are the same as the reset settings.
7 6 5 4 3 2 1 0
R W Power-on Reset: LVD Reset: Any other Reset:
LVDV1 0 u u
PPDF LVWV
0 PPDACK
PPDC2
0 0 0
0 0 0
0 0 0
0 u u
0 0 0
0 0 0
0 0 0
1 2
u = Unaffected by reset
This bit can be written only one time after power-on reset. Additional writes are ignored. This bit can be written only one time after reset. Additional writes are ignored.
Figure 5-10. System Power Management Status and Control 2 Register (SPMSC2) Table 5-11. SPMSC2 Register Field Descriptions
Field 5 LVDV 4 LVWV 3 PPDF 2 PPDACK 0 PPDC Description Low-Voltage Detect Voltage Select This write-once bit selects the low-voltage detect (LVD) trip point setting. It also selects the warning voltage range. See Table 5-12. Low-Voltage Warning Voltage Select This bit selects the low-voltage warning (LVW) trip point voltage. See Table 5-12. Partial Power Down Flag This read-only status bit indicates that the MCU has recovered from stop2 mode. 0 MCU has not recovered from stop2 mode. 1 MCU recovered from stop2 mode. Partial Power Down Acknowledge Writing a 1 to PPDACK clears the PPDF bit. Partial Power Down Control This write-once bit controls whether stop2 or stop3 mode is selected. 0 Stop3 mode enabled. 1 Stop2, partial power down, mode enabled.
Table 5-12. LVD and LVW Trip Point Typical Values1

LVDV:LVWV 0:0 0:1 1:0 1:1
1
LVW Trip Point VLVW0 = 2.74 V VLVW1 = 2.92 V VLVW2 = 4.3 V VLVW3 = 4.6 V
LVD Trip Point VLVD0 = 2.56 V VLVD1 = 4.0 V
See Electrical Characteristics appendix for minimum and maximum values.

This section explains software controls related to parallel input/output (I/O) and pin control. The MC9S08DZ60 Series has seven parallel I/O ports which include a total of up to 53 I/O pins and one input-only pin. See Chapter 2, Pins and Connections, for more information about pin assignments and external hardware considerations of these pins. Many of these pins are shared with on-chip peripherals such as timer systems, communication systems, or pin interrupts as shown in Table 2-1. The peripheral modules have priority over the general-purpose I/O functions so that when a peripheral is enabled, the I/O functions associated with the shared pins are disabled. After reset, the shared peripheral functions are disabled and the pins are congured as inputs (PTxDDn = 0). The pin control functions for each pin are congured as follows: slew rate control enabled (PTxSEn = 1), low drive strength selected (PTxDSn = 0), and internal pull-ups disabled (PTxPEn = 0). NOTE Not all general-purpose I/O pins are available on all packages. To avoid extra current drain from oating input pins, the users reset initialization routine in the application program must either enable on-chip pull-up devices or change the direction of unconnected pins to outputs so the pins do not oat. The PTE1 pin does not contain a clamp diode to VDD and should not be driven above VDD. The voltage measured on the internally pulled up PTE1 pin may be as low as VDD 0.7 V. The internal gates connected to this pin are pulled all the way to VDD.
6.1
Port Data and Data Direction
Reading and writing of parallel I/Os are performed through the port data registers. The direction, either input or output, is controlled through the port data direction registers. The parallel I/O port function for an individual pin is illustrated in the block diagram shown in Figure 6-1. The data direction control bit (PTxDDn) determines whether the output buffer for the associated pin is enabled, and also controls the source for port data register reads. The input buffer for the associated pin is always enabled unless the pin is enabled as an analog function or is an output-only pin. When a shared digital function is enabled for a pin, the output buffer is controlled by the shared function. However, the data direction register bit will continue to control the source for reads of the port data register. When a shared analog function is enabled for a pin, both the input and output buffers are disabled. A value of 0 is read for any port data bit where the bit is an input (PTxDDn = 0) and the input buffer is disabled.
In general, whenever a pin is shared with both an alternate digital function and an analog function, the analog function has priority such that if both the digital and analog functions are enabled, the analog function controls the pin. It is a good programming practice to write to the port data register before changing the direction of a port pin to become an output. This ensures that the pin will not be driven momentarily with an old data value that happened to be in the port data register.
PTxDDn
Output Enable
PTxDn
Output Data
1 Port Read Data 0 Synchronizer Input Data
BUSCLK Figure 6-1. Parallel I/O Block Diagram
6.2
Pull-up, Slew Rate, and Drive Strength
Associated with the parallel I/O ports is a set of registers located in the high page register space that operate independently of the parallel I/O registers. These registers are used to control pull-ups, slew rate, and drive strength for the pins. An internal pull-up device can be enabled for each port pin by setting the corresponding bit in the pull-up enable register (PTxPEn). The pull-up device is disabled if the pin is congured as an output by the parallel I/O control logic or any shared peripheral function regardless of the state of the corresponding pull-up enable register bit. The pull-up device is also disabled if the pin is controlled by an analog function. Slew rate control can be enabled for each port pin by setting the corresponding bit in the slew rate control register (PTxSEn). When enabled, slew control limits the rate at which an output can transition in order to reduce EMC emissions. Slew rate control has no effect on pins that are congured as inputs. NOTE Slew rate reset default values may differ between engineering samples and nal production parts. Always initialize slew rate control to the desired value to ensure correct operation.
An output pin can be selected to have high output drive strength by setting the corresponding bit in the drive strength select register (PTxDSn). When high drive is selected, a pin is capable of sourcing and sinking greater current. Even though every I/O pin can be selected as high drive, the user must ensure that the total current source and sink limits for the MCU are not exceeded. Drive strength selection is intended to affect the DC behavior of I/O pins. However, the AC behavior is also affected. High drive allows a pin to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load. Because of this, the EMC emissions may be affected by enabling pins as high drive.
6.3
Pin Interrupts
Port A, port B, and port D pins can be congured as external interrupt inputs and as an external means of waking the MCU from stop or wait low-power modes. The block diagram for each port interrupt logic is shown Figure 6-2.
PTxACK 1 PTxn 0 S PTxPS0 VDD D CLR Q CK PTxES0 PORT INTERRUPT FF S PTxPSn PTxMOD PTxIE PTxESn STOP STOP BYPASS PTx INTERRUPT REQUEST RESET SYNCHRONIZER BUSCLK PTxIF
1 PTxn 0
Figure 6-2. Port Interrupt Block Diagram
Writing to the PTxPSn bits in the port interrupt pin select register (PTxPS) independently enables or disables each port pin. Each port can be congured as edge sensitive or edge and level sensitive based on the PTxMOD bit in the port interrupt status and control register (PTxSC). Edge sensitivity can be software programmed to be either falling or rising; the level can be either low or high. The polarity of the edge or edge and level sensitivity is selected using the PTxESn bits in the port interrupt edge select register (PTxES). Synchronous logic is used to detect edges. Prior to detecting an edge, enabled port inputs must be at the deasserted logic level. A falling edge is detected when an enabled port input signal is seen as a logic 1 (the deasserted level) during one bus cycle and then a logic 0 (the asserted level) during the next cycle. A rising edge is detected when the input signal is seen as a logic 0 during one bus cycle and then a logic 1 during the next cycle.
6.3.1
Edge Only Sensitivity
A valid edge on an enabled port pin will set PTxIF in PTxSC. If PTxIE in PTxSC is set, an interrupt request will be presented to the CPU. Clearing of PTxIF is accomplished by writing a 1 to PTxACK in PTxSC.
6.3.2
Edge and Level Sensitivity
A valid edge or level on an enabled port pin will set PTxIF in PTxSC. If PTxIE in PTxSC is set, an interrupt request will be presented to the CPU. Clearing of PTxIF is accomplished by writing a 1 to PTxACK in PTxSC provided all enabled port inputs are at their deasserted levels. PTxIF will remain set if any enabled port pin is asserted while attempting to clear by writing a 1 to PTxACK.
6.3.3
Pull-up/Pull-down Resistors
The port interrupt pins can be congured to use an internal pull-up/pull-down resistor using the associated I/O port pull-up enable register. If an internal resistor is enabled, the PTxES register is used to select whether the resistor is a pull-up (PTxESn = 0) or a pull-down (PTxESn = 1).
6.3.4
Pin Interrupt Initialization
When an interrupt pin is rst enabled, it is possible to get a false interrupt ag. To prevent a false interrupt request during pin interrupt initialization, the user should do the following: 1. Mask interrupts by clearing PTxIE in PTxSC. 2. Select the pin polarity by setting the appropriate PTxESn bits in PTxES. 3. If using internal pull-up/pull-down device, congure the associated pull enable bits in PTxPE. 4. Enable the interrupt pins by setting the appropriate PTxPSn bits in PTxPS. 5. Write to PTxACK in PTxSC to clear any false interrupts. 6. Set PTxIE in PTxSC to enable interrupts.
6.4
Pin Behavior in Stop Modes
Pin behavior following execution of a STOP instruction depends on the stop mode that is entered. An explanation of pin behavior for the various stop modes follows: Stop2 mode is a partial power-down mode, whereby I/O latches are maintained in their state as before the STOP instruction was executed. CPU register status and the state of I/O registers should be saved in RAM before the STOP instruction is executed to place the MCU in stop2 mode. Upon recovery from stop2 mode, before accessing any I/O, the user should examine the state of the PPDF bit in the SPMSC2 register. If the PPDF bit is 0, I/O must be initialized as if a power on reset had occurred. If the PPDF bit is 1, peripherals may require initialization to be restored to their pre-stop condition. This can be done using data previously stored in RAM if it was saved before the STOP instruction was executed. The user must then write a 1 to the PPDACK bit in the SPMSC2 register. Access to I/O is now permitted again in the user application program. In stop3 mode, all I/O is maintained because internal logic circuity stays powered up. Upon recovery, normal I/O function is available to the user.
6.5
Parallel I/O and Pin Control Registers
This section provides information about the registers associated with the parallel I/O ports. The data and data direction registers are located in page zero of the memory map. The pull up, slew rate, drive strength, and interrupt control registers are located in the high page section of the memory map. Refer to tables in Chapter 4, Memory, for the absolute address assignments for all parallel I/O and their pin control registers. This section refers to registers and control bits only by their names. A Freescale Semiconductor-provided equate or header le normally is used to translate these names into the appropriate absolute addresses.
6.5.1
Port A Registers
Port A is controlled by the registers listed below.
6.5.1.1
Port A Data Register (PTAD)

7 6 5 4 3 2 1 0
R PTAD7 W Reset: 0 0 0 0 0 0 0 0 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0
Figure 6-3. Port A Data Register (PTAD) Table 6-1. PTAD Register Field Descriptions
Field 7:0 PTAD[7:0] Description Port A Data Register Bits For port A pins that are inputs, reads return the logic level on the pin. For port A pins that are congured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port A pins that are congured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also congures all port pins as high-impedance inputs with pull-ups/pull-downs disabled.
6.5.1.2
Port A Data Direction Register (PTADD)

7 6 5 4 3 2 1 0
R PTADD7 W Reset: 0 0 0 0 0 0 0 0 PTADD6 PTADD5 PTADD4 PTADD3 PTADD2 PTADD1 PTADD0
Figure 6-4. Port A Data Direction Register (PTADD) Table 6-2. PTADD Register Field Descriptions
Field Description
7:0 Data Direction for Port A Bits These read/write bits control the direction of port A pins and what is read for PTADD[7:0] PTAD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.
6.5.1.3
Port A Pull Enable Register (PTAPE)

7 6 5 4 3 2 1 0
R PTAPE7 W Reset: 0 0 0 0 0 0 0 0 PTAPE6 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0
Figure 6-5. Internal Pull Enable for Port A Register (PTAPE) Table 6-3. PTAPE Register Field Descriptions
Field Description
7:0 Internal Pull Enable for Port A Bits Each of these control bits determines if the internal pull-up or pull-down PTAPE[7:0] device is enabled for the associated PTA pin. For port A pins that are congured as outputs, these bits have no effect and the internal pull devices are disabled. 0 Internal pull-up/pull-down device disabled for port A bit n. 1 Internal pull-up/pull-down device enabled for port A bit n.
NOTE Pull-down devices only apply when using pin interrupt functions, when corresponding edge select and pin select functions are congured.
6.5.1.4
Port A Slew Rate Enable Register (PTASE)

7 6 5 4 3 2 1 0
R PTASE7 W Reset: 0 0 0 0 0 0 0 0 PTASE6 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0
Figure 6-6. Slew Rate Enable for Port A Register (PTASE) Table 6-4. PTASE Register Field Descriptions
Field Description
7:0 Output Slew Rate Enable for Port A Bits Each of these control bits determines if the output slew rate control PTASE[7:0] is enabled for the associated PTA pin. For port A pins that are congured as inputs, these bits have no effect. 0 Output slew rate control disabled for port A bit n. 1 Output slew rate control enabled for port A bit n. Note: Slew rate reset default values may differ between engineering samples and nal production parts. Always initialize slew rate control to the desired value to ensure correct operation.
6.5.1.5
Port A Drive Strength Selection Register (PTADS)

7 6 5 4 3 2 1 0
R PTADS7 W Reset: 0 0 0 0 0 0 0 0 PTADS6 PTADS5 PTADS4 PTADS3 PTADS2 PTADS1 PTADS0
Figure 6-7. Drive Strength Selection for Port A Register (PTADS) Table 6-5. PTADS Register Field Descriptions
Field Description
7:0 Output Drive Strength Selection for Port A Bits Each of these control bits selects between low and high PTADS[7:0] output drive for the associated PTA pin. For port A pins that are congured as inputs, these bits have no effect. 0 Low output drive strength selected for port A bit n. 1 High output drive strength selected for port A bit n.
6.5.1.6
Port A Interrupt Status and Control Register (PTASC)

7 6 5 4 3 2 1 0
R W Reset:
PTAIF
0 PTAIE PTAACK PTAMOD 0
Figure 6-8. Port A Interrupt Status and Control Register (PTASC) Table 6-6. PTASC Register Field Descriptions
Field 3 PTAIF 2 PTAACK 1 PTAIE 0 PTAMOD Description Port A Interrupt Flag PTAIF indicates when a port A interrupt is detected. Writes have no effect on PTAIF. 0 No port A interrupt detected. 1 Port A interrupt detected. Port A Interrupt Acknowledge Writing a 1 to PTAACK is part of the ag clearing mechanism. PTAACK always reads as 0. Port A Interrupt Enable PTAIE determines whether a port A interrupt is requested. 0 Port A interrupt request not enabled. 1 Port A interrupt request enabled. Port A Detection Mode PTAMOD (along with the PTAES bits) controls the detection mode of the port A interrupt pins. 0 Port A pins detect edges only. 1 Port A pins detect both edges and levels.
6.5.1.7
Port A Interrupt Pin Select Register (PTAPS)

7 6 5 4 3 2 1 0
R PTAPS7 W Reset: 0 0 0 0 0 0 0 0 PTAPS6 PTAPS5 PTAPS4 PTAPS3 PTAPS2 PTAPS1 PTAPS0
Figure 6-9. Port A Interrupt Pin Select Register (PTAPS) Table 6-7. PTAPS Register Field Descriptions
Field Description
7:0 Port A Interrupt Pin Selects Each of the PTAPSn bits enable the corresponding port A interrupt pin. PTAPS[7:0] 0 Pin not enabled as interrupt. 1 Pin enabled as interrupt.
6.5.1.8
Port A Interrupt Edge Select Register (PTAES)

7 6 5 4 3 2 1 0
R PTAES7 W Reset: 0 0 0 0 0 0 0 0 PTAES6 PTAES5 PTAES4 PTAES3 PTAES2 PTAES1 PTAES0
Figure 6-10. Port A Edge Select Register (PTAES) Table 6-8. PTAES Register Field Descriptions
Field Description
7:0 Port A Edge Selects Each of the PTAESn bits serves a dual purpose by selecting the polarity of the active PTAES[7:0] interrupt edge as well as selecting a pull-up or pull-down device if enabled. 0 A pull-up device is connected to the associated pin and detects falling edge/low level for interrupt generation. 1 A pull-down device is connected to the associated pin and detects rising edge/high level for interrupt generation.
6.5.2
Port B Registers
Port B is controlled by the registers listed below.
6.5.2.1
Port B Data Register (PTBD)

7 6 5 4 3 2 1 0
R PTBD7 W Reset: 0 0 0 0 0 0 0 0 PTBD6 PTBD5 PTBD4 PTBD3 PTBD2 PTBD1 PTBD0
Figure 6-11. Port B Data Register (PTBD) Table 6-9. PTBD Register Field Descriptions
Field 7:0 PTBD[7:0] Description Port B Data Register Bits For port B pins that are inputs, reads return the logic level on the pin. For port B pins that are congured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port B pins that are congured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTBD to all 0s, but these 0s are not driven out the corresponding pins because reset also congures all port pins as high-impedance inputs with pull-ups/pull-downs disabled.
6.5.2.2
Port B Data Direction Register (PTBDD)

7 6 5 4 3 2 1 0
R PTBDD7 W Reset: 0 0 0 0 0 0 0 0 PTBDD6 PTBDD5 PTBDD4 PTBDD3 PTBDD2 PTBDD1 PTBDD0
Figure 6-12. Port B Data Direction Register (PTBDD) Table 6-10. PTBDD Register Field Descriptions
Field Description
7:0 Data Direction for Port B Bits These read/write bits control the direction of port B pins and what is read for PTBDD[7:0] PTBD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn.
6.5.2.3
Port B Pull Enable Register (PTBPE)

7 6 5 4 3 2 1 0
R PTBPE7 W Reset: 0 0 0 0 0 0 0 0 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0
Figure 6-13. Internal Pull Enable for Port B Register (PTBPE) Table 6-11. PTBPE Register Field Descriptions
Field Description
7:0 Internal Pull Enable for Port B Bits Each of these control bits determines if the internal pull-up or pull-down PTBPE[7:0] device is enabled for the associated PTB pin. For port B pins that are congured as outputs, these bits have no effect and the internal pull devices are disabled. 0 Internal pull-up/pull-down device disabled for port B bit n. 1 Internal pull-up/pull-down device enabled for port B bit n.
6.5.2.4
Port B Slew Rate Enable Register (PTBSE)

7 6 5 4 3 2 1 0
R PTBSE7 W Reset: 0 0 0 0 0 0 0 0 PTBSE6 PTBSE5 PTBSE4 PTBSE3 PTBSE2 PTBSE1 PTBSE0
Figure 6-14. Slew Rate Enable for Port B Register (PTBSE) Table 6-12. PTBSE Register Field Descriptions
Field Description
7:0 Output Slew Rate Enable for Port B Bits Each of these control bits determines if the output slew rate control PTBSE[7:0] is enabled for the associated PTB pin. For port B pins that are congured as inputs, these bits have no effect. 0 Output slew rate control disabled for port B bit n. 1 Output slew rate control enabled for port B bit n. Note: Slew rate reset default values may differ between engineering samples and nal production parts. Always initialize slew rate control to the desired value to ensure correct operation.
6.5.2.5
Port B Drive Strength Selection Register (PTBDS)

7 6 5 4 3 2 1 0
R PTBDS7 W Reset: 0 0 0 0 0 0 0 0 PTBDS6 PTBDS5 PTBDS4 PTBDS3 PTBDS2 PTBDS1 PTBDS0
Figure 6-15. Drive Strength Selection for Port B Register (PTBDS) Table 6-13. PTBDS Register Field Descriptions
Field Description
7:0 Output Drive Strength Selection for Port B Bits Each of these control bits selects between low and high PTBDS[7:0] output drive for the associated PTB pin. For port B pins that are congured as inputs, these bits have no effect. 0 Low output drive strength selected for port B bit n. 1 High output drive strength selected for port B bit n.
6.5.2.6
Port B Interrupt Status and Control Register (PTBSC)

7 6 5 4 3 2 1 0
R W Reset:
PTBIF
0 PTBIE PTBACK PTBMOD 0
Figure 6-16. Port B Interrupt Status and Control Register (PTBSC) Table 6-14. PTBSC Register Field Descriptions
Field 3 PTBIF 2 PTBACK 1 PTBIE 0 PTBMOD Description Port B Interrupt Flag PTBIF indicates when a Port B interrupt is detected. Writes have no effect on PTBIF. 0 No Port B interrupt detected. 1 Port B interrupt detected. Port B Interrupt Acknowledge Writing a 1 to PTBACK is part of the ag clearing mechanism. PTBACK always reads as 0. Port B Interrupt Enable PTBIE determines whether a port B interrupt is requested. 0 Port B interrupt request not enabled. 1 Port B interrupt request enabled. Port B Detection Mode PTBMOD (along with the PTBES bits) controls the detection mode of the port B interrupt pins. 0 Port B pins detect edges only. 1 Port B pins detect both edges and levels.
6.5.2.7
Port B Interrupt Pin Select Register (PTBPS)

7 6 5 4 3 2 1 0
R PTBPS7 W Reset: 0 0 0 0 0 0 0 0 PTBPS6 PTBPS5 PTBPS4 PTBPS3 PTBPS2 PTBPS1 PTBPS0
Figure 6-17. Port B Interrupt Pin Select Register (PTBPS) Table 6-15. PTBPS Register Field Descriptions
Field Description
7:0 Port B Interrupt Pin Selects Each of the PTBPSn bits enable the corresponding port B interrupt pin. PTBPS[7:0] 0 Pin not enabled as interrupt. 1 Pin enabled as interrupt.
6.5.2.8
Port B Interrupt Edge Select Register (PTBES)

7 6 5 4 3 2 1 0
R PTBES7 W Reset: 0 0 0 0 0 0 0 0 PTBES6 PTBES5 PTBES4 PTBES3 PTBES2 PTBES1 PTBES0
Figure 6-18. Port B Edge Select Register (PTBES) Table 6-16. PTBES Register Field Descriptions
Field Description
7:0 Port B Edge Selects Each of the PTBESn bits serves a dual purpose by selecting the polarity of the active PTBES[7:0] interrupt edge as well as selecting a pull-up or pull-down device if enabled. 0 A pull-up device is connected to the associated pin and detects falling edge/low level for interrupt generation. 1 A pull-down device is connected to the associated pin and detects rising edge/high level for interrupt generation.
6.5.3
Port C Registers
Port C is controlled by the registers listed below.
6.5.3.1
Port C Data Register (PTCD)

7 6 5 4 3 2 1 0
R PTCD7 W Reset: 0 0 0 0 0 0 0 0 PTCD6 PTCD5 PTCD4 PTCD3 PTCD2 PTCD1 PTCD0
Figure 6-19. Port C Data Register (PTCD) Table 6-17. PTCD Register Field Descriptions
Field 7:0 PTCD[7:0] Description Port C Data Register Bits For port C pins that are inputs, reads return the logic level on the pin. For port C pins that are congured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port C pins that are congured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTCD to all 0s, but these 0s are not driven out the corresponding pins because reset also congures all port pins as high-impedance inputs with pull-ups disabled.
6.5.3.2
Port C Data Direction Register (PTCDD)

7 6 5 4 3 2 1 0
R PTCDD7 W Reset: 0 0 0 0 0 0 0 0 PTCDD6 PTCDD5 PTCDD4 PTCDD3 PTCDD2 PTCDD1 PTCDD0
Figure 6-20. Port C Data Direction Register (PTCDD) Table 6-18. PTCDD Register Field Descriptions
Field Description
7:0 Data Direction for Port C Bits These read/write bits control the direction of port C pins and what is read for PTCDD[7:0] PTCD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port C bit n and PTCD reads return the contents of PTCDn.
6.5.3.3
Port C Pull Enable Register (PTCPE)

7 6 5 4 3 2 1 0
R PTCPE7 W Reset: 0 0 0 0 0 0 0 0 PTCPE6 PTCPE5 PTCPE4 PTCPE3 PTCPE2 PTCPE1 PTCPE0
Figure 6-21. Internal Pull Enable for Port C Register (PTCPE) Table 6-19. PTCPE Register Field Descriptions
Field Description
7:0 Internal Pull Enable for Port C Bits Each of these control bits determines if the internal pull-up device is PTCPE[7:0] enabled for the associated PTC pin. For port C pins that are congured as outputs, these bits have no effect and the internal pull devices are disabled. 0 Internal pull-up device disabled for port C bit n. 1 Internal pull-up device enabled for port C bit n.
6.5.3.4
Port C Slew Rate Enable Register (PTCSE)

7 6 5 4 3 2 1 0
R PTCSE7 W Reset: 0 0 0 0 0 0 0 0 PTCSE6 PTCSE5 PTCSE4 PTCSE3 PTCSE2 PTCSE1 PTCSE0
Figure 6-22. Slew Rate Enable for Port C Register (PTCSE) Table 6-20. PTCSE Register Field Descriptions
Field Description
7:0 Output Slew Rate Enable for Port C Bits Each of these control bits determines if the output slew rate control PTCSE[7:0] is enabled for the associated PTC pin. For port C pins that are congured as inputs, these bits have no effect. 0 Output slew rate control disabled for port C bit n. 1 Output slew rate control enabled for port C bit n. Note: Slew rate reset default values may differ between engineering samples and nal production parts. Always initialize slew rate control to the desired value to ensure correct operation.
6.5.3.5
Port C Drive Strength Selection Register (PTCDS)

7 6 5 4 3 2 1 0
R PTCDS7 W Reset: 0 0 0 0 0 0 0 0 PTCDS6 PTCDS5 PTCDS4 PTCDS3 PTCDS2 PTCDS1 PTCDS0
Figure 6-23. Drive Strength Selection for Port C Register (PTCDS) Table 6-21. PTCDS Register Field Descriptions
Field Description
7:0 Output Drive Strength Selection for Port C Bits Each of these control bits selects between low and high PTCDS[7:0] output drive for the associated PTC pin. For port C pins that are congured as inputs, these bits have no effect. 0 Low output drive strength selected for port C bit n. 1 High output drive strength selected for port C bit n.
6.5.4
Port D Registers
Port D is controlled by the registers listed below.
6.5.4.1
Port D Data Register (PTDD)

7 6 5 4 3 2 1 0
R PTDD7 W Reset: 0 0 0 0 0 0 0 0 PTDD6 PTDD5 PTDD4 PTDD3 PTDD2 PTDD1 PTDD0
Figure 6-24. Port D Data Register (PTDD) Table 6-22. PTDD Register Field Descriptions
Field 7:0 PTDD[7:0] Description Port D Data Register Bits For port D pins that are inputs, reads return the logic level on the pin. For port D pins that are congured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port D pins that are congured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTDD to all 0s, but these 0s are not driven out the corresponding pins because reset also congures all port pins as high-impedance inputs with pull-ups/pull-downs disabled.
6.5.4.2
Port D Data Direction Register (PTDDD)

7 6 5 4 3 2 1 0
R PTDDD7 W Reset: 0 0 0 0 0 0 0 0 PTDDD6 PTDDD5 PTDDD4 PTDDD3 PTDDD2 PTDDD1 PTDDD0
Figure 6-25. Port D Data Direction Register (PTDDD) Table 6-23. PTDDD Register Field Descriptions
Field Description
7:0 Data Direction for Port D Bits These read/write bits control the direction of port D pins and what is read for PTDDD[7:0] PTDD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn.
6.5.4.3
Port D Pull Enable Register (PTDPE)

7 6 5 4 3 2 1 0
R PTDPE7 W Reset: 0 0 0 0 0 0 0 0 PTDPE6 PTDPE5 PTDPE4 PTDPE3 PTDPE2 PTDPE1 PTDPE0
Figure 6-26. Internal Pull Enable for Port D Register (PTDPE) Table 6-24. PTDPE Register Field Descriptions
Field Description
7:0 Internal Pull Enable for Port D Bits Each of these control bits determines if the internal pull-up or pull-down PTDPE[7:0] device is enabled for the associated PTD pin. For port D pins that are congured as outputs, these bits have no effect and the internal pull devices are disabled. 0 Internal pull-up/pull-down device disabled for port D bit n. 1 Internal pull-up/pull-down device enabled for port D bit n.
6.5.4.4
Port D Slew Rate Enable Register (PTDSE)

7 6 5 4 3 2 1 0
R PTDSE7 W Reset: 0 0 0 0 0 0 0 0 PTDSE6 PTDSE5 PTDSE4 PTDSE3 PTDSE2 PTDSE1 PTDSE0
Figure 6-27. Slew Rate Enable for Port D Register (PTDSE) Table 6-25. PTDSE Register Field Descriptions
Field Description
7:0 Output Slew Rate Enable for Port D Bits Each of these control bits determines if the output slew rate control PTDSE[7:0] is enabled for the associated PTD pin. For port D pins that are congured as inputs, these bits have no effect. 0 Output slew rate control disabled for port D bit n. 1 Output slew rate control enabled for port D bit n. Note: Slew rate reset default values may differ between engineering samples and nal production parts. Always initialize slew rate control to the desired value to ensure correct operation.
6.5.4.5
Port D Drive Strength Selection Register (PTDDS)

7 6 5 4 3 2 1 0
R PTDDS7 W Reset: 0 0 0 0 0 0 0 0 PTDDS6 PTDDS5 PTDDS4 PTDDS3 PTDDS2 PTDDS1 PTDDS0
Figure 6-28. Drive Strength Selection for Port D Register (PTDDS) Table 6-26. PTDDS Register Field Descriptions
Field Description
7:0 Output Drive Strength Selection for Port D Bits Each of these control bits selects between low and high PTDDS[7:0] output drive for the associated PTD pin. For port D pins that are congured as inputs, these bits have no effect. 0 Low output drive strength selected for port D bit n. 1 High output drive strength selected for port D bit n.
6.5.4.6
Port D Interrupt Status and Control Register (PTDSC)

7 6 5 4 3 2 1 0
R W Reset:
PTDIF
0 PTDIE PTDACK PTDMOD 0
Figure 6-29. Port D Interrupt Status and Control Register (PTDSC) Table 6-27. PTDSC Register Field Descriptions
Field 3 PTDIF 2 PTDACK 1 PTDIE 0 PTDMOD Description Port D Interrupt Flag PTDIF indicates when a port D interrupt is detected. Writes have no effect on PTDIF. 0 No port D interrupt detected. 1 Port D interrupt detected. Port D Interrupt Acknowledge Writing a 1 to PTDACK is part of the ag clearing mechanism. PTDACK always reads as 0. Port D Interrupt Enable PTDIE determines whether a port D interrupt is requested. 0 Port D interrupt request not enabled. 1 Port D interrupt request enabled. Port A Detection Mode PTDMOD (along with the PTDES bits) controls the detection mode of the port D interrupt pins. 0 Port D pins detect edges only. 1 Port D pins detect both edges and levels.
6.5.4.7
Port D Interrupt Pin Select Register (PTDPS)

7 6 5 4 3 2 1 0
R PTDPS7 W Reset: 0 0 0 0 0 0 0 0 PTDPS6 PTDPS5 PTDPS4 PTDPS3 PTDPS2 PTDPS1 PTDPS0
Figure 6-30. Port D Interrupt Pin Select Register (PTDPS) Table 6-28. PTDPS Register Field Descriptions
Field Description
7:0 Port D Interrupt Pin Selects Each of the PTDPSn bits enable the corresponding port D interrupt pin. PTDPS[7:0] 0 Pin not enabled as interrupt. 1 Pin enabled as interrupt.
6.5.4.8
Port D Interrupt Edge Select Register (PTDES)

7 6 5 4 3 2 1 0
R PTDES7 W Reset: 0 0 0 0 0 0 0 0 PTDES6 PTDES5 PTDES4 PTDES3 PTDES2 PTDES1 PTDES0
Figure 6-31. Port D Edge Select Register (PTDES) Table 6-29. PTDES Register Field Descriptions
Field Description
7:0 Port D Edge Selects Each of the PTDESn bits serves a dual purpose by selecting the polarity of the active PTDES[7:0] interrupt edge as well as selecting a pull-up or pull-down device if enabled. 0 A pull-up device is connected to the associated pin and detects falling edge/low level for interrupt generation. 1 A pull-down device is connected to the associated pin and detects rising edge/high level for interrupt generation.
6.5.5
Port E Registers
Port E is controlled by the registers listed below.
6.5.5.1
Port E Data Register (PTED)

7 6 5 4 3 2 1 0
R PTED7 W Reset: 0 0 0 0 0 0 PTED6 PTED5 PTED4 PTED3 PTED2
PTED11 0
PTED0 0
Figure 6-32. Port E Data Register (PTED)

1
Reads of this bit always return the pin value of the associated pin, regardless of the value stored in the port data direction bit.
Table 6-30. PTED Register Field Descriptions

Field 7:0 PTED[7:0] Description Port E Data Register Bits For port E pins that are inputs, reads return the logic level on the pin. For port E pins that are congured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port E pins that are congured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTED to all 0s, but these 0s are not driven out the corresponding pins because reset also congures all port pins as high-impedance inputs with pull-ups disabled.
6.5.5.2
Port E Data Direction Register (PTEDD)

7 6 5 4 3 2 1 0
R PTEDD7 W Reset: 0 0 0 0 0 0 PTEDD6 PTEDD5 PTEDD4 PTEDD3 PTEDD2
PTEDD11 0
PTEDD0 0
Figure 6-33. Port E Data Direction Register (PTEDD)

1
PTEDD1 has no effect on the input-only PTE1 pin.
Table 6-31. PTEDD Register Field Descriptions

Field Description
7:0 Data Direction for Port E Bits These read/write bits control the direction of port E pins and what is read for PTEDD[7:0] PTED reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port E bit n and PTED reads return the contents of PTEDn.
6.5.5.3
Port E Pull Enable Register (PTEPE)

7 6 5 4 3 2 1 0
R PTEPE7 W Reset: 0 0 0 0 0 0 0 0 PTEPE6 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0
Figure 6-34. Internal Pull Enable for Port E Register (PTEPE) Table 6-32. PTEPE Register Field Descriptions
Field Description
7:0 Internal Pull Enable for Port E Bits Each of these control bits determines if the internal pull-up device is PTEPE[7:0] enabled for the associated PTE pin. For port E pins that are congured as outputs, these bits have no effect and the internal pull devices are disabled. 0 Internal pull-up device disabled for port E bit n. 1 Internal pull-up device enabled for port E bit n.
6.5.5.4
Port E Slew Rate Enable Register (PTESE)

7 6 5 4 3 2 1 0
R PTESE7 W Reset: 0 0 0 0 0 0 PTESE6 PTESE5 PTESE4 PTESE3 PTESE2
PTESE11 0
PTESE0 0
Figure 6-35. Slew Rate Enable for Port E Register (PTESE)

1
PTESE1 has no effect on the input-only PTE1 pin.
Table 6-33. PTESE Register Field Descriptions

Field Description
7:0 Output Slew Rate Enable for Port E Bits Each of these control bits determines if the output slew rate control PTESE[7:0] is enabled for the associated PTE pin. For port E pins that are congured as inputs, these bits have no effect. 0 Output slew rate control disabled for port E bit n. 1 Output slew rate control enabled for port E bit n. Note: Slew rate reset default values may differ between engineering samples and nal production parts. Always initialize slew rate control to the desired value to ensure correct operation.
6.5.5.5
Port E Drive Strength Selection Register (PTEDS)

7 6 5 4 3 2 1 0
R PTEDS7 W Reset: 0 0 0 0 0 0 PTEDS6 PTEDS5 PTEDS4 PTEDS3 PTEDS2
PTEDS11 0
PTEDS0 0
Figure 6-36. Drive Strength Selection for Port E Register (PTEDS)

1
PTEDS1 has no effect on the input-only PTE1 pin.
Table 6-34. PTEDS Register Field Descriptions

Field Description
7:0 Output Drive Strength Selection for Port E Bits Each of these control bits selects between low and high PTEDS[7:0] output drive for the associated PTE pin. For port E pins that are congured as inputs, these bits have no effect. 0 Low output drive strength selected for port E bit n. 1 High output drive strength selected for port E bit n.
6.5.6
Port F Registers
Port F is controlled by the registers listed below.
6.5.6.1
Port F Data Register (PTFD)

7 6 5 4 3 2 1 0
R PTFD7 W Reset: 0 0 0 0 0 0 0 0 PTFD6 PTFD5 PTFD4 PTFD3 PTFD2 PTFD1 PTFD0
Figure 6-37. Port F Data Register (PTFD) Table 6-35. PTFD Register Field Descriptions
Field 7:0 PTFD[7:0] Description Port F Data Register Bits For port F pins that are inputs, reads return the logic level on the pin. For port F pins that are congured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port F pins that are congured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTFD to all 0s, but these 0s are not driven out the corresponding pins because reset also congures all port pins as high-impedance inputs with pull-ups disabled.
6.5.6.2
Port F Data Direction Register (PTFDD)

7 6 5 4 3 2 1 0
R PTFDD7 W Reset: 0 0 0 0 0 0 0 0 PTFDD6 PTFDD5 PTFDD4 PTFDD3 PTFDD2 PTFDD1 PTFDD0
Figure 6-38. Port F Data Direction Register (PTFDD) Table 6-36. PTFDD Register Field Descriptions
Field Description
7:0 Data Direction for Port F Bits These read/write bits control the direction of port F pins and what is read for PTFDD[7:0] PTFD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port F bit n and PTFD reads return the contents of PTFDn.
6.5.6.3
Port F Pull Enable Register (PTFPE)

7 6 5 4 3 2 1 0
R PTFPE7 W Reset: 0 0 0 0 0 0 0 0 PTFPE6 PTFPE5 PTFPE4 PTFPE3 PTFPE2 PTFPE1 PTFPE0
Figure 6-39. Internal Pull Enable for Port F Register (PTFPE) Table 6-37. PTFPE Register Field Descriptions
Field Description
7:0 Internal Pull Enable for Port F Bits Each of these control bits determines if the internal pull-up device is PTFPE[7:0] enabled for the associated PTF pin. For port F pins that are congured as outputs, these bits have no effect and the internal pull devices are disabled. 0 Internal pull-up device disabled for port F bit n. 1 Internal pull-up device enabled for port F bit n.
6.5.6.4
Port F Slew Rate Enable Register (PTFSE)

7 6 5 4 3 2 1 0
R PTFSE7 W Reset: 0 0 0 0 0 0 0 0 PTFSE6 PTFSE5 PTFSE4 PTFSE3 PTFSE2 PTFSE1 PTFSE0
Figure 6-40. Slew Rate Enable for Port F Register (PTFSE) Table 6-38. PTFSE Register Field Descriptions
Field Description
7:0 Output Slew Rate Enable for Port F Bits Each of these control bits determines if the output slew rate control PTFSE[7:0] is enabled for the associated PTF pin. For port F pins that are congured as inputs, these bits have no effect. 0 Output slew rate control disabled for port F bit n. 1 Output slew rate control enabled for port F bit n. Note: Slew rate reset default values may differ between engineering samples and nal production parts. Always initialize slew rate control to the desired value to ensure correct operation.
6.5.6.5
Port F Drive Strength Selection Register (PTFDS)

7 6 5 4 3 2 1 0
R PTFDS7 W Reset: 0 0 0 0 0 0 0 0 PTFDS6 PTFDS5 PTFDS4 PTFDS3 PTFDS2 PTFDS1 PTFDS0
Figure 6-41. Drive Strength Selection for Port F Register (PTFDS) Table 6-39. PTFDS Register Field Descriptions
Field Description
7:0 Output Drive Strength Selection for Port F Bits Each of these control bits selects between low and high PTFDS[7:0] output drive for the associated PTF pin. For port F pins that are congured as inputs, these bits have no effect. 0 Low output drive strength selected for port F bit n. 1 High output drive strength selected for port F bit n.
6.5.7
Port G Registers
Port G is controlled by the registers listed below.
6.5.7.1
Port G Data Register (PTGD)

7 6 5 4 3 2 1 0
R W Reset:
0 PTGD5 PTGD4 0 PTGD3 0 PTGD2 0 PTGD1 0 PTGD0 0
Figure 6-42. Port G Data Register (PTGD) Table 6-40. PTGD Register Field Descriptions
Field 5:0 PTGD[5:0] Description Port G Data Register Bits For port G pins that are inputs, reads return the logic level on the pin. For port G pins that are congured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port G pins that are congured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTGD to all 0s, but these 0s are not driven out the corresponding pins because reset also congures all port pins as high-impedance inputs with pull-ups disabled.
6.5.7.2
Port G Data Direction Register (PTGDD)

7 6 5 4 3 2 1 0
R W Reset:
0 PTGDD5 PTGDD4 0 PTGDD3 0 PTGDD2 0 PTGDD1 0 PTGDD0 0
Figure 6-43. Port G Data Direction Register (PTGDD) Table 6-41. PTGDD Register Field Descriptions
Field Description
5:0 Data Direction for Port G Bits These read/write bits control the direction of port G pins and what is read for PTGDD[5:0] PTGD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port G bit n and PTGD reads return the contents of PTGDn.
6.5.7.3
Port G Pull Enable Register (PTGPE)

7 6 5 4 3 2 1 0
R W Reset:
0 PTGPE5 PTGPE4 0 PTGPE3 0 PTGPE2 0 PTGPE1 0 PTGPE0 0
Figure 6-44. Internal Pull Enable for Port G Register (PTGPE) Table 6-42. PTGPE Register Field Descriptions
Field Description
5:0 Internal Pull Enable for Port G Bits Each of these control bits determines if the internal pull-up device is PTGPE[5:0] enabled for the associated PTG pin. For port G pins that are congured as outputs, these bits have no effect and the internal pull devices are disabled. 0 Internal pull-up device disabled for port G bit n. 1 Internal pull-up device enabled for port G bit n.
6.5.7.4
Port G Slew Rate Enable Register (PTGSE)

7 6 5 4 3 2 1 0
R W Reset:
0 PTGSE5 PTGSE4 0 PTGSE3 0 PTGSE2 0 PTGSE1 0 PTGSE0 0
Figure 6-45. Slew Rate Enable for Port G Register (PTGSE) Table 6-43. PTGSE Register Field Descriptions
Field Description
5:0 Output Slew Rate Enable for Port G Bits Each of these control bits determines if the output slew rate control PTGSE[5:0] is enabled for the associated PTG pin. For port G pins that are congured as inputs, these bits have no effect. 0 Output slew rate control disabled for port G bit n. 1 Output slew rate control enabled for port G bit n. Note: Slew rate reset default values may differ between engineering samples and nal production parts. Always initialize slew rate control to the desired value to ensure correct operation.
6.5.7.5
Port G Drive Strength Selection Register (PTGDS)

7 6 5 4 3 2 1 0
R W Reset:
0 PTGDS5 PTGDS4 0 PTGDS3 0 PTGDS2 0 PTGDS1 0 PTGDS0 0
Figure 6-46. Drive Strength Selection for Port G Register (PTGDS) Table 6-44. PTGDS Register Field Descriptions
Field Description
5:0 Output Drive Strength Selection for Port G Bits Each of these control bits selects between low and high PTGDS[5:0 output drive for the associated PTG pin. For port G pins that are congured as inputs, these bits have no effect. 0 Low output drive strength selected for port G bit n. 1 High output drive strength selected for port G bit n.

7.1 Introduction
This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D. The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU. Several instructions and enhanced addressing modes were added to improve C compiler efciency and to support a new background debug system which replaces the monitor mode of earlier M68HC08 microcontrollers (MCU).
7.1.1
Features
Features of the HCS08 CPU include: Object code fully upward-compatible with M68HC05 and M68HC08 Families All registers and memory are mapped to a single 64-Kbyte address space 16-bit stack pointer (any size stack anywhere in 64-Kbyte address space) 16-bit index register (H:X) with powerful indexed addressing modes 8-bit accumulator (A) Many instructions treat X as a second general-purpose 8-bit register Seven addressing modes: Inherent Operands in internal registers Relative 8-bit signed offset to branch destination Immediate Operand in next object code byte(s) Direct Operand in memory at 0x00000x00FF Extended Operand anywhere in 64-Kbyte address space Indexed relative to H:X Five submodes including auto increment Indexed relative to SP Improves C efciency dramatically Memory-to-memory data move instructions with four address mode combinations Overow, half-carry, negative, zero, and carry condition codes support conditional branching on the results of signed, unsigned, and binary-coded decimal (BCD) operations Efcient bit manipulation instructions Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions STOP and WAIT instructions to invoke low-power operating modes
7.2
Programmers Model and CPU Registers

7 ACCUMULATOR 16-BIT INDEX REGISTER H:X H INDEX REGISTER (HIGH) 15 15 PROGRAM COUNTER 7 0 CONDITION CODE REGISTER V 1 1 H I N Z C 8 INDEX REGISTER (LOW) 7 0 SP 0 PC X 0 A
Figure 7-1 shows the ve CPU registers. CPU registers are not part of the memory map.
STACK POINTER
CCR
CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWOS COMPLEMENT OVERFLOW
Figure 7-1. CPU Registers
7.2.1
Accumulator (A)
The A accumulator is a general-purpose 8-bit register. One operand input to the arithmetic logic unit (ALU) is connected to the accumulator and the ALU results are often stored into the A accumulator after arithmetic and logical operations. The accumulator can be loaded from memory using various addressing modes to specify the address where the loaded data comes from, or the contents of A can be stored to memory using various addressing modes to specify the address where data from A will be stored. Reset has no effect on the contents of the A accumulator.
7.2.2
Index Register (H:X)
This 16-bit register is actually two separate 8-bit registers (H and X), which often work together as a 16-bit address pointer where H holds the upper byte of an address and X holds the lower byte of the address. All indexed addressing mode instructions use the full 16-bit value in H:X as an index reference pointer; however, for compatibility with the earlier M68HC05 Family, some instructions operate only on the low-order 8-bit half (X). Many instructions treat X as a second general-purpose 8-bit register that can be used to hold 8-bit data values. X can be cleared, incremented, decremented, complemented, negated, shifted, or rotated. Transfer instructions allow data to be transferred from A or transferred to A where arithmetic and logical operations can then be performed. For compatibility with the earlier M68HC05 Family, H is forced to 0x00 during reset. Reset has no effect on the contents of X.
7.2.3
Stack Pointer (SP)
This 16-bit address pointer register points at the next available location on the automatic last-in-rst-out (LIFO) stack. The stack may be located anywhere in the 64-Kbyte address space that has RAM and can be any size up to the amount of available RAM. The stack is used to automatically save the return address for subroutine calls, the return address and CPU registers during interrupts, and for local variables. The AIS (add immediate to stack pointer) instruction adds an 8-bit signed immediate value to SP. This is most often used to allocate or deallocate space for local variables on the stack. SP is forced to 0x00FF at reset for compatibility with the earlier M68HC05 Family. HCS08 programs normally change the value in SP to the address of the last location (highest address) in on-chip RAM during reset initialization to free up direct page RAM (from the end of the on-chip registers to 0x00FF). The RSP (reset stack pointer) instruction was included for compatibility with the M68HC05 Family and is seldom used in new HCS08 programs because it only affects the low-order half of the stack pointer.
7.2.4
Program Counter (PC)
The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. During normal program execution, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, interrupt, and return operations load the program counter with an address other than that of the next sequential location. This is called a change-of-ow. During reset, the program counter is loaded with the reset vector that is located at 0xFFFE and 0xFFFF. The vector stored there is the address of the rst instruction that will be executed after exiting the reset state.
7.2.5
Condition Code Register (CCR)
The 8-bit condition code register contains the interrupt mask (I) and ve ags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the functions of the condition code bits in general terms. For a more detailed explanation of how each instruction sets the CCR bits, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMv1.
7 0 CONDITION CODE REGISTER V 1 1 H I N Z C
CCR
CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWOS COMPLEMENT OVERFLOW
Figure 7-2. Condition Code Register Table 7-1. CCR Register Field Descriptions
Field 7 V Description Twos Complement Overow Flag The CPU sets the overow ag when a twos complement overow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overow ag. 0 No overow 1 Overow Half-Carry Flag The CPU sets the half-carry ag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry ag is required for binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C condition code bits to automatically add a correction value to the result from a previous ADD or ADC on BCD operands to correct the result to a valid BCD value. 0 No carry between bits 3 and 4 1 Carry between bits 3 and 4 Interrupt Mask Bit When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the rst instruction of the interrupt service routine is executed. Interrupts are not recognized at the instruction boundary after any instruction that clears I (CLI or TAP). This ensures that the next instruction after a CLI or TAP will always be executed without the possibility of an intervening interrupt, provided I was set. 0 Interrupts enabled 1 Interrupts disabled Negative Flag The CPU sets the negative ag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. Simply loading or storing an 8-bit or 16-bit value causes N to be set if the most signicant bit of the loaded or stored value was 1. 0 Non-negative result 1 Negative result Zero Flag The CPU sets the zero ag when an arithmetic operation, logic operation, or data manipulation produces a result of 0x00 or 0x0000. Simply loading or storing an 8-bit or 16-bit value causes Z to be set if the loaded or stored value was all 0s. 0 Non-zero result 1 Zero result Carry/Borrow Flag The CPU sets the carry/borrow ag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions such as bit test and branch, shift, and rotate also clear or set the carry/borrow ag. 0 No carry out of bit 7 1 Carry out of bit 7
4 H
3 I
2 N
1 Z
0 C
7.3
Addressing Modes
Addressing modes dene the way the CPU accesses operands and data. In the HCS08, all memory, status and control registers, and input/output (I/O) ports share a single 64-Kbyte linear address space so a 16-bit binary address can uniquely identify any memory location. This arrangement means that the same instructions that access variables in RAM can also be used to access I/O and control registers or nonvolatile program space. Some instructions use more than one addressing mode. For instance, move instructions use one addressing mode to specify the source operand and a second addressing mode to specify the destination address. Instructions such as BRCLR, BRSET, CBEQ, and DBNZ use one addressing mode to specify the location of an operand for a test and then use relative addressing mode to specify the branch destination address when the tested condition is true. For BRCLR, BRSET, CBEQ, and DBNZ, the addressing mode listed in the instruction set tables is the addressing mode needed to access the operand to be tested, and relative addressing mode is implied for the branch destination.
7.3.1
Inherent Addressing Mode (INH)
In this addressing mode, operands needed to complete the instruction (if any) are located within CPU registers so the CPU does not need to access memory to get any operands.
7.3.2
Relative Addressing Mode (REL)
Relative addressing mode is used to specify the destination location for branch instructions. A signed 8-bit offset value is located in the memory location immediately following the opcode. During execution, if the branch condition is true, the signed offset is sign-extended to a 16-bit value and is added to the current contents of the program counter, which causes program execution to continue at the branch destination address.
7.3.3
Immediate Addressing Mode (IMM)
In immediate addressing mode, the operand needed to complete the instruction is included in the object code immediately following the instruction opcode in memory. In the case of a 16-bit immediate operand, the high-order byte is located in the next memory location after the opcode, and the low-order byte is located in the next memory location after that.
7.3.4
Direct Addressing Mode (DIR)
In direct addressing mode, the instruction includes the low-order eight bits of an address in the direct page (0x00000x00FF). During execution a 16-bit address is formed by concatenating an implied 0x00 for the high-order half of the address and the direct address from the instruction to get the 16-bit address where the desired operand is located. This is faster and more memory efcient than specifying a complete 16-bit address for the operand.
7.3.5
Extended Addressing Mode (EXT)
In extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of program memory after the opcode (high byte rst).
7.3.6
Indexed Addressing Mode
Indexed addressing mode has seven variations including ve that use the 16-bit H:X index register pair and two that use the stack pointer as the base reference.
7.3.6.1
Indexed, No Offset (IX)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of the operand needed to complete the instruction.
7.3.6.2
Indexed, No Offset with Post Increment (IX+)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of the operand needed to complete the instruction. The index register pair is then incremented (H:X = H:X + 0x0001) after the operand has been fetched. This addressing mode is only used for MOV and CBEQ instructions.
7.3.6.3
Indexed, 8-Bit Offset (IX1)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction.
7.3.6.4
Indexed, 8-Bit Offset with Post Increment (IX1+)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. The index register pair is then incremented (H:X = H:X + 0x0001) after the operand has been fetched. This addressing mode is used only for the CBEQ instruction.
7.3.6.5
Indexed, 16-Bit Offset (IX2)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction.
7.3.6.6
SP-Relative, 8-Bit Offset (SP1)
This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction.
7.3.6.7
SP-Relative, 16-Bit Offset (SP2)
This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction.
7.4
Special Operations
The CPU performs a few special operations that are similar to instructions but do not have opcodes like other CPU instructions. In addition, a few instructions such as STOP and WAIT directly affect other MCU circuitry. This section provides additional information about these operations.
7.4.1
Reset Sequence
Reset can be caused by a power-on-reset (POR) event, internal conditions such as the COP (computer operating properly) watchdog, or by assertion of an external active-low reset pin. When a reset event occurs, the CPU immediately stops whatever it is doing (the MCU does not wait for an instruction boundary before responding to a reset event). For a more detailed discussion about how the MCU recognizes resets and determines the source, refer to the Resets, Interrupts, and System Conguration chapter. The reset event is considered concluded when the sequence to determine whether the reset came from an internal source is done and when the reset pin is no longer asserted. At the conclusion of a reset event, the CPU performs a 6-cycle sequence to fetch the reset vector from 0xFFFE and 0xFFFF and to ll the instruction queue in preparation for execution of the rst program instruction.
7.4.2
Interrupt Sequence
When an interrupt is requested, the CPU completes the current instruction before responding to the interrupt. At this point, the program counter is pointing at the start of the next instruction, which is where the CPU should return after servicing the interrupt. The CPU responds to an interrupt by performing the same sequence of operations as for a software interrupt (SWI) instruction, except the address used for the vector fetch is determined by the highest priority interrupt that is pending when the interrupt sequence started. The CPU sequence for an interrupt is: 1. Store the contents of PCL, PCH, X, A, and CCR on the stack, in that order. 2. Set the I bit in the CCR. 3. Fetch the high-order half of the interrupt vector. 4. Fetch the low-order half of the interrupt vector. 5. Delay for one free bus cycle. 6. Fetch three bytes of program information starting at the address indicated by the interrupt vector to ll the instruction queue in preparation for execution of the rst instruction in the interrupt service routine. After the CCR contents are pushed onto the stack, the I bit in the CCR is set to prevent other interrupts while in the interrupt service routine. Although it is possible to clear the I bit with an instruction in the
interrupt service routine, this would allow nesting of interrupts (which is not recommended because it leads to programs that are difcult to debug and maintain). For compatibility with the earlier M68HC05 MCUs, the high-order half of the H:X index register pair (H) is not saved on the stack as part of the interrupt sequence. The user must use a PSHH instruction at the beginning of the service routine to save H and then use a PULH instruction just before the RTI that ends the interrupt service routine. It is not necessary to save H if you are certain that the interrupt service routine does not use any instructions or auto-increment addressing modes that might change the value of H. The software interrupt (SWI) instruction is like a hardware interrupt except that it is not masked by the global I bit in the CCR and it is associated with an instruction opcode within the program so it is not asynchronous to program execution.
7.4.3
Wait Mode Operation
The WAIT instruction enables interrupts by clearing the I bit in the CCR. It then halts the clocks to the CPU to reduce overall power consumption while the CPU is waiting for the interrupt or reset event that will wake the CPU from wait mode. When an interrupt or reset event occurs, the CPU clocks will resume and the interrupt or reset event will be processed normally. If a serial BACKGROUND command is issued to the MCU through the background debug interface while the CPU is in wait mode, CPU clocks will resume and the CPU will enter active background mode where other serial background commands can be processed. This ensures that a host development system can still gain access to a target MCU even if it is in wait mode.
7.4.4
Stop Mode Operation
Usually, all system clocks, including the crystal oscillator (when used), are halted during stop mode to minimize power consumption. In such systems, external circuitry is needed to control the time spent in stop mode and to issue a signal to wake up the target MCU when it is time to resume processing. Unlike the earlier M68HC05 and M68HC08 MCUs, the HCS08 can be congured to keep a minimum set of clocks running in stop mode. This optionally allows an internal periodic signal to wake the target MCU from stop mode. When a host debug system is connected to the background debug pin (BKGD) and the ENBDM control bit has been set by a serial command through the background interface (or because the MCU was reset into active background mode), the oscillator is forced to remain active when the MCU enters stop mode. In this case, if a serial BACKGROUND command is issued to the MCU through the background debug interface while the CPU is in stop mode, CPU clocks will resume and the CPU will enter active background mode where other serial background commands can be processed. This ensures that a host development system can still gain access to a target MCU even if it is in stop mode. Recovery from stop mode depends on the particular HCS08 and whether the oscillator was stopped in stop mode. Refer to the Modes of Operation chapter for more details.
7.4.5
BGND Instruction
The BGND instruction is new to the HCS08 compared to the M68HC08. BGND would not be used in normal user programs because it forces the CPU to stop processing user instructions and enter the active background mode. The only way to resume execution of the user program is through reset or by a host debug system issuing a GO, TRACE1, or TAGGO serial command through the background debug interface. Software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the BGND opcode. When the program reaches this breakpoint address, the CPU is forced to active background mode rather than continuing the user program.
7.5
HCS08 Instruction Set Summary
Table 7-2 provides a summary of the HCS08 instruction set in all possible addressing modes. The table shows operand construction, execution time in internal bus clock cycles, and cycle-by-cycle details for each addressing mode variation of each instruction.
Table 7-2. Instruction Set Summary (Sheet 1 of 9)
Address Mode Source Form
ADC ADC ADC ADC ADC ADC ADC ADC ADD ADD ADD ADD ADD ADD ADD ADD #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP
Cycles
Operation
Object Code
Cyc-by-Cyc Details
pp rpp prpp prpp rpp rfp pprpp prpp pp rpp prpp prpp rpp rfp pprpp prpp pp
Affect on CCR V11H INZC
Add with Carry A (A) + (M) + (C)
IMM DIR EXT IX2 IX1 IX SP2 SP1 IMM DIR EXT IX2 IX1 IX SP2 SP1 IMM
A9 B9 C9 D9 E9 F9 9E D9 9E E9 AB BB CB DB EB FB 9E DB 9E EB
ii dd hh ll ee ff ff ee ff ff ii dd hh ll ee ff ff ee ff ff
2 3 4 4 3 3 5 4 2 3 4 4 3 3 5 4 2
1 1
Add without Carry A (A) + (M)
1 1
AIS #opr8i
Add Immediate Value (Signed) to Stack Pointer SP (SP) + (M) Add Immediate Value (Signed) to Index Register (H:X) H:X (H:X) + (M)
A7 ii
1 1
AIX #opr8i AND AND AND AND AND AND AND AND #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP
IMM IMM DIR EXT IX2 IX1 IX SP2 SP1 DIR INH INH IX1 IX SP1 DIR INH INH IX1 IX SP1
AF ii A4 B4 C4 D4 E4 F4 9E D4 9E E4 ii dd hh ll ee ff ff ee ff ff
2 2 3 4 4 3 3 5 4 5 1 1 5 4 6 5 1 1 5 4 6
pp pp rpp prpp prpp rpp rfp pprpp prpp rfwpp p p rfwpp rfwp prfwpp rfwpp p p rfwpp rfwp prfwpp
1 1
Logical AND A (A) & (M)
0 1 1
ASL opr8a ASLA ASLX ASL oprx8,X ASL ,X ASL oprx8,SP ASR opr8a ASRA ASRX ASR oprx8,X ASR ,X ASR oprx8,SP
Arithmetic Shift Left

C b7 b0 0
(Same as LSL) Arithmetic Shift Right

C b7 b0
38 dd 48 58 68 ff 78 9E 68 ff 37 dd 47 57 67 ff 77 9E 67 ff
1 1
1 1

Address Mode Source Form Cycles Cyc-by-Cyc Details Affect on CCR V11H INZC
ppp rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp ppp ppp ppp 1 1
Operation
Object Code
BCC rel
Branch if Carry Bit Clear (if C = 0)
REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) REL REL REL
24 rr 11 13 15 17 19 1B 1D 1F dd dd dd dd dd dd dd dd
3 5 5 5 5 5 5 5 5 3 3 3
BCLR n,opr8a
Clear Bit n in Memory (Mn 0)
1 1
BCS rel BEQ rel BGE rel
Branch if Carry Bit Set (if C = 1) (Same as BLO) Branch if Equal (if Z = 1) Branch if Greater Than or Equal To (if N V = 0) (Signed) Enter active background if ENBDM=1 Waits for and processes BDM commands until GO, TRACE1, or TAGGO Branch if Greater Than (if Z | (N V) = 0) (Signed) Branch if Half Carry Bit Clear (if H = 0) Branch if Half Carry Bit Set (if H = 1) Branch if Higher (if C | Z = 0) Branch if Higher or Same (if C = 0) (Same as BCC) Branch if IRQ Pin High (if IRQ pin = 1) Branch if IRQ Pin Low (if IRQ pin = 0)
25 rr 27 rr 90 rr
1 1 1 1 1 1
BGND
INH
82
5+
fp...ppp
1 1
BGT rel BHCC rel BHCS rel BHI rel BHS rel BIH rel BIL rel BIT BIT BIT BIT BIT BIT BIT BIT #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP
REL REL REL REL REL REL REL IMM DIR EXT IX2 IX1 IX SP2 SP1 REL REL REL REL REL REL REL REL
92 rr 28 rr 29 rr 22 rr 24 rr 2F rr 2E rr A5 B5 C5 D5 E5 F5 9E D5 9E E5 ii dd hh ll ee ff ff ee ff ff
3 3 3 3 3 3 3 2 3 4 4 3 3 5 4 3 3 3 3 3 3 3 3
ppp ppp ppp ppp ppp ppp ppp pp rpp prpp prpp rpp rfp pprpp prpp ppp ppp ppp ppp ppp ppp ppp ppp
1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit Test (A) & (M) (CCR Updated but Operands Not Changed)
0 1 1
BLE rel BLO rel BLS rel BLT rel BMC rel BMI rel BMS rel BNE rel
Branch if Less Than or Equal To (if Z | (N V) = 1) (Signed) Branch if Lower (if C = 1) (Same as BCS) Branch if Lower or Same (if C | Z = 1) Branch if Less Than (if N V = 1) (Signed) Branch if Interrupt Mask Clear (if I = 0) Branch if Minus (if N = 1) Branch if Interrupt Mask Set (if I = 1) Branch if Not Equal (if Z = 0)
93 rr 25 rr 23 rr 91 rr 2C rr 2B rr 2D rr 26 rr
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

BPL rel BRA rel
Cycles
Operation
Object Code
Cyc-by-Cyc Details
ppp ppp rpppp rpppp rpppp rpppp rpppp rpppp rpppp rpppp ppp rpppp rpppp rpppp rpppp rpppp rpppp rpppp rpppp rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp

1 1 1 1
Branch if Plus (if N = 0) Branch Always (if I = 1)
REL REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7)
2A rr 20 rr 01 03 05 07 09 0B 0D 0F dd dd dd dd dd dd dd dd rr rr rr rr rr rr rr rr
3 3 5 5 5 5 5 5 5 5 3 rr rr rr rr rr rr rr rr 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5
BRCLR n,opr8a,rel
Branch if Bit n in Memory Clear (if (Mn) = 0)
1 1
BRN rel
Branch Never (if I = 0)
21 rr 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E dd dd dd dd dd dd dd dd dd dd dd dd dd dd dd dd
1 1
BRSET n,opr8a,rel
Branch if Bit n in Memory Set (if (Mn) = 1)
1 1
BSET n,opr8a
Set Bit n in Memory (Mn 1)
1 1
BSR rel
Branch to Subroutine PC (PC) + $0002 push (PCL); SP (SP) $0001 push (PCH); SP (SP) $0001 PC (PC) + rel Compare and... Branch if (A) = (M) Branch if (A) = (M) Branch if (X) = (M) Branch if (A) = (M) Branch if (A) = (M) Branch if (A) = (M)
REL
AD rr
ssppp
1 1
CBEQ opr8a,rel CBEQA #opr8i,rel CBEQX #opr8i,rel CBEQ oprx8,X+,rel CBEQ ,X+,rel CBEQ oprx8,SP,rel CLC CLI CLR opr8a CLRA CLRX CLRH CLR oprx8,X CLR ,X CLR oprx8,SP
DIR IMM IMM IX1+ IX+ SP1 INH INH DIR INH INH INH IX1 IX SP1
31 41 51 61 71 9E 61 98 9A
dd ii ii ff rr ff
rr rr rr rr rr
5 4 4 5 5 6 1 1 5 1 1 1 5 4 6
rpppp pppp pppp rpppp rfppp prpppp p p rfwpp p p p rfwpp rfwp prfwpp
1 1
Clear Carry Bit (C 0) Clear Interrupt Mask Bit (I 0) Clear M $00 A $00 X $00 H $00 M $00 M $00 M $00
1 1 0 1 1 0
3F dd 4F 5F 8C 6F ff 7F 9E 6F ff
0 1 1 0 1

CMP CMP CMP CMP CMP CMP CMP CMP #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP
Cycles
Operation
Object Code
Cyc-by-Cyc Details
pp rpp prpp prpp rpp rfp pprpp prpp rfwpp p p rfwpp rfwp prfwpp prrfpp ppp rrfpp prrfpp pp rpp prpp prpp rpp rfp pprpp prpp p rfwpppp fppp fppp rfwpppp rfwppp prfwpppp rfwpp p p rfwpp rfwp prfwpp fffffp pp rpp prpp prpp rpp rfp pprpp prpp
Compare Accumulator with Memory AM (CCR Updated But Operands Not Changed)
IMM DIR EXT IX2 IX1 IX SP2 SP1 DIR INH INH IX1 IX SP1 EXT IMM DIR SP1 IMM DIR EXT IX2 IX1 IX SP2 SP1 INH
A1 B1 C1 D1 E1 F1 9E D1 9E E1
ii dd hh ll ee ff ff ee ff ff
2 3 4 4 3 3 5 4 5 1 1 5 4 6 6 3 5 6 2 3 4 4 3 3 5 4 1
1 1
COM opr8a COMA COMX COM oprx8,X COM ,X COM oprx8,SP CPHX opr16a CPHX #opr16i CPHX opr8a CPHX oprx8,SP CPX CPX CPX CPX CPX CPX CPX CPX DAA DBNZ opr8a,rel DBNZA rel DBNZX rel DBNZ oprx8,X,rel DBNZ ,X,rel DBNZ oprx8,SP,rel DEC opr8a DECA DECX DEC oprx8,X DEC ,X DEC oprx8,SP DIV EOR EOR EOR EOR EOR EOR EOR EOR #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP
Complement M (M)= $FF (M) (Ones Complement) A (A) = $FF (A) X (X) = $FF (X) M (M) = $FF (M) M (M) = $FF (M) M (M) = $FF (M) Compare Index Register (H:X) with Memory (H:X) (M:M + $0001) (CCR Updated But Operands Not Changed)
33 dd 43 53 63 ff 73 9E 63 ff 3E 65 75 9E F3 A3 B3 C3 D3 E3 F3 9E D3 9E E3 72 3B 4B 5B 6B 7B 9E 6B dd rr rr rr ff rr rr ff rr hh ll jj kk dd ff ii dd hh ll ee ff ff ee ff ff
0 1 1 1
1 1
Compare X (Index Register Low) with Memory XM (CCR Updated But Operands Not Changed)
1 1
Decimal Adjust Accumulator After ADD or ADC of BCD Values
U 1 1
DIR INH Decrement A, X, or M and Branch if Not Zero INH (if (result) 0) IX1 DBNZX Affects X Not H IX SP1 Decrement M (M) $01 A (A) $01 X (X) $01 M (M) $01 M (M) $01 M (M) $01 DIR INH INH IX1 IX SP1 INH IMM DIR EXT IX2 IX1 IX SP2 SP1
7 4 4 7 6 8 5 1 1 5 4 6 6
1 1
3A dd 4A 5A 6A ff 7A 9E 6A ff 52 A8 B8 C8 D8 E8 F8 9E D8 9E E8 ii dd hh ll ee ff ff ee ff ff
1 1
Divide A (H:A)(X); H Remainder Exclusive OR Memory with Accumulator A (A M)
1 1
2 3 4 4 3 3 5 4
0 1 1

INC opr8a INCA INCX INC oprx8,X INC ,X INC oprx8,SP JMP JMP JMP JMP JMP JSR JSR JSR JSR JSR LDA LDA LDA LDA LDA LDA LDA LDA opr8a opr16a oprx16,X oprx8,X ,X opr8a opr16a oprx16,X oprx8,X ,X #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP #opr16i opr8a opr16a ,X oprx16,X oprx8,X oprx8,SP Increment
Cycles
Operation
M (M) + $01 A (A) + $01 X (X) + $01 M (M) + $01 M (M) + $01 M (M) + $01
Object Code
Cyc-by-Cyc Details
rfwpp p p rfwpp rfwp prfwpp ppp pppp pppp ppp ppp ssppp pssppp pssppp ssppp ssppp pp rpp prpp prpp rpp rfp pprpp prpp ppp rrpp prrpp prrfp pprrpp prrpp prrpp pp rpp prpp prpp rpp rfp pprpp prpp rfwpp p p rfwpp rfwp prfwpp rfwpp p p rfwpp rfwp prfwpp
DIR INH INH IX1 IX SP1 DIR EXT IX2 IX1 IX DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX SP2 SP1 IMM DIR EXT IX IX2 IX1 SP1 IMM DIR EXT IX2 IX1 IX SP2 SP1 DIR INH INH IX1 IX SP1 DIR INH INH IX1 IX SP1
3C dd 4C 5C 6C ff 7C 9E 6C ff BC CC DC EC FC BD CD DD ED FD A6 B6 C6 D6 E6 F6 9E D6 9E E6 45 55 32 AE BE CE FE dd hh ll ee ff ff dd hh ll ee ff ff ii dd hh ll ee ff ff ee ff ff jj kk dd hh ll ee ff ff ff ii dd hh ll ee ff ff ee ff ff
5 1 1 5 4 6 3 4 4 3 3 5 6 6 5 5 2 3 4 4 3 3 5 4 3 4 5 5 6 5 5 2 3 4 4 3 3 5 4 5 1 1 5 4 6 5 1 1 5 4 6
1 1
Jump PC Jump Address
1 1
Jump to Subroutine PC (PC) + n (n = 1, 2, or 3) Push (PCL); SP (SP) $0001 Push (PCH); SP (SP) $0001 PC Unconditional Address
1 1
Load Accumulator from Memory A (M)
0 1 1
LDHX LDHX LDHX LDHX LDHX LDHX LDHX LDX LDX LDX LDX LDX LDX LDX LDX
Load Index Register (H:X) H:X (M:M + $0001)
9E 9E 9E 9E
0 1 1
#opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP
Load X (Index Register Low) from Memory X (M)
AE BE CE DE EE FE 9E DE 9E EE
0 1 1
LSL opr8a LSLA LSLX LSL oprx8,X LSL ,X LSL oprx8,SP LSR opr8a LSRA LSRX LSR oprx8,X LSR ,X LSR oprx8,SP
Logical Shift Left

C b7 b0 0
(Same as ASL) Logical Shift Right

0 b7 b0 C
38 dd 48 58 68 ff 78 9E 68 ff 34 dd 44 54 64 ff 74 9E 64 ff
1 1
1 1 0

MOV opr8a,opr8a MOV opr8a,X+ MOV #opr8i,opr8a MOV ,X+,opr8a MUL NEG opr8a NEGA NEGX NEG oprx8,X NEG ,X NEG oprx8,SP NOP NSA ORA ORA ORA ORA ORA ORA ORA ORA #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP
Cycles
Operation
Object Code
Cyc-by-Cyc Details
rpwpp rfwpp pwpp rfwpp ffffp rfwpp p p rfwpp rfwp prfwpp p p pp rpp prpp prpp rpp rfp pprpp prpp sp sp sp ufp ufp ufp rfwpp p p rfwpp rfwp prfwpp rfwpp p p rfwpp rfwp prfwpp

0 1 1
Move (M)destination (M)source In IX+/DIR and DIR/IX+ Modes, H:X (H:X) + $0001 Unsigned multiply X:A (X) (A) Negate M (M) = $00 (M) (Twos Complement) A (A) = $00 (A) X (X) = $00 (X) M (M) = $00 (M) M (M) = $00 (M) M (M) = $00 (M) No Operation Uses 1 Bus Cycle Nibble Swap Accumulator A (A[3:0]:A[7:4])
DIR/DIR DIR/IX+ IMM/DIR IX+/DIR INH DIR INH INH IX1 IX SP1 INH INH IMM DIR EXT IX2 IX1 IX SP2 SP1 INH INH INH INH INH INH DIR INH INH IX1 IX SP1 DIR INH INH IX1 IX SP1
4E 5E 6E 7E 42
dd dd dd ii dd dd
5 5 4 5 5 5 1 1 5 4 6 1 1
1 1 0 0
30 dd 40 50 60 ff 70 9E 60 ff 9D 62 AA BA CA DA EA FA 9E DA 9E EA 87 8B 89 86 8A 88 39 dd 49 59 69 ff 79 9E 69 ff 36 dd 46 56 66 ff 76 9E 66 ff ii dd hh ll ee ff ff ee ff ff
1 1
1 1 1 1
Inclusive OR Accumulator and Memory A (A) | (M)
2 3 4 4 3 3 5 4 2 2 2 3 3 3 5 1 1 5 4 6 5 1 1 5 4 6
0 1 1
PSHA PSHH PSHX PULA PULH PULX ROL opr8a ROLA ROLX ROL oprx8,X ROL ,X ROL oprx8,SP ROR opr8a RORA RORX ROR oprx8,X ROR ,X ROR oprx8,SP
Push Accumulator onto Stack Push (A); SP (SP) $0001 Push H (Index Register High) onto Stack Push (H); SP (SP) $0001 Push X (Index Register Low) onto Stack Push (X); SP (SP) $0001 Pull Accumulator from Stack SP (SP + $0001); Pull (A) Pull H (Index Register High) from Stack SP (SP + $0001); Pull (H) Pull X (Index Register Low) from Stack SP (SP + $0001); Pull (X) Rotate Left through Carry
C b7 b0
1 1 1 1 1 1 1 1 1 1 1 1
1 1
Rotate Right through Carry

C b7 b0
1 1

p 1 1
Operation
Object Code
RSP
Reset Stack Pointer (Low Byte) SPL $FF (High Byte Not Affected) Return from Interrupt SP (SP) + $0001; Pull (CCR) SP (SP) + $0001; Pull (A) SP (SP) + $0001; Pull (X) SP (SP) + $0001; Pull (PCH) SP (SP) + $0001; Pull (PCL) Return from Subroutine SP SP + $0001; Pull (PCH) SP SP + $0001; Pull (PCL) #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP
INH
9C
RTI
INH
80
uuuuufppp
1 1
RTS SBC SBC SBC SBC SBC SBC SBC SBC SEC SEI STA STA STA STA STA STA STA opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP
INH IMM DIR EXT IX2 IX1 IX SP2 SP1 INH INH DIR EXT IX2 IX1 IX SP2 SP1 DIR EXT SP1 INH DIR EXT IX2 IX1 IX SP2 SP1
81 A2 B2 C2 D2 E2 F2 9E D2 9E E2 99 9B B7 C7 D7 E7 F7 9E D7 9E E7 dd hh ll ee ff ff ee ff ff ii dd hh ll ee ff ff ee ff ff
5 2 3 4 4 3 3 5 4 1 1 3 4 4 3 2 5 4 4 5 5 2 dd hh ll ee ff ff ee ff ff 3 4 4 3 2 5 4
ufppp pp rpp prpp prpp rpp rfp pprpp prpp p p wpp pwpp pwpp wpp wp ppwpp pwpp wwpp pwwpp pwwpp fp... wpp pwpp pwpp wpp wp ppwpp pwpp
1 1
Subtract with Carry A (A) (M) (C)
1 1
Set Carry Bit (C 1) Set Interrupt Mask Bit (I 1)
1 1 1 1 1 1
Store Accumulator in Memory M (A)
0 1 1
STHX opr8a STHX opr16a STHX oprx8,SP STOP STX STX STX STX STX STX STX opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP
Store H:X (Index Reg.) (M:M + $0001) (H:X) Enable Interrupts: Stop Processing Refer to MCU Documentation I bit 0; Stop Processing
35 dd 96 hh ll 9E FF ff 8E BF CF DF EF FF 9E DF 9E EF
0 1 1
1 1 0
Store X (Low 8 Bits of Index Register) in Memory M (X)
0 1 1

SUB SUB SUB SUB SUB SUB SUB SUB #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP
Cycles
Operation
Object Code
Cyc-by-Cyc Details
pp rpp prpp prpp rpp rfp pprpp prpp
Subtract A (A) (M)
IMM DIR EXT IX2 IX1 IX SP2 SP1
A0 B0 C0 D0 E0 F0 9E D0 9E E0
ii dd hh ll ee ff ff ee ff ff
2 3 4 4 3 3 5 4
1 1
SWI
Software Interrupt PC (PC) + $0001 Push (PCL); SP (SP) $0001 Push (PCH); SP (SP) $0001 Push (X); SP (SP) $0001 Push (A); SP (SP) $0001 Push (CCR); SP (SP) $0001 I 1; PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte Transfer Accumulator to CCR CCR (A) Transfer Accumulator to X (Index Register Low) X (A) Transfer CCR to Accumulator A (CCR) Test for Negative or Zero (M) $00 (A) $00 (X) $00 (M) $00 (M) $00 (M) $00
INH
83
11
sssssvvfppp
1 1 1
TAP
INH
84
1 1
TAX
INH
97
1 1
TPA TST opr8a TSTA TSTX TST oprx8,X TST ,X TST oprx8,SP TSX TXA
INH DIR INH INH IX1 IX SP1 INH INH
85 3D dd 4D 5D 6D ff 7D 9E 6D ff 95 9F
1 4 1 1 4 3 5 2 1
p rfpp p p rfpp rfp prfpp fp p
1 1
0 1 1
Transfer SP to Index Reg. H:X (SP) + $0001 Transfer X (Index Reg. Low) to Accumulator A (X)
1 1 1 1

fp fp... 1 1 1 1 0
Operation
Object Code
TXS WAIT
Transfer Index Reg. to SP SP (H:X) $0001 Enable Interrupts; Wait for Interrupt I bit 0; Halt CPU
INH INH
94 8F
2 2+
Source Form: Everything in the source forms columns, except expressions in italic characters, is literal information which must appear in the assembly source le exactly as shown. The initial 3- to 5-letter mnemonic and the characters (#, ( ) and +) are always a literal characters. n Any label or expression that evaluates to a single integer in the range 0-7. opr8i Any label or expression that evaluates to an 8-bit immediate value. opr16i Any label or expression that evaluates to a 16-bit immediate value. opr8a Any label or expression that evaluates to an 8-bit direct-page address ($00xx). opr16a Any label or expression that evaluates to a 16-bit address. oprx8 Any label or expression that evaluates to an unsigned 8-bit value, used for indexed addressing. oprx16 Any label or expression that evaluates to a 16-bit value, used for indexed addressing. rel Any label or expression that refers to an address that is within 128 to +127 locations from the start of the next instruction. Operation Symbols: A Accumulator CCR Condition code register H Index register high byte M Memory location n Any bit opr Operand (one or two bytes) PC Program counter PCH Program counter high byte PCL Program counter low byte rel Relative program counter offset byte SP Stack pointer SPL Stack pointer low byte X Index register low byte & Logical AND | Logical OR Logical EXCLUSIVE OR () Contents of + Add Subtract, Negation (twos complement) Multiply Divide # Immediate value Loaded with : Concatenated with CCR Bits: V Overow bit H Half-carry bit I Interrupt mask N Negative bit Z Zero bit C Carry/borrow bit Addressing Modes: DIR Direct addressing mode EXT Extended addressing mode IMM Immediate addressing mode INH Inherent addressing mode IX Indexed, no offset addressing mode IX1 Indexed, 8-bit offset addressing mode IX2 Indexed, 16-bit offset addressing mode IX+ Indexed, no offset, post increment addressing mode IX1+ Indexed, 8-bit offset, post increment addressing mode REL Relative addressing mode SP1 Stack pointer, 8-bit offset addressing mode SP2 Stack pointer 16-bit offset addressing mode Cycle-by-Cycle Codes: f Free cycle. This indicates a cycle where the CPU does not require use of the system buses. An f cycle is always one cycle of the system bus clock and is always a read cycle. p Program fetch; read from next consecutive location in program memory r Read 8-bit operand s Push (write) one byte onto stack u Pop (read) one byte from stack v Read vector from $FFxx (high byte rst) w Write 8-bit operand CCR Effects: Set or cleared Not affected U Undened
Table 7-3. Opcode Map (Sheet 1 of 2)

Bit-Manipulation 00 5 10 5 Branch 20 3 30 5 40 Read-Modify-Write 1 50 1 60 5 70 4 80 Control 9 90 3 A0 2 B0 3 Register/Memory C0 4 D0 4 E0 3 F0 3 IX 3 IX 3 IX 3 IX 3 IX 3
BRSET0
3 01 3 02 3 03 3 04 3 05 3 06 3 07 3 08 3 09 3 0A 3 0B 3 0C 3 0D 3 0E 3 0F 3 INH IMM DIR EXT DD IX+D
BSET0
DIR 2 5 21 DIR 2 5 22 DIR 2 5 23 DIR 2 5 24 DIR 2 5 25 DIR 2 5 26 DIR 2 5 27 DIR 2 5 28 DIR 2 5 29
BRA BRN BHI BLS BCC
NEG CBEQ LDHX
NEGA CBEQA MUL
NEGX CBEQX DIV
NEG CBEQ NSA
NEG
IX 1 5 81 IX+ 1 1 82
RTI
INH 2 6 91
BGE BLT BGT BLE TXS TSX
SUB CMP SBC CPX AND BIT

IX 3
DIR 2 5 11 DIR 2 5 12 DIR 2 5 13 DIR 2 5 14 DIR 2 5 15 DIR 2 5 16 DIR 2 5 17 DIR 2 5 18 DIR 2 5 19 DIR 2 5 1A DIR 2 5 1B DIR 2 5 1C DIR 2 5 1D DIR 2 5 1E DIR 2 5 1F DIR 2
REL 2 3 31 REL 3 3 32 REL 3 3 33 REL 2 3 34 REL 2 3 35
DIR 1 5 41 DIR 3 5 42 EXT 1 5 43 DIR 1 5 44
INH 1 4 51 IMM 3 5 52 INH 1 1 53 INH 1 1 54 INH 1 3 55 IMM 2 1 56 INH 1 1 57 INH 1 1 58 INH 1 1 59 INH 1 1 5A INH 1 4 5B INH 2 1 5C INH 1 1 5D INH 1 5 5E
INH 2 4 61 IMM 3 6 62 INH 1 1 63 INH 2 1 64 INH 2 4 65 DIR 3 1 66 INH 2 1 67 INH 2 1 68 INH 2 1 69 INH 2 1 6A INH 2 4 6B INH 3 1 6C INH 2 1 6D INH 2 5 6E
IX1 1 5 71 IX1+ 2 1 72 INH 1 5 73 IX1 1 5 74
REL 2 3 A1 REL 2 3 A2 REL 2 3 A3 REL 2 2 A4 INH 2 2 A5 INH 2 5 A6 EXT 2 1 A7
IMM 2 2 B1 IMM 2 2 B2 IMM 2 2 B3 IMM 2 2 B4 IMM 2 2 B5 IMM 2 2 B6
DIR 3 3 C1 DIR 3 3 C2 DIR 3 3 C3 DIR 3 3 C4 DIR 3 3 C5 DIR 3 3 C6
EXT 3 4 D1 EXT 3 4 D2 EXT 3 4 D3 EXT 3 4 D4 EXT 3 4 D5 EXT 3 4 D6 EXT 3 4 D7
IX2 2 4 E1 IX2 2 4 E2 IX2 2 4 E3 IX2 2 4 E4 IX2 2 4 E5 IX2 2 4 E6 IX2 2 4 E7
IX1 1 3 F1 IX1 1 3 F2 IX1 1 3 F3 IX1 1 3 F4 IX1 1 3 F5 IX1 1 3 F6
BRCLR0 BRSET1 BRCLR1 BRSET2 BRCLR2 BRSET3 BRCLR3 BRSET4 BRCLR4 BRSET5 BRCLR5 BRSET6 BRCLR6 BRSET7 BRCLR7
BCLR0 BSET1 BCLR1 BSET2 BCLR2 BSET3 BCLR3 BSET4 BCLR4 BSET5
CBEQ DAA COM

IX 1 4 84
RTS
INH 2 5+ 92 INH 2 11 93
BGND SWI
INH 2 1 94
INH 1 4 83
COM LSR STHX ROR ASR LSL ROL DEC DBNZ INC TST CPHX CLR
DIR 1
COMA LSRA LDHX RORA ASRA LSLA ROLA DECA DBNZA INCA TSTA MOV CLRA
INH 1
COMX LSRX LDHX RORX ASRX LSLX ROLX DECX DBNZX INCX TSTX MOV CLRX
INH 2 SP1 SP2 IX+ IX1+
COM LSR
LSR
IX 1 5 85 DIR 1 4 86 IX 1 4 87
TAP
INH 1 1 95
DIR 1 4 45 DIR 3 5 46 DIR 1 5 47 DIR 1 5 48 DIR 1 5 49 DIR 1 5 4A DIR 1 7 4B DIR 2 5 4C DIR 1 4 4D DIR 1 6 4E EXT 3 5 4F
IX1 1 3 75 IMM 2 5 76 IX1 1 5 77
BCS BNE BEQ
CPHX ROR ASR
CPHX ROR ASR LSL ROL DEC DBNZ INC

IX 1 3 IX 5 8E
TPA
INH 1 3 96 INH 3 2 97 INH 1 3 98 INH 1 2 99 INH 1 3 9A INH 1 2 9B
REL 2 3 36 REL 2 3 37 REL 2 3 38 REL 2 3 39 REL 2 3 3A
PULA PSHA PULX
STHX TAX
INH 2 1 A8
LDA
IMM 2 2 B7
LDA STA
LDA STA
LDA STA
IX2 2 4 E8 IX2 2 4 E9
LDA
IX1 1 3 F7
LDA
IX 2
DIR 3 3 C7 DIR 3 3 C8 DIR 3 3 C9 DIR 3 3 CA DIR 3 3 CB DIR 3 3 CC DIR 3 5 CD DIR 3 3 CE DIR 3 3 CF DIR 3
AIS
IMM 2 2 B8 IMM 2 2 B9
STA
IX1 1 3 F8 IX1 1 3 F9 IX1 1 3 FA IX1 1 3 FB
STA
IX 3 IX 3 IX 3 IX 3 IX 3 IX 5 IX 3 IX 2
IX1 1 5 78
IX 1 4 88 IX 1 4 89 IX 1 4 8A IX 1 6 8B IX 1 4 8C
EXT 3 4 D8 EXT 3 4 D9 EXT 3 4 DA EXT 3 4 DB EXT 3 4 DC EXT 3 6 DD EXT 3 4 DE EXT 3 4 DF EXT 3
BHCC BHCS BPL BMI BMC

REL 2 3 3D REL 2 3 3E
LSL
IX1 1 5 79
CLC SEC CLI SEI

INH 2 1
EOR ADC ORA ADD
EOR ADC ORA ADD JMP

5 2 BD
EOR ADC ORA ADD JMP JSR LDX STX

IX2 2
EOR ADC ORA ADD JMP JSR LDX

IX
INH 2 1 A9 INH 2 1 AA INH 2 1 AB
ROL DEC DBNZ INC
PSHX PULH PSHH
DIR 2 5 2A DIR 2 5 2B DIR 2 5 2C DIR 2 5 2D DIR 2 5 2E DIR 2 5 2F DIR 2
IX1 1 5 7A IX1 1 7 7B IX1 2 5 7C IX1 1 4 7D IX1 1 4 7E
IMM 2 2 BA IMM 2 2 BB IMM 2 BC
IX2 2 4 EA IX2 2 4 EB IX2 2 4 EC IX2 2 6 ED IX2 2 4 EE IX2 2 4 EF
REL 2 3 3B REL 3 3 3C
BCLR5 BSET6 BCLR6 BSET7 BCLR7
INH 1 1 9C INH 1 9D 1 2+ 9E INH 2+ 9F
IX1 1 3 FC IX1 1 5 FD IX1 1 3 FE IX1 1 3 FF IX1 1
CLRH
RSP
INH 1 AD
BMS BIL BIH

REL 2 REL IX IX1 IX2 IMD DIX+
TST MOV CLR

IX1 1
TST MOV CLR

IX 1
NOP STOP WAIT

INH 1
BSR LDX
2 AF
JSR LDX STX
INH 2 AE
REL 2 2 BE IMM 2 2 BF
Page 2
1
REL 3 3 3F
DD 2 DIX+ 3 1 5F 1 6F
IMD 2 IX+D 1 5 7F 4 8F
TXA
INH 2
AIX
IMM 2
STX
Inherent Immediate Direct Extended DIR to DIR IX+ to DIR
Relative Indexed, No Offset Indexed, 8-Bit Offset Indexed, 16-Bit Offset IMM to DIR DIR to IX+
Stack Pointer, 8-Bit Offset Stack Pointer, 16-Bit Offset Indexed, No Offset with Post Increment Indexed, 1-Byte Offset with Post Increment
Opcode in Hexadecimal F0 Number of Bytes 1
SUB
3 HCS08 Cycles Instruction Mnemonic IX Addressing Mode
Table 7-3. Opcode Map (Sheet 2 of 2)

Bit-Manipulation Branch Read-Modify-Write 9E60 Control 6 Register/Memory 9ED0 5 9EE0 4
NEG
3 SP1 9E61 6
SUB CMP SBC
SUB CMP SBC

6 SP1
4 SP2 3 SP1 9ED1 5 9EE1 4 4 SP2 3 SP1 9ED2 5 9EE2 4 4 SP2 3 SP1 9ED3 5 9EE3 4 9EF3
CBEQ
4 SP1
9E63
COM
3 SP1 9E64 6
CPX AND BIT
CPX AND BIT LDA STA EOR ADC ORA ADD

SP1
CPHX
4 SP2 3 SP1 3 9ED4 5 9EE4 4 4 SP2 3 SP1 9ED5 5 9EE5 4 4 SP2 3 SP1 9ED6 5 9EE6 4
LSR
3 SP1
9E66
ROR
3 SP1 9E67 6
LDA STA EOR ADC ORA ADD

4 SP2 3
4 SP2 3 SP1 9ED7 5 9EE7 4 4 SP2 3 SP1 9ED8 5 9EE8 4 4 SP2 3 SP1 9ED9 5 9EE9 4 4 SP2 3 SP1 9EDA 5 9EEA 4 4 SP2 3 SP1 9EDB 5 9EEB 4
ASR
3 SP1 9E68 6
LSL
3 SP1 9E69 6
ROL
3 SP1 9E6A 6
DEC
3 SP1 9E6B 8
DBNZ
4 SP1 9E6C 6
INC
3 SP1 9E6D 5
TST
3 SP1 9EAE 2 9E6F 6 SP1 5 9EBE 6 9ECE 5 9EDE 5 9EEE 4 9EFE 5
LDHX
IX 4
LDHX
IX2 3
LDHX
LDX STX
4 SP2 3
LDX STX
SP1 3
LDHX STHX
SP1
IX1 4 SP2 3 SP1 3 SP1 9EDF 5 9EEF 4 9EFF 5
CLR
3 INH IMM DIR EXT DD IX+D Inherent Immediate Direct Extended DIR to DIR IX+ to DIR REL IX IX1 IX2 IMD DIX+ Relative Indexed, No Offset Indexed, 8-Bit Offset Indexed, 16-Bit Offset IMM to DIR DIR to IX+ SP1 SP2 IX+ IX1+
Stack Pointer, 8-Bit Offset Stack Pointer, 16-Bit Offset Indexed, No Offset with Post Increment Indexed, 1-Byte Offset with Post Increment Prebyte (9E) and Opcode in Hexadecimal 9E60 Number of Bytes 3 HCS08 Cycles Instruction Mnemonic SP1 Addressing Mode 6
Note: All Sheet 2 Opcodes are Preceded by the Page 2 Prebyte (9E)
NEG

8.1 Introduction
The multi-purpose clock generator (MCG) module provides several clock source choices for the MCU. The module contains a frequency-locked loop (FLL) and a phase-locked loop (PLL) that are controllable by either an internal or an external reference clock. The module can select either of the FLL or PLL clocks, or either of the internal or external reference clocks as a source for the MCU system clock. Whichever clock source is chosen, it is passed through a reduced bus divider which allows a lower output clock frequency to be derived. The MCG also controls an external oscillator (XOSC) for the use of a crystal or resonator as the external reference clock. All devices in the MC9S08DZ60 Series feature the MCG module. NOTE Refer to Section 1.3, System Clock Distribution, for detailed view of the distribution clock sources throughout the chip.
BDC
BKP
HCS08 SYSTEM CONTROL RESET RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT COP INT VREFH VREFL VDDA VSSA LVD IRQ 24-CHANNEL,12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) 8 IRQ ADP7-ADP0 ADP15-ADP8 ADP23-ADP16 PORT C 2-CHANNEL TIMER/PWM MODULE (TPM2) USER EEPROM MC9S0DZ60 = 2K CONTROLLER AREA NETWORK (MSCAN) SERIAL PERIPHERAL INTERFACE MODULE (SPI) SERIAL COMMUNICATIONS INTERFACE (SCI1) ANALOG COMPARATOR (ACMP2) IIC MODULE (IIC) SERIAL COMMUNICATIONS INTERFACE (SCI2) MULTI-PURPOSE CLOCK GENERATOR (MCG) OSCILLATOR (XOSC) - VREFH/VREFL internally connected to VDDA/VSSA in 48-pin and 32-pin packages - VDD and VSS pins are each internally connected to two pads in 32-pin package XTAL EXTAL TPM2CH1, TPM2CH0 TPM2CLK RxCAN TxCAN MISO MOSI SPSCK SS RxD1 TxD1 ACMP2O ACMP2ACMP2+ SDA SCL RxD2 TxD2 DEBUG MODULE (DBG) REAL-TIME COUNTER (RTC) VDD VDD VSS VSS VOLTAGE REGULATOR
PORT G
PORT F
PORT E
PORT D
USER FLASH MC9S0DZ60 = 60K MC9S0DZ48 = 48K MC9S0DZ32 = 32K MC9S0DZ16 = 16K
PORT B
8.1.1
Features
Key features of the MCG module are: Frequency-locked loop (FLL) 0.2% resolution using internal 32-kHz reference 2% deviation over voltage and temperature using internal 32-kHz reference Internal or external reference can be used to control the FLL Phase-locked loop (PLL) Voltage-controlled oscillator (VCO) Modulo VCO frequency divider Phase/Frequency detector Integrated loop lter Lock detector with interrupt capability Internal reference clock Nine trim bits for accuracy Can be selected as the clock source for the MCU External reference clock Control for external oscillator Clock monitor with reset capability Can be selected as the clock source for the MCU Reference divider is provided Clock source selected can be divided down by 1, 2, 4, or 8 BDC clock (MCGLCLK) is provided as a constant divide by 2 of the DCO output whether in an FLL or PLL mode.
External Oscillator (XOSC)
RANGE HGO CME Clock Monitor
EREFS EREFSTEN IREFSTEN
ERCLKEN IRCLKEN CLKS BDIV
MCGERCLK MCGIRCLK
/ 2n Internal Reference Clock LP n=0-3
MCGOUT
LOC
OSCINIT IREFS
9
TRIM
DCO
DCOOUT
PLLS / 2n RDIV_CLK Filter FLL RDIV LP VCOOUT Phase Detector VDIV Charge Pump Internal Filter PLL /(4,8,12,...,40) VCO n=0-7
Lock Detector
LOLS LOCK MCGFFCLK MCGFFCLKVALID MCGLCLK
/2
Multi-purpose Clock Generator (MCG)
Figure 8-2. Multi-Purpose Clock Generator (MCG) Block Diagram
8.1.2
Modes of Operation
There are nine modes of operation for the MCG: FLL Engaged Internal (FEI) FLL Engaged External (FEE) FLL Bypassed Internal (FBI) FLL Bypassed External (FBE) PLL Engaged External (PEE) PLL Bypassed External (PBE) Bypassed Low Power Internal (BLPI) Bypassed Low Power External (BLPE) Stop For details see Section 8.4.1, Operational Modes.
8.2
External Signal Description
There are no MCG signals that connect off chip.
8.3
8.3.1
Register Denition
MCG Control Register 1 (MCGC1)
7 6 5 4 3 2 1 0
R CLKS W Reset: 0 0 0 0 0 1 0 0 RDIV IREFS IRCLKEN IREFSTEN
Figure 8-3. MCG Control Register 1 (MCGC1) Table 8-1. MCG Control Register 1 Field Descriptions
Field 7:6 CLKS Description Clock Source Select Selects the system clock source. 00 Encoding 0 Output of FLL or PLL is selected. 01 Encoding 1 Internal reference clock is selected. 10 Encoding 2 External reference clock is selected. 11 Encoding 3 Reserved, defaults to 00. Reference Divider Selects the amount to divide down the reference clock selected by the IREFS bit. If the FLL is selected, the resulting frequency must be in the range 31.25 kHz to 39.0625 kHz. If the PLL is selected, the resulting frequency must be in the range 1 MHz to 2 MHz. 000 Encoding 0 Divides reference clock by 1 (reset default) 001 Encoding 1 Divides reference clock by 2 010 Encoding 2 Divides reference clock by 4 011 Encoding 3 Divides reference clock by 8 100 Encoding 4 Divides reference clock by 16 101 Encoding 5 Divides reference clock by 32 110 Encoding 6 Divides reference clock by 64 111 Encoding 7 Divides reference clock by 128 Internal Reference Select Selects the reference clock source. 1 Internal reference clock selected 0 External reference clock selected Internal Reference Clock Enable Enables the internal reference clock for use as MCGIRCLK. 1 MCGIRCLK active 0 MCGIRCLK inactive Internal Reference Stop Enable Controls whether or not the internal reference clock remains enabled when the MCG enters stop mode. 1 Internal reference clock stays enabled in stop if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI mode before entering stop 0 Internal reference clock is disabled in stop
5:3 RDIV
2 IREFS 1 IRCLKEN 0 IREFSTEN
8.3.2

7 6 5 4 3 2 1 0
R BDIV W Reset: 0 1 0 0 0 0 0 0 RANGE HGO LP EREFS ERCLKEN EREFSTEN
Figure 8-4. MCG Control Register 2 (MCGC2) Table 8-2. MCG Control Register 2 Field Descriptions
Field 7:6 BDIV Description Bus Frequency Divider Selects the amount to divide down the clock source selected by the CLKS bits in the MCGC1 register. This controls the bus frequency. 00 Encoding 0 Divides selected clock by 1 01 Encoding 1 Divides selected clock by 2 (reset default) 10 Encoding 2 Divides selected clock by 4 11 Encoding 3 Divides selected clock by 8 Frequency Range Select Selects the frequency range for the external oscillator or external clock source. 1 High frequency range selected for the external oscillator of 1 MHz to 16 MHz (1 MHz to 40 MHz for external clock source) 0 Low frequency range selected for the external oscillator of 32 kHz to 100 kHz (32 kHz to 1 MHz for external clock source) High Gain Oscillator Select Controls the external oscillator mode of operation. 1 Congure external oscillator for high gain operation 0 Congure external oscillator for low power operation Low Power Select Controls whether the FLL (or PLL) is disabled in bypassed modes. 1 FLL (or PLL) is disabled in bypass modes (lower power). 0 FLL (or PLL) is not disabled in bypass modes. External Reference Select Selects the source for the external reference clock. 1 Oscillator requested 0 External Clock Source requested External Reference Enable Enables the external reference clock for use as MCGERCLK. 1 MCGERCLK active 0 MCGERCLK inactive
5 RANGE
4 HGO 3 LP 2 EREFS 1 ERCLKEN
0 External Reference Stop Enable Controls whether or not the external reference clock remains enabled when EREFSTEN the MCG enters stop mode. 1 External reference clock stays enabled in stop if ERCLKEN is set or if MCG is in FEE, FBE, PEE, PBE, or BLPE mode before entering stop 0 External reference clock is disabled in stop
8.3.3
MCG Trim Register (MCGTRM)

7 6 5 4 3 2 1 0
R TRIM W POR: Reset: 1 U 0 U 0 U 0 U 0 U 0 U 0 U 0 U
Figure 8-5. MCG Trim Register (MCGTRM) Table 8-3. MCG Trim Register Field Descriptions
Field 7:0 TRIM Description MCG Trim Setting Controls the internal reference clock frequency by controlling the internal reference clock period. The TRIM bits are binary weighted (i.e., bit 1 will adjust twice as much as bit 0). Increasing the binary value in TRIM will increase the period, and decreasing the value will decrease the period. An additional ne trim bit is available in MCGSC as the FTRIM bit. If a TRIM[7:0] value stored in nonvolatile memory is to be used, its the users responsibility to copy that value from the nonvolatile memory location to this register.
8.3.4
MCG Status and Control Register (MCGSC)

7 6 5 4 3 2 1 0
R W POR: Reset:
LOLS
LOCK
PLLST
IREFST
CLKST
OSCINIT FTRIM
0 0
0 0
0 0
1 1
0 0
0 0
0 0
0 U
Figure 8-6. MCG Status and Control Register (MCGSC) Table 8-4. MCG Status and Control Register Field Descriptions
Field 7 LOLS Description Loss of Lock Status This bit is a sticky indication of lock status for the FLL or PLL. LOLS is set when lock detection is enabled and after acquiring lock, the FLL or PLL output frequency has fallen outside the lock exit frequency tolerance, Dunl. LOLIE determines whether an interrupt request is made when set. LOLS is cleared by reset or by writing a logic 1 to LOLS when LOLS is set. Writing a logic 0 to LOLS has no effect. 0 FLL or PLL has not lost lock since LOLS was last cleared. 1 FLL or PLL has lost lock since LOLS was last cleared. Lock Status Indicates whether the FLL or PLL has acquired lock. Lock detection is disabled when both the FLL and PLL are disabled. If the lock status bit is set then changing the value of any of the following bits IREFS, PLLS, RDIV[2:0], TRIM[7:0] (if in FEI or FBI modes), or VDIV[3:0] (if in PBE or PEE modes), will cause the lock status bit to clear and stay cleared until the FLL or PLL has reacquired lock. Stop mode entry will also cause the lock status bit to clear and stay cleared until the FLL or PLL has reacquired lock. Entry into BLPI or BLPE mode will also cause the lock status bit to clear and stay cleared until the MCG has exited these modes and the FLL or PLL has reacquired lock. 0 FLL or PLL is currently unlocked. 1 FLL or PLL is currently locked. PLL Select Status The PLLST bit indicates the current source for the PLLS clock. The PLLST bit does not update immediately after a write to the PLLS bit due to internal synchronization between clock domains. 0 Source of PLLS clock is FLL clock. 1 Source of PLLS clock is PLL clock. Internal Reference Status The IREFST bit indicates the current source for the reference clock. The IREFST bit does not update immediately after a write to the IREFS bit due to internal synchronization between clock domains. 0 Source of reference clock is external reference clock (oscillator or external clock source as determined by the EREFS bit in the MCGC2 register). 1 Source of reference clock is internal reference clock. Clock Mode Status The CLKST bits indicate the current clock mode. The CLKST bits do not update immediately after a write to the CLKS bits due to internal synchronization between clock domains. 00 Encoding 0 Output of FLL is selected. 01 Encoding 1 Internal reference clock is selected. 10 Encoding 2 External reference clock is selected. 11 Encoding 3 Output of PLL is selected.
6 LOCK
5 PLLST
4 IREFST
3:2 CLKST
Table 8-4. MCG Status and Control Register Field Descriptions (continued)
Field 1 OSCINIT Description OSC Initialization If the external reference clock is selected by ERCLKEN or by the MCG being in FEE, FBE, PEE, PBE, or BLPE mode, and if EREFS is set, then this bit is set after the initialization cycles of the external oscillator clock have completed. This bit is only cleared when either EREFS is cleared or when the MCG is in either FEI, FBI, or BLPI mode and ERCLKEN is cleared. MCG Fine Trim Controls the smallest adjustment of the internal reference clock frequency. Setting FTRIM will increase the period and clearing FTRIM will decrease the period by the smallest amount possible. If an FTRIM value stored in nonvolatile memory is to be used, its the users responsibility to copy that value from the nonvolatile memory location to this registers FTRIM bit.
0 FTRIM
8.3.5

7 6 5 4 3 2 1 0
R LOLIE W Reset: 0 0 0 PLLS CME
0 VDIV 0 0 0 0 1
Figure 8-7. MCG PLL Register (MCGPLL) Table 8-5. MCG PLL Register Field Descriptions
Field 7 LOLIE Description Loss of Lock Interrupt Enable Determines if an interrupt request is made following a loss of lock indication. The LOLIE bit only has an effect when LOLS is set. 0 No request on loss of lock. 1 Generate an interrupt request on loss of lock. PLL Select Controls whether the PLL or FLL is selected. If the PLLS bit is clear, the PLL is disabled in all modes. If the PLLS is set, the FLL is disabled in all modes. 1 PLL is selected 0 FLL is selected
6 PLLS
Table 8-5. MCG PLL Register Field Descriptions (continued)

Field 5 CME Description Clock Monitor Enable Determines if a reset request is made following a loss of external clock indication. The CME bit should only be set to a logic 1 when either the MCG is in an operational mode that uses the external clock (FEE, FBE, PEE, PBE, or BLPE) or the external reference is enabled (ERCLKEN=1 in the MCGC2 register). Whenever the CME bit is set to a logic 1, the value of the RANGE bit in the MCGC2 register should not be changed. 0 Clock monitor is disabled. 1 Generate a reset request on loss of external clock. VCO Divider Selects the amount to divide down the VCO output of PLL. The VDIV bits establish the multiplication factor (M) applied to the reference clock frequency. 0000 Encoding 0 Reserved. 0001 Encoding 1 Multiply by 4. 0010 Encoding 2 Multiply by 8. 0011 Encoding 3 Multiply by 12. 0100 Encoding 4 Multiply by 16. 0101 Encoding 5 Multiply by 20. 0110 Encoding 6 Multiply by 24. 0111 Encoding 7 Multiply by 28. 1000 Encoding 8 Multiply by 32. 1001 Encoding 9 Multiply by 36. 1010 Encoding 10 Multiply by 40. 1011 Encoding 11 Reserved (default to M=40). 11xx Encoding 12-15 Reserved (default to M=40).
3:0 VDIV
8.4
8.4.1
Functional Description
Operational Modes
IREFS=1 CLKS=00 PLLS=0 IREFS=1 CLKS=01 PLLS=0 BDM Enabled or LP=0 Bypassed Low Power Internal (BLPI) PLL Bypassed External (PBE) FLL Engaged Internal (FEI) FLL Engaged External (FEE) IREFS=0 CLKS=00 PLLS=0 IREFS=0 CLKS=10 PLLS=0 BDM Enabled or LP=0 Bypassed IREFS=0 Low Power CLKS=10 External (BLPE) BDM Disabled and LP=1 IREFS=0 CLKS=10 PLLS=1 BDM Enabled or LP=0 IREFS=0 CLKS=00 PLLS=1
FLL Bypassed Internal (FBI)
FLL Bypassed External (FBE)
IREFS=1 CLKS=01 PLLS=0 BDM Disabled and LP=1
PLL Engaged External (PEE)
Entered from any state when MCU enters stop
Stop
Returns to state that was active before MCU entered stop, unless RESET occurs while in stop.
Figure 8-8. Clock Switching Modes
The nine states of the MCG are shown as a state diagram and are described below. The arrows indicate the allowed movements between the states.
8.4.1.1
FLL Engaged Internal (FEI)
FLL engaged internal (FEI) is the default mode of operation and is entered when all the following conditions occur: CLKS bits are written to 00 IREFS bit is written to 1 PLLS bit is written to 0 RDIV bits are written to 000. Since the internal reference clock frequency should already be in the range of 31.25 kHz to 39.0625 kHz after it is trimmed, no further frequency divide is necessary. In FLL engaged internal mode, the MCGOUT clock is derived from the FLL clock, which is controlled by the internal reference clock. The FLL clock frequency locks to 1024 times the reference frequency, as selected by the RDIV bits. The MCGLCLK is derived from the FLL and the PLL is disabled in a low power state.
8.4.1.2
FLL Engaged External (FEE)
The FLL engaged external (FEE) mode is entered when all the following conditions occur: CLKS bits are written to 00 IREFS bit is written to 0 PLLS bit is written to 0 RDIV bits are written to divide reference clock to be within the range of 31.25 kHz to 39.0625 kHz
In FLL engaged external mode, the MCGOUT clock is derived from the FLL clock which is controlled by the external reference clock. The external reference clock which is enabled can be an external crystal/resonator or it can be another external clock source.The FLL clock frequency locks to 1024 times the reference frequency, as selected by the RDIV bits. The MCGLCLK is derived from the FLL and the PLL is disabled in a low power state.
8.4.1.3
FLL Bypassed Internal (FBI)
In FLL bypassed internal (FBI) mode, the MCGOUT clock is derived from the internal reference clock and the FLL is operational but its output clock is not used. This mode is useful to allow the FLL to acquire its target frequency while the MCGOUT clock is driven from the internal reference clock. The FLL bypassed internal mode is entered when all the following conditions occur: CLKS bits are written to 01 IREFS bit is written to 1 PLLS bit is written to 0 RDIV bits are written to 000. Since the internal reference clock frequency should already be in the range of 31.25 kHz to 39.0625 kHz after it is trimmed, no further frequency divide is necessary.
LP bit is written to 0
In FLL bypassed internal mode, the MCGOUT clock is derived from the internal reference clock. The FLL clock is controlled by the internal reference clock, and the FLL clock frequency locks to 1024 times the reference frequency, as selected by the RDIV bits. The MCGLCLK is derived from the FLL and the PLL is disabled in a low power state.
8.4.1.4
FLL Bypassed External (FBE)
In FLL bypassed external (FBE) mode, the MCGOUT clock is derived from the external reference clock and the FLL is operational but its output clock is not used. This mode is useful to allow the FLL to acquire its target frequency while the MCGOUT clock is driven from the external reference clock. The FLL bypassed external mode is entered when all the following conditions occur: CLKS bits are written to 10 IREFS bit is written to 0 PLLS bit is written to 0 RDIV bits are written to divide reference clock to be within the range of 31.25 kHz to 39.0625 kHz LP bit is written to 0 In FLL bypassed external mode, the MCGOUT clock is derived from the external reference clock. The external reference clock which is enabled can be an external crystal/resonator or it can be another external clock source.The FLL clock is controlled by the external reference clock, and the FLL clock frequency locks to 1024 times the reference frequency, as selected by the RDIV bits. The MCGLCLK is derived from the FLL and the PLL is disabled in a low power state. NOTE It is possible to briey operate in FBE mode with an FLL reference clock frequency that is greater than the specied maximum frequency. This can be necessary in applications that operate in PEE mode using an external crystal with a frequency above 5 MHz. Please see 8.5.2.4, Example # 4: Moving from FEI to PEE Mode: External Crystal = 8 MHz, Bus Frequency = 8 MHz for a detailed example.
8.4.1.5
PLL Engaged External (PEE)
The PLL engaged external (PEE) mode is entered when all the following conditions occur: CLKS bits are written to 00 IREFS bit is written to 0 PLLS bit is written to 1 RDIV bits are written to divide reference clock to be within the range of 1 MHz to 2 MHz
In PLL engaged external mode, the MCGOUT clock is derived from the PLL clock which is controlled by the external reference clock. The external reference clock which is enabled can be an external crystal/resonator or it can be another external clock source The PLL clock frequency locks to a
multiplication factor, as selected by the VDIV bits, times the reference frequency, as selected by the RDIV bits. If BDM is enabled then the MCGLCLK is derived from the DCO (open-loop mode) divided by two. If BDM is not enabled then the FLL is disabled in a low power state.
8.4.1.6
PLL Bypassed External (PBE)
In PLL bypassed external (PBE) mode, the MCGOUT clock is derived from the external reference clock and the PLL is operational but its output clock is not used. This mode is useful to allow the PLL to acquire its target frequency while the MCGOUT clock is driven from the external reference clock. The PLL bypassed external mode is entered when all the following conditions occur: CLKS bits are written to 10 IREFS bit is written to 0 PLLS bit is written to 1 RDIV bits are written to divide reference clock to be within the range of 1 MHz to 2 MHz LP bit is written to 0 In PLL bypassed external mode, the MCGOUT clock is derived from the external reference clock. The external reference clock which is enabled can be an external crystal/resonator or it can be another external clock source. The PLL clock frequency locks to a multiplication factor, as selected by the VDIV bits, times the reference frequency, as selected by the RDIV bits. If BDM is enabled then the MCGLCLK is derived from the DCO (open-loop mode) divided by two. If BDM is not enabled then the FLL is disabled in a low power state.
8.4.1.7
Bypassed Low Power Internal (BLPI)
The bypassed low power internal (BLPI) mode is entered when all the following conditions occur: CLKS bits are written to 01 IREFS bit is written to 1 PLLS bit is written to 0 LP bit is written to 1 BDM mode is not active In bypassed low power internal mode, the MCGOUT clock is derived from the internal reference clock. The PLL and the FLL are disabled at all times in BLPI mode and the MCGLCLK will not be available for BDC communications If the BDM becomes active the mode will switch to FLL bypassed internal (FBI) mode.
8.4.1.8
Bypassed Low Power External (BLPE)
The bypassed low power external (BLPE) mode is entered when all the following conditions occur: CLKS bits are written to 10 IREFS bit is written to 0 PLLS bit is written to 0 or 1
LP bit is written to 1 BDM mode is not active
In bypassed low power external mode, the MCGOUT clock is derived from the external reference clock. The external reference clock which is enabled can be an external crystal/resonator or it can be another external clock source. The PLL and the FLL are disabled at all times in BLPE mode and the MCGLCLK will not be available for BDC communications. If the BDM becomes active the mode will switch to one of the bypassed external modes as determined by the state of the PLLS bit.
8.4.1.9
Stop
Stop mode is entered whenever the MCU enters a STOP state. In this mode, the FLL and PLL are disabled and all MCG clock signals are static except in the following cases: MCGIRCLK will be active in stop mode when all the following conditions occur: IRCLKEN = 1 IREFSTEN = 1 MCGERCLK will be active in stop mode when all the following conditions occur: ERCLKEN = 1 EREFSTEN = 1
8.4.2
Mode Switching
When switching between engaged internal and engaged external modes the IREFS bit can be changed at anytime, but the RDIV bits must be changed simultaneously so that the reference frequency stays in the range required by the state of the PLLS bit (31.25 kHz to 39.0625 kHz if the FLL is selected, or 1 MHz to 2 MHz if the PLL is selected). After a change in the IREFS value the FLL or PLL will begin locking again after the switch is completed. The completion of the switch is shown by the IREFST bit . For the special case of entering stop mode immediately after switching to FBE mode, if the external clock and the internal clock are disabled in stop mode, (EREFSTEN = 0 and IREFSTEN = 0), it is necessary to allow 100us after the IREFST bit is cleared to allow the internal reference to shutdown. For most cases the delay due to instruction execution times will be sufcient. The CLKS bits can also be changed at anytime, but in order for the MCGLCLK to be congured correctly the RDIV bits must be changed simultaneously so that the reference frequency stays in the range required by the state of the PLLS bit (31.25 kHz to 39.0625 kHz if the FLL is selected, or 1 MHz to 2MHz if the PLL is selected). The actual switch to the newly selected clock will be shown by the CLKST bits. If the newly selected clock is not available, the previous clock will remain selected. For details see Figure 8-8.
8.4.3
Bus Frequency Divider
The BDIV bits can be changed at anytime and the actual switch to the new frequency will occur immediately.
8.4.4
Low Power Bit Usage
The low power bit (LP) is provided to allow the FLL or PLL to be disabled and thus conserve power when these systems are not being used. However, in some applications it may be desirable to enable the FLL or PLL and allow it to lock for maximum accuracy before switching to an engaged mode. Do this by writing the LP bit to 0.
8.4.5
Internal Reference Clock
When IRCLKEN is set the internal reference clock signal will be presented as MCGIRCLK, which can be used as an additional clock source. The MCGIRCLK frequency can be re-targeted by trimming the period of the internal reference clock. This can be done by writing a new value to the TRIM bits in the MCGTRM register. Writing a larger value will decrease the MCGIRCLK frequency, and writing a smaller value to the MCGTRM register will increase the MCGIRCLK frequency. The TRIM bits will effect the MCGOUT frequency if the MCG is in FLL engaged internal (FEI), FLL bypassed internal (FBI), or bypassed low power internal (BLPI) mode. The TRIM and FTRIM value is initialized by POR but is not affected by other resets. Until MCGIRCLK is trimmed, programming low reference divider (RDIV) factors may result in MCGOUT frequencies that exceed the maximum chip-level frequency and violate the chip-level clock timing specications (see the Device Overview chapter). If IREFSTEN and IRCLKEN bits are both set, the internal reference clock will keep running during stop mode in order to provide a fast recovery upon exiting stop.
8.4.6
External Reference Clock
The MCG module can support an external reference clock with frequencies between 31.25 kHz to 5 MHz in FEE and FBE modes, 1 MHz to 16 MHz in PEE and PBE modes, and 0 to 40 MHz in BLPE mode. When ERCLKEN is set, the external reference clock signal will be presented as MCGERCLK, which can be used as an additional clock source. When IREFS = 1, the external reference clock will not be used by the FLL or PLL and will only be used as MCGERCLK. In these modes, the frequency can be equal to the maximum frequency the chip-level timing specications will support (see the Device Overview chapter). If EREFSTEN and ERCLKEN bits are both set or the MCG is in FEE, FBE, PEE, PBE or BLPE mode, the external reference clock will keep running during stop mode in order to provide a fast recovery upon exiting stop. If CME bit is written to 1, the clock monitor is enabled. If the external reference falls below a certain frequency (floc_high or floc_low depending on the RANGE bit in the MCGC2), the MCU will reset. The LOC bit in the System Reset Status (SRS) register will be set to indicate the error.
8.4.7
Fixed Frequency Clock
The MCG presents the divided reference clock as MCGFFCLK for use as an additional clock source. The MCGFFCLK frequency must be no more than 1/4 of the MCGOUT frequency to be valid. Because of this requirement, the MCGFFCLK is not valid in bypass modes for the following combinations of BDIV and RDIV values: BDIV=00 (divide by 1), RDIV < 010 BDIV=01 (divide by 2), RDIV < 011 When MCGFFCLK is valid then MCGFFCLKVALID is set to 1. When MCGFFCLK is not valid then MCGFFCLKVALID is set to 0.
8.5
Initialization / Application Information
This section describes how to initialize and congure the MCG module in application. The following sections include examples on how to initialize the MCG and properly switch between the various available modes.
8.5.1
MCG Module Initialization Sequence
The MCG comes out of reset congured for FEI mode with the BDIV set for divide-by-2. The internal reference will stabilize in tirefst microseconds before the FLL can acquire lock. As soon as the internal reference is stable, the FLL will acquire lock in tl_lock milliseconds. Upon POR, the internal reference will require trimming to guarantee an accurate clock. Freescale recommends using FLASH location 0xFFAE for storing the ne trim bit, FTRIM in the MCGSC register, and 0xFFAF for storing the 8-bit trim value in the MCGTRM register. The MCU will not automatically copy the values in these FLASH locations to the respective registers. Therefore, user code must copy these values from FLASH to the registers. NOTE The BDIV value should not be changed to divide-by-1 without rst trimming the internal reference. Failure to do so could result in the MCU running out of specication.
8.5.1.1
Initializing the MCG
Because the MCG comes out of reset in FEI mode, the only MCG modes which can be directly switched to upon reset are FEE, FBE, and FBI modes (see Figure 8-8). Reaching any of the other modes requires rst conguring the MCG for one of these three initial modes. Care must be taken to check relevant status bits in the MCGSC register reecting all conguration changes within each mode. To change from FEI mode to FEE or FBE modes, follow this procedure: 1. Enable the external clock source by setting the appropriate bits in MCGC2. 2. Write to MCGC1 to select the clock mode.
If entering FEE, set RDIV appropriately, clear the IREFS bit to switch to the external reference, and leave the CLKS bits at %00 so that the output of the FLL is selected as the system clock source. If entering FBE, clear the IREFS bit to switch to the external reference and change the CLKS bits to %10 so that the external reference clock is selected as the system clock source. The RDIV bits should also be set appropriately here according to the external reference frequency because although the FLL is bypassed, it is still on in FBE mode. The internal reference can optionally be kept running by setting the IRCLKEN bit. This is useful if the application will switch back and forth between internal and external modes. For minimum power consumption, leave the internal reference disabled while in an external clock mode. 3. After the proper conguration bits have been set, wait for the affected bits in the MCGSC register to be changed appropriately, reecting that the MCG has moved into the proper mode. If ERCLKEN was set in step 1 or the MCG is in FEE, FBE, PEE, PBE, or BLPE mode, and EREFS was also set in step 1, wait here for the OSCINIT bit to become set indicating that the external clock source has nished its initialization cycles and stabilized. Typical crystal startup times are given in Appendix A, Electrical Characteristics. If in FEE mode, check to make sure the IREFST bit is cleared and the LOCK bit is set before moving on. If in FBE mode, check to make sure the IREFST bit is cleared, the LOCK bit is set, and the CLKST bits have changed to %10 indicating the external reference clock has been appropriately selected. Although the FLL is bypassed in FBE mode, it is still on and will lock in FBE mode. To change from FEI clock mode to FBI clock mode, follow this procedure: 1. Change the CLKS bits to %01 so that the internal reference clock is selected as the system clock source. 2. Wait for the CLKST bits in the MCGSC register to change to %01, indicating that the internal reference clock has been appropriately selected.
8.5.2
MCG Mode Switching
When switching between operational modes of the MCG, certain conguration bits must be changed in order to properly move from one mode to another. Each time any of these bits are changed (PLLS, IREFS, CLKS, or EREFS), the corresponding bits in the MCGSC register (PLLST, IREFST, CLKST, or OSCINIT) must be checked before moving on in the application software. Additionally, care must be taken to ensure that the reference clock divider (RDIV) is set properly for the mode being switched to. For instance, in PEE mode, if using a 4 MHz crystal, RDIV must be set to %001 (divide-by-2) or %010 (divide -by-4) in order to divide the external reference down to the required frequency between 1 and 2 MHz. The RDIV and IREFS bits should always be set properly before changing the PLLS bit so that the FLL or PLL clock has an appropriate reference clock frequency to switch to.
The table below shows MCGOUT frequency calculations using RDIV, BDIV, and VDIV settings for each clock mode. The bus frequency is equal to MCGOUT divided by 2.
Table 8-6. MCGOUT Frequency Calculation Options
Clock Mode FEI (FLL engaged internal) fMCGOUT1 (fint * 1024) / B Note Typical fMCGOUT = 16 MHz immediately after reset. RDIV bits set to %000. fext / R must be in the range of 31.25 kHz to 39.0625 kHz fext / R must be in the range of 31.25 kHz to 39.0625 kHz Typical fint = 32 kHz fext / R must be in the range of 1 MHz to 2 MHz fext / R must be in the range of 1 MHz to 2 MHz
FEE (FLL engaged external) FBE (FLL bypassed external) FBI (FLL bypassed internal) PEE (PLL engaged external) PBE (PLL bypassed external) BLPI (Bypassed low power internal) BLPE (Bypassed low power external)
1
(fext / R *1024) / B fext / B fint / B [(fext / R) * M] / B fext / B fint / B fext / B
R is the reference divider selected by the RDIV bits, B is the bus frequency divider selected by the BDIV bits, and M is the multiplier selected by the VDIV bits.
This section will include 3 mode switching examples using a 4 MHz external crystal. If using an external clock source less than 1 MHz, the MCG should not be congured for any of the PLL modes (PEE and PBE).
8.5.2.1
Example # 1: Moving from FEI to PEE Mode: External Crystal = 4 MHz, Bus Frequency = 8 MHz
In this example, the MCG will move through the proper operational modes from FEI to PEE mode until the 4 MHz crystal reference frequency is set to achieve a bus frequency of 8 MHz. Because the MCG is in FEI mode out of reset, this example also shows how to initialize the MCG for PEE mode out of reset. First, the code sequence will be described. Then a owchart will be included which illustrates the sequence. 1. First, FEI must transition to FBE mode: a) MCGC2 = 0x36 (%00110110) BDIV (bits 7 and 6) set to %00, or divide-by-1 RANGE (bit 5) set to 1 because the frequency of 4 MHz is within the high frequency range HGO (bit 4) set to 1 to congure external oscillator for high gain operation EREFS (bit 2) set to 1, because a crystal is being used ERCLKEN (bit 1) set to 1 to ensure the external reference clock is active b) Loop until OSCINIT (bit 1) in MCGSC is 1, indicating the crystal selected by the EREFS bit has been initialized.
c) MCGC1 = 0xB8 (%10111000) CLKS (bits 7 and 6) set to %10 in order to select external reference clock as system clock source RDIV (bits 5-3) set to %111, or divide-by-128 because 4 MHz / 128 = 31.25 kHz which is in the 31.25 kHz to 39.0625 kHz range required by the FLL IREFS (bit 2) cleared to 0, selecting the external reference clock d) Loop until IREFST (bit 4) in MCGSC is 0, indicating the external reference is the current source for the reference clock e) Loop until CLKST (bits 3 and 2) in MCGSC are %10, indicating that the external reference clock is selected to feed MCGOUT 2. Then, FBE must transition either directly to PBE mode or rst through BLPE mode and then to PBE mode: a) BLPE: If a transition through BLPE mode is desired, rst set LP (bit 3) in MCGC2 to 1. b) BLPE/PBE: MCGC1 = 0x90 (%10010000) RDIV (bits 5-3) set to %010, or divide-by-4 because 4 MHz / 4 = 1 MHz which is in the 1 MHz to 2 MHz range required by the PLL. In BLPE mode, the conguration of the RDIV does not matter because both the FLL and PLL are disabled. Changing them only sets up the the dividers for PLL usage in PBE mode c) BLPE/PBE: MCGC3 = 0x44 (%01000100) PLLS (bit 6) set to 1, selects the PLL. In BLPE mode, changing this bit only prepares the MCG for PLL usage in PBE mode VDIV (bits 3-0) set to %0100, or multiply-by-16 because 1 MHz reference * 16 = 16 MHz. In BLPE mode, the conguration of the VDIV bits does not matter because the PLL is disabled. Changing them only sets up the multiply value for PLL usage in PBE mode d) BLPE: If transitioning through BLPE mode, clear LP (bit 3) in MCGC2 to 0 here to switch to PBE mode e) PBE: Loop until PLLST (bit 5) in MCGSC is set, indicating that the current source for the PLLS clock is the PLL f) PBE: Then loop until LOCK (bit 6) in MCGSC is set, indicating that the PLL has acquired lock 3. Last, PBE mode transitions into PEE mode: a) MCGC1 = 0x10 (%00010000) CLKS (bits7 and 6) in MCGSC1 set to %00 in order to select the output of the PLL as the system clock source b) Loop until CLKST (bits 3 and 2) in MCGSC are %11, indicating that the PLL output is selected to feed MCGOUT in the current clock mode Now, With an RDIV of divide-by-4, a BDIV of divide-by-1, and a VDIV of multiply-by-16, MCGOUT = [(4 MHz / 4) * 16] / 1 = 16 MHz, and the bus frequency is MCGOUT / 2, or 8 MHz
START
IN FEI MODE
MCGC2 = $36 IN BLPE MODE ? (LP=1) CHECK OSCINIT = 1 ? NO YES MCGC2 = $36 (LP = 0) NO
YES
MCGC1 = $B8 CHECK PLLST = 1? CHECK IREFST = 0? YES CHECK LOCK = 1? CHECK CLKST = %10? NO YES YES MCGC1 = $10 NO NO YES NO
ENTER BLPE MODE ?
NO CHECK CLKST = %11? NO
YES MCGC2 = $3E (LP = 1) YES
CONTINUE IN PEE MODE MCGC1 = $90 MCGC3 = $44
Figure 8-9. Flowchart of FEI to PEE Mode Transition using a 4 MHz crystal
8.5.2.2
Example # 2: Moving from PEE to BLPI Mode: External Crystal = 4 MHz, Bus Frequency =16 kHz
In this example, the MCG will move through the proper operational modes from PEE mode with a 4 MHz crystal congured for an 8 MHz bus frequency (see previous example) to BLPI mode with a 16 kHz bus frequency.First, the code sequence will be described. Then a owchart will be included which illustrates the sequence. 1. First, PEE must transition to PBE mode: a) MCGC1 = 0x90 (%10010000) CLKS (bits 7 and 6) set to %10 in order to switch the system clock source to the external reference clock b) Loop until CLKST (bits 3 and 2) in MCGSC are %10, indicating that the external reference clock is selected to feed MCGOUT 2. Then, PBE must transition either directly to FBE mode or rst through BLPE mode and then to FBE mode: a) BLPE: If a transition through BLPE mode is desired, rst set LP (bit 3) in MCGC2 to 1 b) BLPE/FBE: MCGC1 = 0xB8 (%10111000) RDIV (bits 5-3) set to %111, or divide-by-128 because 4 MHz / 128 = 31.25 kHz which is in the 31.25 kHz to 39.0625 kHz range required by the FLL. In BLPE mode, the conguration of the RDIV does not matter because both the FLL and PLL are disabled. Changing them only sets up the dividers for FLL usage in FBE mode c) BLPE/FBE: MCGC3 = 0x04 (%00000100) PLLS (bit 6) clear to 0 to select the FLL. In BLPE mode, changing this bit only prepares the MCG for FLL usage in FBE mode. With PLLS = 0, the VDIV value does not matter. d) BLPE: If transitioning through BLPE mode, clear LP (bit 3) in MCGC2 to 0 here to switch to FBE mode e) FBE: Loop until PLLST (bit 5) in MCGSC is clear, indicating that the current source for the PLLS clock is the FLL f) FBE: Optionally, loop until LOCK (bit 6) in the MCGSC is set, indicating that the FLL has acquired lock. Although the FLL is bypassed in FBE mode, it is still enabled and running. 3. Next, FBE mode transitions into FBI mode: a) MCGC1 = 0x44 (%01000100) CLKS (bits7 and 6) in MCGSC1 set to %01 in order to switch the system clock to the internal reference clock IREFS (bit 2) set to 1 to select the internal reference clock as the reference clock source RDIV (bits 5-3) set to %000, or divide-by-1 because the trimmed internal reference should be within the 31.25 kHz to 39.0625 kHz range required by the FLL b) Loop until IREFST (bit 4) in MCGSC is 1, indicating the internal reference clock has been selected as the reference clock source c) Loop until CLKST (bits 3 and 2) in MCGSC are %01, indicating that the internal reference clock is selected to feed MCGOUT
4. Lastly, FBI transitions into BLPI mode. a) MCGC2 = 0x08 (%00001000) LP (bit 3) in MCGSC is 1
START IN PEE MODE
MCGC1 = $90 CHECK PLLST = 0? CHECK CLKST = %10 ? NO NO
YES
YES
ENTER BLPE MODE ?
OPTIONAL: CHECK LOCK = 1? NO YES MCGC1 = $44
NO
YES MCGC2 = $3E
CHECK IREFST = 0? MCGC1 = $B8 MCGC3 = $04 YES
NO
IN BLPE MODE ? (LP=1)
NO
CHECK CLKST = %01?
NO
YES YES MCGC2 = $36 (LP = 0) MCGC2 = $08
CONTINUE IN BLPI MODE
Figure 8-10. Flowchart of PEE to BLPI Mode Transition using a 4 MHz crystal
8.5.2.3
Example #3: Moving from BLPI to FEE Mode: External Crystal = 4 MHz, Bus Frequency = 16 MHz
In this example, the MCG will move through the proper operational modes from BLPI mode at a 16 kHz bus frequency running off of the internal reference clock (see previous example) to FEE mode using a 4 MHz crystal congured for a 16 MHz bus frequency. First, the code sequence will be described. Then a owchart will be included which illustrates the sequence. 1. First, BLPI must transition to FBI mode. a) MCGC2 = 0x00 (%00000000) LP (bit 3) in MCGSC is 0 b) Optionally, loop until LOCK (bit 6) in the MCGSC is set, indicating that the FLL has acquired lock. Although the FLL is bypassed in FBI mode, it is still enabled and running. 2. Next, FBI will transition to FEE mode. a) MCGC2 = 0x36 (%00110110) RANGE (bit 5) set to 1 because the frequency of 4 MHz is within the high frequency range HGO (bit 4) set to 1 to congure external oscillator for high gain operation EREFS (bit 2) set to 1, because a crystal is being used ERCLKEN (bit 1) set to 1 to ensure the external reference clock is active b) Loop until OSCINIT (bit 1) in MCGSC is 1, indicating the crystal selected by the EREFS bit has been initialized. c) MCGC1 = 0x38 (%00111000) CLKS (bits 7 and 6) set to %00 in order to select the output of the FLL as system clock source RDIV (bits 5-3) set to %111, or divide-by-128 because 4 MHz / 128 = 31.25 kHz which is in the 31.25 kHz to 39.0625 kHz range required by the FLL IREFS (bit 1) cleared to 0, selecting the external reference clock d) Loop until IREFST (bit 4) in MCGSC is 0, indicating the external reference clock is the current source for the reference clock e) Optionally, loop until LOCK (bit 6) in the MCGSC is set, indicating that the FLL has reacquired lock. f) Loop until CLKST (bits 3 and 2) in MCGSC are %00, indicating that the output of the FLL is selected to feed MCGOUT
START
IN BLPI MODE
CHECK IREFST = 0? MCGC2 = $00 YES NO
OPTIONAL: CHECK LOCK = 1? YES MCGC2 = $36
NO
OPTIONAL: CHECK LOCK = 1? YES
NO
CHECK CLKST = %00?
NO
CHECK OSCINIT = 1 ?
NO
YES
CONTINUE YES IN FEE MODE
MCGC1 = $38
Figure 8-11. Flowchart of BLPI to FEE Mode Transition using a 4 MHz crystal
8.5.2.4
Example # 4: Moving from FEI to PEE Mode: External Crystal = 8 MHz, Bus Frequency = 8 MHz
In this example, the MCG will move through the proper operational modes from FEI to PEE mode until the 8 MHz crystal reference frequency is set to achieve a bus frequency of 8 MHz. This example is similar to example number one except that in this case the frequency of the external crystal is 8 MHz instead of 4 MHz. Special consideration must be taken with this case since there is a period of time along the way from FEI mode to PEE mode where the FLL operates based on a reference clock with a frequency that is greater than the maximum allowed for the FLL. This occurs because with an 8 MHz
external crystal and a maximum reference divider factor of 128, the resulting frequency of the reference clock for the FLL is 62.5 kHz (greater than the 39.0625 kHz maximum allowed). Care must be taken in the software to minimize the amount of time spent in this state where the FLL is operating in this condition. The following code sequence describes how to move from FEI mode to PEE mode until the 8 MHz crystal reference frequency is set to achieve a bus frequency of 8 MHz. Because the MCG is in FEI mode out of reset, this example also shows how to initialize the MCG for PEE mode out of reset. First, the code sequence will be described. Then a owchart will be included which illustrates the sequence. 1. First, FEI must transition to FBE mode: a) MCGC2 = 0x36 (%00110110) BDIV (bits 7 and 6) set to %00, or divide-by-1 RANGE (bit 5) set to 1 because the frequency of 8 MHz is within the high frequency range HGO (bit 4) set to 1 to congure external oscillator for high gain operation EREFS (bit 2) set to 1, because a crystal is being used ERCLKEN (bit 1) set to 1 to ensure the external reference clock is active b) Loop until OSCINIT (bit 1) in MCGSC is 1, indicating the crystal selected by the EREFS bit has been initialized. c) Block Interrupts (If applicable by setting the interrupt bit in the CCR). d) MCGC1 = 0xB8 (%10111000) CLKS (bits 7 and 6) set to %10 in order to select external reference clock as system clock source RDIV (bits 5-3) set to %111, or divide-by-128. NOTE 8 MHz / 128 = 62.5 kHz which is greater than the 31.25 kHz to 39.0625 kHz range required by the FLL. Therefore after the transition to FBE is complete, software must progress through to BLPE mode immediately by setting the LP bit in MCGC2. IREFS (bit 2) cleared to 0, selecting the external reference clock e) Loop until IREFST (bit 4) in MCGSC is 0, indicating the external reference is the current source for the reference clock f) Loop until CLKST (bits 3 and 2) in MCGSC are %10, indicating that the external reference clock is selected to feed MCGOUT 2. Then, FBE mode transitions into BLPE mode: a) MCGC2 = 0x3E (%00111110) LP (bit 3) in MCGC2 to 1 (BLPE mode entered) NOTE There must be no extra steps (including interrupts) between steps 1d and 2a. b) Enable Interrupts (if applicable by clearing the interrupt bit in the CCR).
c) MCGC1 = 0x98 (%10011000) RDIV (bits 5-3) set to %011, or divide-by-8 because 8 MHz / 8= 1 MHz which is in the 1 MHz to 2 MHz range required by the PLL. In BLPE mode, the conguration of the RDIV does not matter because both the FLL and PLL are disabled. Changing them only sets up the the dividers for PLL usage in PBE mode d) MCGC3 = 0x44 (%01000100) PLLS (bit 6) set to 1, selects the PLL. In BLPE mode, changing this bit only prepares the MCG for PLL usage in PBE mode VDIV (bits 3-0) set to %0100, or multiply-by-16 because 1 MHz reference * 16 = 16 MHz. In BLPE mode, the conguration of the VDIV bits does not matter because the PLL is disabled. Changing them only sets up the multiply value for PLL usage in PBE mode e) Loop until PLLST (bit 5) in MCGSC is set, indicating that the current source for the PLLS clock is the PLL 3. Then, BLPE mode transitions into PBE mode: a) Clear LP (bit 3) in MCGC2 to 0 here to switch to PBE mode b) Then loop until LOCK (bit 6) in MCGSC is set, indicating that the PLL has acquired lock 4. Last, PBE mode transitions into PEE mode: a) MCGC1 = 0x18 (%00011000) CLKS (bits7 and 6) in MCGSC1 set to %00 in order to select the output of the PLL as the system clock source b) Loop until CLKST (bits 3 and 2) in MCGSC are %11, indicating that the PLL output is selected to feed MCGOUT in the current clock mode Now, With an RDIV of divide-by-8, a BDIV of divide-by-1, and a VDIV of multiply-by-16, MCGOUT = [(8 MHz / 8) * 16] / 1 = 16 MHz, and the bus frequency is MCGOUT / 2, or 8 MHz
START
IN FEI MODE
MCGC2 = $36
CHECK OSCINIT = 1 ?
NO
CHECK PLLST = 1? YES
NO
YES MCGC2 = $36 (LP = 0) MCGC1 = $B8
CHECK IREFST = 0? YES
NO CHECK LOCK = 1? NO
YES CHECK CLKST = %10? NO MCGC1 = $18
YES MCGC2 = $3E (LP = 1) CHECK CLKST = %11? NO
YES MCGC1 = $98 MCGC3 = $44
CONTINUE IN PEE MODE
Figure 8-12. Flowchart of FEI to PEE Mode Transition using a 8 MHz crystal
8.5.3
Calibrating the Internal Reference Clock (IRC)
The IRC is calibrated by writing to the MCGTRM register rst, then using the FTRIM bit to ne tune the frequency. We will refer to this total 9-bit value as the trim value, ranging from 0x000 to 0x1FF, where the FTRIM bit is the LSB. The trim value after a POR is always 0x100 (MCGTRM = 0x80 and FTRIM = 0). Writing a larger value will decrease the frequency and smaller values will increase the frequency. The trim value is linear with the period, except that slight variations in wafer fab processing produce slight non-linearities between trim value and period. These non-linearities are why an iterative trimming approach to search for the best trim value is recommended. In Example #5: Internal Reference Clock Trim this approach will be demonstrated. After a trim value has been found for a device, this value can be stored in FLASH memory to save the value. If power is removed from the device, the IRC can easily be re-trimmed by copying the saved value from FLASH to the MCG registers. Freescale identies recommended FLASH locations for storing the trim value for each MCU. Consult the memory map in the data sheet for these locations. On devices that are factory trimmed, the factory trim value will be stored in these locations.
8.5.3.1
Example #5: Internal Reference Clock Trim
For applications that require a tight frequency tolerance, a trimming procedure is provided that will allow a very accurate internal clock source. This section outlines one example of trimming the internal oscillator. Many other possible trimming procedures are valid and can be used. In the example below, the MCG trim will be calibrated for the 9-bit MCGTRM and FTRIM collective value. This value will be referred to as TRMVAL.
Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) Initial conditions: 1) Clock supplied from ATE has 500 s duty period 2) MCG configured for internal reference with 8MHz bus START TRIM PROCEDURE TRMVAL = $100 n=1
MEASURE INCOMING CLOCK WIDTH (COUNT = # OF BUS CLOCKS / 8)
COUNT < EXPECTED = 500 (RUNNING TOO SLOW) . CASE STATEMENT COUNT = EXPECTED = 500
COUNT > EXPECTED = 500 (RUNNING TOO FAST) TRMVAL = TRMVAL - 256/ (2**n) (DECREASING TRMVAL INCREASES THE FREQUENCY) TRMVAL = TRMVAL + 256/ (2**n) (INCREASING TRMVAL DECREASES THE FREQUENCY) STORE MCGTRM AND FTRIM VALUES IN NON-VOLATILE MEMORY
CONTINUE n = n+1
YES IS n > 9?
NO
Figure 8-13. Trim Procedure
In this particular case, the MCU has been attached to a PCB and the entire assembly is undergoing nal test with automated test equipment. A separate signal or message is provided to the MCU operating under user provided software control. The MCU initiates a trim procedure as outlined in Figure 8-13 while the tester supplies a precision reference signal. If the intended bus frequency is near the maximum allowed for the device, it is recommended to trim using a reference divider value (RDIV setting) of twice the nal value. After the trim procedure is complete, the reference divider can be restored. This will prevent accidental overshoot of the maximum clock frequency.

9.1 Introduction
The analog comparator module (ACMP) provides a circuit for comparing two analog input voltages or for comparing one analog input voltage to an internal reference voltage. The comparator circuit is designed to operate across the full range of the supply voltage (rail-to-rail operation). All MC9S08DZ60 Series MCUs have two full function ACMPs in a 64-pin package. MCUs in the 48-pin package have two ACMPs, but the output of ACMP2 is not accessible. MCUs in the 32-pin package contain one full function ACMP. NOTE MC9S08DZ60 Series devices operate at a higher voltage range (2.7 V to 5.5 V) and do not include stop1 mode. Please ignore references to stop1.
9.1.1
ACMP Conguration Information
When using the bandgap reference voltage for input to ACMP+, the user must enable the bandgap buffer by setting BGBE =1 in SPMSC1 see Section 5.8.7, System Power Management Status and Control 1 Register (SPMSC1). For value of bandgap voltage reference see Section A.6, DC Characteristics.
BDC
BKP
PORT G
PORT F
PORT E
PORT D
PORT B
9.1.2
Features
The ACMP has the following features: Full rail to rail supply operation. Selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator output. Option to compare to xed internal bandgap reference voltage. Option to allow comparator output to be visible on a pin, ACMPxO.
9.1.3
Modes of Operation
This section denes the ACMP operation in wait, stop, and background debug modes.
9.1.3.1
ACMP in Wait Mode
The ACMP continues to run in wait mode if enabled before executing the appropriate instruction. Therefore, the ACMP can be used to bring the MCU out of wait mode if the ACMP interrupt is enabled (ACIE is set). For lowest possible current consumption, the ACMP should be disabled by software if not required as an interrupt source during wait mode.
9.1.3.2
ACMP in Stop Modes
The ACMP is disabled in all stop modes, regardless of the settings before executing the stop instruction. Therefore, the ACMP cannot be used as a wake up source from stop modes. During stop2 mode, the ACMP module is fully powered down. Upon wake-up from stop2 mode, the ACMP module is in the reset state. During stop3 mode, clocks to the ACMP module are halted. No registers are affected. In addition, the ACMP comparator circuit enters a low-power state. No compare operation occurs while in stop3. If stop3 is exited with a reset, the ACMP is put into its reset state. If stop3 is exited with an interrupt, the ACMP continues from the state it was in when stop3 was entered.
9.1.3.3
ACMP in Active Background Mode
When the microcontroller is in active background mode, the ACMP continues to operate normally.
9.1.4
Block Diagram
The block diagram for the analog comparator module is shown Figure 9-2.
Internal Bus Internal Reference ACBGS ACME Status & Control Register ACMOD ACIE ACF ACOPE set ACF ACMPx INTERRUPT REQUEST
ACMPx+ + Comparator
Interrupt Control
ACMPx-
ACMPxO
Figure 9-2. Analog Comparator (ACMP) Block Diagram
9.2
The ACMP has two analog input pins, ACMPx+ and ACMPx and one digital output pin ACMPxO. Each of these pins can accept an input voltage that varies across the full operating voltage range of the MCU. As shown in Figure 9-2, the ACMPx- pin is connected to the inverting input of the comparator, and the ACMPx+ pin is connected to the comparator non-inverting input if ACBGS is a 0. As shown in Figure 9-2, the ACMPxO pin can be enabled to drive an external pin. The signal properties of ACMP are shown in Table 9-1.
Table 9-1. Signal Properties
Signal ACMPxACMPx+ ACMPxO Function Inverting analog input to the ACMP. (Minus input) Non-inverting analog input to the ACMP. (Positive input) Digital output of the ACMP. I/O I I O
9.3
Memory Map/Register Denition
The ACMP includes one register: An 8-bit status and control register Refer to the direct-page register summary in the memory section of this document for the absolute address assignments for the ACMP register.This section refers to register and control bits only by their names and relative address offsets. Some MCUs may have more than one ACMP, so register names include placeholder characters (x) to identify which ACMP is being referenced.
Table 9-2. ACMP Register Summary
Name R ACMPxSC W ACME ACBGS ACF ACIE
7 6 5 4 3 2 1 0
ACO ACOPE ACMOD
9.3.1
ACMPx Status and Control Register (ACMPxSC)
ACMPxSC contains the status ag and control bits used to enable and congure the ACMP.
7 6 5 4 3 2 1 0
R ACME W Reset: 0 0 0 0 ACBGS ACF ACIE
ACO ACOPE 0 0 0 ACMOD 0
Figure 9-3. ACMPx Status and Control Register (ACMPxSC) Table 9-3. ACMPxSC Field Descriptions
Field 7 ACME 6 ACBGS Description Analog Comparator Module Enable. Enables the ACMP module. 0 ACMP not enabled 1 ACMP is enabled Analog Comparator Bandgap Select. Selects between the bandgap reference voltage or the ACMPx+ pin as the input to the non-inverting input of the analog comparator. 0 External pin ACMPx+ selected as non-inverting input to comparator 1 Internal reference select as non-inverting input to comparator Analog Comparator Flag. ACF is set when a compare event occurs. Compare events are dened by ACMOD. ACF is cleared by writing a one to it. 0 Compare event has not occurred 1 Compare event has occurred Analog Comparator Interrupt Enable. Enables the interrupt from the ACMP. When ACIE is set, an interrupt is asserted when ACF is set. 0 Interrupt disabled 1 Interrupt enabled
5 ACF
4 ACIE
Table 9-3. ACMPxSC Field Descriptions (continued)

Field 3 ACO 2 ACOPE Description Analog Comparator Output. Reading ACO returns the current value of the analog comparator output. ACO is reset to a 0 and reads as a 0 when the ACMP is disabled (ACME = 0). Analog Comparator Output Pin Enable. Enables the comparator output to be placed onto the external pin, ACMPxO. 0 Analog comparator output not available on ACMPxO 1 Analog comparator output is driven out on ACMPxO Analog Comparator Mode. ACMOD selects the type of compare event which sets ACF. 00 Encoding 0 Comparator output falling edge 01 Encoding 1 Comparator output rising edge 10 Encoding 2 Comparator output falling edge 11 Encoding 3 Comparator output rising or falling edge
1:0 ACMOD
9.4
The analog comparator can compare two analog input voltages applied to ACMPx+ and ACMPx, or it can compare an analog input voltage applied to ACMPx with an internal bandgap reference voltage. ACBGS selects between the bandgap reference voltage or the ACMPx+ pin as the input to the non-inverting input of the analog comparator. The comparator output is high when the non-inverting input is greater than the inverting input, and is low when the non-inverting input is less than the inverting input. ACMOD selects the condition that causes ACF to be set. ACF can be set on a rising edge of the comparator output, a falling edge of the comparator output, or a rising or a falling edge (toggle). The comparator output can be read directly through ACO. The comparator output can be driven onto the ACMPxO pin using ACOPE.

10.1 Introduction
The 12-bit analog-to-digital converter (ADC) is a successive approximation ADC designed for operation within an integrated microcontroller system-on-chip. NOTE MC9S08DZ60 Series devices operate at a higher voltage range (2.7 V to 5.5 V) and do not include stop1 mode. Please ignore references to stop1.
10.1.1
Analog Power and Ground Signal Names
References to VDDAD and VSSAD in this chapter correspond to signals VDDA and VSSA, respectively.
10.1.2
Channel Assignments
NOTE The ADC channel assignments for the MC9S08DZ60 Series devices are shown in Table 10-1. Reserved channels convert to an unknown value. This chapter shows bits for all S08ADC12V1 channels. MC9S08DZ60 Series MCUs do not use all of these channels. All bits corresponding to channels that are not available on a device are reserved.
Table 10-1. ADC Channel Assignment

ADCH 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 Channel AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 Input PTA0/ADP0/MCLK PTA1/ADP1/ACMP1+ PTA2/ADP2/ACMP1PPTA3/ADP3/ACMP1O PTA4/ADP4 PTA5/ADP5 PTA6/ADP6 PTA7/ADP7 PTB0/ADP8 PTB1/ADP9 PTB2/ADP10 PTB3/ADP11 PTB4/ADP12 PTB5/ADP13 PTB6/ADP14 ADCH 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 AD26 AD27 Reserved VREFH V Temperature Sensor1 Internal Bandgap2 Reserved VREFH V Channel AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 through AD25 Input PTB7/ADP15 PTC0/ADP16 PTC1/ADP17 PTC2/ADP18 PTC3/ADP19 PTC4/ADP20 PTC5/ADP21 PTC6/ADP22 PTC7/ADP23 Reserved
10.1.3
Alternate Clock
The ADC module is capable of performing conversions using the MCU bus clock, the bus clock divided by two, the local asynchronous clock (ADACK) within the module, or the alternate clock, ALTCLK. The alternate clock for the MC9S08DZ60 Series MCU devices is the external reference clock (MCGERCLK). The selected clock source must run at a frequency such that the ADC conversion clock (ADCK) runs at a frequency within its specied range (fADCK) after being divided down from the ALTCLK input as determined by the ADIV bits. ALTCLK is active while the MCU is in wait mode provided the conditions described above are met. This allows ALTCLK to be used as the conversion clock source for the ADC while the MCU is in wait mode. ALTCLK cannot be used as the ADC conversion clock source while the MCU is in either stop2 or stop3.
10.1.4
Hardware Trigger
The ADC hardware trigger, ADHWT, is the output from the real time counter (RTC). The RTC counter can be clocked by either MCGERCLK or a nominal 1 kHz clock source. The period of the RTC is determined by the input clock frequency, the RTCPS bits, and the RTCMOD register. When the ADC hardware trigger is enabled, a conversion is initiated upon an RTC counter overow. The RTC can be congured to cause a hardware trigger in MCU run, wait, and stop3.
10.1.5
Temperature Sensor
To use the on-chip temperature sensor, the user must perform the following: Congure ADC for long sample with a maximum of 1 MHz clock Convert the bandgap voltage reference channel (AD27) By converting the digital value of the bandgap voltage reference channel using the value of VBG the user can determine VDD. For value of bandgap voltage, see Section A.6, DC Characteristics. Convert the temperature sensor channel (AD26) By using the calculated value of VDD, convert the digital value of AD26 into a voltage, VTEMP Equation 10-1 provides an approximate transfer function of the temperature sensor.
Temp = 25 - ((VTEMP -VTEMP25) m) Eqn. 10-1
where: VTEMP is the voltage of the temperature sensor channel at the ambient temperature. VTEMP25 is the voltage of the temperature sensor channel at 25C. m is the hot or cold voltage versus temperature slope in V/C. For temperature calculations, use the VTEMP25 and m values from the ADC Electricals table. In application code, the user reads the temperature sensor channel, calculates VTEMP, and compares to VTEMP25. If VTEMP is greater than VTEMP25 the cold slope value is applied in Equation 10-1. If VTEMP is less than VTEMP25 the hot slope value is applied in Equation 10-1. To improve accuracy the user should calibrate the bandgap voltage reference and temperature sensor. Calibrating at 25C will improve accuracy to 4.5C. Calibration at three points, -40C, 25C, and 125C will improve accuracy to 2.5C. Once calibration has been completed, the user will need to calculate the slope for both hot and cold. In application code, the user would then calculate the temperature using Equation 10-1 as detailed above and then determine if the temperature is above or below 25C. Once determined if the temperature is above or below 25C, the user can recalculate the temperature using the hot or cold slope value obtained during calibration.
HCS08 CORE PORT A CPU BKGD/MS ANALOG COMPARATOR (ACMP1)

ACMP1O ACMP1ACMP1+
BDC
BKP
Figure 10-1. MC9S08DZ60 Block Diagram Emphasizing the ADC Module and Pins
PORT G
PORT F
PORT E
PORT D
PORT B
10.1.6
Features
Features of the ADC module include: Linear successive approximation algorithm with 12-bit resolution Up to 28 analog inputs Output formatted in 12-, 10-, or 8-bit right-justied unsigned format Single or continuous conversion (automatic return to idle after single conversion) Congurable sample time and conversion speed/power Conversion complete ag and interrupt Input clock selectable from up to four sources Operation in wait or stop3 modes for lower noise operation Asynchronous clock source for lower noise operation Selectable asynchronous hardware conversion trigger Automatic compare with interrupt for less-than, or greater-than or equal-to, programmable value Temperature sensor
10.1.7
ADC Module Block Diagram
Figure 10-2 provides a block diagram of the ADC module.
Compare true
ADCSC1
COCO AIEN
ADCCFG
ADLSMP
complete
ADTRG
ADICLK
ADLPC
ADCH
MODE
ADCO
ADIV
Async Clock Gen
ADACK MCU STOP ADHWT ADCK Clock Divide
Bus Clock
2 ALTCLK
Control Sequencer
initialize transfer convert sample abort
AD0
AIEN 1
Interrupt
ADVIN
SAR Converter
COCO 2
AD27
VREFH VREFL
Data Registers Sum
Compare true Compare Logic Value ACFGT
Compare Value Registers
ADCSC2
Figure 10-2. ADC Block Diagram
10.2
The ADC module supports up to 28 separate analog inputs. It also requires four supply/reference/ground connections.
Name AD27AD0 VREFH VREFL VDDAD VSSAD Function Analog Channel inputs High reference voltage Low reference voltage Analog power supply Analog ground
10.2.1
Analog Power (VDDAD)
The ADC analog portion uses VDDAD as its power connection. In some packages, VDDAD is connected internally to VDD. If externally available, connect the VDDAD pin to the same voltage potential as VDD. External ltering may be necessary to ensure clean VDDAD for good results.
10.2.2
Analog Ground (VSSAD)
The ADC analog portion uses VSSAD as its ground connection. In some packages, VSSAD is connected internally to VSS. If externally available, connect the VSSAD pin to the same voltage potential as VSS.
10.2.3
Voltage Reference High (VREFH)
VREFH is the high reference voltage for the converter. In some packages, VREFH is connected internally to VDDAD. If externally available, VREFH may be connected to the same potential as VDDAD or may be driven by an external source between the minimum VDDAD spec and the VDDAD potential (VREFH must never exceed VDDAD).
10.2.4
Voltage Reference Low (VREFL)
VREFL is the low-reference voltage for the converter. In some packages, VREFL is connected internally to VSSAD. If externally available, connect the VREFL pin to the same voltage potential as VSSAD.
10.2.5
Analog Channel Inputs (ADx)
The ADC module supports up to 28 separate analog inputs. An input is selected for conversion through the ADCH channel select bits.
10.3

Register Denition
Status and control register, ADCSC1 Status and control register, ADCSC2 Data result registers, ADCRH and ADCRL Compare value registers, ADCCVH and ADCCVL Conguration register, ADCCFG Pin control registers, APCTL1, APCTL2, APCTL3
These memory-mapped registers control and monitor operation of the ADC:
10.3.1
Status and Control Register 1 (ADCSC1)
This section describes the function of the ADC status and control register (ADCSC1). Writing ADCSC1 aborts the current conversion and initiates a new conversion (if the ADCH bits are equal to a value other than all 1s).
R W Reset:
COCO AIEN 0 0 ADCO 0 1 1 ADCH 1 1 1
Figure 10-3. Status and Control Register (ADCSC1) Table 10-3. ADCSC1 Field Descriptions
Field 7 COCO Description Conversion Complete Flag. The COCO ag is a read-only bit set each time a conversion is completed when the compare function is disabled (ACFE = 0). When the compare function is enabled (ACFE = 1), the COCO ag is set upon completion of a conversion only if the compare result is true. This bit is cleared when ADCSC1 is written or when ADCRL is read. 0 Conversion not completed 1 Conversion completed Interrupt Enable AIEN enables conversion complete interrupts. When COCO becomes set while AIEN is high, an interrupt is asserted. 0 Conversion complete interrupt disabled 1 Conversion complete interrupt enabled Continuous Conversion Enable. ADCO enables continuous conversions. 0 One conversion following a write to the ADCSC1 when software triggered operation is selected, or one conversion following assertion of ADHWT when hardware triggered operation is selected. 1 Continuous conversions initiated following a write to ADCSC1 when software triggered operation is selected. Continuous conversions are initiated by an ADHWT event when hardware triggered operation is selected. Input Channel Select. The ADCH bits form a 5-bit eld that selects one of the input channels. The input channels are detailed in Table 10-4. The successive approximation converter subsystem is turned off when the channel select bits are all set. This feature allows for explicit disabling of the ADC and isolation of the input channel from all sources. Terminating continuous conversions this way prevents an additional, single conversion from being performed. It is not necessary to set the channel select bits to all ones to place the ADC in a low-power state when continuous conversions are not enabled because the module automatically enters a low-power state when a conversion completes.
6 AIEN
5 ADCO
4:0 ADCH
Table 10-4. Input Channel Select

ADCH 0000001111 1000011011 11100 11101 11110 11111 Input Select AD015 AD1627 Reserved VREFH VREFL Module disabled
10.3.2
Status and Control Register 2 (ADCSC2)
The ADCSC2 register controls the compare function, conversion trigger, and conversion active of the ADC module.
7 6 5 4 3 2 1 0
Reset:
Figure 10-4. Status and Control Register 2 (ADCSC2) Table 10-5. ADCSC2 Register Field Descriptions
Field 7 ADACT Description Conversion Active. Indicates that a conversion is in progress. ADACT is set when a conversion is initiated and cleared when a conversion is completed or aborted. 0 Conversion not in progress 1 Conversion in progress Conversion Trigger Select. Selects the type of trigger used for initiating a conversion. Two types of triggers are selectable: software trigger and hardware trigger. When software trigger is selected, a conversion is initiated following a write to ADCSC1. When hardware trigger is selected, a conversion is initiated following the assertion of the ADHWT input. 0 Software trigger selected 1 Hardware trigger selected Compare Function Enable. Enables the compare function. 0 Compare function disabled 1 Compare function enabled Compare Function Greater Than Enable. Congures the compare function to trigger when the result of the conversion of the input being monitored is greater than or equal to the compare value. The compare function defaults to triggering when the result of the compare of the input being monitored is less than the compare value. 0 Compare triggers when input is less than compare value 1 Compare triggers when input is greater than or equal to compare value
6 ADTRG
5 ACFE 4 ACFGT
10.3.3
Data Result High Register (ADCRH)
In 12-bit operation, ADCRH contains the upper four bits of the result of a 12-bit conversion. In 10-bit mode, ADCRH contains the upper two bits of the result of a 10-bit conversion. When congured for 10-bit mode, ADR[11:10] are cleared. When congured for 8-bit mode, ADR[11:8] are cleared. In 12-bit and 10-bit mode, ADCRH is updated each time a conversion completes except when automatic compare is enabled and the compare condition is not met. When a compare event does occur, the value is the addition of the conversion result and the twos complement of the compare value. In 12-bit and 10-bit mode, reading ADCRH prevents the ADC from transferring subsequent conversion results into the result registers until ADCRL is read. If ADCRL is not read until after the next conversion is completed, the intermediate conversion result is lost. In 8-bit mode, there is no interlocking with ADCRL.
If the MODE bits are changed, any data in ADCRH becomes invalid.
7 6 5 4 3 2 1 0
R W Reset:
ADR11
ADR10
ADR9
ADR8
Figure 10-5. Data Result High Register (ADCRH)
10.3.4
Data Result Low Register (ADCRL)
ADCRL contains the lower eight bits of the result of a 12-bit or 10-bit conversion, and all eight bits of an 8-bit conversion. This register is updated each time a conversion completes except when automatic compare is enabled and the compare condition is not met. When a compare event does occur, the value is the addition of the conversion result and the twos complement of the compare value. In 12-bit and 10-bit mode, reading ADCRH prevents the ADC from transferring subsequent conversion results into the result registers until ADCRL is read. If ADCRL is not read until the after next conversion is completed, the intermediate conversion results are lost. In 8-bit mode, there is no interlocking with ADCRH. If the MODE bits are changed, any data in ADCRL becomes invalid.
7 6 5 4 3 2 1 0
R W Reset:
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
ADR0
Figure 10-6. Data Result Low Register (ADCRL)
10.3.5
Compare Value High Register (ADCCVH)
In 12-bit mode, the ADCCVH register holds the upper four bits of the 12-bit compare value. When the compare function is enabled, these bits are compared to the upper four bits of the result following a conversion in 12-bit mode.
7 6 5 4 3 2 1 0
R W Reset:
0 ADCV11 ADCV10 0 ADCV9 0 ADCV8 0
Figure 10-7. Compare Value High Register (ADCCVH)
In 10-bit mode, the ADCCVH register holds the upper two bits of the 10-bit compare value (ADCV[9:8]). These bits are compared to the upper two bits of the result following a conversion in 10-bit mode when the compare function is enabled. In 8-bit mode, ADCCVH is not used during compare.
10.3.6
Compare Value Low Register (ADCCVL)
This register holds the lower 8 bits of the 12-bit or 10-bit compare value or all 8 bits of the 8-bit compare value. When the compare function is enabled, bits ADCV[7:0] are compared to the lower 8 bits of the result following a conversion in 12-bit, 10-bit or 8-bit mode.
7 6 5 4 3 2 1 0
R ADCV7 W Reset: 0 0 0 0 0 0 0 0 ADCV6 ADCV5 ADCV4 ADCV3 ADCV2 ADCV1 ADCV0
Figure 10-8. Compare Value Low Register (ADCCVL)
10.3.7
Conguration Register (ADCCFG)
ADCCFG selects the mode of operation, clock source, clock divide, and congures for low power and long sample time.
7 6 5 4 3 2 1 0
R ADLPC W Reset: 0 0 0 0 0 0 0 0 ADIV ADLSMP MODE ADICLK
Figure 10-9. Conguration Register (ADCCFG) Table 10-6. ADCCFG Register Field Descriptions
Field 7 ADLPC Description Low-Power Conguration. ADLPC controls the speed and power conguration of the successive approximation converter. This optimizes power consumption when higher sample rates are not required. 0 High speed conguration 1 Low power conguration: The power is reduced at the expense of maximum clock speed. Clock Divide Select. ADIV selects the divide ratio used by the ADC to generate the internal clock ADCK. Table 10-7 shows the available clock congurations. Long Sample Time Conguration. ADLSMP selects between long and short sample time. This adjusts the sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion speed for lower impedance inputs. Longer sample times can also be used to lower overall power consumption when continuous conversions are enabled if high conversion rates are not required. 0 Short sample time 1 Long sample time
6:5 ADIV 4 ADLSMP
Table 10-6. ADCCFG Register Field Descriptions (continued)

Field 3:2 MODE 1:0 ADICLK Description Conversion Mode Selection. MODE bits are used to select between 12-, 10-, or 8-bit operation. See Table 10-8. Input Clock Select. ADICLK bits select the input clock source to generate the internal clock ADCK. See Table 10-9.
Table 10-7. Clock Divide Select

ADIV 00 01 10 11 Divide Ratio 1 2 4 8 Clock Rate Input clock Input clock 2 Input clock 4 Input clock 8
Table 10-8. Conversion Modes

MODE 00 01 10 11 Mode Description 8-bit conversion (N=8) 12-bit conversion (N=12) 10-bit conversion (N=10) Reserved
Table 10-9. Input Clock Select

ADICLK 00 01 10 11 Bus clock Bus clock divided by 2 Alternate clock (ALTCLK) Asynchronous clock (ADACK) Selected Clock Source
10.3.8
Pin Control 1 Register (APCTL1)
The pin control registers disable the I/O port control of MCU pins used as analog inputs. APCTL1 is
used to control the pins associated with channels 07 of the ADC module.
7 6 5 4 3 2 1 0
R ADPC7 W Reset: 0 0 0 0 0 0 0 0 ADPC6 ADPC5 ADPC4 ADPC3 ADPC2 ADPC1 ADPC0
Figure 10-10. Pin Control 1 Register (APCTL1) Table 10-10. APCTL1 Register Field Descriptions
Field 7 ADPC7 6 ADPC6 5 ADPC5 4 ADPC4 3 ADPC3 2 ADPC2 1 ADPC1 0 ADPC0 Description ADC Pin Control 7. ADPC7 controls the pin associated with channel AD7. 0 AD7 pin I/O control enabled 1 AD7 pin I/O control disabled ADC Pin Control 6. ADPC6 controls the pin associated with channel AD6. 0 AD6 pin I/O control enabled 1 AD6 pin I/O control disabled ADC Pin Control 5. ADPC5 controls the pin associated with channel AD5. 0 AD5 pin I/O control enabled 1 AD5 pin I/O control disabled ADC Pin Control 4. ADPC4 controls the pin associated with channel AD4. 0 AD4 pin I/O control enabled 1 AD4 pin I/O control disabled ADC Pin Control 3. ADPC3 controls the pin associated with channel AD3. 0 AD3 pin I/O control enabled 1 AD3 pin I/O control disabled ADC Pin Control 2. ADPC2 controls the pin associated with channel AD2. 0 AD2 pin I/O control enabled 1 AD2 pin I/O control disabled ADC Pin Control 1. ADPC1 controls the pin associated with channel AD1. 0 AD1 pin I/O control enabled 1 AD1 pin I/O control disabled ADC Pin Control 0. ADPC0 controls the pin associated with channel AD0. 0 AD0 pin I/O control enabled 1 AD0 pin I/O control disabled
10.3.9
Pin Control 2 Register (APCTL2)
APCTL2 controls channels 815 of the ADC module.

7 6 5 4 3 2 1 0
Figure 10-11. Pin Control 2 Register (APCTL2)

Table 10-11. APCTL2 Register Field Descriptions

10.3.10 Pin Control 3 Register (APCTL3)

APCTL3 controls channels 1623 of the ADC module.
7 6 5 4 3 2 1 0
Figure 10-12. Pin Control 3 Register (APCTL3)
Table 10-12. APCTL3 Register Field Descriptions

10.4
The ADC module is disabled during reset or when the ADCH bits are all high. The module is idle when a conversion has completed and another conversion has not been initiated. When idle, the module is in its lowest power state. The ADC can perform an analog-to-digital conversion on any of the software selectable channels. In 12-bit and 10-bit mode, the selected channel voltage is converted by a successive approximation algorithm into a 12-bit digital result. In 8-bit mode, the selected channel voltage is converted by a successive approximation algorithm into a 9-bit digital result. When the conversion is completed, the result is placed in the data registers (ADCRH and ADCRL). In 10-bit mode, the result is rounded to 10 bits and placed in the data registers (ADCRH and ADCRL). In 8-bit mode, the result is rounded to 8 bits and placed in ADCRL. The conversion complete ag (COCO) is then set and an interrupt is generated if the conversion complete interrupt has been enabled (AIEN = 1). The ADC module has the capability of automatically comparing the result of a conversion with the contents of its compare registers. The compare function is enabled by setting the ACFE bit and operates with any of the conversion modes and congurations.
10.4.1
Clock Select and Divide Control
One of four clock sources can be selected as the clock source for the ADC module. This clock source is then divided by a congurable value to generate the input clock to the converter (ADCK). The clock is selected from one of the following sources by means of the ADICLK bits. The bus clock, which is equal to the frequency at which software is executed. This is the default selection following reset. The bus clock divided by two. For higher bus clock rates, this allows a maximum divide by 16 of the bus clock. ALTCLK, as dened for this MCU (See module section introduction). The asynchronous clock (ADACK). This clock is generated from a clock source within the ADC module. When selected as the clock source, this clock remains active while the MCU is in wait or stop3 mode and allows conversions in these modes for lower noise operation. Whichever clock is selected, its frequency must fall within the specied frequency range for ADCK. If the available clocks are too slow, the ADC do not perform according to specications. If the available clocks are too fast, the clock must be divided to the appropriate frequency. This divider is specied by the ADIV bits and can be divide-by 1, 2, 4, or 8.
10.4.2
Input Select and Pin Control
The pin control registers (APCTL3, APCTL2, and APCTL1) disable the I/O port control of the pins used as analog inputs.When a pin control register bit is set, the following conditions are forced for the associated MCU pin: The output buffer is forced to its high impedance state. The input buffer is disabled. A read of the I/O port returns a zero for any pin with its input buffer disabled. The pullup is disabled.
10.4.3
Hardware Trigger
The ADC module has a selectable asynchronous hardware conversion trigger, ADHWT, that is enabled when the ADTRG bit is set. This source is not available on all MCUs. Consult the module introduction for information on the ADHWT source specic to this MCU. When ADHWT source is available and hardware trigger is enabled (ADTRG=1), a conversion is initiated on the rising edge of ADHWT. If a conversion is in progress when a rising edge occurs, the rising edge is ignored. In continuous convert conguration, only the initial rising edge to launch continuous conversions is observed. The hardware trigger function operates in conjunction with any of the conversion modes and congurations.
10.4.4
Conversion Control
Conversions can be performed in 12-bit mode, 10-bit mode, or 8-bit mode as determined by the MODE bits. Conversions can be initiated by a software or hardware trigger. In addition, the ADC module can be
congured for low power operation, long sample time, continuous conversion, and automatic compare of the conversion result to a software determined compare value.
10.4.4.1
Initiating Conversions
A conversion is initiated: Following a write to ADCSC1 (with ADCH bits not all 1s) if software triggered operation is selected. Following a hardware trigger (ADHWT) event if hardware triggered operation is selected. Following the transfer of the result to the data registers when continuous conversion is enabled. If continuous conversions are enabled, a new conversion is automatically initiated after the completion of the current conversion. In software triggered operation, continuous conversions begin after ADCSC1 is written and continue until aborted. In hardware triggered operation, continuous conversions begin after a hardware trigger event and continue until aborted.
10.4.4.2
Completing Conversions
A conversion is completed when the result of the conversion is transferred into the data result registers, ADCRH and ADCRL. This is indicated by the setting of COCO. An interrupt is generated if AIEN is high at the time that COCO is set. A blocking mechanism prevents a new result from overwriting previous data in ADCRH and ADCRL if the previous data is in the process of being read while in 12-bit or 10-bit MODE (the ADCRH register has been read but the ADCRL register has not). When blocking is active, the data transfer is blocked, COCO is not set, and the new result is lost. In the case of single conversions with the compare function enabled and the compare condition false, blocking has no effect and ADC operation is terminated. In all other cases of operation, when a data transfer is blocked, another conversion is initiated regardless of the state of ADCO (single or continuous conversions enabled). If single conversions are enabled, the blocking mechanism could result in several discarded conversions and excess power consumption. To avoid this issue, the data registers must not be read after initiating a single conversion until the conversion completes.
10.4.4.3

Aborting Conversions
Any conversion in progress is aborted when: A write to ADCSC1 occurs (the current conversion will be aborted and a new conversion will be initiated, if ADCH are not all 1s). A write to ADCSC2, ADCCFG, ADCCVH, or ADCCVL occurs. This indicates a mode of operation change has occurred and the current conversion is therefore invalid. The MCU is reset. The MCU enters stop mode with ADACK not enabled.
When a conversion is aborted, the contents of the data registers, ADCRH and ADCRL, are not altered. However, they continue to be the values transferred after the completion of the last successful conversion. If the conversion was aborted by a reset, ADCRH and ADCRL return to their reset states.
10.4.4.4
Power Control
The ADC module remains in its idle state until a conversion is initiated. If ADACK is selected as the conversion clock source, the ADACK clock generator is also enabled. Power consumption when active can be reduced by setting ADLPC. This results in a lower maximum value for fADCK (see the electrical specications).
10.4.4.5
Sample Time and Total Conversion Time
The total conversion time depends on the sample time (as determined by ADLSMP), the MCU bus frequency, the conversion mode (8-bit, 10-bit or 12-bit), and the frequency of the conversion clock (fADCK). After the module becomes active, sampling of the input begins. ADLSMP selects between short (3.5 ADCK cycles) and long (23.5 ADCK cycles) sample times.When sampling is complete, the converter is isolated from the input channel and a successive approximation algorithm is performed to determine the digital value of the analog signal. The result of the conversion is transferred to ADCRH and ADCRL upon completion of the conversion algorithm. If the bus frequency is less than the fADCK frequency, precise sample time for continuous conversions cannot be guaranteed when short sample is enabled (ADLSMP=0). If the bus frequency is less than 1/11th of the fADCK frequency, precise sample time for continuous conversions cannot be guaranteed when long sample is enabled (ADLSMP=1). The maximum total conversion time for different conditions is summarized in Table 10-13.
Table 10-13. Total Conversion Time vs. Control Conditions
Conversion Type Single or rst continuous 8-bit Single or rst continuous 10-bit or 12-bit Single or rst continuous 8-bit Single or rst continuous 10-bit or 12-bit Single or rst continuous 8-bit Single or rst continuous 10-bit or 12-bit Single or rst continuous 8-bit Single or rst continuous 10-bit or 12-bit Subsequent continuous 8-bit; fBUS > fADCK Subsequent continuous 10-bit or 12-bit; fBUS > fADCK Subsequent continuous 8-bit; fBUS > fADCK/11 ADICLK 0x, 10 0x, 10 0x, 10 0x, 10 11 11 11 11 xx xx xx ADLSMP 0 0 1 1 0 0 1 1 0 0 1 Max Total Conversion Time 20 ADCK cycles + 5 bus clock cycles 23 ADCK cycles + 5 bus clock cycles 40 ADCK cycles + 5 bus clock cycles 43 ADCK cycles + 5 bus clock cycles 5 s + 20 ADCK + 5 bus clock cycles 5 s + 23 ADCK + 5 bus clock cycles 5 s + 40 ADCK + 5 bus clock cycles 5 s + 43 ADCK + 5 bus clock cycles 17 ADCK cycles 20 ADCK cycles 37 ADCK cycles
Table 10-13. Total Conversion Time vs. Control Conditions

Conversion Type Subsequent continuous 10-bit or 12-bit; fBUS > fADCK/11 ADICLK xx ADLSMP 1 Max Total Conversion Time 40 ADCK cycles
The maximum total conversion time is determined by the clock source chosen and the divide ratio selected. The clock source is selectable by the ADICLK bits, and the divide ratio is specied by the ADIV bits. For example, in 10-bit mode, with the bus clock selected as the input clock source, the input clock divide-by-1 ratio selected, and a bus frequency of 8 MHz, then the conversion time for a single conversion is:
Conversion time = 23 ADCK Cyc 8 MHz/1 + 5 bus Cyc 8 MHz = 3.5 ms
Number of bus cycles = 3.5 ms x 8 MHz = 28 cycles
NOTE The ADCK frequency must be between fADCK minimum and fADCK maximum to meet ADC specications.
10.4.5
Automatic Compare Function
The compare function can be congured to check for an upper or lower limit. After the input is sampled and converted, the result is added to the twos complement of the compare value (ADCCVH and ADCCVL). When comparing to an upper limit (ACFGT = 1), if the result is greater-than or equal-to the compare value, COCO is set. When comparing to a lower limit (ACFGT = 0), if the result is less than the compare value, COCO is set. The value generated by the addition of the conversion result and the twos complement of the compare value is transferred to ADCRH and ADCRL. Upon completion of a conversion while the compare function is enabled, if the compare condition is not true, COCO is not set and no data is transferred to the result registers. An ADC interrupt is generated upon the setting of COCO if the ADC interrupt is enabled (AIEN = 1). NOTE The compare function can monitor the voltage on a channel while the MCU is in wait or stop3 mode. The ADC interrupt wakes the MCU when the compare condition is met.
10.4.6
MCU Wait Mode Operation
Wait mode is a lower power-consumption standby mode from which recovery is fast because the clock sources remain active. If a conversion is in progress when the MCU enters wait mode, it continues until completion. Conversions can be initiated while the MCU is in wait mode by means of the hardware trigger or if continuous conversions are enabled. The bus clock, bus clock divided by two, and ADACK are available as conversion clock sources while in wait mode. The use of ALTCLK as the conversion clock source in wait is dependent on the denition of
ALTCLK for this MCU. Consult the module introduction for information on ALTCLK specic to this MCU. A conversion complete event sets the COCO and generates an ADC interrupt to wake the MCU from wait mode if the ADC interrupt is enabled (AIEN = 1).
10.4.7
MCU Stop3 Mode Operation
Stop mode is a low power-consumption standby mode during which most or all clock sources on the MCU are disabled.
10.4.7.1
Stop3 Mode With ADACK Disabled
If the asynchronous clock, ADACK, is not selected as the conversion clock, executing a stop instruction aborts the current conversion and places the ADC in its idle state. The contents of ADCRH and ADCRL are unaffected by stop3 mode. After exiting from stop3 mode, a software or hardware trigger is required to resume conversions.
10.4.7.2
Stop3 Mode With ADACK Enabled
If ADACK is selected as the conversion clock, the ADC continues operation during stop3 mode. For guaranteed ADC operation, the MCUs voltage regulator must remain active during stop3 mode. Consult the module introduction for conguration information for this MCU. If a conversion is in progress when the MCU enters stop3 mode, it continues until completion. Conversions can be initiated while the MCU is in stop3 mode by means of the hardware trigger or if continuous conversions are enabled. A conversion complete event sets the COCO and generates an ADC interrupt to wake the MCU from stop3 mode if the ADC interrupt is enabled (AIEN = 1). NOTE The ADC module can wake the system from low-power stop and cause the MCU to begin consuming run-level currents without generating a system level interrupt. To prevent this scenario, software should ensure the data transfer blocking mechanism (discussed in Section 10.4.4.2, Completing Conversions) is cleared when entering stop3 and continuing ADC conversions.
10.4.8
MCU Stop2 Mode Operation
The ADC module is automatically disabled when the MCU enters stop2 mode. All module registers contain their reset values following exit from stop2. Therefore, the module must be re-enabled and re-congured following exit from stop2.
10.5
Initialization Information
This section gives an example that provides some basic direction on how to initialize and congure the ADC module. You can congure the module for 8-, 10-, or 12-bit resolution, single or continuous conversion, and a polled or interrupt approach, among many other options. Refer to Table 10-7, Table 10-8, and Table 10-9 for information used in this example. NOTE Hexadecimal values designated by a preceding 0x, binary values designated by a preceding %, and decimal values have no preceding character.
10.5.1
10.5.1.1
ADC Module Initialization Example

Initialization Sequence
Before the ADC module can be used to complete conversions, an initialization procedure must be performed. A typical sequence is as follows: 1. Update the conguration register (ADCCFG) to select the input clock source and the divide ratio used to generate the internal clock, ADCK. This register is also used for selecting sample time and low-power conguration. 2. Update status and control register 2 (ADCSC2) to select the conversion trigger (hardware or software) and compare function options, if enabled. 3. Update status and control register 1 (ADCSC1) to select whether conversions will be continuous or completed only once, and to enable or disable conversion complete interrupts. The input channel on which conversions will be performed is also selected here.
10.5.1.2
Pseudo-Code Example
In this example, the ADC module is set up with interrupts enabled to perform a single 10-bit conversion at low power with a long sample time on input channel 1, where the internal ADCK clock is derived from the bus clock divided by 1. ADCCFG = 0x98 (%10011000)
Bit Bit Bit Bit Bit 7 6:5 4 3:2 1:0 ADLPC ADIV ADLSMP MODE ADICLK 1 00 1 10 00 Configures for low power (lowers maximum clock speed) Sets the ADCK to the input clock 1 Configures for long sample time Sets mode at 10-bit conversions Selects bus clock as input clock source
ADCSC2 = 0x00 (%00000000)

Bit Bit Bit Bit Bit Bit 7 6 5 4 3:2 1:0 ADACT ADTRG ACFE ACFGT 0 0 0 0 00 00 Flag indicates if a conversion is in progress Software trigger selected Compare function disabled Not used in this example Reserved, always reads zero Reserved for Freescales internal use; always write zero
ADCSC1 = 0x41 (%01000001)

Bit Bit Bit Bit 7 6 5 4:0 COCO AIEN ADCO ADCH 0 1 0 00001 Read-only flag which is set when a conversion completes Conversion complete interrupt enabled One conversion only (continuous conversions disabled) Input channel 1 selected as ADC input channel
ADCRH/L = 0xxx
Holds results of conversion. Read high byte (ADCRH) before low byte (ADCRL) so that conversion data cannot be overwritten with data from the next conversion.
ADCCVH/L = 0xxx
Holds compare value when compare function enabled
APCTL1=0x02
AD1 pin I/O control disabled. All other AD pins remain general purpose I/O pins
APCTL2=0x00
All other AD pins remain general purpose I/O pins
Reset
Initialize ADC ADCCFG = 0x98 ADCSC2 = 0x00 ADCSC1 = 0x41
Check COCO=1? Yes Read ADCRH Then ADCRL To Clear COCO Bit
No
Continue
Figure 10-13. Initialization Flowchart for Example
10.6
Application Information
This section contains information for using the ADC module in applications. The ADC has been designed to be integrated into a microcontroller for use in embedded control applications requiring an A/D converter.
10.6.1
External Pins and Routing
The following sections discuss the external pins associated with the ADC module and how they should be used for best results.
10.6.1.1
Analog Supply Pins
The ADC module has analog power and ground supplies (VDDAD and VSSAD) available as separate pins on some devices. VSSAD is shared on the same pin as the MCU digital VSS on some devices. On other devices, VSSAD and VDDAD are shared with the MCU digital supply pins. In these cases, there are separate pads for the analog supplies bonded to the same pin as the corresponding digital supply so that some degree of isolation between the supplies is maintained. When available on a separate pin, both VDDAD and VSSAD must be connected to the same voltage potential as their corresponding MCU digital supply (VDD and VSS) and must be routed carefully for maximum noise immunity and bypass capacitors placed as near as possible to the package. If separate power supplies are used for analog and digital power, the ground connection between these supplies must be at the VSSAD pin. This should be the only ground connection between these supplies if possible. The VSSAD pin makes a good single point ground location.
10.6.1.2
Analog Reference Pins
In addition to the analog supplies, the ADC module has connections for two reference voltage inputs. The high reference is VREFH, which may be shared on the same pin as VDDAD on some devices. The low reference is VREFL, which may be shared on the same pin as VSSAD on some devices. When available on a separate pin, VREFH may be connected to the same potential as VDDAD, or may be driven by an external source between the minimum VDDAD spec and the VDDAD potential (VREFH must never exceed VDDAD). When available on a separate pin, VREFL must be connected to the same voltage potential as VSSAD. VREFH and VREFL must be routed carefully for maximum noise immunity and bypass capacitors placed as near as possible to the package. AC current in the form of current spikes required to supply charge to the capacitor array at each successive approximation step is drawn through the VREFH and VREFL loop. The best external component to meet this current demand is a 0.1 F capacitor with good high frequency characteristics. This capacitor is connected between VREFH and VREFL and must be placed as near as possible to the package pins. Resistance in the path is not recommended because the current causes a voltage drop that could result in conversion errors. Inductance in this path must be minimum (parasitic only).
10.6.1.3
Analog Input Pins
The external analog inputs are typically shared with digital I/O pins on MCU devices. The pin I/O control is disabled by setting the appropriate control bit in one of the pin control registers. Conversions can be performed on inputs without the associated pin control register bit set. It is recommended that the pin control register bit always be set when using a pin as an analog input. This avoids problems with contention because the output buffer is in its high impedance state and the pullup is disabled. Also, the input buffer draws DC current when its input is not at VDD or VSS. Setting the pin control register bits for all pins used as analog inputs should be done to achieve lowest operating current. Empirical data shows that capacitors on the analog inputs improve performance in the presence of noise or when the source impedance is high. Use of 0.01 F capacitors with good high-frequency characteristics is sufcient. These capacitors are not necessary in all cases, but when used they must be placed as near as possible to the package pins and be referenced to VSSA. For proper conversion, the input voltage must fall between VREFH and VREFL. If the input is equal to or exceeds VREFH, the converter circuit converts the signal to 0xFFF (full scale 12-bit representation), 0x3FF (full scale 10-bit representation) or 0xFF (full scale 8-bit representation). If the input is equal to or less than VREFL, the converter circuit converts it to 0x000. Input voltages between VREFH and VREFL are straight-line linear conversions. There is a brief current associated with VREFL when the sampling capacitor is charging. The input is sampled for 3.5 cycles of the ADCK source when ADLSMP is low, or 23.5 cycles when ADLSMP is high. For minimal loss of accuracy due to current injection, pins adjacent to the analog input pins should not be transitioning during conversions.
10.6.2
Sources of Error
Several sources of error exist for A/D conversions. These are discussed in the following sections.
10.6.2.1
Sampling Error
For proper conversions, the input must be sampled long enough to achieve the proper accuracy. Given the maximum input resistance of approximately 7k and input capacitance of approximately 5.5 pF, sampling to within 1/4LSB (at 12-bit resolution) can be achieved within the minimum sample window (3.5 cycles @ 8 MHz maximum ADCK frequency) provided the resistance of the external analog source (RAS) is kept below 2 k. Higher source resistances or higher-accuracy sampling is possible by setting ADLSMP (to increase the sample window to 23.5 cycles) or decreasing ADCK frequency to increase sample time.
10.6.2.2
Pin Leakage Error
Leakage on the I/O pins can cause conversion error if the external analog source resistance (RAS) is high. If this error cannot be tolerated by the application, keep RAS lower than VDDAD / (2N*ILEAK) for less than 1/4LSB leakage error (N = 8 in 8-bit, 10 in 10-bit or 12 in 12-bit mode).
10.6.2.3
Noise-Induced Errors
System noise that occurs during the sample or conversion process can affect the accuracy of the conversion. The ADC accuracy numbers are guaranteed as specied only if the following conditions are met: There is a 0.1 F low-ESR capacitor from VREFH to VREFL. There is a 0.1 F low-ESR capacitor from VDDAD to VSSAD. If inductive isolation is used from the primary supply, an additional 1 F capacitor is placed from VDDAD to VSSAD. VSSAD (and VREFL, if connected) is connected to VSS at a quiet point in the ground plane. Operate the MCU in wait or stop3 mode before initiating (hardware triggered conversions) or immediately after initiating (hardware or software triggered conversions) the ADC conversion. For software triggered conversions, immediately follow the write to ADCSC1 with a wait instruction or stop instruction. For stop3 mode operation, select ADACK as the clock source. Operation in stop3 reduces VDD noise but increases effective conversion time due to stop recovery. There is no I/O switching, input or output, on the MCU during the conversion. There are some situations where external system activity causes radiated or conducted noise emissions or excessive VDD noise is coupled into the ADC. In these situations, or when the MCU cannot be placed in wait or stop3 or I/O activity cannot be halted, these recommended actions may reduce the effect of noise on the accuracy: Place a 0.01 F capacitor (CAS) on the selected input channel to VREFL or VSSAD (this improves noise issues, but affects the sample rate based on the external analog source resistance). Average the result by converting the analog input many times in succession and dividing the sum of the results. Four samples are required to eliminate the effect of a 1LSB, one-time error. Reduce the effect of synchronous noise by operating off the asynchronous clock (ADACK) and averaging. Noise that is synchronous to ADCK cannot be averaged out.
10.6.2.4
Code Width and Quantization Error
The ADC quantizes the ideal straight-line transfer function into 4096 steps (in 12-bit mode). Each step ideally has the same height (1 code) and width. The width is dened as the delta between the transition points to one code and the next. The ideal code width for an N bit converter (in this case N can be 8, 10 or 12), dened as 1LSB, is:
1 lsb = (VREFH - VREFL) / 2N Eqn. 10-2
There is an inherent quantization error due to the digitization of the result. For 8-bit or 10-bit conversions the code transitions when the voltage is at the midpoint between the points where the straight line transfer function is exactly represented by the actual transfer function. Therefore, the quantization error will be 1/2 lsb in 8- or 10-bit mode. As a consequence, however, the code width of the rst (0x000) conversion is only 1/2 lsb and the code width of the last (0xFF or 0x3FF) is 1.5 lsb.
For 12-bit conversions the code transitions only after the full code width is present, so the quantization error is 1 lsb to 0 lsb and the code width of each step is 1 lsb.
10.6.2.5
Linearity Errors
The ADC may also exhibit non-linearity of several forms. Every effort has been made to reduce these errors but the system should be aware of them because they affect overall accuracy. These errors are: Zero-scale error (EZS) (sometimes called offset) This error is dened as the difference between the actual code width of the rst conversion and the ideal code width (1/2 lsb in 8-bit or 10-bit modes and 1 lsb in 12-bit mode). If the rst conversion is 0x001, the difference between the actual 0x001 code width and its ideal (1 lsb) is used. Full-scale error (EFS) This error is dened as the difference between the actual code width of the last conversion and the ideal code width (1.5 lsb in 8-bit or 10-bit modes and 1LSB in 12-bit mode). If the last conversion is 0x3FE, the difference between the actual 0x3FE code width and its ideal (1LSB) is used. Differential non-linearity (DNL) This error is dened as the worst-case difference between the actual code width and the ideal code width for all conversions. Integral non-linearity (INL) This error is dened as the highest-value the (absolute value of the) running sum of DNL achieves. More simply, this is the worst-case difference of the actual transition voltage to a given code and its corresponding ideal transition voltage, for all codes. Total unadjusted error (TUE) This error is dened as the difference between the actual transfer function and the ideal straight-line transfer function and includes all forms of error.
10.6.2.6
Code Jitter, Non-Monotonicity, and Missing Codes
Analog-to-digital converters are susceptible to three special forms of error. These are code jitter, non-monotonicity, and missing codes. Code jitter is when, at certain points, a given input voltage converts to one of two values when sampled repeatedly. Ideally, when the input voltage is innitesimally smaller than the transition voltage, the converter yields the lower code (and vice-versa). However, even small amounts of system noise can cause the converter to be indeterminate (between two codes) for a range of input voltages around the transition voltage. This range is normally around 1/2lsb in 8-bit or 10-bit mode, or around 2 lsb in 12-bit mode, and increases with noise. This error may be reduced by repeatedly sampling the input and averaging the result. Additionally the techniques discussed in Section 10.6.2.3 reduces this error. Non-monotonicity is dened as when, except for code jitter, the converter converts to a lower code for a higher input voltage. Missing codes are those values never converted for any input value. In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and have no missing codes.

11.1 Introduction
The inter-integrated circuit (IIC) provides a method of communication between a number of devices. The interface is designed to operate up to 100 kbps with maximum bus loading and timing. The device is capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. The maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pF. All MC9S08DZ60 Series MCUs feature the IIC, as shown in the following block diagram. NOTE Drive strength must be disabled (DSE=0) for the IIC pins when using the IIC module for correct operation.
BDC
BKP
PORT G
PORT F
PORT E
PORT D
PORT B
11.1.1
Features
The IIC includes these distinctive features: Compatible with IIC bus standard Multi-master operation Software programmable for one of 64 different serial clock frequencies Software selectable acknowledge bit Interrupt driven byte-by-byte data transfer Arbitration lost interrupt with automatic mode switching from master to slave Calling address identication interrupt Start and stop signal generation/detection Repeated start signal generation Acknowledge bit generation/detection Bus busy detection General call recognition 10-bit address extension
11.1.2
Modes of Operation
A brief description of the IIC in the various MCU modes is given here. Run mode This is the basic mode of operation. To conserve power in this mode, disable the module. Wait mode The module continues to operate while the MCU is in wait mode and can provide a wake-up interrupt. Stop mode The IIC is inactive in stop3 mode for reduced power consumption. The stop instruction does not affect IIC register states. Stop2 resets the register contents.
11.1.3
Block Diagram
Address Interrupt ADDR_DECODE DATA_MUX Data Bus
Figure 11-2 is a block diagram of the IIC.
CTRL_REG
FREQ_REG
ADDR_REG
STATUS_REG
DATA_REG
Input Sync Start Stop Arbitration Control Clock Control In/Out Data Shift Register
Address Compare
SCL
SDA
Figure 11-2. IIC Functional Block Diagram
11.2
This section describes each user-accessible pin signal.
11.2.1
SCL Serial Clock Line
The bidirectional SCL is the serial clock line of the IIC system.
11.2.2
SDA Serial Data Line
The bidirectional SDA is the serial data line of the IIC system.
11.3
Register Denition
This section consists of the IIC register descriptions in address order.

Refer to the direct-page register summary in the memory chapter of this document for the absolute address assignments for all IIC registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header le is used to translate these names into the appropriate absolute addresses.
11.3.1
IIC Address Register (IICA)

7 6 5 4 3 2 1 0
R AD7 W Reset 0 0 0 0 0 0 0 AD6 AD5 AD4 AD3 AD2 AD1
Figure 11-3. IIC Address Register (IICA) Table 11-1. IICA Field Descriptions
Field 71 AD[7:1] Description Slave Address. The AD[7:1] eld contains the slave address to be used by the IIC module. This eld is used on the 7-bit address scheme and the lower seven bits of the 10-bit address scheme.
11.3.2
IIC Frequency Divider Register (IICF)

7 6 5 4 3 2 1 0
R MULT W Reset 0 0 0 0 0 0 0 0 ICR
Figure 11-4. IIC Frequency Divider Register (IICF)
Table 11-2. IICF Field Descriptions

Field 76 MULT Description IIC Multiplier Factor. The MULT bits dene the multiplier factor, mul. This factor, along with the SCL divider, generates the IIC baud rate. The multiplier factor mul as dened by the MULT bits is provided below. 00 mul = 01 01 mul = 02 10 mul = 04 11 Reserved IIC Clock Rate. The ICR bits are used to prescale the bus clock for bit rate selection. These bits and the MULT bits determine the IIC baud rate, the SDA hold time, the SCL Start hold time, and the SCL Stop hold time. Table 11-4 provides the SCL divider and hold values for corresponding values of the ICR. The SCL divider multiplied by multiplier factor mul generates IIC baud rate. bus speed (Hz) IIC baud rate = -------------------------------------------mul SCLdivider
50 ICR
Eqn. 11-1
SDA hold time is the delay from the falling edge of SCL (IIC clock) to the changing of SDA (IIC data). SDA hold time = bus period (s) mul SDA hold value
Eqn. 11-2
SCL start hold time is the delay from the falling edge of SDA (IIC data) while SCL is high (Start condition) to the falling edge of SCL (IIC clock). SCL Start hold time = bus period (s) mul SCL Start hold value SCL stop hold time is the delay from the rising edge of SCL (IIC clock) to the rising edge of SDA SDA (IIC data) while SCL is high (Stop condition). SCL Stop hold time = bus period (s) mul SCL Stop hold value
Eqn. 11-3
Eqn. 11-4
For example, if the bus speed is 8 MHz, the table below shows the possible hold time values with different ICR and MULT selections to achieve an IIC baud rate of 100kbps.
Table 11-3. Hold Time Values for 8 MHz Bus Speed
Hold Times (s) MULT ICR SDA 0x2 0x1 0x1 0x0 0x0 0x00 0x07 0x0B 0x14 0x18 3.500 2.500 2.250 2.125 1.125 SCL Start 3.000 4.000 4.000 4.250 4.750 SCL Stop 5.500 5.250 5.250 5.125 5.125
Table 11-4. IIC Divider and Hold Values

ICR (hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F SCL Divider 20 22 24 26 28 30 34 40 28 32 36 40 44 48 56 68 48 56 64 72 80 88 104 128 80 96 112 128 144 160 192 240 SDA Hold Value 7 7 8 8 9 9 10 10 7 7 9 9 11 11 13 13 9 9 13 13 17 17 21 21 9 9 17 17 25 25 33 33 SCL Hold (Start) Value 6 7 8 9 10 11 13 16 10 12 14 16 18 20 24 30 18 22 26 30 34 38 46 58 38 46 54 62 70 78 94 118 SDA Hold (Stop) Value 11 12 13 14 15 16 18 21 15 17 19 21 23 25 29 35 25 29 33 37 41 45 53 65 41 49 57 65 73 81 97 121 ICR (hex) 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F SCL Divider 160 192 224 256 288 320 384 480 320 384 448 512 576 640 768 960 640 768 896 1024 1152 1280 1536 1920 1280 1536 1792 2048 2304 2560 3072 3840 SDA Hold Value 17 17 33 33 49 49 65 65 33 33 65 65 97 97 129 129 65 65 129 129 193 193 257 257 129 129 257 257 385 385 513 513 SCL Hold (Start) Value 78 94 110 126 142 158 190 238 158 190 222 254 286 318 382 478 318 382 446 510 574 638 766 958 638 766 894 1022 1150 1278 1534 1918 SCL Hold (Stop) Value 81 97 113 129 145 161 193 241 161 193 225 257 289 321 385 481 321 385 449 513 577 641 769 961 641 769 897 1025 1153 1281 1537 1921
11.3.3
IIC Control Register (IICC1)

7 6 5 4 3 2 1 0
R IICEN W Reset 0 0 0 0 0 IICIE MST TX TXAK
0 RSTA 0
Figure 11-5. IIC Control Register (IICC1) Table 11-5. IICC1 Field Descriptions
Field 7 IICEN 6 IICIE 5 MST Description IIC Enable. The IICEN bit determines whether the IIC module is enabled. 0 IIC is not enabled 1 IIC is enabled IIC Interrupt Enable. The IICIE bit determines whether an IIC interrupt is requested. 0 IIC interrupt request not enabled 1 IIC interrupt request enabled Master Mode Select. The MST bit changes from a 0 to a 1 when a start signal is generated on the bus and master mode is selected. When this bit changes from a 1 to a 0 a stop signal is generated and the mode of operation changes from master to slave. 0 Slave mode 1 Master mode Transmit Mode Select. The TX bit selects the direction of master and slave transfers. In master mode, this bit should be set according to the type of transfer required. Therefore, for address cycles, this bit is always high. When addressed as a slave, this bit should be set by software according to the SRW bit in the status register. 0 Receive 1 Transmit Transmit Acknowledge Enable. This bit species the value driven onto the SDA during data acknowledge cycles for master and slave receivers. 0 An acknowledge signal is sent out to the bus after receiving one data byte 1 No acknowledge signal response is sent Repeat start. Writing a 1 to this bit generates a repeated start condition provided it is the current master. This bit is always read as cleared. Attempting a repeat at the wrong time results in loss of arbitration.
4 TX
3 TXAK
2 RSTA
11.3.4
IIC Status Register (IICS)

7 6 5 4 3 2 1 0
R W Reset
TCF IAAS 1 0
BUSY ARBL 0 0
SRW IICIF
RXAK
Figure 11-6. IIC Status Register (IICS) Table 11-6. IICS Field Descriptions
Field 7 TCF Description Transfer Complete Flag. This bit is set on the completion of a byte transfer. This bit is only valid during or immediately following a transfer to the IIC module or from the IIC module.The TCF bit is cleared by reading the IICD register in receive mode or writing to the IICD in transmit mode. 0 Transfer in progress 1 Transfer complete Addressed as a Slave. The IAAS bit is set when the calling address matches the programmed slave address or when the GCAEN bit is set and a general call is received. Writing the IICC register clears this bit. 0 Not addressed 1 Addressed as a slave Bus Busy. The BUSY bit indicates the status of the bus regardless of slave or master mode. The BUSY bit is set when a start signal is detected and cleared when a stop signal is detected. 0 Bus is idle 1 Bus is busy Arbitration Lost. This bit is set by hardware when the arbitration procedure is lost. The ARBL bit must be cleared by software by writing a 1 to it. 0 Standard bus operation 1 Loss of arbitration Slave Read/Write. When addressed as a slave, the SRW bit indicates the value of the R/W command bit of the calling address sent to the master. 0 Slave receive, master writing to slave 1 Slave transmit, master reading from slave IIC Interrupt Flag. The IICIF bit is set when an interrupt is pending. This bit must be cleared by software, by writing a 1 to it in the interrupt routine. One of the following events can set the IICIF bit: One byte transfer completes Match of slave address to calling address Arbitration lost 0 No interrupt pending 1 Interrupt pending Receive Acknowledge. When the RXAK bit is low, it indicates an acknowledge signal has been received after the completion of one byte of data transmission on the bus. If the RXAK bit is high it means that no acknowledge signal is detected. 0 Acknowledge received 1 No acknowledge received
6 IAAS
5 BUSY
4 ARBL
2 SRW
1 IICIF
0 RXAK
11.3.5
IIC Data I/O Register (IICD)

7 6 5 4 3 2 1 0
R DATA W Reset 0 0 0 0 0 0 0 0
Figure 11-7. IIC Data I/O Register (IICD) Table 11-7. IICD Field Descriptions
Field 70 DATA Description Data In master transmit mode, when data is written to the IICD, a data transfer is initiated. The most signicant bit is sent rst. In master receive mode, reading this register initiates receiving of the next byte of data.
NOTE When transitioning out of master receive mode, the IIC mode should be switched before reading the IICD register to prevent an inadvertent initiation of a master receive data transfer. In slave mode, the same functions are available after an address match has occurred. The TX bit in IICC must correctly reect the desired direction of transfer in master and slave modes for the transmission to begin. For instance, if the IIC is congured for master transmit but a master receive is desired, reading the IICD does not initiate the receive. Reading the IICD returns the last byte received while the IIC is congured in master receive or slave receive modes. The IICD does not reect every byte transmitted on the IIC bus, nor can software verify that a byte has been written to the IICD correctly by reading it back. In master transmit mode, the rst byte of data written to IICD following assertion of MST is used for the address transfer and should comprise of the calling address (in bit 7 to bit 1) concatenated with the required R/W bit (in position bit 0).
11.3.6
IIC Control Register 2 (IICC2)

7 6 5 4 3 2 1 0
R GCAEN W Reset 0 0 ADEXT
0 AD10 AD9 0 AD8 0
= Unimplemented or Reserved Figure 11-8. IIC Control Register (IICC2)
Table 11-8. IICC2 Field Descriptions

Field 7 GCAEN 6 ADEXT 20 AD[10:8] Description General Call Address Enable. The GCAEN bit enables or disables general call address. 0 General call address is disabled 1 General call address is enabled Address Extension. The ADEXT bit controls the number of bits used for the slave address. 0 7-bit address scheme 1 10-bit address scheme Slave Address. The AD[10:8] eld contains the upper three bits of the slave address in the 10-bit address scheme. This eld is only valid when the ADEXT bit is set.
11.4
This section provides a complete functional description of the IIC module.
11.4.1
IIC Protocol
The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices connected to it must have open drain or open collector outputs. A logic AND function is exercised on both lines with external pull-up resistors. The value of these resistors is system dependent. Normally, a standard communication is composed of four parts: Start signal Slave address transmission Data transfer Stop signal The stop signal should not be confused with the CPU stop instruction. The IIC bus system communication is described briey in the following sections and illustrated in Figure 11-9.
msb SCL 1 2 3 4 5 6 7
lsb 8 9
msb 1 2 3 4 5 6 7
lsb 8 9
SDA
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
XXX
D7
D6
D5
D4
D3
D2
D1
D0
Start Signal
Calling Address
Read/ Ack Write Bit
Data Byte
No Ack Bit lsb
Stop Signal
msb SCL 1 2 3 4 5 6 7
lsb 8 9
msb 1 2 3 4 5 6 7
SDA
XX
Start Signal
Calling Address
Read/ Ack Write Bit
Repeated Start Signal
New Calling Address
Read/ Write
No Ack Bit
Stop Signal
Figure 11-9. IIC Bus Transmission Signals
11.4.1.1
Start Signal
When the bus is free, no master device is engaging the bus (SCL and SDA lines are at logical high), a master may initiate communication by sending a start signal. As shown in Figure 11-9, a start signal is dened as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle states.
11.4.1.2
Slave Address Transmission
The rst byte of data transferred immediately after the start signal is the slave address transmitted by the master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired direction of data transfer. 1 = Read transfer, the slave transmits data to the master. 0 = Write transfer, the master transmits data to the slave. Only the slave with a calling address that matches the one transmitted by the master responds by sending back an acknowledge bit. This is done by pulling the SDA low at the ninth clock (see Figure 11-9). No two slaves in the system may have the same address. If the IIC module is the master, it must not transmit an address equal to its own slave address. The IIC cannot be master and slave at the same time. However, if arbitration is lost during an address cycle, the IIC reverts to slave mode and operates correctly even if it is being addressed by another master.
11.4.1.3
Data Transfer
Before successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction specied by the R/W bit sent by the calling master. All transfers that come after an address cycle are referred to as data transfers, even if they carry sub-address information for the slave device Each data byte is 8 bits long. Data may be changed only while SCL is low and must be held stable while SCL is high as shown in Figure 11-9. There is one clock pulse on SCL for each data bit, the msb being transferred rst. Each data byte is followed by a 9th (acknowledge) bit, which is signalled from the receiving device. An acknowledge is signalled by pulling the SDA low at the ninth clock. In summary, one complete data transfer needs nine clock pulses. If the slave receiver does not acknowledge the master in the ninth bit time, the SDA line must be left high by the slave. The master interprets the failed acknowledge as an unsuccessful data transfer. If the master receiver does not acknowledge the slave transmitter after a data byte transmission, the slave interprets this as an end of data transfer and releases the SDA line. In either case, the data transfer is aborted and the master does one of two things: Relinquishes the bus by generating a stop signal. Commences a new calling by generating a repeated start signal.
11.4.1.4
Stop Signal
The master can terminate the communication by generating a stop signal to free the bus. However, the master may generate a start signal followed by a calling command without generating a stop signal rst. This is called repeated start. A stop signal is dened as a low-to-high transition of SDA while SCL at logical 1 (see Figure 11-9). The master can generate a stop even if the slave has generated an acknowledge at which point the slave must release the bus.
11.4.1.5
Repeated Start Signal
As shown in Figure 11-9, a repeated start signal is a start signal generated without rst generating a stop signal to terminate the communication. This is used by the master to communicate with another slave or with the same slave in different mode (transmit/receive mode) without releasing the bus.
11.4.1.6
Arbitration Procedure
The IIC bus is a true multi-master bus that allows more than one master to be connected on it. If two or more masters try to control the bus at the same time, a clock synchronization procedure determines the bus clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest one among the masters. The relative priority of the contending masters is determined by a data arbitration procedure, a bus master loses arbitration if it transmits logic 1 while another master transmits logic 0. The losing masters immediately switch over to slave receive mode and stop driving SDA output. In this case,
the transition from master to slave mode does not generate a stop condition. Meanwhile, a status bit is set by hardware to indicate loss of arbitration.
11.4.1.7
Clock Synchronization
Because wire-AND logic is performed on the SCL line, a high-to-low transition on the SCL line affects all the devices connected on the bus. The devices start counting their low period and after a devices clock has gone low, it holds the SCL line low until the clock high state is reached. However, the change of low to high in this device clock may not change the state of the SCL line if another device clock is still within its low period. Therefore, synchronized clock SCL is held low by the device with the longest low period. Devices with shorter low periods enter a high wait state during this time (see Figure 11-10). When all devices concerned have counted off their low period, the synchronized clock SCL line is released and pulled high. There is then no difference between the device clocks and the state of the SCL line and all the devices start counting their high periods. The rst device to complete its high period pulls the SCL line low again.
Delay SCL1 Start Counting High Period
SCL2
SCL
Internal Counter Reset
Figure 11-10. IIC Clock Synchronization
11.4.1.8
Handshaking
The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold the SCL low after completion of one byte transfer (9 bits). In such a case, it halts the bus clock and forces the master clock into wait states until the slave releases the SCL line.
11.4.1.9
Clock Stretching
The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After the master has driven SCL low the slave can drive SCL low for the required period and then release it. If the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low period is stretched.
11.4.2
10-bit Address
For 10-bit addressing, 0x11110 is used for the rst 5 bits of the rst address byte. Various combinations of read/write formats are possible within a transfer that includes 10-bit addressing.
11.4.2.1
Master-Transmitter Addresses a Slave-Receiver
The transfer direction is not changed (see Table 11-9). When a 10-bit address follows a start condition, each slave compares the first seven bits of the first byte of the slave address (11110XX) with its own address and tests whether the eighth bit (R/W direction bit) is 0. More than one device can find a match and generate an acknowledge (A1). Then, each slave that finds a match compares the eight bits of the second byte of the slave address with its own address. Only one slave finds a match and generates an acknowledge (A2). The matching slave remains addressed by the master until it receives a stop condition (P) or a repeated start condition (Sr) followed by a different slave address.
S Slave Address 1st 7 bits 11110 + AD10 + AD9 R/W 0 A1 Slave Address 2nd byte AD[8:1] A2 Data A ... Data A/A P
Table 11-9. Master-Transmitter Addresses Slave-Receiver with a 10-bit Address
After the master-transmitter has sent the first byte of the 10-bit address, the slave-receiver sees an IIC interrupt. Software must ensure the contents of IICD are ignored and not treated as valid data for this interrupt.
11.4.2.2
Master-Receiver Addresses a Slave-Transmitter
The transfer direction is changed after the second R/W bit (see Table 11-10). Up to and including acknowledge bit A2, the procedure is the same as that described for a master-transmitter addressing a slave-receiver. After the repeated start condition (Sr), a matching slave remembers that it was addressed before. This slave then checks whether the rst seven bits of the rst byte of the slave address following Sr are the same as they were after the start condition (S) and tests whether the eighth (R/W) bit is 1. If there is a match, the slave considers that it has been addressed as a transmitter and generates acknowledge A3. The slave-transmitter remains addressed until it receives a stop condition (P) or a repeated start condition (Sr) followed by a different slave address. After a repeated start condition (Sr), all other slave devices also compare the rst seven bits of the rst byte of the slave address with their own addresses and test the eighth (R/W) bit. However, none of them are addressed because R/W = 1 (for 10-bit devices) or the 11110XX slave address (for 7-bit devices) does not match.
S Slave Address 1st 7 bits 11110 + AD10 + AD9 R/W 0 A1 Slave Address 2nd byte AD[8:1] A2 Sr Slave Address 1st 7 bits 11110 + AD10 + AD9 R/W 1 A3 Data A ... Data A P
Table 11-10. Master-Receiver Addresses a Slave-Transmitter with a 10-bit Address
After the master-receiver has sent the rst byte of the 10-bit address, the slave-transmitter sees an IIC interrupt. Software must ensure the contents of IICD are ignored and not treated as valid data for this interrupt.
11.4.3
General Call Address
General calls can be requested in 7-bit address or 10-bit address. If the GCAEN bit is set, the IIC matches the general call address as well as its own slave address. When the IIC responds to a general call, it acts as a slave-receiver and the IAAS bit is set after the address cycle. Software must read the IICD register after the rst byte transfer to determine whether the address matches is its own slave address or a general call. If the value is 00, the match is a general call. If the GCAEN bit is clear, the IIC ignores any data supplied from a general call address by not issuing an acknowledgement.
11.5
Resets
The IIC is disabled after reset. The IIC cannot cause an MCU reset.
11.6
Interrupts
The IIC generates a single interrupt. An interrupt from the IIC is generated when any of the events in Table 11-11 occur, provided the IICIE bit is set. The interrupt is driven by bit IICIF (of the IIC status register) and masked with bit IICIE (of the IIC control register). The IICIF bit must be cleared by software by writing a 1 to it in the interrupt routine. You can determine the interrupt type by reading the status register.
Table 11-11. Interrupt Summary
Interrupt Source Complete 1-byte transfer Match of received calling address Arbitration Lost Status TCF IAAS ARBL Flag IICIF IICIF IICIF Local Enable IICIE IICIE IICIE
11.6.1
Byte Transfer Interrupt
The TCF (transfer complete ag) bit is set at the falling edge of the ninth clock to indicate the completion of byte transfer.
11.6.2
Address Detect Interrupt
When the calling address matches the programmed slave address (IIC address register) or when the GCAEN bit is set and a general call is received, the IAAS bit in the status register is set. The CPU is interrupted, provided the IICIE is set. The CPU must check the SRW bit and set its Tx mode accordingly.
11.6.3
Arbitration Lost Interrupt
The IIC is a true multi-master bus that allows more than one master to be connected on it. If two or more masters try to control the bus at the same time, the relative priority of the contending masters is determined by a data arbitration procedure. The IIC module asserts this interrupt when it loses the data arbitration process and the ARBL bit in the status register is set.
Arbitration is lost in the following circumstances: SDA sampled as a low when the master drives a high during an address or data transmit cycle. SDA sampled as a low when the master drives a high during the acknowledge bit of a data receive cycle. A start cycle is attempted when the bus is busy. A repeated start cycle is requested in slave mode. A stop condition is detected when the master did not request it. This bit must be cleared by software writing a 1 to it.
11.7
1.
Initialization/Application Information
Module Initialization (Slave) Write: IICC2 to enable or disable general call to select 10-bit or 7-bit addressing mode Write: IICA to set the slave address Write: IICC1 to enable IIC and interrupts Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data Initialize RAM variables used to achieve the routine shown in Figure 11-12
2. 3. 4. 5.
1. 2. 3. 4. 5. 6. 7.
Module Initialization (Master) Write: IICF to set the IIC baud rate (example provided in this chapter) Write: IICC1 to enable IIC and interrupts Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data Initialize RAM variables used to achieve the routine shown in Figure 11-12 Write: IICC1 to enable TX Write: IICC1 to enable MST (master mode) Write: IICD with the address of the target slave. (The lsb of this byte determines whether the communication is master receive or transmit.) Module Use The routine shown in Figure 11-12 can handle both master and slave IIC operations. For slave operation, an incoming IIC message that contains the proper address begins IIC communication. For master operation, communication must be initiated by writing to the IICD register.
Register Model IICA MULT AD[7:1] 0
When addressed as a slave (in slave mode), the module responds to this address IICF ICR Baud rate = BUSCLK / (2 x MULT x (SCL DIVIDER)) IICC1 IICS IICD IICEN TCF IICIE IAAS MST BUSY TX ARBL DATA Data register; Write to transmit IIC data read to read IIC data IICC2 GCAEN ADEXT Address conguration 0 0 0 AD10 AD9 AD8 TXAK 0 RSTA SRW 0 IICIF 0 RXAK
Module conguration Module status ags
Figure 11-11. IIC Module Quick Start
Clear IICIF
Master Mode ?
TX
Tx/Rx ?
RX
Arbitration Lost ? N
Last Byte Transmitted ? N
Clear ARBL
RXAK=0 ? Y
Last Byte to Be Read ? N
N Y
IAAS=1 ? Y
IAAS=1 ? N Data Transfer See Note 2 TX/RX ? TX RX
Address Transfer See Note 1 Y End of Addr Cycle (Master Rx) ? N Y 2nd Last Byte to Be Read ? N Y (Read) SRW=1 ? N (Write)
Write Next Byte to IICD
Set TXACK =1
Generate Stop Signal (MST = 0)
Set TX Mode
ACK from Receiver ? N Read Data from IICD and Store
Write Data to IICD
Tx Next Byte
Switch to Rx Mode
Set RX Mode
Switch to Rx Mode
Dummy Read from IICD
Generate Stop Signal (MST = 0)
Read Data from IICD and Store
RTI NOTES: 1. If general call is enabled, a check must be done to determine whether the received address was a general call address (0x00). If the received address was a general call address, then the general call must be handled by user software. 2. When 10-bit addressing is used to address a slave, the slave sees an interrupt following the rst byte of the extended address. User software must ensure that for this interrupt, the contents of IICD are ignored and not treated as a valid data transfer
Figure 11-12. Typical IIC Interrupt Routine


12.1 Introduction
The Freescale controller area network (MSCAN) is a communication controller implementing the CAN 2.0A/B protocol as dened in the Bosch specication dated September 1991. To fully understand the MSCAN specication, it is recommended that the Bosch specication be read rst to gain familiarity with the terms and concepts contained within this document. Though not exclusively intended for automotive applications, CAN protocol is designed to meet the specic requirements of a vehicle serial data bus: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness, and required bandwidth. MSCAN uses an advanced buffer arrangement resulting in predictable real-time behavior and simplied application software. The MSCAN module is available in all devices in the MC9S08DZ60 Series.
BDC
BKP
PORT G
PORT F
PORT E
PORT D
PORT B
Chapter 12 Freescales Controller Area Network (S08MSCANV1)
12.1.1
Features
The basic features of the MSCAN are as follows: Implementation of the CAN protocol Version 2.0A/B Standard and extended data frames Zero to eight bytes data length Programmable bit rate up to 1 Mbps1 Support for remote frames Five receive buffers with FIFO storage scheme Three transmit buffers with internal prioritization using a local priority concept Flexible maskable identier lter supports two full-size (32-bit) extended identier lters, or four 16-bit lters, or eight 8-bit lters Programmable wakeup functionality with integrated low-pass lter Programmable loopback mode supports self-test operation Programmable listen-only mode for monitoring of CAN bus Programmable bus-off recovery functionality Separate signalling and interrupt capabilities for all CAN receiver and transmitter error states (warning, error passive, bus-off) Programmable MSCAN clock source either bus clock or oscillator clock Internal timer for time-stamping of received and transmitted messages Three low-power modes: sleep, power down, and MSCAN enable Global initialization of conguration registers
12.1.2
Modes of Operation
The following modes of operation are specic to the MSCAN. See Section 12.5, Functional Description, for details. Listen-Only Mode MSCAN Sleep Mode MSCAN Initialization Mode MSCAN Power Down Mode Loopback Self Test Mode
1. Depending on the actual bit timing and the clock jitter of the PLL. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 221
12.1.3
Block Diagram MSCAN

Oscillator Clock Bus Clock
CANCLK
MUX
Presc.
Tq Clk
Receive/ Transmit Engine
RXCAN TXCAN
Transmit Interrupt Req. Receive Interrupt Req. Errors Interrupt Req. Wake-Up Interrupt Req.
Control and Status
Message Filtering and Buffering
Conguration Registers
Wake-Up
Low Pass Filter
Figure 12-2. MSCAN Block Diagram
12.2
The MSCAN uses two external pins:
12.2.1
RXCAN CAN Receiver Input Pin
RXCAN is the MSCAN receiver input pin.
12.2.2
TXCAN CAN Transmitter Output Pin
TXCAN is the MSCAN transmitter output pin. The TXCAN output pin represents the logic level on the CAN bus: 0 = Dominant state 1 = Recessive state
12.2.3
CAN System
A typical CAN system with MSCAN is shown in Figure 12-3. Each CAN node is connected physically to the CAN bus lines through a transceiver device. The transceiver is capable of driving the large current needed for the CAN bus and has current protection against defective CAN or defective nodes.
Chapter 12 Freescales Controller Area Network (S08MSCANV1) CAN node 1 MCU CAN Controller (MSCAN) CAN node 2 CAN node n
TXCAN
RXCAN
Transceiver CAN_H CAN_L CAN Bus
Figure 12-3. CAN System
12.3
Register Denition
This section describes in detail all the registers and register bits in the MSCAN module. Each description includes a standard register diagram with an associated gure number. Details of register bit and eld function follow the register diagrams, in bit order. All bits of all registers in this module are completely synchronous to internal clocks during a register read.
12.3.1
MSCAN Control Register 0 (CANCTL0)
The CANCTL0 register provides various control bits of the MSCAN module as described below.
7 6 5 4 3 2 1 0
R W Reset:
RXFRM
RXACT CSWAI
SYNCH TIME 0 0 WUPE 0 SLPRQ 0 INITRQ 1
0 = Unimplemented
Figure 12-4. MSCAN Control Register 0 (CANCTL0)
NOTE The CANCTL0 register, except WUPE, INITRQ, and SLPRQ, is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable again as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime when out of initialization mode; exceptions are read-only RXACT and SYNCH, RXFRM (which is set by the module only), and INITRQ (which is also writable in initialization mode).
Table 12-1. CANCTL0 Register Field Descriptions

Field 7 RXFRM1 Description Received Frame Flag This bit is read and clear only. It is set when a receiver has received a valid message correctly, independently of the lter conguration. After it is set, it remains set until cleared by software or reset. Clearing is done by writing a 1. Writing a 0 is ignored. This bit is not valid in loopback mode. 0 No valid message was received since last clearing this ag 1 A valid message was received since last clearing of this ag Receiver Active Status This read-only ag indicates the MSCAN is receiving a message. The ag is controlled by the receiver front end. This bit is not valid in loopback mode. 0 MSCAN is transmitting or idle2 1 MSCAN is receiving a message (including when arbitration is lost)2 CAN Stops in Wait Mode Enabling this bit allows for lower power consumption in wait mode by disabling all the clocks at the CPU bus interface to the MSCAN module. 0 The module is not affected during wait mode 1 The module ceases to be clocked during wait mode Synchronized Status This read-only ag indicates whether the MSCAN is synchronized to the CAN bus and able to participate in the communication process. It is set and cleared by the MSCAN. 0 MSCAN is not synchronized to the CAN bus 1 MSCAN is synchronized to the CAN bus Timer Enable This bit activates an internal 16-bit wide free running timer which is clocked by the bit clock rate. If the timer is enabled, a 16-bit time stamp will be assigned to each transmitted/received message within the active TX/RX buffer. As soon as a message is acknowledged on the CAN bus, the time stamp will be written to the highest bytes (0x000E, 0x000F) in the appropriate buffer (see Section 12.4, Programmers Model of Message Storage). The internal timer is reset (all bits set to 0) when disabled. This bit is held low in initialization mode. 0 Disable internal MSCAN timer 1 Enable internal MSCAN timer Wake-Up Enable This conguration bit allows the MSCAN to restart from sleep mode when trafc on CAN is detected (see Section 12.5.5.4, MSCAN Sleep Mode). This bit must be congured before sleep mode entry for the selected function to take effect. 0 Wake-up disabled The MSCAN ignores trafc on CAN 1 Wake-up enabled The MSCAN is able to restart
6 RXACT
5 CSWAI3
4 SYNCH
3 TIME
2 WUPE4
Table 12-1. CANCTL0 Register Field Descriptions (continued)

Field 1 SLPRQ5 Description Sleep Mode Request This bit requests the MSCAN to enter sleep mode, which is an internal power saving mode (see Section 12.5.5.4, MSCAN Sleep Mode). The sleep mode request is serviced when the CAN bus is idle, i.e., the module is not receiving a message and all transmit buffers are empty. The module indicates entry to sleep mode by setting SLPAK = 1 (see Section 12.3.2, MSCAN Control Register 1 (CANCTL1)). SLPRQ cannot be set while the WUPIF ag is set (see Section 12.3.4.1, MSCAN Receiver Flag Register (CANRFLG)). Sleep mode will be active until SLPRQ is cleared by the CPU or, depending on the setting of WUPE, the MSCAN detects activity on the CAN bus and clears SLPRQ itself. 0 Running The MSCAN functions normally 1 Sleep mode request The MSCAN enters sleep mode when CAN bus idle Initialization Mode Request When this bit is set by the CPU, the MSCAN skips to initialization mode (see Section 12.5.5.5, MSCAN Initialization Mode). Any ongoing transmission or reception is aborted and synchronization to the CAN bus is lost. The module indicates entry to initialization mode by setting INITAK = 1 (Section 12.3.2, MSCAN Control Register 1 (CANCTL1)). The following registers enter their hard reset state and restore their default values: CANCTL08, CANRFLG9, CANRIER10, CANTFLG, CANTIER, CANTARQ, CANTAAK, and CANTBSEL. The registers CANCTL1, CANBTR0, CANBTR1, CANIDAC, CANIDAR0-7, and CANIDMR0-7 can only be written by the CPU when the MSCAN is in initialization mode (INITRQ = 1 and INITAK = 1). The values of the error counters are not affected by initialization mode. When this bit is cleared by the CPU, the MSCAN restarts and then tries to synchronize to the CAN bus. If the MSCAN is not in bus-off state, it synchronizes after 11 consecutive recessive bits on the CAN bus; if the MSCAN is in bus-off state, it continues to wait for 128 occurrences of 11 consecutive recessive bits. Writing to other bits in CANCTL0, CANRFLG, CANRIER, CANTFLG, or CANTIER must be done only after initialization mode is exited, which is INITRQ = 0 and INITAK = 0. 0 Normal operation 1 MSCAN in initialization mode
0 INITRQ6,7
1 2
The MSCAN must be in normal mode for this bit to become set. See the Bosch CAN 2.0A/B specication for a detailed denition of transmitter and receiver states. 3 In order to protect from accidentally violating the CAN protocol, the TXCAN pin is immediately forced to a recessive state when the CPU enters wait (CSWAI = 1) or stop mode (see Section 12.5.5.2, Operation in Wait Mode and Section 12.5.5.3, Operation in Stop Mode). 4 The CPU has to make sure that the WUPE bit and the WUPIE wake-up interrupt enable bit (see Section 12.3.5, MSCAN Receiver Interrupt Enable Register (CANRIER)) is enabled, if the recovery mechanism from stop or wait is required. 5 The CPU cannot clear SLPRQ before the MSCAN has entered sleep mode (SLPRQ = 1 and SLPAK = 1). 6 The CPU cannot clear INITRQ before the MSCAN has entered initialization mode (INITRQ = 1 and INITAK = 1). 7 In order to protect from accidentally violating the CAN protocol, the TXCAN pin is immediately forced to a recessive state when the initialization mode is requested by the CPU. Thus, the recommended procedure is to bring the MSCAN into sleep mode (SLPRQ = 1 and SLPAK = 1) before requesting initialization mode. 8 Not including WUPE, INITRQ, and SLPRQ. 9 TSTAT1 and TSTAT0 are not affected by initialization mode. 10 RSTAT1 and RSTAT0 are not affected by initialization mode.
12.3.2
MSCAN Control Register 1 (CANCTL1)
The CANCTL1 register provides various control bits and handshake status information of the MSCAN module as described below.
7 6 5 4 3 2 1 0
R CANE W Reset: 0 0 = Unimplemented 0 1 0 0 CLKSRC LOOPB LISTEN BORM WUPM
SLPAK
INITAK
Figure 12-5. MSCAN Control Register 1(CANCTL1)
Read: Anytime Write: Anytime when INITRQ = 1 and INITAK = 1, except CANE which is write once in normal and anytime in special system operation modes when the MSCAN is in initialization mode (INITRQ = 1 and INITAK = 1).
Table 12-2. CANCTL1 Register Field Descriptions
Field 7 CANE 6 CLKSRC MSCAN Enable 0 MSCAN module is disabled 1 MSCAN module is enabled MSCAN Clock Source This bit denes the clock source for the MSCAN module (only for systems with a clock generation module; Section 12.5.3.3, Clock System, and Section Figure 12-42., MSCAN Clocking Scheme,). 0 MSCAN clock source is the oscillator clock 1 MSCAN clock source is the bus clock Loopback Self Test Mode When this bit is set, the MSCAN performs an internal loopback which can be used for self test operation. The bit stream output of the transmitter is fed back to the receiver internally.Section 12.5.4.6, Loopback Self Test Mode. 0 Loopback self test disabled 1 Loopback self test enabled Listen Only Mode This bit congures the MSCAN as a CAN bus monitor. When LISTEN is set, all valid CAN messages with matching ID are received, but no acknowledgement or error frames are sent out (see Section 12.5.4.4, Listen-Only Mode). In addition, the error counters are frozen. Listen only mode supports applications which require hot plugging or throughput analysis. The MSCAN is unable to transmit any messages when listen only mode is active. 0 Normal operation 1 Listen only mode activated Bus-Off Recovery Mode This bits congures the bus-off state recovery mode of the MSCAN. Refer to Section 12.6.2, Bus-Off Recovery, for details. 0 Automatic bus-off recovery (see Bosch CAN 2.0A/B protocol specication) 1 Bus-off recovery upon user request Wake-Up Mode If WUPE in CANCTL0 is enabled, this bit denes whether the integrated low-pass lter is applied to protect the MSCAN from spurious wake-up (see Section 12.5.5.4, MSCAN Sleep Mode). 0 MSCAN wakes up on any dominant level on the CAN bus 1 MSCAN wakes up only in case of a dominant pulse on the CAN bus that has a length of Twup Description
5 LOOPB
4 LISTEN
3 BORM
2 WUPM
Table 12-2. CANCTL1 Register Field Descriptions (continued)

Field 1 SLPAK Description Sleep Mode Acknowledge This ag indicates whether the MSCAN module has entered sleep mode (see Section 12.5.5.4, MSCAN Sleep Mode). It is used as a handshake ag for the SLPRQ sleep mode request. Sleep mode is active when SLPRQ = 1 and SLPAK = 1. Depending on the setting of WUPE, the MSCAN will clear the ag if it detects activity on the CAN bus while in sleep mode.CPU clearing the SLPRQ bit will also reset the SLPAK bit. 0 Running The MSCAN operates normally 1 Sleep mode active The MSCAN has entered sleep mode Initialization Mode Acknowledge This ag indicates whether the MSCAN module is in initialization mode (see Section 12.5.5.5, MSCAN Initialization Mode). It is used as a handshake ag for the INITRQ initialization mode request. Initialization mode is active when INITRQ = 1 and INITAK = 1. The registers CANCTL1, CANBTR0, CANBTR1, CANIDAC, CANIDAR0CANIDAR7, and CANIDMR0CANIDMR7 can be written only by the CPU when the MSCAN is in initialization mode. 0 Running The MSCAN operates normally 1 Initialization mode active The MSCAN is in initialization mode
0 INITAK
12.3.3
MSCAN Bus Timing Register 0 (CANBTR0)
The CANBTR0 register congures various CAN bus timing parameters of the MSCAN module.
7 6 5 4 3 2 1 0
R SJW1 W Reset: 0 0 0 0 0 0 0 0 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
Figure 12-6. MSCAN Bus Timing Register 0 (CANBTR0)
Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)

Table 12-3. CANBTR0 Register Field Descriptions
Field 7:6 SJW[1:0] 5:0 BRP[5:0] Description Synchronization Jump Width The synchronization jump width denes the maximum number of time quanta (Tq) clock cycles a bit can be shortened or lengthened to achieve resynchronization to data transitions on the CAN bus (see Table 12-4). Baud Rate Prescaler These bits determine the time quanta (Tq) clock which is used to build up the bit timing (see Table 12-5).
Table 12-4. Synchronization Jump Width

SJW1 0 0 1 1 SJW0 0 1 0 1 Synchronization Jump Width 1 Tq clock cycle 2 Tq clock cycles 3 Tq clock cycles 4 Tq clock cycles
Table 12-5. Baud Rate Prescaler

BRP5 0 0 0 0 : 1 BRP4 0 0 0 0 : 1 BRP3 0 0 0 0 : 1 BRP2 0 0 0 0 : 1 BRP1 0 0 1 1 : 1 BRP0 0 1 0 1 : 1 Prescaler value (P) 1 2 3 4 : 64
12.3.4
MSCAN Bus Timing Register 1 (CANBTR1)
The CANBTR1 register congures various CAN bus timing parameters of the MSCAN module.
7 6 5 4 3 2 1 0
R SAMP W Reset: 0 0 0 0 0 0 0 0 TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
Figure 12-7. MSCAN Bus Timing Register 1 (CANBTR1)

Table 12-6. CANBTR1 Register Field Descriptions
Field 7 SAMP Description Sampling This bit determines the number of CAN bus samples taken per bit time. 0 One sample per bit. 1 Three samples per bit1. If SAMP = 0, the resulting bit value is equal to the value of the single bit positioned at the sample point. If SAMP = 1, the resulting bit value is determined by using majority rule on the three total samples. For higher bit rates, it is recommended that only one sample is taken per bit time (SAMP = 0).
6:4 Time Segment 2 Time segments within the bit time x the number of clock cycles per bit time and the location TSEG2[2:0] of the sample point (see Figure 12-43). Time segment 2 (TSEG2) values are programmable as shown in Table 12-7. 3:0 Time Segment 1 Time segments within the bit time x the number of clock cycles per bit time and the location TSEG1[3:0] of the sample point (see Figure 12-43). Time segment 1 (TSEG1) values are programmable as shown in Table 12-8.
1
In this case, PHASE_SEG1 must be at least 2 time quanta (Tq).
Table 12-7. Time Segment 2 Values

TSEG22 0 0 : 1 1
1
TSEG21 0 0 : 1 1
TSEG20 0 1 : 0 1
Time Segment 2 1 Tq clock cycle1 2 Tq clock cycles : 7 Tq clock cycles 8 Tq clock cycles
This setting is not valid. Please refer to Table 12-35 for valid settings.
Table 12-8. Time Segment 1 Values

TSEG13 0 0 0 0 : 1 1
1
TSEG12 0 0 0 0 : 1 1
TSEG11 0 0 1 1 : 1 1
TSEG10 0 1 0 1 : 0 1
Time segment 1 1 Tq clock cycle1 2 Tq clock cycles1 3 Tq clock cycles1 4 Tq clock cycles : 15 Tq clock cycles 16 Tq clock cycles
This setting is not valid. Please refer to Table 12-35 for valid settings.
The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time quanta (Tq) clock cycles per bit (as shown in Table 12-7 and Table 12-8).
Eqn. 12-1
( Prescaler value ) Bit Time = ----------------------------------------------------- ( 1 + TimeSegment1 + TimeSegment2 ) f CANCLK
12.3.4.1
MSCAN Receiver Flag Register (CANRFLG)
A ag can be cleared only by software (writing a 1 to the corresponding bit position) when the condition which caused the setting is no longer valid. Every ag has an associated interrupt enable bit in the CANRIER register.
7 6 5 4 3 2 1 0
R WUPIF W Reset: 0 0 CSCIF
RSTAT1
RSTAT0
TSTAT1
TSTAT0 OVRIF RXF 0
= Unimplemented
Figure 12-8. MSCAN Receiver Flag Register (CANRFLG)
NOTE The CANRFLG register is held in the reset state1 when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable again as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime when out of initialization mode, except RSTAT[1:0] and TSTAT[1:0] ags which are read-only; write of 1 clears ag; write of 0 is ignored.
Table 12-9. CANRFLG Register Field Descriptions
Field 7 WUPIF Description Wake-Up Interrupt Flag If the MSCAN detects CAN bus activity while in sleep mode (see Section 12.5.5.4, MSCAN Sleep Mode,) and WUPE = 1 in CANTCTL0 (see Section 12.3.1, MSCAN Control Register 0 (CANCTL0)), the module will set WUPIF. If not masked, a wake-up interrupt is pending while this ag is set. 0 No wake-up activity observed while in sleep mode 1 MSCAN detected activity on the CAN bus and requested wake-up CAN Status Change Interrupt Flag This ag is set when the MSCAN changes its current CAN bus status due to the actual value of the transmit error counter (TEC) and the receive error counter (REC). An additional 4-bit (RSTAT[1:0], TSTAT[1:0]) status register, which is split into separate sections for TEC/REC, informs the system on the actual CAN bus status (see Section 12.3.5, MSCAN Receiver Interrupt Enable Register (CANRIER)). If not masked, an error interrupt is pending while this ag is set. CSCIF provides a blocking interrupt. That guarantees that the receiver/transmitter status bits (RSTAT/TSTAT) are only updated when no CAN status change interrupt is pending. If the TECs/RECs change their current value after the CSCIF is asserted, which would cause an additional state change in the RSTAT/TSTAT bits, these bits keep their status until the current CSCIF interrupt is cleared again. 0 No change in CAN bus status occurred since last interrupt 1 MSCAN changed current CAN bus status
6 CSCIF
5:4 Receiver Status Bits The values of the error counters control the actual CAN bus status of the MSCAN. As RSTAT[1:0] soon as the status change interrupt ag (CSCIF) is set, these bits indicate the appropriate receiver related CAN bus status of the MSCAN. The coding for the bits RSTAT1, RSTAT0 is: 00 RxOK: 0 receive error counter 96 01 RxWRN: 96 < receive error counter 127 10 RxERR: 127 < receive error counter 11 Bus-off1: transmit error counter > 255 3:2 Transmitter Status Bits The values of the error counters control the actual CAN bus status of the MSCAN. TSTAT[1:0] As soon as the status change interrupt ag (CSCIF) is set, these bits indicate the appropriate transmitter related CAN bus status of the MSCAN. The coding for the bits TSTAT1, TSTAT0 is: 00 TxOK: 0 transmit error counter 96 01 TxWRN: 96 < transmit error counter 127 10 TxERR: 127 < transmit error counter 255 11 Bus-Off: transmit error counter > 255
1. The RSTAT[1:0], TSTAT[1:0] bits are not affected by initialization mode. MC9S08DZ60 Series Data Sheet, Rev. 4 230 Freescale Semiconductor
Table 12-9. CANRFLG Register Field Descriptions (continued)

Field 1 OVRIF Description Overrun Interrupt Flag This ag is set when a data overrun condition occurs. If not masked, an error interrupt is pending while this ag is set. 0 No data overrun condition 1 A data overrun detected Receive Buffer Full Flag RXF is set by the MSCAN when a new message is shifted in the receiver FIFO. This ag indicates whether the shifted buffer is loaded with a correctly received message (matching identier, matching cyclic redundancy code (CRC) and no other errors detected). After the CPU has read that message from the RxFG buffer in the receiver FIFO, the RXF ag must be cleared to release the buffer. A set RXF ag prohibits the shifting of the next FIFO entry into the foreground buffer (RxFG). If not masked, a receive interrupt is pending while this ag is set. 0 No new message available within the RxFG 1 The receiver FIFO is not empty. A new message is available in the RxFG
0 RXF2
Redundant Information for the most critical CAN bus status which is bus-off. This only occurs if the Tx error counter exceeds a number of 255 errors. Bus-off affects the receiver state. As soon as the transmitter leaves its bus-off state the receiver state skips to RxOK too. Refer also to TSTAT[1:0] coding in this register. 2 To ensure data integrity, do not read the receive buffer registers while the RXF ag is cleared. For MCUs with dual CPUs, reading the receive buffer registers while the RXF ag is cleared may result in a CPU fault condition.
12.3.5
MSCAN Receiver Interrupt Enable Register (CANRIER)
This register contains the interrupt enable bits for the interrupt ags described in the CANRFLG register.
7 6 5 4 3 2 1 0
R WUPIE W Reset: 0 0 0 0 0 0 0 0 CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE
Figure 12-9. MSCAN Receiver Interrupt Enable Register (CANRIER)
NOTE The CANRIER register is held in the reset state when the initialization mode is active (INITRQ=1 and INITAK=1). This register is writable when not in initialization mode (INITRQ=0 and INITAK=0). The RSTATE[1:0], TSTATE[1:0] bits are not affected by initialization mode. Read: Anytime Write: Anytime when not in initialization mode
Table 12-10. CANRIER Register Field Descriptions

Field 7 WUPIE1 6 CSCIE Description Wake-Up Interrupt Enable 0 No interrupt request is generated from this event. 1 A wake-up event causes a Wake-Up interrupt request. CAN Status Change Interrupt Enable 0 No interrupt request is generated from this event. 1 A CAN Status Change event causes an error interrupt request.
5:4 Receiver Status Change Enable These RSTAT enable bits control the sensitivity level in which receiver state RSTATE[1:0] changes are causing CSCIF interrupts. Independent of the chosen sensitivity level the RSTAT ags continue to indicate the actual receiver state and are only updated if no CSCIF interrupt is pending. 00 Do not generate any CSCIF interrupt caused by receiver state changes. 01 Generate CSCIF interrupt only if the receiver enters or leaves bus-off state. Discard other receiver state changes for generating CSCIF interrupt. 10 Generate CSCIF interrupt only if the receiver enters or leaves RxErr or bus-off2 state. Discard other receiver state changes for generating CSCIF interrupt. 11 Generate CSCIF interrupt on all state changes. 3:2 Transmitter Status Change Enable These TSTAT enable bits control the sensitivity level in which transmitter TSTATE[1:0] state changes are causing CSCIF interrupts. Independent of the chosen sensitivity level, the TSTAT ags continue to indicate the actual transmitter state and are only updated if no CSCIF interrupt is pending. 00 Do not generate any CSCIF interrupt caused by transmitter state changes. 01 Generate CSCIF interrupt only if the transmitter enters or leaves bus-off state. Discard other transmitter state changes for generating CSCIF interrupt. 10 Generate CSCIF interrupt only if the transmitter enters or leaves TxErr or bus-off state. Discard other transmitter state changes for generating CSCIF interrupt. 11 Generate CSCIF interrupt on all state changes. 1 OVRIE 0 RXFIE
1
Overrun Interrupt Enable 0 No interrupt request is generated from this event. 1 An overrun event causes an error interrupt request. Receiver Full Interrupt Enable 0 No interrupt request is generated from this event. 1 A receive buffer full (successful message reception) event causes a receiver interrupt request.
WUPIE and WUPE (see Section 12.3.1, MSCAN Control Register 0 (CANCTL0)) must both be enabled if the recovery mechanism from stop or wait is required. 2 Bus-off state is dened by the CAN standard (see Bosch CAN 2.0A/B protocol specication: for only transmitters. Because the only possible state change for the transmitter from bus-off to TxOK also forces the receiver to skip its current state to RxOK, the coding of the RXSTAT[1:0] ags dene an additional bus-off state for the receiver (see Section 12.3.4.1, MSCAN Receiver Flag Register (CANRFLG)).
12.3.6
MSCAN Transmitter Flag Register (CANTFLG)
The transmit buffer empty ags each have an associated interrupt enable bit in the CANTIER register.
R W Reset:
0 TXE2 TXE1 1 TXE0 1
= Unimplemented
Figure 12-10. MSCAN Transmitter Flag Register (CANTFLG)
NOTE The CANTFLG register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime for TXEx ags when not in initialization mode; write of 1 clears ag, write of 0 is ignored
Table 12-11. CANTFLG Register Field Descriptions
Field 2:0 TXE[2:0] Description Transmitter Buffer Empty This ag indicates that the associated transmit message buffer is empty, and thus not scheduled for transmission. The CPU must clear the ag after a message is set up in the transmit buffer and is due for transmission. The MSCAN sets the ag after the message is sent successfully. The ag is also set by the MSCAN when the transmission request is successfully aborted due to a pending abort request (see Section 12.3.8, MSCAN Transmitter Message Abort Request Register (CANTARQ)). If not masked, a transmit interrupt is pending while this ag is set. Clearing a TXEx ag also clears the corresponding ABTAKx (see Section 12.3.9, MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)). When a TXEx ag is set, the corresponding ABTRQx bit is cleared (see Section 12.3.8, MSCAN Transmitter Message Abort Request Register (CANTARQ)). When listen-mode is active (see Section 12.3.2, MSCAN Control Register 1 (CANCTL1)) the TXEx ags cannot be cleared and no transmission is started. Read and write accesses to the transmit buffer are blocked, if the corresponding TXEx bit is cleared (TXEx = 0) and the buffer is scheduled for transmission. 0 The associated message buffer is full (loaded with a message due for transmission) 1 The associated message buffer is empty (not scheduled)
12.3.7
MSCAN Transmitter Interrupt Enable Register (CANTIER)
This register contains the interrupt enable bits for the transmit buffer empty interrupt ags.
7 6 5 4 3 2 1 0
R W Reset:
0 TXEIE2 TXEIE1 0 TXEIE0 0
= Unimplemented
Figure 12-11. MSCAN Transmitter Interrupt Enable Register (CANTIER)
NOTE The CANTIER register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime when not in initialization mode
Table 12-12. CANTIER Register Field Descriptions
Field 2:0 TXEIE[2:0] Description Transmitter Empty Interrupt Enable 0 No interrupt request is generated from this event. 1 A transmitter empty (transmit buffer available for transmission) event causes a transmitter empty interrupt request. See Section 12.5.2.2, Transmit Structures for details.
12.3.8
MSCAN Transmitter Message Abort Request Register (CANTARQ)
The CANTARQ register allows abort request of messages queued for transmission.
7 6 5 4 3 2 1 0
R W Reset:
0 ABTRQ2 ABTRQ1 0 ABTRQ0 0
= Unimplemented
Figure 12-12. MSCAN Transmitter Message Abort Request Register (CANTARQ)
NOTE The CANTARQ register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime when not in initialization mode
Table 12-13. CANTARQ Register Field Descriptions
Field Description
2:0 Abort Request The CPU sets the ABTRQx bit to request that a scheduled message buffer (TXEx = 0) be ABTRQ[2:0] aborted. The MSCAN grants the request if the message has not already started transmission, or if the transmission is not successful (lost arbitration or error). When a message is aborted, the associated TXE (see Section 12.3.6, MSCAN Transmitter Flag Register (CANTFLG)) and abort acknowledge ags (ABTAK, see Section 12.3.9, MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)) are set and a transmit interrupt occurs if enabled. The CPU cannot reset ABTRQx. ABTRQx is reset whenever the associated TXE ag is set. 0 No abort request 1 Abort request pending
12.3.9
MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)
The CANTAAK register indicates the successful abort of messages queued for transmission, if requested by the appropriate bits in the CANTARQ register.
7 6 5 4 3 2 1 0
R W Reset:
ABTAK2
ABTAK1
ABTAK0
= Unimplemented
Figure 12-13. MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)
NOTE The CANTAAK register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). Read: Anytime Write: Unimplemented for ABTAKx ags
Table 12-14. CANTAAK Register Field Descriptions
Field Description
2:0 Abort Acknowledge This ag acknowledges that a message was aborted due to a pending transmission ABTAK[2:0] abort request from the CPU. After a particular message buffer is agged empty, this ag can be used by the application software to identify whether the message was aborted successfully or was sent anyway. The ABTAKx ag is cleared whenever the corresponding TXE ag is cleared. 0 The message was not aborted. 1 The message was aborted.
12.3.10 MSCAN Transmit Buffer Selection Register (CANTBSEL)

The CANTBSEL selections of the actual transmit message buffer, which is accessible in the CANTXFG register space.
7 6 5 4 3 2 1 0
R W Reset:
0 TX2 TX1 0 TX0 0
= Unimplemented
Figure 12-14. MSCAN Transmit Buffer Selection Register (CANTBSEL)
NOTE The CANTBSEL register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK=1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Read: Find the lowest ordered bit set to 1, all other bits will be read as 0 Write: Anytime when not in initialization mode
Table 12-15. CANTBSEL Register Field Descriptions
Field 2:0 TX[2:0] Description Transmit Buffer Select The lowest numbered bit places the respective transmit buffer in the CANTXFG register space (e.g., TX1 = 1 and TX0 = 1 selects transmit buffer TX0; TX1 = 1 and TX0 = 0 selects transmit buffer TX1). Read and write accesses to the selected transmit buffer will be blocked, if the corresponding TXEx bit is cleared and the buffer is scheduled for transmission (see Section 12.3.6, MSCAN Transmitter Flag Register (CANTFLG)). 0 The associated message buffer is deselected 1 The associated message buffer is selected, if lowest numbered bit
The following gives a short programming example of the usage of the CANTBSEL register: To get the next available transmit buffer, application software must read the CANTFLG register and write this value back into the CANTBSEL register. In this example Tx buffers TX1 and TX2 are available. The value read from CANTFLG is therefore 0b0000_0110. When writing this value back to CANTBSEL, the Tx buffer TX1 is selected in the CANTXFG because the lowest numbered bit set to 1 is at bit position 1. Reading back this value out of CANTBSEL results in 0b0000_0010, because only the lowest numbered bit position set to 1 is presented. This mechanism eases the application software the selection of the next available Tx buffer. LDD CANTFLG; value read is 0b0000_0110 STD CANTBSEL; value written is 0b0000_0110 LDD CANTBSEL; value read is 0b0000_0010 If all transmit message buffers are deselected, no accesses are allowed to the CANTXFG buffer register.
12.3.11 MSCAN Identier Acceptance Control Register (CANIDAC)

The CANIDAC register is used for identier lter acceptance control as described below.
7 6 5 4 3 2 1 0
R W Reset:
0 IDAM1 IDAM0 0
IDHIT2
IDHIT1
IDHIT0
= Unimplemented
Figure 12-15. MSCAN Identier Acceptance Control Register (CANIDAC)
Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1), except bits IDHITx, which are read-only
Table 12-16. CANIDAC Register Field Descriptions
Field 5:4 IDAM[1:0] 2:0 IDHIT[2:0] Description Identier Acceptance Mode The CPU sets these ags to dene the identier acceptance lter organization (see Section 12.5.3, Identier Acceptance Filter). Table 12-17 summarizes the different settings. In lter closed mode, no message is accepted such that the foreground buffer is never reloaded. Identier Acceptance Hit Indicator The MSCAN sets these ags to indicate an identier acceptance hit (see Section 12.5.3, Identier Acceptance Filter). Table 12-18 summarizes the different settings.
Table 12-17. Identier Acceptance Mode Settings

IDAM1 0 0 1 1 IDAM0 0 1 0 1 Identier Acceptance Mode Two 32-bit acceptance lters Four 16-bit acceptance lters Eight 8-bit acceptance lters Filter closed
Table 12-18. Identier Acceptance Hit Indication

IDHIT2 0 0 0 0 1 1 1 1 IDHIT1 0 0 1 1 0 0 1 1 IDHIT0 0 1 0 1 0 1 0 1 Identier Acceptance Hit Filter 0 hit Filter 1 hit Filter 2 hit Filter 3 hit Filter 4 hit Filter 5 hit Filter 6 hit Filter 7 hit
The IDHITx indicators are always related to the message in the foreground buffer (RxFG). When a message gets shifted into the foreground buffer of the receiver FIFO the indicators are updated as well.
12.3.12 MSCAN Miscellaneous Register (CANMISC)

This register provides additional features.
R W Reset:
0 BOHOLD
= Unimplemented
Figure 12-16. MSCAN Miscellaneous Register (CANMISC)
Read: Anytime Write: Anytime; write of 1 clears ag; write of 0 ignored

Table 12-19. CANMISC Register Field Descriptions
Field 0 BOHOLD Description Bus-off State Hold Until User Request If BORM is set in Section 12.3.2, MSCAN Control Register 1 (CANCTL1), this bit indicates whether the module has entered the bus-off state. Clearing this bit requests the recovery from bus-off. Refer to Section 12.6.2, Bus-Off Recovery, for details. 0 Module is not bus-off or recovery has been requested by user in bus-off state 1 Module is bus-off and holds this state until user request
12.3.13 MSCAN Receive Error Counter (CANRXERR)

This register reects the status of the MSCAN receive error counter.
7 6 5 4 3 2 1 0
R W Reset:
RXERR7
RXERR6
RXERR5
RXERR4
RXERR3
RXERR2
RXERR1
RXERR0
= Unimplemented
Figure 12-17. MSCAN Receive Error Counter (CANRXERR)
Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1) Write: Unimplemented NOTE Reading this register when in any other mode other than sleep or initialization mode may return an incorrect value. For MCUs with dual CPUs, this may result in a CPU fault condition. Writing to this register when in special modes can alter the MSCAN functionality.
12.3.14 MSCAN Transmit Error Counter (CANTXERR)

This register reects the status of the MSCAN transmit error counter.
7 6 5 4 3 2 1 0
R W Reset:
TXERR7
TXERR6
TXERR5
TXERR4
TXERR3
TXERR2
TXERR1
TXERR0
= Unimplemented
Figure 12-18. MSCAN Transmit Error Counter (CANTXERR)
Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1) Write: Unimplemented NOTE Reading this register when in any other mode other than sleep or initialization mode, may return an incorrect value. For MCUs with dual CPUs, this may result in a CPU fault condition. Writing to this register when in special modes can alter the MSCAN functionality.
12.3.15 MSCAN Identier Acceptance Registers (CANIDAR0-7)

On reception, each message is written into the background receive buffer. The CPU is only signalled to read the message if it passes the criteria in the identier acceptance and identier mask registers (accepted); otherwise, the message is overwritten by the next message (dropped). The acceptance registers of the MSCAN are applied on the IDR0IDR3 registers (see Section 12.4.1, Identier Registers (IDR0IDR3)) of incoming messages in a bit by bit manner (see Section 12.5.3, Identier Acceptance Filter). For extended identiers, all four acceptance and mask registers are applied. For standard identiers, only the rst two (CANIDAR0/1, CANIDMR0/1) are applied.
7 6 5 4 3 2 1 0
R W Reset
AC7 0
AC6 0
AC5 0
AC4 0
AC3 0
AC2 0
AC1 0
AC0 0
Figure 12-19. MSCAN Identier Acceptance Registers (First Bank) CANIDAR0CANIDAR3
Table 12-20. CANIDAR0CANIDAR3 Register Field Descriptions

Field 7:0 AC[7:0] Description Acceptance Code Bits AC[7:0] comprise a user-dened sequence of bits with which the corresponding bits of the related identier register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the corresponding identier mask register.
R W Reset
AC7 0
AC6 0
AC5 0
AC4 0
AC3 0
AC2 0
AC1 0
AC0 0
Figure 12-20. MSCAN Identier Acceptance Registers (Second Bank) CANIDAR4CANIDAR7

Table 12-21. CANIDAR4CANIDAR7 Register Field Descriptions
Field 7:0 AC[7:0] Description Acceptance Code Bits AC[7:0] comprise a user-dened sequence of bits with which the corresponding bits of the related identier register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the corresponding identier mask register.
12.3.16 MSCAN Identier Mask Registers (CANIDMR0CANIDMR7)

The identier mask register species which of the corresponding bits in the identier acceptance register are relevant for acceptance ltering. To receive standard identiers in 32 bit lter mode, it is required to program the last three bits (AM[2:0]) in the mask registers CANIDMR1 and CANIDMR5 to dont care. To receive standard identiers in 16 bit lter mode, it is required to program the last three bits (AM[2:0]) in the mask registers CANIDMR1, CANIDMR3, CANIDMR5, and CANIDMR7 to dont care.
7 6 5 4 3 2 1 0
R W Reset
AM7 0
AM6 0
AM5 0
AM4 0
AM3 0
AM2 0
AM1 0
AM0 0
Figure 12-21. MSCAN Identier Mask Registers (First Bank) CANIDMR0CANIDMR3
Table 12-22. CANIDMR0CANIDMR3 Register Field Descriptions

Field 7:0 AM[7:0] Description Acceptance Mask Bits If a particular bit in this register is cleared, this indicates that the corresponding bit in the identier acceptance register must be the same as its identier bit before a match is detected. The message is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identier acceptance register does not affect whether or not the message is accepted. 0 Match corresponding acceptance code register and identier bits 1 Ignore corresponding acceptance code register bit (dont care)
R W Reset
AM7 0
AM6 0
AM5 0
AM4 0
AM3 0
AM2 0
AM1 0
AM0 0
Figure 12-22. MSCAN Identier Mask Registers (Second Bank) CANIDMR4CANIDMR7
Table 12-23. CANIDMR4CANIDMR7 Register Field Descriptions

Field 7:0 AM[7:0] Description Acceptance Mask Bits If a particular bit in this register is cleared, this indicates that the corresponding bit in the identier acceptance register must be the same as its identier bit before a match is detected. The message is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identier acceptance register does not affect whether or not the message is accepted. 0 Match corresponding acceptance code register and identier bits 1 Ignore corresponding acceptance code register bit (dont care)
12.4
Programmers Model of Message Storage
The following section details the organization of the receive and transmit message buffers and the associated control registers. To simplify the programmer interface, the receive and transmit message buffers have the same outline. Each message buffer allocates 16 bytes in the memory map containing a 13 byte data structure. An additional transmit buffer priority register (TBPR) is dened for the transmit buffers. Within the last two bytes of this memory map, the MSCAN stores a special 16-bit time stamp, which is sampled from an internal timer after successful transmission or reception of a message. This feature is only available for transmit and receiver buffers if the TIME bit is set (see Section 12.3.1, MSCAN Control Register 0 (CANCTL0)). The time stamp register is written by the MSCAN. The CPU can only read these registers.
Table 12-24. Message Buffer Organization

Offset Address 0x00X0 0x00X1 0x00X2 0x00X3 0x00X4 0x00X5 0x00X6 0x00X7 0x00X8 0x00X9 0x00XA 0x00XB 0x00XC 0x00XD 0x00XE 0x00XF
1 2
Register Identier Register 0 Identier Register 1 Identier Register 2 Identier Register 3 Data Segment Register 0 Data Segment Register 1 Data Segment Register 2 Data Segment Register 3 Data Segment Register 4 Data Segment Register 5 Data Segment Register 6 Data Segment Register 7 Data Length Register Transmit Buffer Priority Register1 Time Stamp Register (High Byte)2 Time Stamp Register (Low Byte)3
Access
Not applicable for receive buffers Read-only for CPU 3 Read-only for CPU
Figure 12-23 shows the common 13-byte data structure of receive and transmit buffers for extended identiers. The mapping of standard identiers into the IDR registers is shown in Figure 12-24. All bits of the receive and transmit buffers are x out of reset because of RAM-based implementation1. All reserved or unused bits of the receive and transmit buffers always read x.
1. Exception: The transmit priority registers are 0 out of reset. MC9S08DZ60 Series Data Sheet, Rev. 4 242 Freescale Semiconductor
Register Name IDR0 R W R W R IDR2 W R IDR3 W R DSR0 W R DSR1 W R DSR2 W R DSR3 W R DSR4 W R DSR5 W R DSR6 W R DSR7 W R DLR W
Bit 7 ID28
6 ID27
5 ID26
4 ID25
3 ID24
2 ID23
1 ID22
Bit0 ID21
IDR1
ID20
ID19
ID18
SRR(1)
IDE(1)
ID17
ID16
ID15
ID14
ID13
ID12
ID11
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR2
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DLC3
DLC2
DLC1
DLC0
= Unused, always read x
Figure 12-23. Receive/Transmit Message Buffer Extended Identier Mapping

1 2
SRR and IDE are both 1s. The position of RTR differs between extended and standard indentier mapping.
Read: For transmit buffers, anytime when TXEx ag is set (see Section 12.3.6, MSCAN Transmitter Flag Register (CANTFLG)) and the corresponding transmit buffer is selected in CANTBSEL (see
Section 12.3.10, MSCAN Transmit Buffer Selection Register (CANTBSEL)). For receive buffers, only when RXF ag is set (see Section 12.3.4.1, MSCAN Receiver Flag Register (CANRFLG)). Write: For transmit buffers, anytime when TXEx ag is set (see Section 12.3.6, MSCAN Transmitter Flag Register (CANTFLG)) and the corresponding transmit buffer is selected in CANTBSEL (see Section 12.3.10, MSCAN Transmit Buffer Selection Register (CANTBSEL)). Unimplemented for receive buffers. Reset: Undened (0x00XX) because of RAM-based implementation
Register Name IDR0 R W R W R W R W Bit 7 ID10 6 ID9 5 ID8 4 ID7 3 ID6 2 ID5 1 ID4 Bit 0 ID3
IDR1
ID2
ID1
ID0
RTR1
IDE2
IDR2
IDR3
= Unused, always read x
Figure 12-24. Receive/Transmit Message Buffer Standard Identier Mapping

1 2
The position of RTR differs between extended and standard indentier mapping. IDE is 0.
12.4.1
Identier Registers (IDR0IDR3)
The identier registers for an extended format identier consist of a total of 32 bits; ID[28:0], SRR, IDE, and RTR bits. The identier registers for a standard format identier consist of a total of 13 bits; ID[10:0], RTR, and IDE bits.
12.4.1.1
IDR0IDR3 for Extended Identier Mapping

7 6 5 4 3 2 1 0
R ID28 W Reset: x x x x x x x x ID27 ID26 ID25 ID24 ID23 ID22 ID21
Figure 12-25. Identier Register 0 (IDR0) Extended Identier Mapping
Table 12-25. IDR0 Register Field Descriptions Extended

Field 7:0 ID[28:21] Description Extended Format Identier The identiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most signicant bit and is transmitted rst on the CAN bus during the arbitration procedure. The priority of an identier is dened to be highest for the smallest binary number.
R ID20 W Reset: x x x ID19 ID18
SRR(1) x
IDE(1) x
ID17 x
ID16 x
ID15 x
Figure 12-26. Identier Register 1 (IDR1) Extended Identier Mapping

1
SRR and IDE are both 1s.
Table 12-26. IDR1 Register Field Descriptions Extended

Field 7:5 ID[20:18] 4 SRR 3 IDE Description Extended Format Identier The identiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most signicant bit and is transmitted rst on the CAN bus during the arbitration procedure. The priority of an identier is dened to be highest for the smallest binary number. Substitute Remote Request This xed recessive bit is used only in extended format. It must be set to 1 by the user for transmission buffers and is stored as received on the CAN bus for receive buffers. ID Extended This ag indicates whether the extended or standard identier format is applied in this buffer. In the case of a receive buffer, the ag is set as received and indicates to the CPU how to process the buffer identier registers. In the case of a transmit buffer, the ag indicates to the MSCAN what type of identier to send. 0 Standard format (11 bit) 1 Extended format (29 bit) Extended Format Identier The identiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most signicant bit and is transmitted rst on the CAN bus during the arbitration procedure. The priority of an identier is dened to be highest for the smallest binary number.
2:0 ID[17:15]
Figure 12-27. Identier Register 2 (IDR2) Extended Identier Mapping Table 12-27. IDR2 Register Field Descriptions Extended
Field 7:0 ID[14:7] Description Extended Format Identier The identiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most signicant bit and is transmitted rst on the CAN bus during the arbitration procedure. The priority of an identier is dened to be highest for the smallest binary number.
R ID6 W Reset: x x x x x x x x ID5 ID4 ID3 ID2 ID1 ID0 RTR
Figure 12-28. Identier Register 3 (IDR3) Extended Identier Mapping Table 12-28. IDR3 Register Field Descriptions Extended
Field 7:1 ID[6:0] 0 RTR Description Extended Format Identier The identiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most signicant bit and is transmitted rst on the CAN bus during the arbithation procedure. The priority of an identier is dened to be highest for the smallest binary number. Remote Transmission Request This ag reects the status of the remote transmission request bit in the CAN frame. In the case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. In the case of a transmit buffer, this ag denes the setting of the RTR bit to be sent. 0 Data frame 1 Remote frame
12.4.2
IDR0IDR3 for Standard Identier Mapping

7 6 5 4 3 2 1 0
Figure 12-29. Identier Register 0 Standard Mapping Table 12-29. IDR0 Register Field Descriptions Standard
Field 7:0 ID[10:3] Description Standard Format Identier The identiers consist of 11 bits (ID[10:0]) for the standard format. ID10 is the most signicant bit and is transmitted rst on the CAN bus during the arbitration procedure. The priority of an identier is dened to be highest for the smallest binary number. See also ID bits in Table 12-30.
R ID2 W Reset: x x x x ID1 ID0 RTR
IDE(1) x x x x
= Unused; always read x
Figure 12-30. Identier Register 1 Standard Mapping

1
IDE is 0.
Table 12-30. IDR1 Register Field Descriptions

Field 7:5 ID[2:0] 4 RTR Description Standard Format Identier The identiers consist of 11 bits (ID[10:0]) for the standard format. ID10 is the most signicant bit and is transmitted rst on the CAN bus during the arbitration procedure. The priority of an identier is dened to be highest for the smallest binary number. See also ID bits in Table 12-29. Remote Transmission Request This ag reects the status of the Remote Transmission Request bit in the CAN frame. In the case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. In the case of a transmit buffer, this ag denes the setting of the RTR bit to be sent. 0 Data frame 1 Remote frame ID Extended This ag indicates whether the extended or standard identier format is applied in this buffer. In the case of a receive buffer, the ag is set as received and indicates to the CPU how to process the buffer identier registers. In the case of a transmit buffer, the ag indicates to the MSCAN what type of identier to send. 0 Standard format (11 bit) 1 Extended format (29 bit)
3 IDE
R W Reset: x x x x x x x x

7 6 5 4 3 2 1 0
R W Reset: x x x x x x x x
12.4.3
Data Segment Registers (DSR0-7)
The eight data segment registers, each with bits DB[7:0], contain the data to be transmitted or received. The number of bytes to be transmitted or received is determined by the data length code in the corresponding DLR register.
R DB7 W Reset: x x x x x x x x DB6 DB5 DB4 DB3 DB2 DB1 DB0
Figure 12-33. Data Segment Registers (DSR0DSR7) Extended Identier Mapping
Table 12-31. DSR0DSR7 Register Field Descriptions

Field 7:0 DB[7:0] Data bits 7:0 Description
12.4.4
Data Length Register (DLR)
This register keeps the data length eld of the CAN frame.
7 6 5 4 3 2 1 0
R DLC3 W Reset: x x x x x x x x DLC2 DLC1 DLC0
Figure 12-34. Data Length Register (DLR) Extended Identier Mapping
Table 12-32. DLR Register Field Descriptions

Field 3:0 DLC[3:0] Description Data Length Code Bits The data length code contains the number of bytes (data byte count) of the respective message. During the transmission of a remote frame, the data length code is transmitted as programmed while the number of transmitted data bytes is always 0. The data byte count ranges from 0 to 8 for a data frame. Table 12-33 shows the effect of setting the DLC bits.
Table 12-33. Data Length Codes

Data Length Code DLC3 0 0 0 0 0 0 0 0 1 DLC2 0 0 0 0 1 1 1 1 0 DLC1 0 0 1 1 0 0 1 1 0 DLC0 0 1 0 1 0 1 0 1 0 Data Byte Count 0 1 2 3 4 5 6 7 8
12.4.5
Transmit Buffer Priority Register (TBPR)
This register denes the local priority of the associated message transmit buffer. The local priority is used for the internal prioritization process of the MSCAN and is dened to be highest for the smallest binary number. The MSCAN implements the following internal prioritization mechanisms: All transmission buffers with a cleared TXEx ag participate in the prioritization immediately before the SOF (start of frame) is sent. The transmission buffer with the lowest local priority eld wins the prioritization. In cases of more than one buffer having the same lowest priority, the message buffer with the lower index number wins.
7 6 5 4 3 2 1 0
R PRIO7 W Reset: 0 0 0 0 0 0 0 0 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0
Figure 12-35. Transmit Buffer Priority Register (TBPR)
Read: Anytime when TXEx ag is set (see Section 12.3.6, MSCAN Transmitter Flag Register (CANTFLG)) and the corresponding transmit buffer is selected in CANTBSEL (see Section 12.3.10, MSCAN Transmit Buffer Selection Register (CANTBSEL)). Write: Anytime when TXEx ag is set (see Section 12.3.6, MSCAN Transmitter Flag Register (CANTFLG)) and the corresponding transmit buffer is selected in CANTBSEL (see Section 12.3.10, MSCAN Transmit Buffer Selection Register (CANTBSEL)).
12.4.6
Time Stamp Register (TSRHTSRL)
If the TIME bit is enabled, the MSCAN will write a time stamp to the respective registers in the active transmit or receive buffer as soon as a message has been acknowledged on the CAN bus (see
Section 12.3.1, MSCAN Control Register 0 (CANCTL0)). In case of a transmission, the CPU can only read the time stamp after the respective transmit buffer has been agged empty. The timer value, which is used for stamping, is taken from a free running internal CAN bit clock. A timer overrun is not indicated by the MSCAN. The timer is reset (all bits set to 0) during initialization mode. The CPU can only read the time stamp registers.
7 6 5 4 3 2 1 0
R W Reset:
TSR15
TSR14
TSR13
TSR12
TSR11
TSR10
TSR9
TSR8
Figure 12-36. Time Stamp Register High Byte (TSRH)

7 6 5 4 3 2 1 0
R W Reset:
TSR7
TSR6
TSR5
TSR4
TSR3
TSR2
TSR1
TSR0
Figure 12-37. Time Stamp Register Low Byte (TSRL)
Read: Anytime when TXEx ag is set (see Section 12.3.6, MSCAN Transmitter Flag Register (CANTFLG)) and the corresponding transmit buffer is selected in CANTBSEL (see Section 12.3.10, MSCAN Transmit Buffer Selection Register (CANTBSEL)). Write: Unimplemented
12.5
12.5.1
General
This section provides a complete functional description of the MSCAN. It describes each of the features and modes listed in the introduction.
12.5.2
Message Storage
CAN Receive / Transmit Engine CPU12 Memory Mapped I/O
Rx0
Rx1 Rx2 Rx3 Rx4
RXF
RxBG
MSCAN
Receiver
Tx0
RxFG
CPU bus
TXE0
TxBG
Tx1
PRIO
TXE1
TxFG
MSCAN
CPU bus
PRIO
Tx2
TXE2
Transmitter
TxBG
PRIO
Figure 12-38. User Model for Message Buffer Organization
MSCAN facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications.
12.5.2.1
Message Transmit Background
Modern application layer software is built upon two fundamental assumptions: Any CAN node is able to send out a stream of scheduled messages without releasing the CAN bus between the two messages. Such nodes arbitrate for the CAN bus immediately after sending the previous message and only release the CAN bus in case of lost arbitration. The internal message queue within any CAN node is organized such that the highest priority message is sent out rst, if more than one message is ready to be sent. The behavior described in the bullets above cannot be achieved with a single transmit buffer. That buffer must be reloaded immediately after the previous message is sent. This loading process lasts a nite amount of time and must be completed within the inter-frame sequence (IFS) to be able to send an uninterrupted stream of messages. Even if this is feasible for limited CAN bus speeds, it requires that the CPU reacts with short latencies to the transmit interrupt. A double buffer scheme de-couples the reloading of the transmit buffer from the actual message sending and, therefore, reduces the reactiveness requirements of the CPU. Problems can arise if the sending of a message is nished while the CPU re-loads the second buffer. No buffer would then be ready for transmission, and the CAN bus would be released. At least three transmit buffers are required to meet the rst of the above requirements under all circumstances. The MSCAN has three transmit buffers. The second requirement calls for some sort of internal prioritization which the MSCAN implements with the local priority concept described in Section 12.5.2.2, Transmit Structures.
12.5.2.2
Transmit Structures
The MSCAN triple transmit buffer scheme optimizes real-time performance by allowing multiple messages to be set up in advance. The three buffers are arranged as shown in Figure 12-38. All three buffers have a 13-byte data structure similar to the outline of the receive buffers (see Section 12.4, Programmers Model of Message Storage). An additional Section 12.4.5, Transmit Buffer Priority Register (TBPR) contains an 8-bit local priority eld (PRIO) (see Section 12.4.5, Transmit Buffer Priority Register (TBPR)). The remaining two bytes are used for time stamping of a message, if required (see Section 12.4.6, Time Stamp Register (TSRHTSRL)). To transmit a message, the CPU must identify an available transmit buffer, which is indicated by a set transmitter buffer empty (TXEx) ag (see Section 12.3.6, MSCAN Transmitter Flag Register (CANTFLG)). If a transmit buffer is available, the CPU must set a pointer to this buffer by writing to the CANTBSEL register (see Section 12.3.10, MSCAN Transmit Buffer Selection Register (CANTBSEL)). This makes the respective buffer accessible within the CANTXFG address space (see Section 12.4, Programmers Model of Message Storage). The algorithmic feature associated with the CANTBSEL register simplies the transmit buffer selection. In addition, this scheme makes the handler software simpler because only one address area is applicable for the transmit process, and the required address space is minimized. The CPU then stores the identier, the control bits, and the data content into one of the transmit buffers. Finally, the buffer is agged as ready for transmission by clearing the associated TXE ag.
The MSCAN then schedules the message for transmission and signals the successful transmission of the buffer by setting the associated TXE ag. A transmit interrupt (see Section 12.5.7.2, Transmit Interrupt) is generated1 when TXEx is set and can be used to drive the application software to re-load the buffer. If more than one buffer is scheduled for transmission when the CAN bus becomes available for arbitration, the MSCAN uses the local priority setting of the three buffers to determine the prioritization. For this purpose, every transmit buffer has an 8-bit local priority eld (PRIO). The application software programs this eld when the message is set up. The local priority reects the priority of this particular message relative to the set of messages being transmitted from this node. The lowest binary value of the PRIO eld is dened to be the highest priority. The internal scheduling process takes place whenever the MSCAN arbitrates for the CAN bus. This is also the case after the occurrence of a transmission error. When a high priority message is scheduled by the application software, it may become necessary to abort a lower priority message in one of the three transmit buffers. Because messages that are already in transmission cannot be aborted, the user must request the abort by setting the corresponding abort request bit (ABTRQ) (see Section 12.3.8, MSCAN Transmitter Message Abort Request Register (CANTARQ).) The MSCAN then grants the request, if possible, by: 1. Setting the corresponding abort acknowledge ag (ABTAK) in the CANTAAK register. 2. Setting the associated TXE ag to release the buffer. 3. Generating a transmit interrupt. The transmit interrupt handler software can determine from the setting of the ABTAK ag whether the message was aborted (ABTAK = 1) or sent (ABTAK = 0).
12.5.2.3
Receive Structures
The received messages are stored in a ve stage input FIFO. The ve message buffers are alternately mapped into a single memory area (see Figure 12-38). The background receive buffer (RxBG) is exclusively associated with the MSCAN, but the foreground receive buffer (RxFG) is addressable by the CPU (see Figure 12-38). This scheme simplies the handler software because only one address area is applicable for the receive process. All receive buffers have a size of 15 bytes to store the CAN control bits, the identier (standard or extended), the data contents, and a time stamp, if enabled (see Section 12.4, Programmers Model of Message Storage). The receiver full ag (RXF) (see Section 12.3.4.1, MSCAN Receiver Flag Register (CANRFLG)) signals the status of the foreground receive buffer. When the buffer contains a correctly received message with a matching identier, this ag is set. On reception, each message is checked to see whether it passes the lter (see Section 12.5.3, Identier Acceptance Filter) and simultaneously is written into the active RxBG. After successful reception of a valid message, the MSCAN shifts the content of RxBG into the receiver FIFO2, sets the RXF ag, and generates a receive interrupt (see Section 12.5.7.3, Receive Interrupt) to the CPU3. The users receive handler must read the received message from the RxFG and then reset the RXF ag to acknowledge the interrupt and to release the foreground buffer. A new message, which can follow immediately after the IFS
1. The transmit interrupt occurs only if not masked. A polling scheme can be applied on TXEx also. 2. Only if the RXF ag is not set. 3. The receive interrupt occurs only if not masked. A polling scheme can be applied on RXF also. MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 253
eld of the CAN frame, is received into the next available RxBG. If the MSCAN receives an invalid message in its RxBG (wrong identier, transmission errors, etc.) the actual contents of the buffer will be over-written by the next message. The buffer will then not be shifted into the FIFO. When the MSCAN module is transmitting, the MSCAN receives its own transmitted messages into the background receive buffer, RxBG, but does not shift it into the receiver FIFO, generate a receive interrupt, or acknowledge its own messages on the CAN bus. The exception to this rule is in loopback mode (see Section 12.3.2, MSCAN Control Register 1 (CANCTL1)) where the MSCAN treats its own messages exactly like all other incoming messages. The MSCAN receives its own transmitted messages in the event that it loses arbitration. If arbitration is lost, the MSCAN must be prepared to become a receiver. An overrun condition occurs when all receive message buffers in the FIFO are lled with correctly received messages with accepted identiers and another message is correctly received from the CAN bus with an accepted identier. The latter message is discarded and an error interrupt with overrun indication is generated if enabled (see Section 12.5.7.5, Error Interrupt). The MSCAN remains able to transmit messages while the receiver FIFO is full, but all incoming messages are discarded. As soon as a receive buffer in the FIFO is available again, new valid messages will be accepted.
12.5.3
Identier Acceptance Filter
The MSCAN identier acceptance registers (see Section 12.3.11, MSCAN Identier Acceptance Control Register (CANIDAC)) dene the acceptable patterns of the standard or extended identier (ID[10:0] or ID[28:0]). Any of these bits can be marked dont care in the MSCAN identier mask registers (see Section 12.3.16, MSCAN Identier Mask Registers (CANIDMR0CANIDMR7)). A lter hit is indicated to the application software by a set receive buffer full ag (RXF = 1) and three bits in the CANIDAC register (see Section 12.3.11, MSCAN Identier Acceptance Control Register (CANIDAC)). These identier hit ags (IDHIT[2:0]) clearly identify the lter section that caused the acceptance. They simplify the application softwares task to identify the cause of the receiver interrupt. If more than one hit occurs (two or more lters match), the lower hit has priority. A very exible programmable generic identier acceptance lter has been introduced to reduce the CPU interrupt loading. The lter is programmable to operate in four different modes (see Bosch CAN 2.0A/B protocol specication): Two identier acceptance lters, each to be applied to: The full 29 bits of the extended identier and to the following bits of the CAN 2.0B frame: Remote transmission request (RTR) Identier extension (IDE) Substitute remote request (SRR) The 11 bits of the standard identier plus the RTR and IDE bits of the CAN 2.0A/B messages1. This mode implements two lters for a full length CAN 2.0B compliant extended identier. Figure 12-39 shows how the rst 32-bit lter bank (CANIDAR0CANIDAR3, CANIDMR0CANIDMR3) produces a lter 0 hit. Similarly, the second lter bank (CANIDAR4CANIDAR7, CANIDMR4CANIDMR7) produces a lter 1 hit.
1.Although this mode can be used for standard identifiers, it is recommended to use the four or eight identifier acceptance filters for standard identifiers MC9S08DZ60 Series Data Sheet, Rev. 4 254 Freescale Semiconductor
Four identier acceptance lters, each to be applied to a) the 14 most signicant bits of the extended identier plus the SRR and IDE bits of CAN 2.0B messages or b) the 11 bits of the standard identier, the RTR and IDE bits of CAN 2.0A/B messages. Figure 12-40 shows how the rst 32-bit lter bank (CANIDAR0CANIDA3, CANIDMR03CANIDMR) produces lter 0 and 1 hits. Similarly, the second lter bank (CANIDAR4CANIDAR7, CANIDMR4CANIDMR7) produces lter 2 and 3 hits. Eight identier acceptance lters, each to be applied to the rst 8 bits of the identier. This mode implements eight independent lters for the rst 8 bits of a CAN 2.0A/B compliant standard identier or a CAN 2.0B compliant extended identier. Figure 12-41 shows how the rst 32-bit lter bank (CANIDAR0CANIDAR3, CANIDMR0CANIDMR3) produces lter 0 to 3 hits. Similarly, the second lter bank (CANIDAR4CANIDAR7, CANIDMR4CANIDMR7) produces lter 4 to 7 hits. Closed lter. No CAN message is copied into the foreground buffer RxFG, and the RXF ag is never set.
IDR0 IDR0 ID21 ID3 ID20 ID2 IDR1 IDR1 ID15 IDE ID14 ID10 IDR2 IDR2 ID7 ID3 ID6 ID10 IDR3 IDR3 RTR ID3
CAN 2.0B Extended Identier ID28 CAN 2.0A/B Standard Identier ID10
AM7
CANIDMR0
AM0
AM7
CANIDMR1
AM0
AM7
CANIDMR2
AM0
AM7
CANIDMR3
AM0
AC7
CANIDAR0
AC0
AC7
CANIDAR1
AC0
AC7
CANIDAR2
AC0
AC7
CANIDAR3
AC0
ID Accepted (Filter 0 Hit)
Figure 12-39. 32-bit Maskable Identier Acceptance Filter
CAN 2.0B Extended Identier CAN 2.0A/B Standard Identier
ID28 ID10
IDR0 IDR0
ID21 ID3
ID20 ID2
IDR1 IDR1
ID15 IDE
ID14 ID10
IDR2 IDR2
ID7 ID3
ID6 ID10
IDR3 IDR3
RTR ID3
AM7
CANIDMR0
AM0
AM7
CANIDMR1
AM0
AC7
CANIDAR0
AC0
AC7
CANIDAR1
AC0
AM7
CANIDMR2
AM0
AM7
CANIDMR3
AM0
AC7
CANIDAR2
AC0
AC7
CANIDAR3
AC0
Figure 12-40. 16-bit Maskable Identier Acceptance Filters
CAN 2.0B Extended Identier ID28 CAN 2.0A/B Standard Identier ID10
IDR0 IDR0
ID21 ID3
ID20 ID2
IDR1 IDR1
ID15 IDE
ID14 ID10
IDR2 IDR2
ID7 ID3
ID6 ID10
IDR3 IDR3
RTR ID3
AM7
CIDMR0
AM0
AC7
CIDAR0
AC0
AM7
CIDMR1
AM0
AC7
CIDAR1
AC0
AM7
CIDMR2
AM0
AC7
CIDAR2
AC0
AM7
CIDMR3
AM0
AC7
CIDAR3
AC0
Figure 12-41. 8-bit Maskable Identier Acceptance Filters
MSCAN lter uses three sets of registers to provide the lter conguration. Firstly, the CANIDAC register determines the conguration of the banks into lter sizes and number of lters. Secondly, registers CANIDMR0/1/2/3 determine those bits on which the lter will operate by placing a 0 at the appropriate
bit position in the lter register. Finally, registers CANIDAR0/1/2/3 determine the value of those bits determined by CANIDMR0/1/2/3. For instance in the case of the lter value of: 0001x1001x0 The CANIDMR0/1/2/3 register would be congured as: 00001000010 and so all message identier bits except bit 1 and bit 6 would be compared against the CANIDAR0/1/2/3 registers. These would be congured as: 00010100100 In this case bits 1 and 6 are set to 0, but since they are ignored it is equally valid to set them to 1.
12.5.3.1
Identier Acceptance Filters example
As described above, lters work by comparisons to individual bits in the CAN message identier eld. The lter will check each one of the eleven bits of a standard CAN message identier. Suppose a lter value of 0001x1001x0. In this simple example, there are only three possible CAN messages. Filter value: 0001x1001x0 Message 1: 00011100110 Message 2: 00110100110 Message 3: 00010100100 Message 2 will be rejected since its third most signicant bit is not 0 - 001. The lter is simply a convenient way of dening the set of messages that the CPU must receive. For full 29-bits of an extended CAN message identier, the lter identies two sets of messages: one set that it receives and one set that it rejects. Alternatively, the lter may be split into two. This allows the MSCAN to examine only the rst 16 bits of a message identier, but allows two separate lters to perform the checking. See the example below: Filter value A: 0001x1001x0 Filter value B: 00x101x01x0 Message 1: 00011100110 Message 2: 00110100110 Message 3: 00010100100 MSCAN will accept all three messages. Filter A will accept messages 1 and 3 as before and lter B will accept message 2. In practice, it is unimportant which lter accepts the message - messages accepted by either will be placed in the input buffer. A message may be accepted by more than one lter.
12.5.3.2
Protocol Violation Protection
The MSCAN protects the user from accidentally violating the CAN protocol through programming errors. The protection logic implements the following features: The receive and transmit error counters cannot be written or otherwise manipulated. All registers which control the conguration of the MSCAN cannot be modied while the MSCAN is on-line. The MSCAN has to be in Initialization Mode. The corresponding INITRQ/INITAK handshake bits in the CANCTL0/CANCTL1 registers (see Section 12.3.1, MSCAN Control Register 0 (CANCTL0)) serve as a lock to protect the following registers: MSCAN control 1 register (CANCTL1) MSCAN bus timing registers 0 and 1 (CANBTR0, CANBTR1) MSCAN identier acceptance control register (CANIDAC) MSCAN identier acceptance registers (CANIDAR0CANIDAR7) MSCAN identier mask registers (CANIDMR0CANIDMR7) The TXCAN pin is immediately forced to a recessive state when the MSCAN goes into the power down mode or initialization mode (see Section 12.5.5.6, MSCAN Power Down Mode, and Section 12.5.5.5, MSCAN Initialization Mode). The MSCAN enable bit (CANE) is writable only once in normal system operation modes, which provides further protection against inadvertently disabling the MSCAN.
12.5.3.3
Clock System
Figure 12-42 shows the structure of the MSCAN clock generation circuitry.
MSCAN
Bus Clock
CANCLK CLKSRC
Prescaler (1 .. 64)
Time quanta clock (Tq)
CLKSRC Oscillator Clock
Figure 12-42. MSCAN Clocking Scheme
The clock source bit (CLKSRC) in the CANCTL1 register (12.3.2/-226) denes whether the internal CANCLK is connected to the output of a crystal oscillator (oscillator clock) or to the bus clock. The clock source has to be chosen such that the tight oscillator tolerance requirements (up to 0.4%) of the CAN protocol are met. Additionally, for high CAN bus rates (1 Mbps), a 45% to 55% duty cycle of the clock is required.
If the bus clock is generated from a PLL, it is recommended to select the oscillator clock rather than the bus clock due to jitter considerations, especially at the faster CAN bus rates. PLL lock may also be too wide to ensure adequate clock tolerance. For microcontrollers without a clock and reset generator (CRG), CANCLK is driven from the crystal oscillator (oscillator clock). A programmable prescaler generates the time quanta (Tq) clock from CANCLK. A time quantum is the atomic unit of time handled by the MSCAN.
Eqn. 12-2
f CANCLK = ----------------------------------------------------Tq ( Prescaler value ) A bit time is subdivided into three segments as described in the Bosch CAN specication. (see Figure 12-43): SYNC_SEG: This segment has a xed length of one time quantum. Signal edges are expected to happen within this section. Time Segment 1: This segment includes the PROP_SEG and the PHASE_SEG1 of the CAN standard. It can be programmed by setting the parameter TSEG1 to consist of 4 to 16 time quanta. Time Segment 2: This segment represents the PHASE_SEG2 of the CAN standard. It can be programmed by setting the TSEG2 parameter to be 2 to 8 time quanta long.
Eqn. 12-3
f Tq Bit Rate = -------------------------------------------------------------------------------( number of Time Quanta )
NRZ Signal
SYNC_SEG
Time Segment 1 (PROP_SEG + PHASE_SEG1) 4 ... 16 8 ... 25 Time Quanta = 1 Bit Time
Time Segment 2 (PHASE_SEG2) 2 ... 8
Transmit Point
Sample Point (single or triple sampling)
Figure 12-43. Segments within the Bit Time
Table 12-34. Time Segment Syntax

Syntax SYNC_SEG Transmit Point Description System expects transitions to occur on the CAN bus during this period. A node in transmit mode transfers a new value to the CAN bus at this point. A node in receive mode samples the CAN bus at this point. If the three samples per bit option is selected, then this point marks the position of the third sample.
Sample Point
The synchronization jump width (see the Bosch CAN specication for details) can be programmed in a range of 1 to 4 time quanta by setting the SJW parameter. The SYNC_SEG, TSEG1, TSEG2, and SJW parameters are set by programming the MSCAN bus timing registers (CANBTR0, CANBTR1) (see Section 12.3.3, MSCAN Bus Timing Register 0 (CANBTR0) and Section 12.3.4, MSCAN Bus Timing Register 1 (CANBTR1)). Table 12-35 gives an overview of the CAN compliant segment settings and the related parameter values. NOTE It is the users responsibility to ensure the bit time settings are in compliance with the CAN standard.
Table 12-35. CAN Standard Compliant Bit Time Segment Settings
Time Segment 1 5 .. 10 4 .. 11 5 .. 12 6 .. 13 7 .. 14 8 .. 15 9 .. 16 TSEG1 4 .. 9 3 .. 10 4 .. 11 5 .. 12 6 .. 13 7 .. 14 8 .. 15 Time Segment 2 2 3 4 5 6 7 8 TSEG2 1 2 3 4 5 6 7 Synchronization Jump Width 1 .. 2 1 .. 3 1 .. 4 1 .. 4 1 .. 4 1 .. 4 1 .. 4 SJW 0 .. 1 0 .. 2 0 .. 3 0 .. 3 0 .. 3 0 .. 3 0 .. 3
12.5.4
12.5.4.1
Modes of Operation
Normal Modes
The MSCAN module behaves as described within this specication in all normal system operation modes.
12.5.4.2
Special Modes
The MSCAN module behaves as described within this specication in all special system operation modes.
12.5.4.3
Emulation Modes
In all emulation modes, the MSCAN module behaves just like normal system operation modes as described within this specication.
12.5.4.4
Listen-Only Mode
In an optional CAN bus monitoring mode (listen-only), the CAN node is able to receive valid data frames and valid remote frames, but it sends only recessive bits on the CAN bus. In addition, it cannot start a transmision. If the MAC sub-layer is required to send a dominant bit (ACK bit, overload ag, or active error ag), the bit is rerouted internally so that the MAC sub-layer monitors this dominant bit, although the CAN bus may remain in recessive state externally.
12.5.4.5
Security Modes
The MSCAN module has no security features.
12.5.4.6
Loopback Self Test Mode
Loopback self test mode is sometimes used to check software, independent of connections in the external system, to help isolate system problems. In this mode, the transmitter output is internally connected to the receiver input. The RXCAN input pin is ignored and the TXCAN output goes to the recessive state (logic 1). The MSCAN behaves as it does normally when transmitting and treats its own transmitted message as a message received from a remote node. In this state, the MSCAN ignores the bit sent during the ACK slot in the CAN frame acknowledge eld to ensure proper reception of its own message. Both transmit and receive interrupts are generated.
12.5.5
Low-Power Options
If the MSCAN is disabled (CANE = 0), the MSCAN clocks are stopped for power saving. If the MSCAN is enabled (CANE = 1), the MSCAN has two additional modes with reduced power consumption, compared to normal mode: sleep and power down mode. In sleep mode, power consumption is reduced by stopping all clocks except those to access the registers from the CPU side. In power down mode, all clocks are stopped and no power is consumed. Table 12-36 summarizes the combinations of MSCAN and CPU modes. A particular combination of modes is entered by the given settings on the CSWAI and SLPRQ/SLPAK bits. For all modes, an MSCAN wake-up interrupt can occur only if the MSCAN is in sleep mode (SLPRQ = 1 and SLPAK = 1), wake-up functionality is enabled (WUPE = 1), and the wake-up interrupt is enabled (WUPIE = 1).
Table 12-36. CPU vs. MSCAN Operating Modes

MSCAN Mode CPU Mode Normal Sleep CSWAI = X1 SLPRQ = 0 SLPAK = 0 CSWAI = 0 SLPRQ = 0 SLPAK = 0 CSWAI = X SLPRQ = 1 SLPAK = 1 CSWAI = 0 SLPRQ = 1 SLPAK = 1 CSWAI = X2 SLPRQ = 1 SLPAK = 1 CSWAI = 1 SLPRQ = X SLPAK = X CSWAI = X SLPRQ = 0 SLPAK = 0 CSWAI = X SLPRQ = X SLPAK = X Power Down Reduced Power Consumption Disabled (CANE=0) CSWAI = X SLPRQ = X SLPAK = X CSWAI = X SLPRQ = X SLPAK = X CSWAI = X SLPRQ = X SLPAK = X CSWAI = X SLPRQ = X SLPAK = X
Run
Wait
Stop3
Stop1 or 2
1 2
X means dont care. For a safe wake up from Sleep mode, SLPRQ and SLPAK must be set to 1 before going into Stop3 mode.
12.5.5.1
Operation in Run Mode
As shown in Table 12-36, only MSCAN sleep mode is available as low power option when the CPU is in run mode.
12.5.5.2
Operation in Wait Mode
The WAIT instruction puts the MCU in a low power consumption stand-by mode. If the CSWAI bit is set, additional power can be saved in power down mode because the CPU clocks are stopped. After leaving this power down mode, the MSCAN restarts its internal controllers and enters normal mode again. While the CPU is in wait mode, the MSCAN can be operated in normal mode and generate interrupts (registers can be accessed via background debug mode). The MSCAN can also operate in any of the low-power modes depending on the values of the SLPRQ/SLPAK and CSWAI bits as seen in Table 12-36.
12.5.5.3
Operation in Stop Mode
The STOP instruction puts the MCU in a low power consumption stand-by mode. In stop1 or stop2 modes, the MSCAN is set in power down mode regardless of the value of the SLPRQ/SLPAK. In stop3 mode, power down or sleep modes are determined by the SLPRQ/SLPAK values set prior to entering stop3. CSWAI bit has no function in any of the stop modes.Table 12-36.
12.5.5.4
MSCAN Sleep Mode
The CPU can request the MSCAN to enter this low power mode by asserting the SLPRQ bit in the CANCTL0 register. The time when the MSCAN enters sleep mode depends on a xed synchronization delay and its current activity: If there are one or more message buffers scheduled for transmission (TXEx = 0), the MSCAN will continue to transmit until all transmit message buffers are empty (TXEx = 1, transmitted successfully or aborted) and then goes into sleep mode. If the MSCAN is receiving, it continues to receive and goes into sleep mode as soon as the CAN bus next becomes idle. If the MSCAN is neither transmitting nor receiving, it immediately goes into sleep mode.
Bus Clock Domain
CAN Clock Domain SLPRQ Flag
SLPRQ CPU Sleep Request
SYNC
sync. SLPRQ
SLPAK Flag
sync.
SLPAK
SYNC
SLPAK MSCAN in Sleep Mode
Figure 12-44. Sleep Request / Acknowledge Cycle
NOTE The application software must avoid setting up a transmission (by clearing one or more TXEx ag(s)) and immediately request sleep mode (by setting SLPRQ). Whether the MSCAN starts transmitting or goes into sleep mode directly depends on the exact sequence of operations. If sleep mode is active, the SLPRQ and SLPAK bits are set (Figure 12-44). The application software must use SLPAK as a handshake indication for the request (SLPRQ) to go into sleep mode. When in sleep mode (SLPRQ = 1 and SLPAK = 1), the MSCAN stops its internal clocks. However, clocks that allow register accesses from the CPU side continue to run. If the MSCAN is in bus-off state, it stops counting the 128 occurrences of 11 consecutive recessive bits due to the stopped clocks. The TXCAN pin remains in a recessive state. If RXF = 1, the message can be read and RXF can be cleared. Shifting a new message into the foreground buffer of the receiver FIFO (RxFG) does not take place while in sleep mode. It is possible to access the transmit buffers and to clear the associated TXE ags. No message abort takes place while in sleep mode.
If the WUPE bit in CANCLT0 is not asserted, the MSCAN will mask any activity it detects on CAN. The RXCAN pin is therefore held internally in a recessive state. This locks the MSCAN in sleep mode (Figure 12-45). WUPE must be set before entering sleep mode to take effect.
The MSCAN is able to leave sleep mode (wake up) only when: CAN bus activity occurs and WUPE = 1 or the CPU clears the SLPRQ bit NOTE The CPU cannot clear the SLPRQ bit before sleep mode (SLPRQ = 1 and SLPAK = 1) is active. After wake-up, the MSCAN waits for 11 consecutive recessive bits to synchronize to the CAN bus. As a consequence, if the MSCAN is woken-up by a CAN frame, this frame is not received. The receive message buffers (RxFG and RxBG) contain messages if they were received before sleep mode was entered. All pending actions will be executed upon wake-up; copying of RxBG into RxFG, message aborts and message transmissions. If the MSCAN remains in bus-off state after sleep mode was exited, it continues counting the 128 occurrences of 11 consecutive recessive bits.
CAN Activity
StartUp
Wait for Idle

CAN Activity SLPRQ
(CAN Activity & WUPE) | SLPRQ
CAN Activity & SLPRQ
Idle
Sleep
(CAN Activity & WUPE) |
CAN Activity & SLPRQ
CAN Activity CAN Activity
Tx/Rx Message Active
CAN Activity
Figure 12-45. Simplied State Transitions for Entering/Leaving Sleep Mode
12.5.5.5
MSCAN Initialization Mode
In initialization mode, any on-going transmission or reception is immediately aborted and synchronization to the CAN bus is lost, potentially causing CAN protocol violations. To protect the CAN bus system from fatal consequences of violations, the MSCAN immediately drives the TXCAN pin into a recessive state. NOTE The user is responsible for ensuring that the MSCAN is not active when initialization mode is entered. The recommended procedure is to bring the MSCAN into sleep mode (SLPRQ = 1 and SLPAK = 1) before setting the INITRQ bit in the CANCTL0 register. Otherwise, the abort of an on-going message can cause an error condition and can impact other CAN bus devices. In initialization mode, the MSCAN is stopped. However, interface registers remain accessible. This mode is used to reset the CANCTL0, CANRFLG, CANRIER, CANTFLG, CANTIER, CANTARQ, CANTAAK, and CANTBSEL registers to their default values. In addition, the MSCAN enables the conguration of the CANBTR0, CANBTR1 bit timing registers; CANIDAC; and the CANIDAR, CANIDMR message lters. See Section 12.3.1, MSCAN Control Register 0 (CANCTL0), for a detailed description of the initialization mode.
Bus Clock Domain
CAN Clock Domain INIT Flag
INITRQ CPU Init Request
SYNC
sync. INITRQ
INITAK Flag
sync.
INITAK
SYNC
INITAK
Figure 12-46. Initialization Request/Acknowledge Cycle
Due to independent clock domains within the MSCAN, INITRQ must be synchronized to all domains by using a special handshake mechanism. This handshake causes additional synchronization delay (see Section Figure 12-46., Initialization Request/Acknowledge Cycle). If there is no message transfer ongoing on the CAN bus, the minimum delay will be two additional bus clocks and three additional CAN clocks. When all parts of the MSCAN are in initialization mode, the INITAK ag is set. The application software must use INITAK as a handshake indication for the request (INITRQ) to go into initialization mode. NOTE The CPU cannot clear INITRQ before initialization mode (INITRQ = 1 and INITAK = 1) is active.
12.5.5.6
MSCAN Power Down Mode
The MSCAN is in power down mode (Table 12-36) when CPU is in stop mode or CPU is in wait mode and the CSWAI bit is set When entering the power down mode, the MSCAN immediately stops all ongoing transmissions and receptions, potentially causing CAN protocol violations. To protect the CAN bus system from fatal consequences of violations to the above rule, the MSCAN immediately drives the TXCAN pin into a recessive state. NOTE The user is responsible for ensuring that the MSCAN is not active when power down mode is entered. The recommended procedure is to bring the MSCAN into Sleep mode before the STOP or WAIT instruction (if CSWAI is set) is executed. Otherwise, the abort of an ongoing message can cause an error condition and impact other CAN bus devices. In power down mode, all clocks are stopped and no registers can be accessed. If the MSCAN was not in sleep mode before power down mode became active, the module performs an internal recovery cycle after powering up. This causes some xed delay before the module enters normal mode again.
12.5.5.7
Programmable Wake-Up Function
The MSCAN can be programmed to wake up the MSCAN as soon as CAN bus activity is detected (see control bit WUPE in Section 12.3.1, MSCAN Control Register 0 (CANCTL0)). The sensitivity to existing CAN bus action can be modied by applying a low-pass lter function to the RXCAN input line while in sleep mode (see control bit WUPM in Section 12.3.2, MSCAN Control Register 1 (CANCTL1)). This feature can be used to protect the MSCAN from wake-up due to short glitches on the CAN bus lines. Such glitches can result fromfor exampleelectromagnetic interference within noisy environments.
12.5.6
Reset Initialization
The reset state of each individual bit is listed in Section 12.3, Register Denition, which details all the registers and their bit-elds.
12.5.7
Interrupts
This section describes all interrupts originated by the MSCAN. It documents the enable bits and generated ags. Each interrupt is listed and described separately.
12.5.7.1
Description of Interrupt Operation
The MSCAN supports four interrupt vectors (see Table 12-37), any of which can be individually masked (for details see sections from Section 12.3.5, MSCAN Receiver Interrupt Enable Register (CANRIER), to Section 12.3.7, MSCAN Transmitter Interrupt Enable Register (CANTIER)). NOTE The dedicated interrupt vector addresses are dened in the Resets and Interrupts chapter.
Table 12-37. Interrupt Vectors
Interrupt Source Wake-Up Interrupt (WUPIF) Error Interrupts Interrupt (CSCIF, OVRIF) Receive Interrupt (RXF) Transmit Interrupts (TXE[2:0]) CCR Mask I bit I bit I bit I bit Local Enable CANRIER (WUPIE) CANRIER (CSCIE, OVRIE) CANRIER (RXFIE) CANTIER (TXEIE[2:0])
12.5.7.2
Transmit Interrupt
At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. The TXEx ag of the empty message buffer is set.
12.5.7.3
Receive Interrupt
A message is successfully received and shifted into the foreground buffer (RxFG) of the receiver FIFO. This interrupt is generated immediately after receiving the EOF symbol. The RXF ag is set. If there are multiple messages in the receiver FIFO, the RXF ag is set as soon as the next message is shifted to the foreground buffer.
12.5.7.4
Wake-Up Interrupt
A wake-up interrupt is generated if activity on the CAN bus occurs during MSCAN internal sleep mode. WUPE (see Section 12.3.1, MSCAN Control Register 0 (CANCTL0)) must be enabled.
12.5.7.5
Error Interrupt
An error interrupt is generated if an overrun of the receiver FIFO, error, warning, or bus-off condition occurrs. Section 12.3.4.1, MSCAN Receiver Flag Register (CANRFLG) indicates one of the following conditions: Overrun An overrun condition of the receiver FIFO as described in Section 12.5.2.3, Receive Structures, occurred. CAN Status Change The actual value of the transmit and receive error counters control the CAN bus state of the MSCAN. As soon as the error counters skip into a critical range (Tx/Rx-warning, Tx/Rx-error, bus-off) the MSCAN ags an error condition. The status change, which caused the error condition, is indicated by the TSTAT and RSTAT ags (see
Section 12.3.4.1, MSCAN Receiver Flag Register (CANRFLG) and Section 12.3.5, MSCAN Receiver Interrupt Enable Register (CANRIER)).
12.5.7.6
Interrupt Acknowledge
Interrupts are directly associated with one or more status ags in either the Section 12.3.4.1, MSCAN Receiver Flag Register (CANRFLG) or the Section 12.3.6, MSCAN Transmitter Flag Register (CANTFLG). Interrupts are pending as long as one of the corresponding ags is set. The ags in CANRFLG and CANTFLG must be reset within the interrupt handler to handshake the interrupt. The ags are reset by writing a 1 to the corresponding bit position. A ag cannot be cleared if the respective condition prevails. NOTE It must be guaranteed that the CPU clears only the bit causing the current interrupt. For this reason, bit manipulation instructions (BSET) must not be used to clear interrupt ags. These instructions may cause accidental clearing of interrupt ags which are set after entering the current interrupt service routine.
12.5.7.7
Recovery from Stop or Wait
The MSCAN can recover from stop or wait via the wake-up interrupt. This interrupt can only occur if the MSCAN was in sleep mode (SLPRQ = 1 and SLPAK = 1) before entering power down mode, the wake-up option is enabled (WUPE = 1), and the wake-up interrupt is enabled (WUPIE = 1).
12.6
12.6.1
MSCAN initialization
The procedure to initially start up the MSCAN module out of reset is as follows: 1. Assert CANE 2. Write to the conguration registers in initialization mode 3. Clear INITRQ to leave initialization mode and enter normal mode If the conguration of registers which are writable in initialization mode needs to be changed only when the MSCAN module is in normal mode: 1. Bring the module into sleep mode by setting SLPRQ and awaiting SLPAK to assert after the CAN bus becomes idle. 2. Enter initialization mode: assert INITRQ and await INITAK 3. Write to the conguration registers in initialization mode 4. Clear INITRQ to leave initialization mode and continue in normal mode
12.6.2
Bus-Off Recovery
The bus-off recovery is user congurable. The bus-off state can either be exited automatically or on user request. For reasons of backwards compatibility, the MSCAN defaults to automatic recovery after reset. In this case, the MSCAN will become error active again after counting 128 occurrences of 11 consecutive recessive bits on the CAN bus (See the Bosch CAN specication for details). If the MSCAN is congured for user request (BORM set in Section 12.3.2, MSCAN Control Register 1 (CANCTL1)), the recovery from bus-off starts after both independent events have become true: 128 occurrences of 11 consecutive recessive bits on the CAN bus have been monitored BOHOLD in Section 12.3.12, MSCAN Miscellaneous Register (CANMISC) has been cleared by the user These two events may occur in any order.

13.1 Introduction
The serial peripheral interface (SPI) module provides for full-duplex, synchronous, serial communication between the MCU and peripheral devices. These peripheral devices can include other microcontrollers, analog-to-digital converters, shift registers, sensors, memories, etc. The SPI runs at a baud rate up to the bus clock divided by two in master mode and bus clock divided by four in slave mode. All devices in the MC9S08DZ60 Series MCUs contain one SPI module, as shown in the following block diagram. NOTE Ensure that the SPI should not be disabled (SPE=0) at the same time as a bit change to the CPHA bit. These changes should be performed as separate operations or unexpected behavior may occur.
BDC
BKP
PORT G
PORT F
PORT E
PORT D
PORT B
13.1.1
Features
Features of the SPI module include: Master or slave mode operation Full-duplex or single-wire bidirectional option Programmable transmit bit rate Double-buffered transmit and receive Serial clock phase and polarity options Slave select output Selectable MSB-rst or LSB-rst shifting
13.1.2
Block Diagrams
This section includes block diagrams showing SPI system connections, the internal organization of the SPI module, and the SPI clock dividers that control the master mode bit rate.
13.1.2.1
SPI System Block Diagram
Figure 13-2 shows the SPI modules of two MCUs connected in a master-slave arrangement. The master device initiates all SPI data transfers. During a transfer, the master shifts data out (on the MOSI pin) to the slave while simultaneously shifting data in (on the MISO pin) from the slave. The transfer effectively exchanges the data that was in the SPI shift registers of the two SPI systems. The SPSCK signal is a clock output from the master and an input to the slave. The slave device must be selected by a low level on the slave select input (SS pin). In this system, the master device has congured its SS pin as an optional slave select output.
MASTER MOSI SPI SHIFTER 7 6 5 4 3 2 1 0 MISO MISO 7 MOSI
SLAVE
SPI SHIFTER 6 5 4 3 2 1 0
SPSCK
SPSCK
CLOCK GENERATOR
SS
SS
Figure 13-2. SPI System Connections
The most common uses of the SPI system include connecting simple shift registers for adding input or output ports or connecting small peripheral devices such as serial A/D or D/A converters. Although Figure 13-2 shows a system where data is exchanged between two MCUs, many practical systems involve simpler connections where data is unidirectionally transferred from the master MCU to a slave or from a slave to the master MCU.
13.1.2.2
SPI Module Block Diagram
Figure 13-3 is a block diagram of the SPI module. The central element of the SPI is the SPI shift register. Data is written to the double-buffered transmitter (write to SPID) and gets transferred to the SPI shift register at the start of a data transfer. After shifting in a byte of data, the data is transferred into the double-buffered receiver where it can be read (read from SPID). Pin multiplexing logic controls connections between MCU pins and the SPI module. When the SPI is congured as a master, the clock output is routed to the SPSCK pin, the shifter output is routed to MOSI, and the shifter input is routed from the MISO pin. When the SPI is congured as a slave, the SPSCK pin is routed to the clock input of the SPI, the shifter output is routed to MISO, and the shifter input is routed from the MOSI pin. In the external SPI system, simply connect all SPSCK pins to each other, all MISO pins together, and all MOSI pins together. Peripheral devices often use slightly different names for these pins.
Chapter 13 Serial Peripheral Interface (S08SPIV3) PIN CONTROL M SPE Tx BUFFER (WRITE SPID) ENABLE SPI SYSTEM SHIFT OUT SPI SHIFT REGISTER SHIFT IN SPC0 BIDIROE LSBFE SHIFT DIRECTION SHIFT CLOCK Rx BUFFER FULL Tx BUFFER EMPTY M S MISO (SISO) S MOSI (MOMI)
Rx BUFFER (READ SPID)
MASTER CLOCK BUS RATE CLOCK MSTR SPIBR CLOCK GENERATOR MASTER/SLAVE MODE SELECT MODFEN MODE FAULT DETECTION SSOE CLOCK LOGIC SLAVE CLOCK
M SPSCK S MASTER/ SLAVE
SS
SPRF
SPTEF SPTIE SPI INTERRUPT REQUEST
MODF SPIE
Figure 13-3. SPI Module Block Diagram
13.1.3
SPI Baud Rate Generation
As shown in Figure 13-4, the clock source for the SPI baud rate generator is the bus clock. The three prescale bits (SPPR2:SPPR1:SPPR0) choose a prescale divisor of 1, 2, 3, 4, 5, 6, 7, or 8. The three rate select bits (SPR2:SPR1:SPR0) divide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, or 256 to get the internal SPI master mode bit-rate clock.
Chapter 13 Serial Peripheral Interface (S08SPIV3) PRESCALER BUS CLOCK DIVIDE BY 1, 2, 3, 4, 5, 6, 7, or 8 CLOCK RATE DIVIDER DIVIDE BY 2, 4, 8, 16, 32, 64, 128, or 256 MASTER SPI BIT RATE
SPPR2:SPPR1:SPPR0
SPR2:SPR1:SPR0
Figure 13-4. SPI Baud Rate Generation
13.2
The SPI optionally shares four port pins. The function of these pins depends on the settings of SPI control bits. When the SPI is disabled (SPE = 0), these four pins revert to being general-purpose port I/O pins that are not controlled by the SPI.
13.2.1
SPSCK SPI Serial Clock
When the SPI is enabled as a slave, this pin is the serial clock input. When the SPI is enabled as a master, this pin is the serial clock output.
13.2.2
MOSI Master Data Out, Slave Data In
When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this pin is the serial data output. When the SPI is enabled as a slave and SPC0 = 0, this pin is the serial data input. If SPC0 = 1 to select single-wire bidirectional mode, and master mode is selected, this pin becomes the bidirectional data I/O pin (MOMI). Also, the bidirectional mode output enable bit determines whether the pin acts as an input (BIDIROE = 0) or an output (BIDIROE = 1). If SPC0 = 1 and slave mode is selected, this pin is not used by the SPI and reverts to being a general-purpose port I/O pin.
13.2.3
MISO Master Data In, Slave Data Out
When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this pin is the serial data input. When the SPI is enabled as a slave and SPC0 = 0, this pin is the serial data output. If SPC0 = 1 to select single-wire bidirectional mode, and slave mode is selected, this pin becomes the bidirectional data I/O pin (SISO) and the bidirectional mode output enable bit determines whether the pin acts as an input (BIDIROE = 0) or an output (BIDIROE = 1). If SPC0 = 1 and master mode is selected, this pin is not used by the SPI and reverts to being a general-purpose port I/O pin.
13.2.4
SS Slave Select
When the SPI is enabled as a slave, this pin is the low-true slave select input. When the SPI is enabled as a master and mode fault enable is off (MODFEN = 0), this pin is not used by the SPI and reverts to being a general-purpose port I/O pin. When the SPI is enabled as a master and MODFEN = 1, the slave select output enable bit determines whether this pin acts as the mode fault input (SSOE = 0) or as the slave select output (SSOE = 1).
13.3
13.3.1
Modes of Operation
SPI in Stop Modes
The SPI is disabled in all stop modes, regardless of the settings before executing the STOP instruction. During either stop1 or stop2 mode, the SPI module will be fully powered down. Upon wake-up from stop1 or stop2 mode, the SPI module will be in the reset state. During stop3 mode, clocks to the SPI module are halted. No registers are affected. If stop3 is exited with a reset, the SPI will be put into its reset state. If stop3 is exited with an interrupt, the SPI continues from the state it was in when stop3 was entered.
13.4
Register Denition
The SPI has ve 8-bit registers to select SPI options, control baud rate, report SPI status, and for transmit/receive data. Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all SPI registers. This section refers to registers and control bits only by their names, and a Freescale-provided equate or header le is used to translate these names into the appropriate absolute addresses.
13.4.1
SPI Control Register 1 (SPIC1)
This read/write register includes the SPI enable control, interrupt enables, and conguration options.
7 6 5 4 3 2 1 0
R SPIE W Reset 0 0 0 0 0 1 0 0 SPE SPTIE MSTR CPOL CPHA SSOE LSBFE
Figure 13-5. SPI Control Register 1 (SPIC1) Table 13-1. SPIC1 Field Descriptions
Field 7 SPIE Description SPI Interrupt Enable (for SPRF and MODF) This is the interrupt enable for SPI receive buffer full (SPRF) and mode fault (MODF) events. 0 Interrupts from SPRF and MODF inhibited (use polling) 1 When SPRF or MODF is 1, request a hardware interrupt SPI System Enable Disabling the SPI halts any transfer that is in progress, clears data buffers, and initializes internal state machines. SPRF is cleared and SPTEF is set to indicate the SPI transmit data buffer is empty. 0 SPI system inactive 1 SPI system enabled SPI Transmit Interrupt Enable This is the interrupt enable bit for SPI transmit buffer empty (SPTEF). 0 Interrupts from SPTEF inhibited (use polling) 1 When SPTEF is 1, hardware interrupt requested
6 SPE
5 SPTIE
Table 13-1. SPIC1 Field Descriptions (continued)

Field 4 MSTR 3 CPOL Description Master/Slave Mode Select 0 SPI module congured as a slave SPI device 1 SPI module congured as a master SPI device Clock Polarity This bit effectively places an inverter in series with the clock signal from a master SPI or to a slave SPI device. Refer to Section 13.5.1, SPI Clock Formats for more details. 0 Active-high SPI clock (idles low) 1 Active-low SPI clock (idles high) Clock Phase This bit selects one of two clock formats for different kinds of synchronous serial peripheral devices. Refer to Section 13.5.1, SPI Clock Formats for more details. 0 First edge on SPSCK occurs at the middle of the rst cycle of an 8-cycle data transfer 1 First edge on SPSCK occurs at the start of the rst cycle of an 8-cycle data transfer Slave Select Output Enable This bit is used in combination with the mode fault enable (MODFEN) bit in SPCR2 and the master/slave (MSTR) control bit to determine the function of the SS pin as shown in Table 13-2. LSB First (Shifter Direction) 0 SPI serial data transfers start with most signicant bit 1 SPI serial data transfers start with least signicant bit
2 CPHA
1 SSOE 0 LSBFE
Table 13-2. SS Pin Function

MODFEN 0 0 1 1 SSOE 0 1 0 1 Master Mode General-purpose I/O (not SPI) General-purpose I/O (not SPI) SS input for mode fault Automatic SS output Slave Mode Slave select input Slave select input Slave select input Slave select input
NOTE Ensure that the SPI should not be disabled (SPE=0) at the same time as a bit change to the CPHA bit. These changes should be performed as separate operations or unexpected behavior may occur.
13.4.2
SPI Control Register 2 (SPIC2)
This read/write register is used to control optional features of the SPI system. Bits 7, 6, 5, and 2 are not implemented and always read 0.
7 6 5 4 3 2 1 0
R W Reset
0 MODFEN BIDIROE 0
0 SPISWAI 0 0 SPC0 0
Figure 13-6. SPI Control Register 2 (SPIC2)
Table 13-3. SPIC2 Register Field Descriptions

Field 4 MODFEN Description Master Mode-Fault Function Enable When the SPI is congured for slave mode, this bit has no meaning or effect. (The SS pin is the slave select input.) In master mode, this bit determines how the SS pin is used (refer to Table 13-2 for more details). 0 Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI 1 Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output Bidirectional Mode Output Enable When bidirectional mode is enabled by SPI pin control 0 (SPC0) = 1, BIDIROE determines whether the SPI data output driver is enabled to the single bidirectional SPI I/O pin. Depending on whether the SPI is congured as a master or a slave, it uses either the MOSI (MOMI) or MISO (SISO) pin, respectively, as the single SPI data I/O pin. When SPC0 = 0, BIDIROE has no meaning or effect. 0 Output driver disabled so SPI data I/O pin acts as an input 1 SPI I/O pin enabled as an output SPI Stop in Wait Mode 0 SPI clocks continue to operate in wait mode 1 SPI clocks stop when the MCU enters wait mode SPI Pin Control 0 The SPC0 bit chooses single-wire bidirectional mode. If MSTR = 0 (slave mode), the SPI uses the MISO (SISO) pin for bidirectional SPI data transfers. If MSTR = 1 (master mode), the SPI uses the MOSI (MOMI) pin for bidirectional SPI data transfers. When SPC0 = 1, BIDIROE is used to enable or disable the output driver for the single bidirectional SPI I/O pin. 0 SPI uses separate pins for data input and data output 1 SPI congured for single-wire bidirectional operation
3 BIDIROE
1 SPISWAI 0 SPC0
13.4.3
SPI Baud Rate Register (SPIBR)
This register is used to set the prescaler and bit rate divisor for an SPI master. This register may be read or written at any time.
7 6 5 4 3 2 1 0
R W Reset
0 SPPR2 0 0 SPPR1 0 SPPR0 0
0 SPR2 0 0 SPR1 0 SPR0 0
Figure 13-7. SPI Baud Rate Register (SPIBR) Table 13-4. SPIBR Register Field Descriptions
Field 6:4 SPPR[2:0] 2:0 SPR[2:0] Description SPI Baud Rate Prescale Divisor This 3-bit eld selects one of eight divisors for the SPI baud rate prescaler as shown in Table 13-5. The input to this prescaler is the bus rate clock (BUSCLK). The output of this prescaler drives the input of the SPI baud rate divider (see Figure 13-4). SPI Baud Rate Divisor This 3-bit eld selects one of eight divisors for the SPI baud rate divider as shown in Table 13-6. The input to this divider comes from the SPI baud rate prescaler (see Figure 13-4). The output of this divider is the SPI bit rate clock for master mode.
Table 13-5. SPI Baud Rate Prescaler Divisor

SPPR2:SPPR1:SPPR0 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 Prescaler Divisor 1 2 3 4 5 6 7 8
Table 13-6. SPI Baud Rate Divisor

SPR2:SPR1:SPR0 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 Rate Divisor 2 4 8 16 32 64 128 256
13.4.4
SPI Status Register (SPIS)
This register has three read-only status bits. Bits 6, 3, 2, 1, and 0 are not implemented and always read 0. Writes have no meaning or effect.
7 6 5 4 3 2 1 0
R W Reset
SPRF
SPTEF
MODF
Figure 13-8. SPI Status Register (SPIS)
Table 13-7. SPIS Register Field Descriptions

Field 7 SPRF Description SPI Read Buffer Full Flag SPRF is set at the completion of an SPI transfer to indicate that received data may be read from the SPI data register (SPID). SPRF is cleared by reading SPRF while it is set, then reading the SPI data register. 0 No data available in the receive data buffer 1 Data available in the receive data buffer SPI Transmit Buffer Empty Flag This bit is set when there is room in the transmit data buffer. It is cleared by reading SPIS with SPTEF set, followed by writing a data value to the transmit buffer at SPID. SPIS must be read with SPTEF = 1 before writing data to SPID or the SPID write will be ignored. SPTEF generates an SPTEF CPU interrupt request if the SPTIE bit in the SPIC1 is also set. SPTEF is automatically set when a data byte transfers from the transmit buffer into the transmit shift register. For an idle SPI (no data in the transmit buffer or the shift register and no transfer in progress), data written to SPID is transferred to the shifter almost immediately so SPTEF is set within two bus cycles allowing a second 8-bit data value to be queued into the transmit buffer. After completion of the transfer of the value in the shift register, the queued value from the transmit buffer will automatically move to the shifter and SPTEF will be set to indicate there is room for new data in the transmit buffer. If no new data is waiting in the transmit buffer, SPTEF simply remains set and no data moves from the buffer to the shifter. 0 SPI transmit buffer not empty 1 SPI transmit buffer empty Master Mode Fault Flag MODF is set if the SPI is congured as a master and the slave select input goes low, indicating some other SPI device is also congured as a master. The SS pin acts as a mode fault error input only when MSTR = 1, MODFEN = 1, and SSOE = 0; otherwise, MODF will never be set. MODF is cleared by reading MODF while it is 1, then writing to SPI control register 1 (SPIC1). 0 No mode fault error 1 Mode fault error detected
5 SPTEF
4 MODF
13.4.5
R
SPI Data Register (SPID)

7 6 5 4 3 2 1 0
Bit 7 W Reset 0
6 0
5 0
4 0
3 0
2 0
1 0
Bit 0 0
Figure 13-9. SPI Data Register (SPID)
Reads of this register return the data read from the receive data buffer. Writes to this register write data to the transmit data buffer. When the SPI is congured as a master, writing data to the transmit data buffer initiates an SPI transfer. Data should not be written to the transmit data buffer unless the SPI transmit buffer empty ag (SPTEF) is set, indicating there is room in the transmit buffer to queue a new transmit byte. Data may be read from SPID any time after SPRF is set and before another transfer is nished. Failure to read the data out of the receive data buffer before a new transfer ends causes a receive overrun condition and the data from the new transfer is lost.
13.5
An SPI transfer is initiated by checking for the SPI transmit buffer empty ag (SPTEF = 1) and then writing a byte of data to the SPI data register (SPID) in the master SPI device. When the SPI shift register is available, this byte of data is moved from the transmit data buffer to the shifter, SPTEF is set to indicate there is room in the buffer to queue another transmit character if desired, and the SPI serial transfer starts. During the SPI transfer, data is sampled (read) on the MISO pin at one SPSCK edge and shifted, changing the bit value on the MOSI pin, one-half SPSCK cycle later. After eight SPSCK cycles, the data that was in the shift register of the master has been shifted out the MOSI pin to the slave while eight bits of data were shifted in the MISO pin into the masters shift register. At the end of this transfer, the received data byte is moved from the shifter into the receive data buffer and SPRF is set to indicate the data can be read by reading SPID. If another byte of data is waiting in the transmit buffer at the end of a transfer, it is moved into the shifter, SPTEF is set, and a new transfer is started. Normally, SPI data is transferred most signicant bit (MSB) rst. If the least signicant bit rst enable (LSBFE) bit is set, SPI data is shifted LSB rst. When the SPI is congured as a slave, its SS pin must be driven low before a transfer starts and SS must stay low throughout the transfer. If a clock format where CPHA = 0 is selected, SS must be driven to a logic 1 between successive transfers. If CPHA = 1, SS may remain low between successive transfers. See Section 13.5.1, SPI Clock Formats for more details. Because the transmitter and receiver are double buffered, a second byte, in addition to the byte currently being shifted out, can be queued into the transmit data buffer, and a previously received character can be in the receive data buffer while a new character is being shifted in. The SPTEF ag indicates when the transmit buffer has room for a new character. The SPRF ag indicates when a received character is available in the receive data buffer. The received character must be read out of the receive buffer (read SPID) before the next transfer is nished or a receive overrun error results. In the case of a receive overrun, the new data is lost because the receive buffer still held the previous character and was not ready to accept the new data. There is no indication for such an overrun condition so the application system designer must ensure that previous data has been read from the receive buffer before a new transfer is initiated.
13.5.1
SPI Clock Formats
To accommodate a wide variety of synchronous serial peripherals from different manufacturers, the SPI system has a clock polarity (CPOL) bit and a clock phase (CPHA) control bit to select one of four clock formats for data transfers. CPOL selectively inserts an inverter in series with the clock. CPHA chooses between two different clock phase relationships between the clock and data. Figure 13-10 shows the clock formats when CPHA = 1. At the top of the gure, the eight bit times are shown for reference with bit 1 starting at the rst SPSCK edge and bit 8 ending one-half SPSCK cycle after the sixteenth SPSCK edge. The MSB rst and LSB rst lines show the order of SPI data bits depending on the setting in LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms applies for a specic transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output
pin from a master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies to the slave select output from a master (provided MODFEN and SSOE = 1). The master SS output goes to active low one-half SPSCK cycle before the start of the transfer and goes back high at the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a slave.
BIT TIME # (REFERENCE) 1 2 ... 6 7 8
SPSCK (CPOL = 0)
SPSCK (CPOL = 1)
SAMPLE IN (MISO OR MOSI)
MOSI (MASTER OUT) MSB FIRST LSB FIRST MISO (SLAVE OUT) BIT 7 BIT 0 BIT 6 BIT 1 ... ... BIT 2 BIT 5 BIT 1 BIT 6 BIT 0 BIT 7
SS OUT (MASTER)
SS IN (SLAVE)
Figure 13-10. SPI Clock Formats (CPHA = 1)
When CPHA = 1, the slave begins to drive its MISO output when SS goes to active low, but the data is not dened until the rst SPSCK edge. The rst SPSCK edge shifts the rst bit of data from the shifter onto the MOSI output of the master and the MISO output of the slave. The next SPSCK edge causes both the master and the slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the third SPSCK edge, the SPI shifter shifts one bit position which shifts in the bit value that was just sampled, and shifts the second data bit value out the other end of the shifter to the MOSI and MISO outputs of the master and slave, respectively. When CHPA = 1, the slaves SS input is not required to go to its inactive high level between transfers. Figure 13-11 shows the clock formats when CPHA = 0. At the top of the gure, the eight bit times are shown for reference with bit 1 starting as the slave is selected (SS IN goes low), and bit 8 ends at the last SPSCK edge. The MSB rst and LSB rst lines show the order of SPI data bits depending on the setting
in LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms applies for a specic transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output pin from a master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies to the slave select output from a master (provided MODFEN and SSOE = 1). The master SS output goes to active low at the start of the rst bit time of the transfer and goes back high one-half SPSCK cycle after the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a slave.
BIT TIME # (REFERENCE) SPSCK (CPOL = 0) 1 2 ... 6 7 8
SPSCK (CPOL = 1)
SAMPLE IN (MISO OR MOSI)
MOSI (MASTER OUT) MSB FIRST LSB FIRST MISO (SLAVE OUT) BIT 7 BIT 0 BIT 6 BIT 1 ... ... BIT 2 BIT 5 BIT 1 BIT 6 BIT 0 BIT 7
SS OUT (MASTER)
SS IN (SLAVE)
Figure 13-11. SPI Clock Formats (CPHA = 0)
When CPHA = 0, the slave begins to drive its MISO output with the rst data bit value (MSB or LSB depending on LSBFE) when SS goes to active low. The rst SPSCK edge causes both the master and the slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the second SPSCK edge, the SPI shifter shifts one bit position which shifts in the bit value that was just sampled and shifts the second data bit value out the other end of the shifter to the MOSI and MISO outputs of the master and slave, respectively. When CPHA = 0, the slaves SS input must go to its inactive high level between transfers.
13.5.2
SPI Interrupts
There are three ag bits, two interrupt mask bits, and one interrupt vector associated with the SPI system. The SPI interrupt enable mask (SPIE) enables interrupts from the SPI receiver full ag (SPRF) and mode fault ag (MODF). The SPI transmit interrupt enable mask (SPTIE) enables interrupts from the SPI transmit buffer empty ag (SPTEF). When one of the ag bits is set, and the associated interrupt mask bit is set, a hardware interrupt request is sent to the CPU. If the interrupt mask bits are cleared, software can poll the associated ag bits instead of using interrupts. The SPI interrupt service routine (ISR) should check the ag bits to determine what event caused the interrupt. The service routine should also clear the ag bit(s) before returning from the ISR (usually near the beginning of the ISR).
13.5.3
Mode Fault Detection
A mode fault occurs and the mode fault ag (MODF) becomes set when a master SPI device detects an error on the SS pin (provided the SS pin is congured as the mode fault input signal). The SS pin is congured to be the mode fault input signal when MSTR = 1, mode fault enable is set (MODFEN = 1), and slave select output enable is clear (SSOE = 0). The mode fault detection feature can be used in a system where more than one SPI device might become a master at the same time. The error is detected when a masters SS pin is low, indicating that some other SPI device is trying to address this master as if it were a slave. This could indicate a harmful output driver conict, so the mode fault logic is designed to disable all SPI output drivers when such an error is detected. When a mode fault is detected, MODF is set and MSTR is cleared to change the SPI conguration back to slave mode. The output drivers on the SPSCK, MOSI, and MISO (if not bidirectional mode) are disabled. MODF is cleared by reading it while it is set, then writing to the SPI control register 1 (SPIC1). User software should verify the error condition has been corrected before changing the SPI back to master mode.

14.1 Introduction
NOTE MC9S08DZ60 Series devices operate at a higher voltage range (2.7 V to 5.5 V) and do not include stop1 mode. Please ignore references to stop1. The RxD1 pin does not contain a clamp diode to VDD and should not be driven above VDD. The voltage measured on the internally pulled up RxD1 pin may be as low as VDD 0.7 V. The internal gates connected to this pin are pulled all the way to VDD. All MCUs in the MC9S08DZ60 Series include SCI1 and SCI2.
14.1.1
SCI2 Conguration Information
The SCI2 module pins, TxD2 and RxD2 can be repositioned under software control using SCI2PS in SOPT1 as shown in Table 14-1. SCI2PS in SOPT1 selects which general-purpose I/O ports are associated with SCI2 operation.
Table 14-1. SCI2 Position Options
SCI2PS in SOPT1 0 (default) 1 Port Pin for TxD2 PTF0 PTE6 Port Pin for RxD2 PTF1 PTE7
BDC
BKP
PORT G
PORT F
PORT E
PORT D
PORT B
14.1.2
Features
Features of SCI module include: Full-duplex, standard non-return-to-zero (NRZ) format Double-buffered transmitter and receiver with separate enables Programmable baud rates (13-bit modulo divider) Interrupt-driven or polled operation: Transmit data register empty and transmission complete Receive data register full Receive overrun, parity error, framing error, and noise error Idle receiver detect Active edge on receive pin Break detect supporting LIN Hardware parity generation and checking Programmable 8-bit or 9-bit character length Receiver wakeup by idle-line or address-mark Optional 13-bit break character generation / 11-bit break character detection Selectable transmitter output polarity
14.1.3
Modes of Operation
See Section 14.3, Functional Description, For details concerning SCI operation in these modes: 8- and 9-bit data modes Stop mode operation Loop mode Single-wire mode
14.1.4
Block Diagram
INTERNAL BUS (WRITE-ONLY) LOOPS SCID Tx BUFFER RSRC LOOP CONTROL
Figure 14-2 shows the transmitter portion of the SCI.
11-BIT TRANSMIT SHIFT REGISTER START STOP M
TO RECEIVE DATA IN
SHIFT DIRECTION
LSB
1 BAUD RATE CLOCK
TO TxD PIN
TXINV PREAMBLE (ALL 1s)
LOAD FROM SCIxD
T8
PE PT
PARITY GENERATION
BREAK (ALL 0s) SCI CONTROLS TxD
TE SBK TXDIR BRK13 TRANSMIT CONTROL
SHIFT ENABLE
TxD DIRECTION
TO TxD PIN LOGIC
TDRE TIE TC TCIE Tx INTERRUPT REQUEST
Figure 14-2. SCI Transmitter Block Diagram
Figure 14-3 shows the receiver portion of the SCI.

INTERNAL BUS (READ-ONLY) 16 BAUD RATE CLOCK FROM TRANSMITTER SINGLE-WIRE LOOP CONTROL STOP M LBKDE ALL 1s DATA RECOVERY MSB LSB 8 7 6 5 4 3 2 1 0 SHIFT DIRECTION RWU RWUID RDRF RIE IDLE ILIE LBKDIF LBKDIE RXEDGIF RXEDGIE OR ORIE FE FEIE NF NEIE PE PT PARITY CHECKING PF PEIE ERROR INTERRUPT REQUEST Rx INTERRUPT REQUEST LOOPS RSRC FROM RxD PIN RXINV START L 11-BIT RECEIVE SHIFT REGISTER DIVIDE BY 16 SCID Rx BUFFER
WAKE ILT ACTIVE EDGE DETECT
WAKEUP LOGIC
Figure 14-3. SCI Receiver Block Diagram
14.2
Register Denition
The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for transmit/receive data. Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all SCI registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header le is used to translate these names into the appropriate absolute addresses.
14.2.1
SCI Baud Rate Registers (SCIxBDH, SCIxBDL)
This pair of registers controls the prescale divisor for SCI baud rate generation. To update the 13-bit baud rate setting [SBR12:SBR0], rst write to SCIxBDH to buffer the high half of the new value and then write to SCIxBDL. The working value in SCIxBDH does not change until SCIxBDL is written. SCIxBDL is reset to a non-zero value, so after reset the baud rate generator remains disabled until the rst time the receiver or transmitter is enabled (RE or TE bits in SCIxC2 are written to 1).
7 6 5 4 3 2 1 0
R LBKDIE W Reset 0 0 RXEDGIE
0 SBR12 0 0 SBR11 0 SBR10 0 SBR9 0 SBR8 0
Figure 14-4. SCI Baud Rate Register (SCIxBDH) Table 14-2. SCIxBDH Field Descriptions
Field 7 LBKDIE 6 RXEDGIE 4:0 SBR[12:8] Description LIN Break Detect Interrupt Enable (for LBKDIF) 0 Hardware interrupts from LBKDIF disabled (use polling). 1 Hardware interrupt requested when LBKDIF ag is 1. RxD Input Active Edge Interrupt Enable (for RXEDGIF) 0 Hardware interrupts from RXEDGIF disabled (use polling). 1 Hardware interrupt requested when RXEDGIF ag is 1. Baud Rate Modulo Divisor The 13 bits in SBR[12:0] are referred to collectively as BR, and they set the modulo divide rate for the SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to reduce supply current. When BR = 1 to 8191, the SCI baud rate = BUSCLK/(16BR). See also BR bits in Table 14-3.
R SBR7 W Reset 0 0 0 0 0 1 0 0 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0
Figure 14-5. SCI Baud Rate Register (SCIxBDL) Table 14-3. SCIxBDL Field Descriptions
Field 7:0 SBR[7:0] Description Baud Rate Modulo Divisor These 13 bits in SBR[12:0] are referred to collectively as BR, and they set the modulo divide rate for the SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to reduce supply current. When BR = 1 to 8191, the SCI baud rate = BUSCLK/(16BR). See also BR bits in Table 14-2.
14.2.2
SCI Control Register 1 (SCIxC1)
This read/write register is used to control various optional features of the SCI system.
R LOOPS W Reset 0 0 0 0 0 0 0 0 SCISWAI RSRC M WAKE ILT PE PT
Figure 14-6. SCI Control Register 1 (SCIxC1) Table 14-4. SCIxC1 Field Descriptions
Field 7 LOOPS Description Loop Mode Select Selects between loop back modes and normal 2-pin full-duplex modes. When LOOPS = 1, the transmitter output is internally connected to the receiver input. 0 Normal operation RxD and TxD use separate pins. 1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) RxD pin is not used by SCI. SCI Stops in Wait Mode 0 SCI clocks continue to run in wait mode so the SCI can be the source of an interrupt that wakes up the CPU. 1 SCI clocks freeze while CPU is in wait mode. Receiver Source Select This bit has no meaning or effect unless the LOOPS bit is set to 1. When LOOPS = 1, the receiver input is internally connected to the TxD pin and RSRC determines whether this connection is also connected to the transmitter output. 0 Provided LOOPS = 1, RSRC = 0 selects internal loop back mode and the SCI does not use the RxD pins. 1 Single-wire SCI mode where the TxD pin is connected to the transmitter output and receiver input. 9-Bit or 8-Bit Mode Select 0 Normal start + 8 data bits (LSB rst) + stop. 1 Receiver and transmitter use 9-bit data characters start + 8 data bits (LSB rst) + 9th data bit + stop.
6 SCISWAI 5 RSRC
4 M
Table 14-4. SCIxC1 Field Descriptions (continued)

Field 3 WAKE Description Receiver Wakeup Method Select Refer to Section 14.3.3.2, Receiver Wakeup Operation for more information. 0 Idle-line wakeup. 1 Address-mark wakeup. Idle Line Type Select Setting this bit to 1 ensures that the stop bit and logic 1 bits at the end of a character do not count toward the 10 or 11 bit times of logic high level needed by the idle line detection logic. Refer to Section 14.3.3.2.1, Idle-Line Wakeup for more information. 0 Idle character bit count starts after start bit. 1 Idle character bit count starts after stop bit. Parity Enable Enables hardware parity generation and checking. When parity is enabled, the most signicant bit (MSB) of the data character (eighth or ninth data bit) is treated as the parity bit. 0 No hardware parity generation or checking. 1 Parity enabled. Parity Type Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd parity means the total number of 1s in the data character, including the parity bit, is odd. Even parity means the total number of 1s in the data character, including the parity bit, is even. 0 Even parity. 1 Odd parity.
2 ILT
1 PE
0 PT
14.2.3
This register can be read or written at any time.

7 6 5 4 3 2 1 0
R TIE W Reset 0 0 0 0 0 0 0 0 TCIE RIE ILIE TE RE RWU SBK
Field 7 TIE 6 TCIE 5 RIE 4 ILIE Description Transmit Interrupt Enable (for TDRE) 0 Hardware interrupts from TDRE disabled (use polling). 1 Hardware interrupt requested when TDRE ag is 1. Transmission Complete Interrupt Enable (for TC) 0 Hardware interrupts from TC disabled (use polling). 1 Hardware interrupt requested when TC ag is 1. Receiver Interrupt Enable (for RDRF) 0 Hardware interrupts from RDRF disabled (use polling). 1 Hardware interrupt requested when RDRF ag is 1. Idle Line Interrupt Enable (for IDLE) 0 Hardware interrupts from IDLE disabled (use polling). 1 Hardware interrupt requested when IDLE ag is 1.

Field 3 TE Description Transmitter Enable 0 Transmitter off. 1 Transmitter on. TE must be 1 in order to use the SCI transmitter. When TE = 1, the SCI forces the TxD pin to act as an output for the SCI system. When the SCI is congured for single-wire operation (LOOPS = RSRC = 1), TXDIR controls the direction of trafc on the single SCI communication line (TxD pin). TE also can be used to queue an idle character by writing TE = 0 then TE = 1 while a transmission is in progress. Refer to Section 14.3.2.1, Send Break and Queued Idle for more details. When TE is written to 0, the transmitter keeps control of the port TxD pin until any data, queued idle, or queued break character nishes transmitting before allowing the pin to revert to a general-purpose I/O pin. Receiver Enable When the SCI receiver is off, the RxD pin reverts to being a general-purpose port I/O pin. If LOOPS = 1 the RxD pin reverts to being a general-purpose I/O pin even if RE = 1. 0 Receiver off. 1 Receiver on. Receiver Wakeup Control This bit can be written to 1 to place the SCI receiver in a standby state where it waits for automatic hardware detection of a selected wakeup condition. The wakeup condition is either an idle line between messages (WAKE = 0, idle-line wakeup), or a logic 1 in the most signicant data bit in a character (WAKE = 1, address-mark wakeup). Application software sets RWU and (normally) a selected hardware condition automatically clears RWU. Refer to Section 14.3.3.2, Receiver Wakeup Operation for more details. 0 Normal SCI receiver operation. 1 SCI receiver in standby waiting for wakeup condition. Send Break Writing a 1 and then a 0 to SBK queues a break character in the transmit data stream. Additional break characters of 10 or 11 (13 or 14 if BRK13 = 1) bit times of logic 0 are queued as long as SBK = 1. Depending on the timing of the set and clear of SBK relative to the information currently being transmitted, a second break character may be queued before software clears SBK. Refer to Section 14.3.2.1, Send Break and Queued Idle for more details. 0 Normal transmitter operation. 1 Queue break character(s) to be sent.
2 RE
1 RWU
0 SBK
14.2.4
SCI Status Register 1 (SCIxS1)
This register has eight read-only status ags. Writes have no effect. Special software sequences (which do not involve writing to this register) are used to clear these status ags.
R W Reset
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
Figure 14-8. SCI Status Register 1 (SCIxS1)
Table 14-6. SCIxS1 Field Descriptions

Field 7 TDRE Description Transmit Data Register Empty Flag TDRE is set out of reset and when a transmit data value transfers from the transmit data buffer to the transmit shifter, leaving room for a new character in the buffer. To clear TDRE, read SCIxS1 with TDRE = 1 and then write to the SCI data register (SCIxD). 0 Transmit data register (buffer) full. 1 Transmit data register (buffer) empty. Transmission Complete Flag TC is set out of reset and when TDRE = 1 and no data, preamble, or break character is being transmitted. 0 Transmitter active (sending data, a preamble, or a break). 1 Transmitter idle (transmission activity complete). TC is cleared automatically by reading SCIxS1 with TC = 1 and then doing one of the following three things: Write to the SCI data register (SCIxD) to transmit new data Queue a preamble by changing TE from 0 to 1 Queue a break character by writing 1 to SBK in SCIxC2 Receive Data Register Full Flag RDRF becomes set when a character transfers from the receive shifter into the receive data register (SCIxD). To clear RDRF, read SCIxS1 with RDRF = 1 and then read the SCI data register (SCIxD). 0 Receive data register empty. 1 Receive data register full. Idle Line Flag IDLE is set when the SCI receive line becomes idle for a full character time after a period of activity. When ILT = 0, the receiver starts counting idle bit times after the start bit. So if the receive character is all 1s, these bit times and the stop bit time count toward the full character time of logic high (10 or 11 bit times depending on the M control bit) needed for the receiver to detect an idle line. When ILT = 1, the receiver doesnt start counting idle bit times until after the stop bit. So the stop bit and any logic high bit times at the end of the previous character do not count toward the full character time of logic high needed for the receiver to detect an idle line. To clear IDLE, read SCIxS1 with IDLE = 1 and then read the SCI data register (SCIxD). After IDLE has been cleared, it cannot become set again until after a new character has been received and RDRF has been set. IDLE will get set only once even if the receive line remains idle for an extended period. 0 No idle line detected. 1 Idle line was detected. Receiver Overrun Flag OR is set when a new serial character is ready to be transferred to the receive data register (buffer), but the previously received character has not been read from SCIxD yet. In this case, the new character (and all associated error information) is lost because there is no room to move it into SCIxD. To clear OR, read SCIxS1 with OR = 1 and then read the SCI data register (SCIxD). 0 No overrun. 1 Receive overrun (new SCI data lost). Noise Flag The advanced sampling technique used in the receiver takes seven samples during the start bit and three samples in each data bit and the stop bit. If any of these samples disagrees with the rest of the samples within any bit time in the frame, the ag NF will be set at the same time as the ag RDRF gets set for the character. To clear NF, read SCIxS1 and then read the SCI data register (SCIxD). 0 No noise detected. 1 Noise detected in the received character in SCIxD.
6 TC
5 RDRF
4 IDLE
3 OR
2 NF
Table 14-6. SCIxS1 Field Descriptions (continued)

Field 1 FE Description Framing Error Flag FE is set at the same time as RDRF when the receiver detects a logic 0 where the stop bit was expected. This suggests the receiver was not properly aligned to a character frame. To clear FE, read SCIxS1 with FE = 1 and then read the SCI data register (SCIxD). 0 No framing error detected. This does not guarantee the framing is correct. 1 Framing error. Parity Error Flag PF is set at the same time as RDRF when parity is enabled (PE = 1) and the parity bit in the received character does not agree with the expected parity value. To clear PF, read SCIxS1 and then read the SCI data register (SCIxD). 0 No parity error. 1 Parity error.
0 PF
14.2.5
SCI Status Register 2 (SCIxS2)
This register has one read-only status ag.

7 6 5 4 3 2 1 0
R LBKDIF W Reset 0 0 RXEDGIF
0 RXINV 0 0 RWUID 0 BRK13 0 LBKDE 0
RAF
Figure 14-9. SCI Status Register 2 (SCIxS2) Table 14-7. SCIxS2 Field Descriptions
Field 7 LBKDIF Description LIN Break Detect Interrupt Flag LBKDIF is set when the LIN break detect circuitry is enabled and a LIN break character is detected. LBKDIF is cleared by writing a 1 to it. 0 No LIN break character has been detected. 1 LIN break character has been detected. RxD Pin Active Edge Interrupt Flag RXEDGIF is set when an active edge (falling if RXINV = 0, rising if RXINV=1) on the RxD pin occurs. RXEDGIF is cleared by writing a 1 to it. 0 No active edge on the receive pin has occurred. 1 An active edge on the receive pin has occurred. Receive Data Inversion Setting this bit reverses the polarity of the received data input. 0 Receive data not inverted 1 Receive data inverted Receive Wake Up Idle Detect RWUID controls whether the idle character that wakes up the receiver sets the IDLE bit. 0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. 1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. Break Character Generation Length BRK13 is used to select a longer transmitted break character length. Detection of a framing error is not affected by the state of this bit. 0 Break character is transmitted with length of 10 bit times (11 if M = 1) 1 Break character is transmitted with length of 13 bit times (14 if M = 1)
6 RXEDGIF
4 RXINV1 3 RWUID
2 BRK13
Table 14-7. SCIxS2 Field Descriptions (continued)

Field 1 LBKDE Description LIN Break Detection Enable LBKDE is used to select a longer break character detection length. While LBKDE is set, framing error (FE) and receive data register full (RDRF) ags are prevented from setting. 0 Break character is detected at length of 10 bit times (11 if M = 1). 1 Break character is detected at length of 11 bit times (12 if M = 1). Receiver Active Flag RAF is set when the SCI receiver detects the beginning of a valid start bit, and RAF is cleared automatically when the receiver detects an idle line. This status ag can be used to check whether an SCI character is being received before instructing the MCU to go to stop mode. 0 SCI receiver idle waiting for a start bit. 1 SCI receiver active (RxD input not idle).
0 RAF
Setting RXINV inverts the RxD input for all cases: data bits, start and stop bits, break, and idle.
When using an internal oscillator in a LIN system, it is necessary to raise the break detection threshold by one bit time. Under the worst case timing conditions allowed in LIN, it is possible that a 0x00 data character can appear to be 10.26 bit times long at a slave which is running 14% faster than the master. This would trigger normal break detection circuitry which is designed to detect a 10 bit break symbol. When the LBKDE bit is set, framing errors are inhibited and the break detection threshold changes from 10 bits to 11 bits, preventing false detection of a 0x00 data character as a LIN break symbol.
14.2.6

7 6 5 4 3 2 1 0
R W Reset
R8 T8 0 0 TXDIR 0 TXINV 0 ORIE 0 NEIE 0 FEIE 0 PEIE 0
Field 7 R8 Description Ninth Data Bit for Receiver When the SCI is congured for 9-bit data (M = 1), R8 can be thought of as a ninth receive data bit to the left of the MSB of the buffered data in the SCIxD register. When reading 9-bit data, read R8 before reading SCIxD because reading SCIxD completes automatic ag clearing sequences which could allow R8 and SCIxD to be overwritten with new data. Ninth Data Bit for Transmitter When the SCI is congured for 9-bit data (M = 1), T8 may be thought of as a ninth transmit data bit to the left of the MSB of the data in the SCIxD register. When writing 9-bit data, the entire 9-bit value is transferred to the SCI shift register after SCIxD is written so T8 should be written (if it needs to change from its previous value) before SCIxD is written. If T8 does not need to change in the new value (such as when it is used to generate mark or space parity), it need not be written each time SCIxD is written. TxD Pin Direction in Single-Wire Mode When the SCI is congured for single-wire half-duplex operation (LOOPS = RSRC = 1), this bit determines the direction of data at the TxD pin. 0 TxD pin is an input in single-wire mode. 1 TxD pin is an output in single-wire mode.
6 T8
5 TXDIR

Field 4 TXINV1 3 ORIE 2 NEIE 1 FEIE Description Transmit Data Inversion Setting this bit reverses the polarity of the transmitted data output. 0 Transmit data not inverted 1 Transmit data inverted Overrun Interrupt Enable This bit enables the overrun ag (OR) to generate hardware interrupt requests. 0 OR interrupts disabled (use polling). 1 Hardware interrupt requested when OR = 1. Noise Error Interrupt Enable This bit enables the noise ag (NF) to generate hardware interrupt requests. 0 NF interrupts disabled (use polling). 1 Hardware interrupt requested when NF = 1. Framing Error Interrupt Enable This bit enables the framing error ag (FE) to generate hardware interrupt requests. 0 FE interrupts disabled (use polling). 1 Hardware interrupt requested when FE = 1. Parity Error Interrupt Enable This bit enables the parity error ag (PF) to generate hardware interrupt requests. 0 PF interrupts disabled (use polling). 1 Hardware interrupt requested when PF = 1.
0 PEIE
Setting TXINV inverts the TxD output for all cases: data bits, start and stop bits, break, and idle.
14.2.7
SCI Data Register (SCIxD)
This register is actually two separate registers. Reads return the contents of the read-only receive data buffer and writes go to the write-only transmit data buffer. Reads and writes of this register are also involved in the automatic ag clearing mechanisms for the SCI status ags.
7 6 5 4 3 2 1 0
R W Reset
R7 T7 0
R6 T6 0
R5 T5 0
R4 T4 0
R3 T3 0
R2 T2 0
R1 T1 0
R0 T0 0
Figure 14-11. SCI Data Register (SCIxD)
14.3
The SCI allows full-duplex, asynchronous, NRZ serial communication among the MCU and remote devices, including other MCUs. The SCI comprises a baud rate generator, transmitter, and receiver block. The transmitter and receiver operate independently, although they use the same baud rate generator. During normal operation, the MCU monitors the status of the SCI, writes the data to be transmitted, and processes received data. The following describes each of the blocks of the SCI.
14.3.1
Baud Rate Generation
As shown in Figure 14-12, the clock source for the SCI baud rate generator is the bus-rate clock.
MODULO DIVIDE BY (1 THROUGH 8191) DIVIDE BY 16 Tx BAUD RATE
BUSCLK
SBR12:SBR0 BAUD RATE GENERATOR OFF IF [SBR12:SBR0] = 0
Rx SAMPLING CLOCK (16 BAUD RATE) BAUD RATE = BUSCLK [SBR12:SBR0] 16
Figure 14-12. SCI Baud Rate Generation
SCI communications require the transmitter and receiver (which typically derive baud rates from independent clock sources) to use the same baud rate. Allowed tolerance on this baud frequency depends on the details of how the receiver synchronizes to the leading edge of the start bit and how bit sampling is performed. The MCU resynchronizes to bit boundaries on every high-to-low transition, but in the worst case, there are no such transitions in the full 10- or 11-bit time character frame so any mismatch in baud rate is accumulated for the whole character time. For a Freescale Semiconductor SCI system whose bus frequency is driven by a crystal, the allowed baud rate mismatch is about 4.5percent for 8-bit data format and about 4 percent for 9-bit data format. Although baud rate modulo di ider settings do not always v produce baud rates that exactly match standard rates, it is normally possible to get within a few percent, which is acceptable for reliable communications.
14.3.2
Transmitter Functional Description
This section describes the overall block diagram for the SCI transmitter, as well as specialized functions for sending break and idle characters. The transmitter block diagram is shown in Figure 14-2. The transmitter output (TxD) idle state defaults to logic high (TXINV = 0 following reset). The transmitter output is inverted by setting TXINV = 1. The transmitter is enabled by setting the TE bit in SCIxC2. This queues a preamble character that is one full character frame of the idle state. The transmitter then remains idle until data is available in the transmit data buffer. Programs store data into the transmit data buffer by writing to the SCI data register (SCIxD). The central element of the SCI transmitter is the transmit shift register that is either 10 or 11 bits long depending on the setting in the M control bit. For the remainder of this section, we will assume M = 0, selecting the normal 8-bit data mode. In 8-bit data mode, the shift register holds a start bit, eight data bits, and a stop bit. When the transmit shift register is available for a new SCI character, the value waiting in the transmit data register is transferred to the shift register (synchronized with the baud rate clock) and the transmit data register empty (TDRE) status ag is set to indicate another character may be written to the transmit data buffer at SCIxD. If no new character is waiting in the transmit data buffer after a stop bit is shifted out the TxD pin, the transmitter sets the transmit complete ag and enters an idle mode, with TxD high, waiting for more characters to transmit.
Writing 0 to TE does not immediately release the pin to be a general-purpose I/O pin. Any transmit activity that is in progress must rst be completed. This includes data characters in progress, queued idle characters, and queued break characters.
14.3.2.1
Send Break and Queued Idle
The SBK control bit in SCIxC2 is used to send break characters which were originally used to gain the attention of old teletype receivers. Break characters are a full character time of logic 0 (10 bit times including the start and stop bits). A longer break of 13 bit times can be enabled by setting BRK13 = 1. Normally, a program would wait for TDRE to become set to indicate the last character of a message has moved to the transmit shifter, then write 1 and then write 0 to the SBK bit. This action queues a break character to be sent as soon as the shifter is available. If SBK is still 1 when the queued break moves into the shifter (synchronized to the baud rate clock), an additional break character is queued. If the receiving device is another Freescale Semiconductor SCI, the break characters will be received as 0s in all eight data bits and a framing error (FE = 1) occurs. When idle-line wakeup is used, a full character time of idle (logic 1) is needed between messages to wake up any sleeping receivers. Normally, a program would wait for TDRE to become set to indicate the last character of a message has moved to the transmit shifter, then write 0 and then write 1 to the TE bit. This action queues an idle character to be sent as soon as the shifter is available. As long as the character in the shifter does not nish while TE = 0, the SCI transmitter never actually releases control of the TxD pin. If there is a possibility of the shifter nishing while TE = 0, set the general-purpose I/O controls so the pin that is shared with TxD is an output driving a logic 1. This ensures that the TxD line will look like a normal idle line even if the SCI loses control of the port pin between writing 0 and then 1 to TE. The length of the break character is affected by the BRK13 and M bits as shown below.
Table 14-9. Break Character Length
BRK13 0 0 1 1 M 0 1 0 1 Break Character Length 10 bit times 11 bit times 13 bit times 14 bit times
14.3.3
Receiver Functional Description
In this section, the receiver block diagram (Figure 14-3) is used as a guide for the overall receiver functional description. Next, the data sampling technique used to reconstruct receiver data is described in more detail. Finally, two variations of the receiver wakeup function are explained. The receiver input is inverted by setting RXINV = 1. The receiver is enabled by setting the RE bit in SCIxC2. Character frames consist of a start bit of logic 0, eight (or nine) data bits (LSB rst), and a stop bit of logic 1. For information about 9-bit data mode, refer to Section 14.3.5.1, 8- and 9-Bit Data Modes. For the remainder of this discussion, we assume the SCI is congured for normal 8-bit data mode. After receiving the stop bit into the receive shifter, and provided the receive data register is not already full, the data character is transferred to the receive data register and the receive data register full (RDRF) status
ag is set. If RDRF was already set indicating the receive data register (buffer) was already full, the overrun (OR) status ag is set and the new data is lost. Because the SCI receiver is double-buffered, the program has one full character time after RDRF is set before the data in the receive data buffer must be read to avoid a receiver overrun. When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive data register by reading SCIxD. The RDRF ag is cleared automatically by a 2-step sequence which is normally satised in the course of the users program that handles receive data. Refer to Section 14.3.4, Interrupts and Status Flags for more details about ag clearing.
14.3.3.1
Data Sampling Technique
The SCI receiver uses a 16 baud rate clock for sampling. The receiver starts by taking logic level samples at 16 times the baud rate to search for a falling edge on the RxD serial data input pin. A falling edge is dened as a logic 0 sample after three consecutive logic 1 samples. The 16 baud rate clock is used to divide the bit time into 16 segments labeled RT1 through RT16. When a falling edge is located, three more samples are taken at RT3, RT5, and RT7 to make sure this was a real start bit and not merely noise. If at least two of these three samples are 0, the receiver assumes it is synchronized to a receive character. The receiver then samples each bit time, including the start and stop bits, at RT8, RT9, and RT10 to determine the logic level for that bit. The logic level is interpreted to be that of the majority of the samples taken during the bit time. In the case of the start bit, the bit is assumed to be 0 if at least two of the samples at RT3, RT5, and RT7 are 0 even if one or all of the samples taken at RT8, RT9, and RT10 are 1s. If any sample in any bit time (including the start and stop bits) in a character frame fails to agree with the logic level for that bit, the noise ag (NF) will be set when the received character is transferred to the receive data buffer. The falling edge detection logic continuously looks for falling edges, and if an edge is detected, the sample clock is resynchronized to bit times. This improves the reliability of the receiver in the presence of noise or mismatched baud rates. It does not improve worst case analysis because some characters do not have any extra falling edges anywhere in the character frame. In the case of a framing error, provided the received character was not a break character, the sampling logic that searches for a falling edge is lled with three logic 1 samples so that a new start bit can be detected almost immediately. In the case of a framing error, the receiver is inhibited from receiving any new characters until the framing error ag is cleared. The receive shift register continues to function, but a complete character cannot transfer to the receive data buffer if FE is still set.
14.3.3.2
Receiver Wakeup Operation
Receiver wakeup is a hardware mechanism that allows an SCI receiver to ignore the characters in a message that is intended for a different SCI receiver. In such a system, all receivers evaluate the rst character(s) of each message, and as soon as they determine the message is intended for a different receiver, they write logic 1 to the receiver wake up (RWU) control bit in SCIxC2. When RWU bit is set, the status ags associated with the receiver (with the exception of the idle bit, IDLE, when RWUID bit is set) are inhibited from setting, thus eliminating the software overhead for handling the unimportant
message characters. At the end of a message, or at the beginning of the next message, all receivers automatically force RWU to 0 so all receivers wake up in time to look at the rst character(s) of the next message. 14.3.3.2.1 Idle-Line Wakeup
When WAKE = 0, the receiver is congured for idle-line wakeup. In this mode, RWU is cleared automatically when the receiver detects a full character time of the idle-line level. The M control bit selects 8-bit or 9-bit data mode that determines how many bit times of idle are needed to constitute a full character time (10 or 11 bit times because of the start and stop bits). When RWU is one and RWUID is zero, the idle condition that wakes up the receiver does not set the IDLE ag. The receiver wakes up and waits for the rst data character of the next message which will set the RDRF ag and generate an interrupt if enabled. When RWUID is one, any idle condition sets the IDLE ag and generates an interrupt if enabled, regardless of whether RWU is zero or one. The idle-line type (ILT) control bit selects one of two ways to detect an idle line. When ILT = 0, the idle bit counter starts after the start bit so the stop bit and any logic 1s at the end of a character count toward the full character time of idle. When ILT = 1, the idle bit counter does not start until after a stop bit time, so the idle detection is not affected by the data in the last character of the previous message. 14.3.3.2.2 Address-Mark Wakeup
When WAKE = 1, the receiver is congured for address-mark wakeup. In this mode, RWU is cleared automatically when the receiver detects a logic 1 in the most signicant bit of a received character (eighth bit in M = 0 mode and ninth bit in M = 1 mode). Address-mark wakeup allows messages to contain idle characters but requires that the MSB be reserved for use in address frames. The logic 1 MSB of an address frame clears the RWU bit before the stop bit is received and sets the RDRF ag. In this case the character with the MSB set is received even though the receiver was sleeping during most of this character time.
14.3.4
Interrupts and Status Flags
The SCI system has three separate interrupt vectors to reduce the amount of software needed to isolate the cause of the interrupt. One interrupt vector is associated with the transmitter for TDRE and TC events. Another interrupt vector is associated with the receiver for RDRF, IDLE, RXEDGIF and LBKDIF events, and a third vector is used for OR, NF, FE, and PF error conditions. Each of these ten interrupt sources can be separately masked by local interrupt enable masks. The ags can still be polled by software when the local masks are cleared to disable generation of hardware interrupt requests. The SCI transmitter has two status ags that optionally can generate hardware interrupt requests. Transmit data register empty (TDRE) indicates when there is room in the transmit data buffer to write another transmit character to SCIxD. If the transmit interrupt enable (TIE) bit is set, a hardware interrupt will be requested whenever TDRE = 1. Transmit complete (TC) indicates that the transmitter is nished transmitting all data, preamble, and break characters and is idle with TxD at the inactive level. This ag is often used in systems with modems to determine when it is safe to turn off the modem. If the transmit complete interrupt enable (TCIE) bit is set, a hardware interrupt will be requested whenever TC = 1.
Instead of hardware interrupts, software polling may be used to monitor the TDRE and TC status ags if the corresponding TIE or TCIE local interrupt masks are 0s. When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive data register by reading SCIxD. The RDRF ag is cleared by reading SCIxS1 while RDRF = 1 and then reading SCIxD. When polling is used, this sequence is naturally satised in the normal course of the user program. If hardware interrupts are used, SCIxS1 must be read in the interrupt service routine (ISR). Normally, this is done in the ISR anyway to check for receive errors, so the sequence is automatically satised. The IDLE status ag includes logic that prevents it from getting set repeatedly when the RxD line remains idle for an extended period of time. IDLE is cleared by reading SCIxS1 while IDLE = 1 and then reading SCIxD. After IDLE has been cleared, it cannot become set again until the receiver has received at least one new character and has set RDRF. If the associated error was detected in the received character that caused RDRF to be set, the error ags noise ag (NF), framing error (FE), and parity error ag (PF) get set at the same time as RDRF. These ags are not set in overrun cases. If RDRF was already set when a new character is ready to be transferred from the receive shifter to the receive data buffer, the overrun (OR) ag gets set instead the data along with any associated NF, FE, or PF condition is lost. At any time, an active edge on the RxD serial data input pin causes the RXEDGIF flag to set. The RXEDGIF ag is cleared by writing a 1 to it. This function does depend on the receiver being enabled (RE = 1).
14.3.5
Additional SCI Functions
The following sections describe additional SCI functions.
14.3.5.1
8- and 9-Bit Data Modes
The SCI system (transmitter and receiver) can be congured to operate in 9-bit data mode by setting the M control bit in SCIxC1. In 9-bit mode, there is a ninth data bit to the left of the MSB of the SCI data register. For the transmit data buffer, this bit is stored in T8 in SCIxC3. For the receiver, the ninth bit is held in R8 in SCIxC3. For coherent writes to the transmit data buffer, write to the T8 bit before writing to SCIxD. If the bit value to be transmitted as the ninth bit of a new character is the same as for the previous character, it is not necessary to write to T8 again. When data is transferred from the transmit data buffer to the transmit shifter, the value in T8 is copied at the same time data is transferred from SCIxD to the shifter. 9-bit data mode typically is used in conjunction with parity to allow eight bits of data plus the parity in the ninth bit. Or it is used with address-mark wakeup so the ninth data bit can serve as the wakeup bit. In custom protocols, the ninth bit can also serve as a software-controlled marker.
14.3.5.2
Stop Mode Operation
During all stop modes, clocks to the SCI module are halted. In stop1 and stop2 modes, all SCI register data is lost and must be re-initialized upon recovery from these two stop modes. No SCI module registers are affected in stop3 mode. The receive input active edge detect circuit is still active in stop3 mode, but not in stop2.. An active edge on the receive input brings the CPU out of stop3 mode if the interrupt is not masked (RXEDGIE = 1). Note, because the clocks are halted, the SCI module will resume operation upon exit from stop (only in stop3 mode). Software should ensure stop mode is not entered while there is a character being transmitted out of or received into the SCI module.
14.3.5.3
Loop Mode
When LOOPS = 1, the RSRC bit in the same register chooses between loop mode (RSRC = 0) or single-wire mode (RSRC = 1). Loop mode is sometimes used to check software, independent of connections in the external system, to help isolate system problems. In this mode, the transmitter output is internally connected to the receiver input and the RxD pin is not used by the SCI, so it reverts to a general-purpose port I/O pin.
14.3.5.4
Single-Wire Operation
When LOOPS = 1, the RSRC bit in the same register chooses between loop mode (RSRC = 0) or single-wire mode (RSRC = 1). Single-wire mode is used to implement a half-duplex serial connection. The receiver is internally connected to the transmitter output and to the TxD pin. The RxD pin is not used and reverts to a general-purpose port I/O pin. In single-wire mode, the TXDIR bit in SCIxC3 controls the direction of serial data on the TxD pin. When TXDIR = 0, the TxD pin is an input to the SCI receiver and the transmitter is temporarily disconnected from the TxD pin so an external device can send serial data to the receiver. When TXDIR = 1, the TxD pin is an output driven by the transmitter. In single-wire mode, the internal loop back connection from the transmitter to the receiver causes the receiver to receive characters that are sent out by the transmitter.

15.1 Introduction
The RTC module consists of one 8-bit counter, one 8-bit comparator, several binary-based and decimal-based prescaler dividers, three clock sources, and one programmable periodic interrupt. This module can be used for time-of-day, calendar or any task scheduling functions. It can also serve as a cyclic wake up from low power modes without the need of external components. All devices in the MC9S08DZ60 Series feature the RTC.
15.1.1
RTC Clock Signal Names
References to ERCLK and IRCLK in this chapter correspond to signals MCGERCLK and MCGIRCLK, respectively.
BDC
BKP
PORT G
PORT F
PORT E
PORT D
PORT B
15.1.2
Features
Features of the RTC module include: 8-bit up-counter 8-bit modulo match limit Software controllable periodic interrupt on match Three software selectable clock sources for input to prescaler with selectable binary-based and decimal-based divider values 1-kHz internal low-power oscillator (LPO) External clock (ERCLK) 32-kHz internal clock (IRCLK)
15.1.3
Modes of Operation
This section denes the operation in stop, wait and background debug modes.
15.1.3.1
Wait Mode
The RTC continues to run in wait mode if enabled before executing the appropriate instruction. Therefore, the RTC can bring the MCU out of wait mode if the real-time interrupt is enabled. For lowest possible current consumption, the RTC should be stopped by software if not needed as an interrupt source during wait mode.
15.1.3.2
Stop Modes
The RTC continues to run in stop2 or stop3 mode if the RTC is enabled before executing the STOP instruction. Therefore, the RTC can bring the MCU out of stop modes with no external components, if the real-time interrupt is enabled. The LPO clock can be used in stop2 and stop3 modes. ERCLK and IRCLK clocks are only available in stop3 mode. Power consumption is lower when all clock sources are disabled, but in that case, the real-time interrupt cannot wake up the MCU from stop modes.
15.1.3.3
Active Background Mode
The RTC suspends all counting during active background mode until the microcontroller returns to normal user operating mode. Counting resumes from the suspended value as long as the RTCMOD register is not written and the RTCPS and RTCLKS bits are not altered.
15.1.4
Block Diagram
The block diagram for the RTC module is shown in Figure 15-2.
LPO ERCLK IRCLK 8-Bit Modulo (RTCMOD)
VDD
Clock Source Select
RTCLKS
Background Mode
RTCLKS[0] RTCPS
RTIF
RTC Interrupt Request
8-Bit Comparator
E R
Write 1 to RTIF RTIE
Prescaler Divide-By
RTC Clock
8-Bit Counter (RTCCNT)
Figure 15-2. Real-Time Counter (RTC) Block Diagram
15.2
The RTC does not include any off-chip signals.
15.3
Register Denition
The RTC includes a status and control register, an 8-bit counter register, and an 8-bit modulo register. Refer to the direct-page register summary in the memory section of this document for the absolute address assignments for all RTC registers.This section refers to registers and control bits only by their names and relative address offsets. Table 15-1 is a summary of RTC registers.
Table 15-1. RTC Register Summary
Name R RTCSC W R RTCCNT W R RTCMOD W RTCMOD RTCCNT RTIF RTCLKS RTIE RTCPS
7 6 5 4 3 2 1 0
15.3.1
RTC Status and Control Register (RTCSC)
RTCSC contains the real-time interrupt status ag (RTIF), the clock select bits (RTCLKS), the real-time interrupt enable bit (RTIE), and the prescaler select bits (RTCPS).
7 6 5 4 3 2 1 0
R RTIF W Reset: 0 0 0 0 0 0 0 0 RTCLKS RTIE RTCPS
Figure 15-3. RTC Status and Control Register (RTCSC) Table 15-2. RTCSC Field Descriptions
Field 7 RTIF Description Real-Time Interrupt Flag This status bit indicates the RTC counter register reached the value in the RTC modulo register. Writing a logic 0 has no effect. Writing a logic 1 clears the bit and the real-time interrupt request. Reset clears RTIF. 0 RTC counter has not reached the value in the RTC modulo register. 1 RTC counter has reached the value in the RTC modulo register. Real-Time Clock Source Select. These two read/write bits select the clock source input to the RTC prescaler. Changing the clock source clears the prescaler and RTCCNT counters. When selecting a clock source, ensure that the clock source is properly enabled (if applicable) to ensure correct operation of the RTC. Reset clears RTCLKS. 00 Real-time clock source is the 1-kHz low power oscillator (LPO) 01 Real-time clock source is the external clock (ERCLK) 1x Real-time clock source is the internal clock (IRCLK) Real-Time Interrupt Enable. This read/write bit enables real-time interrupts. If RTIE is set, then an interrupt is generated when RTIF is set. Reset clears RTIE. 0 Real-time interrupt requests are disabled. Use software polling. 1 Real-time interrupt requests are enabled. Real-Time Clock Prescaler Select. These four read/write bits select binary-based or decimal-based divide-by values for the clock source. See Table 15-3. Changing the prescaler value clears the prescaler and RTCCNT counters. Reset clears RTCPS.
65 RTCLKS
4 RTIE
30 RTCPS
Table 15-3. RTC Prescaler Divide-by values

RTCPS RTCLKS[0] 0 0 1 Off Off 1 23 210 2 25 211 3 26 212 4 27 213 5 28 214 6 29 215 7 210 216 8 1 103 9 2 10 22 11 10 104 12 24 13 102 14 5x102 105 15 103 2x105
2x103 5x103
2x104 5x104
15.3.2
RTC Counter Register (RTCCNT)
RTCCNT is the read-only value of the current RTC count of the 8-bit counter.
7 6 5 4 3 2 1 0
R W Reset: 0 0 0 0
RTCCNT
Figure 15-4. RTC Counter Register (RTCCNT) Table 15-4. RTCCNT Field Descriptions
Field 7:0 RTCCNT Description RTC Count. These eight read-only bits contain the current value of the 8-bit counter. Writes have no effect to this register. Reset, writing to RTCMOD, or writing different values to RTCLKS and RTCPS clear the count to 0x00.
15.3.3
RTC Modulo Register (RTCMOD)

7 6 5 4 3 2 1 0
R RTCMOD W Reset: 0 0 0 0 0 0 0 0
Figure 15-5. RTC Modulo Register (RTCMOD) Table 15-5. RTCMOD Field Descriptions
Field Description
7:0 RTC Modulo. These eight read/write bits contain the modulo value used to reset the count to 0x00 upon a compare RTCMOD match and set the RTIF status bit. A value of 0x00 sets the RTIF bit on each rising edge of the prescaler output. Writing to RTCMOD resets the prescaler and the RTCCNT counters to 0x00. Reset sets the modulo to 0x00.
15.4
The RTC is composed of a main 8-bit up-counter with an 8-bit modulo register, a clock source selector, and a prescaler block with binary-based and decimal-based selectable values. The module also contains software selectable interrupt logic. After any MCU reset, the counter is stopped and reset to 0x00, the modulus register is set to 0x00, and the prescaler is off. The 1-kHz internal oscillator clock is selected as the default clock source. To start the prescaler, write any value other than zero to the prescaler select bits (RTCPS). Three clock sources are software selectable: the low power oscillator clock (LPO), the external clock (ERCLK), and the internal clock (IRCLK). The RTC clock select bits (RTCLKS) select the desired clock source. If a different value is written to RTCLKS, the prescaler and RTCCNT counters are reset to 0x00.
RTCPS and the RTCLKS[0] bit select the desired divide-by value. If a different value is written to RTCPS, the prescaler and RTCCNT counters are reset to 0x00. Table 15-6 shows different prescaler period values.
Table 15-6. Prescaler Period
RTCPS 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 1-kHz Internal Clock (RTCLKS = 00) Off 8 ms 32 ms 64 ms 128 ms 256 ms 512 ms 1.024 s 1 ms 2 ms 4 ms 10 ms 16 ms 0.1 s 0.5 s 1s 1-MHz External Clock 32-kHz Internal Clock 32-kHz Internal Clock (RTCLKS = 01) (RTCLKS = 10) (RTCLKS = 11) Off 1.024 ms 2.048 ms 4.096 ms 8.192 ms 16.4 ms 32.8 ms 65.5 ms 1 ms 2 ms 5 ms 10 ms 20 ms 50 ms 0.1 s 0.2 s Off 250 s 1 ms 2 ms 4 ms 8 ms 16 ms 32 ms 31.25 s 62.5 s 125 s 312.5 s 0.5 ms 3.125 ms 15.625 ms 31.25 ms Off 32 ms 64 ms 128 ms 256 ms 512 ms 1.024 s 2.048 s 31.25 ms 62.5 ms 156.25 ms 312.5 ms 0.625 s 1.5625 s 3.125 s 6.25 s
The RTC modulo register (RTCMOD) allows the compare value to be set to any value from 0x00 to 0xFF. When the counter is active, the counter increments at the selected rate until the count matches the modulo value. When these values match, the counter resets to 0x00 and continues counting. The real-time interrupt ag (RTIF) is set when a match occurs. The ag sets on the transition from the modulo value to 0x00. Writing to RTCMOD resets the prescaler and the RTCCNT counters to 0x00. The RTC allows for an interrupt to be generated when RTIF is set. To enable the real-time interrupt, set the real-time interrupt enable bit (RTIE) in RTCSC. RTIF is cleared by writing a 1 to RTIF.
15.4.1
RTC Operation Example
This section shows an example of the RTC operation as the counter reaches a matching value from the modulo register.
Internal 1-kHz Clock Source RTC Clock (RTCPS = 0xA) RTCCNT 0x52 0x53 0x54 0x55 0x00 0x01
RTIF
RTCMOD
0x55
Figure 15-6. RTC Counter Overow Example
In the example of Figure 15-6, the selected clock source is the 1-kHz internal oscillator clock source. The prescaler (RTCPS) is set to 0xA or divide-by-4. The modulo value in the RTCMOD register is set to 0x55. When the counter, RTCCNT, reaches the modulo value of 0x55, the counter overows to 0x00 and continues counting. The real-time interrupt ag, RTIF, sets when the counter value changes from 0x55 to 0x00. A real-time interrupt is generated when RTIF is set, if RTIE is set.
15.5
This section provides example code to give some basic direction to a user on how to initialize and congure the RTC module. The example software is implemented in C language. The example below shows how to implement time of day with the RTC using the 1-kHz clock source to achieve the lowest possible power consumption. Because the 1-kHz clock source is not as accurate as a crystal, software can be added for any adjustments. For accuracy without adjustments at the expense of additional power consumption, the external clock (ERCLK) or the internal clock (IRCLK) can be selected with appropriate prescaler and modulo values.
/* Initialize the elapsed time counters */ Seconds = 0; Minutes = 0; Hours = 0; Days=0; /* Configure RTC to interrupt every 1 second from 1-kHz clock source */ RTCMOD.byte = 0x00; RTCSC.byte = 0x1F; /********************************************************************** Function Name : RTC_ISR Notes : Interrupt service routine for RTC module. **********************************************************************/
#pragma TRAP_PROC void RTC_ISR(void) { /* Clear the interrupt flag */ RTCSC.byte = RTCSC.byte | 0x80; /* RTC interrupts every 1 Second */ Seconds++; /* 60 seconds in a minute */ if (Seconds > 59){ Minutes++; Seconds = 0; } /* 60 minutes in an hour */ if (Minutes > 59){ Hours++; Minutes = 0; } /* 24 hours in a day */ if (Hours > 23){ Days ++; Hours = 0; }
Chapter 16 Timer Pulse-Width Modulator (S08TPMV3)

NOTE This chapter refers to S08TPM version 3, which applies to the 0M74K and newer mask sets of this device. 3M05C and older mask set devices use S08TPM version 2. If your device uses mask 3M05C or older, please refer to Appendix B, Timer Pulse-Width Modulator (TPMV2) on page 391 for information pertaining to that module.
16.1
Introduction
The TPM is a one-to-eight-channel timer system which supports traditional input capture, output compare, or edge-aligned PWM on each channel. A control bit allows the TPM to be congured such that all channels may be used for center-aligned PWM functions. Timing functions are based on a 16-bit counter with prescaler and modulo features to control frequency and range (period between overows) of the time reference. This timing system is ideally suited for a wide range of control applications, and the center-aligned PWM capability extends the eld of application to motor control in small appliances. The TPM uses one input/output (I/O) pin per channel, TPMxCHn, where x is the TPM number (for example, 1 or 2) and n is the channel number (for example, 05). The TPM shares its I/O pins with general-purpose I/O port pins (refer to the Pins and Connections chapter for more information). MC9S08DZ60 Series MCUs have two TPM modules. In all packages, TPM2 is 2-channel. The number of channels available on external pins in TPM1 depends on the package: Six channels in 64-pin and 48-pin packages Four channels in 32-pin packages.
Chapter 16 Timer Pulse-Width Modulator (S08TPMV3)
BDC
BKP
HCS08 SYSTEM CONTROL RESET RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT COP INT VREFH VREFL VDDA VSSA LVD IRQ 24-CHANNEL,12--BIT ANALOG-TO-DIGITAL CONVERTER (ADC) 8 IRQ ADP7-ADP0 ADP15-ADP8 ADP23-ADP16 PORT C 2-CHANNEL TIMER/PWM MODULE (TPM2) USER EEPROM MC9S0DZ60 = 2K CONTROLLER AREA NETWORK (MSCAN) SERIAL PERIPHERAL INTERFACE MODULE (SPI) SERIAL COMMUNICATIONS INTERFACE (SCI1) ANALOG COMPARATOR (ACMP2) IIC MODULE (IIC) SERIAL COMMUNICATIONS INTERFACE (SCI2) MULTI-PURPOSE CLOCK GENERATOR (MCG) OSCILLATOR (XOSC) - VREFH/VREFL internally connected to VDDA/VSSA in 48-pin and 32-pin packages - VDD and VSS pins are each internally connected to two pads in 32-pin package XTAL EXTAL TPM2CH1, TPM2CH0 TPM2CLK RxCAN TxCAN MISO MOSI SPSCK SS RxD1 TxD1 ACMP2O ACMP2ACMP2+ SDA SCL RxD2 TxD2 DEBUG MODULE (DBG) REAL-TIME COUNTER (RTC) VDD VDD VSS VSS VOLTAGE REGULATOR
PORT G
PORT F
PORT E
PORT D
PORT B
Chapter 16 Timer/PWM Module (S08TPMV3)
16.1.1
Features
The TPM includes these distinctive features: One to eight channels: Each channel may be input capture, output compare, or edge-aligned PWM Rising-Edge, falling-edge, or any-edge input capture trigger Set, clear, or toggle output compare action Selectable polarity on PWM outputs Module may be congured for buffered, center-aligned pulse-width-modulation (CPWM) on all channels Timer clock source selectable as prescaled bus clock, xed system clock, or an external clock pin Prescale taps for divide-by 1, 2, 4, 8, 16, 32, 64, or 128 Fixed system clock source are synchronized to the bus clock by an on-chip synchronization circuit External clock pin may be shared with any timer channel pin or a separated input pin 16-bit free-running or modulo up/down count operation Timer system enable One interrupt per channel plus terminal count interrupt
16.1.2
Modes of Operation
In general, TPM channels may be independently congured to operate in input capture, output compare, or edge-aligned PWM modes. A control bit allows the whole TPM (all channels) to switch to center-aligned PWM mode. When center-aligned PWM mode is selected, input capture, output compare, and edge-aligned PWM functions are not available on any channels of this TPM module. When the microcontroller is in active BDM background or BDM foreground mode, the TPM temporarily suspends all counting until the microcontroller returns to normal user operating mode. During stop mode, all system clocks, including the main oscillator, are stopped; therefore, the TPM is effectively disabled until clocks resume. During wait mode, the TPM continues to operate normally. Provided the TPM does not need to produce a real time reference or provide the interrupt source(s) needed to wake the MCU from wait mode, the user can save power by disabling TPM functions before entering wait mode. Input capture mode When a selected edge event occurs on the associated MCU pin, the current value of the 16-bit timer counter is captured into the channel value register and an interrupt ag bit is set. Rising edges, falling edges, any edge, or no edge (disable channel) may be selected as the active edge which triggers the input capture. Output compare mode When the value in the timer counter register matches the channel value register, an interrupt ag bit is set, and a selected output action is forced on the associated MCU pin. The output compare action may be selected to force the pin to zero, force the pin to one, toggle the pin, or ignore the pin (used for software timing functions).
Edge-aligned PWM mode The value of a 16-bit modulo register plus 1 sets the period of the PWM output signal. The channel value register sets the duty cycle of the PWM output signal. The user may also choose the polarity of the PWM output signal. Interrupts are available at the end of the period and at the duty-cycle transition point. This type of PWM signal is called edge-aligned because the leading edges of all PWM signals are aligned with the beginning of the period, which is the same for all channels within a TPM. Center-aligned PWM mode Twice the value of a 16-bit modulo register sets the period of the PWM output, and the channel-value register sets the half-duty-cycle duration. The timer counter counts up until it reaches the modulo value and then counts down until it reaches zero. As the count matches the channel value register while counting down, the PWM output becomes active. When the count matches the channel value register while counting up, the PWM output becomes inactive. This type of PWM signal is called center-aligned because the centers of the active duty cycle periods for all channels are aligned with a count value of zero. This type of PWM is required for types of motors used in small appliances.
This is a high-level description only. Detailed descriptions of operating modes are in later sections.
16.1.3
Block Diagram
The TPM uses one input/output (I/O) pin per channel, TPMxCHn (timer channel n) where n is the channel number (1-8). The TPM shares its I/O pins with general purpose I/O port pins (refer to I/O pin descriptions in full-chip specication for the specic chip implementation). Figure 16-2 shows the TPM structure. The central component of the TPM is the 16-bit counter that can operate as a free-running counter or a modulo up/down counter. The TPM counter (when operating in normal up-counting mode) provides the timing reference for the input capture, output compare, and edge-aligned PWM functions. The timer counter modulo registers, TPMxMODH:TPMxMODL, control the modulo value of the counter (the values 0x0000 or 0xFFFF effectively make the counter free running). Software can read the counter value at any time without affecting the counting sequence. Any write to either half of the TPMxCNT counter resets the counter, regardless of the data value written.
BUS CLOCK FIXED SYSTEM CLOCK EXTERNAL CLOCK
SYNC
CLOCK SOURCE SELECT OFF, BUS, FIXED SYSTEM CLOCK, EXT
PRESCALE AND SELECT 1, 2, 4, 8, 16, 32, 64, or 128
CLKSB:CLKSA CPWMS 16-BIT COUNTER COUNTER RESET 16-BIT COMPARATOR TPMxMODH:TPMxMODL ELS0B ELS0A
PS2:PS1:PS0
TOF TOIE
INTERRUPT LOGIC
CHANNEL 0 16-BIT COMPARATOR TPMxC0VH:TPMxC0VL 16-BIT LATCH
PORT LOGIC CH0F INTERRUPT LOGIC
TPMxCH0
MS0B
MS0A
CH0IE
INTERNAL BUS
ELS1B
ELS1A
TPMxCH1
MS1B
MS1A
CH1IE
Up to 8 channels
ELS7B
ELS7A
TPMxCH7
MS7B
MS7A
CH7IE
Figure 16-2. TPM Block Diagram
The TPM channels are programmable independently as input capture, output compare, or edge-aligned PWM channels. Alternately, the TPM can be congured to produce CPWM outputs on all channels. When the TPM is congured for CPWMs, the counter operates as an up/down counter; input capture, output compare, and EPWM functions are not practical. If a channel is congured as input capture, an internal pullup device may be enabled for that channel. The details of how a module interacts with pin controls depends upon the chip implementation because the I/O pins and associated general purpose I/O controls are not part of the module. Refer to the discussion of the I/O port logic in a full-chip specication. Because center-aligned PWMs are usually used to drive 3-phase AC-induction motors and brushless DC motors, they are typically used in sets of three or six channels.
16.2
Signal Description
Table 16-1 shows the user-accessible signals for the TPM. The number of channels may be varied from one to eight. When an external clock is included, it can be shared with the same pin as any TPM channel; however, it could be connected to a separate input pin. Refer to the I/O pin descriptions in full-chip specication for the specic chip implementation.
Name EXTCLK1 TPMxCHn
1 2
Function External clock source which may be selected to drive the TPM counter. I/O pin associated with TPM channel n
When preset, this signal can share any channel pin; however depending upon full-chip implementation, this signal could be connected to a separate external pin. 2 n=channel number (1 to 8)
Refer to documentation for the full-chip for details about reset states, port connections, and whether there is any pullup device on these pins. TPM channel pins can be associated with general purpose I/O pins and have passive pullup devices which can be enabled with a control bit when the TPM or general purpose I/O controls have congured the associated pin as an input. When no TPM function is enabled to use a corresponding pin, the pin reverts to being controlled by general purpose I/O controls, including the port-data and data-direction registers. Immediately after reset, no TPM functions are enabled, so all associated pins revert to general purpose I/O control.
16.2.1
Detailed Signal Descriptions
This section describes each user-accessible pin signal in detail. Although Table 16-1 grouped all channel pins together, any TPM pin can be shared with the external clock source signal. Since I/O pin logic is not part of the TPM, refer to full-chip documentation for a specic derivative for more details about the interaction of TPM pin functions and general purpose I/O controls including port data, data direction, and pullup controls.
16.2.1.1
EXTCLK External Clock Source
Control bits in the timer status and control register allow the user to select nothing (timer disable), the bus-rate clock (the normal default source), a crystal-related clock, or an external clock as the clock which drives the TPM prescaler and subsequently the 16-bit TPM counter. The external clock source is synchronized in the TPM. The bus clock clocks the synchronizer; the frequency of the external source must be no more than one-fourth the frequency of the bus-rate clock, to meet Nyquist criteria and allowing for jitter. The external clock signal shares the same pin as a channel I/O pin, so the channel pin will not be usable for channel I/O function when selected as the external clock source. It is the users responsibility to avoid such settings. If this pin is used as an external clock source (CLKSB:CLKSA = 1:1), the channel can still be used in output compare mode as a software timer (ELSnB:ELSnA = 0:0).
16.2.1.2
TPMxCHn TPM Channel n I/O Pin(s)
Each TPM channel is associated with an I/O pin on the MCU. The function of this pin depends on the channel conguration. The TPM pins share with general purpose I/O pins, where each pin has a port data register bit, and a data direction control bit, and the port has optional passive pullups which may be enabled whenever a port pin is acting as an input. The TPM channel does not control the I/O pin when (ELSnB:ELSnA = 0:0) or when (CLKSB:CLKSA = 0:0) so it normally reverts to general purpose I/O control. When CPWMS = 1 (and ELSnB:ELSnA not = 0:0), all channels within the TPM are congured for center-aligned PWM and the TPMxCHn pins are all controlled by the TPM system. When CPWMS=0, the MSnB:MSnA control bits determine whether the channel is congured for input capture, output compare, or edge-aligned PWM. When a channel is congured for input capture (CPWMS=0, MSnB:MSnA = 0:0 and ELSnB:ELSnA not = 0:0), the TPMxCHn pin is forced to act as an edge-sensitive input to the TPM. ELSnB:ELSnA control bits determine what polarity edge or edges will trigger input-capture events. A synchronizer based on the bus clock is used to synchronize input edges to the bus clock. This implies the minimum pulse widththat can be reliably detectedon an input capture pin is four bus clock periods (with ideal clock pulses as near as two bus clocks can be detected). TPM uses this pin as an input capture input to override the port data and data direction controls for the same pin. When a channel is congured for output compare (CPWMS=0, MSnB:MSnA = 0:1 and ELSnB:ELSnA not = 0:0), the associated data direction control is overridden, the TPMxCHn pin is considered an output controlled by the TPM, and the ELSnB:ELSnA control bits determine how the pin is controlled. The remaining three combinations of ELSnB:ELSnA determine whether the TPMxCHn pin is toggled, cleared, or set each time the 16-bit channel value register matches the timer counter. When the output compare toggle mode is initially selected, the previous value on the pin is driven out until the next output compare eventthen the pin is toggled.
When a channel is congured for edge-aligned PWM (CPWMS=0, MSnB=1 and ELSnB:ELSnA not = 0:0), the data direction is overridden, the TPMxCHn pin is forced to be an output controlled by the TPM, and ELSnA controls the polarity of the PWM output signal on the pin. When ELSnB:ELSnA=1:0, the TPMxCHn pin is forced high at the start of each new period (TPMxCNT=0x0000), and the pin is forced low when the channel value register matches the timer counter. When ELSnA=1, the TPMxCHn pin is forced low at the start of each new period (TPMxCNT=0x0000), and the pin is forced high when the channel value register matches the timer counter.
TPMxMODH:TPMxMODL = 0x0008 TPMxCnVH:TPMxCnVL = 0x0005
TPMxCNTH:TPMxCNTL TPMxCHn CHnF BIT TOF BIT
...
...
Figure 16-3. High-True Pulse of an Edge-Aligned PWM

...
...
Figure 16-4. Low-True Pulse of an Edge-Aligned PWM
When the TPM is congured for center-aligned PWM (and ELSnB:ELSnA not = 0:0), the data direction for all channels in this TPM are overridden, the TPMxCHn pins are forced to be outputs controlled by the TPM, and the ELSnA bits control the polarity of each TPMxCHn output. If ELSnB:ELSnA=1:0, the corresponding TPMxCHn pin is cleared when the timer counter is counting up, and the channel value register matches the timer counter; the TPMxCHn pin is set when the timer counter is counting down, and the channel value register matches the timer counter. If ELSnA=1, the corresponding TPMxCHn pin is set when the timer counter is counting up and the channel value register matches the timer counter; the TPMxCHn pin is cleared when the timer counter is counting down and the channel value register matches the timer counter.
...
...
Figure 16-5. High-True Pulse of a Center-Aligned PWM

...
...
Figure 16-6. Low-True Pulse of a Center-Aligned PWM
16.3
Register Denition
This section consists of register descriptions in address order. A typical MCU system may contain multiple TPMs, and each TPM may have one to eight channels, so register names include placeholder characters to identify which TPM and which channel is being referenced. For example, TPMxCnSC refers to timer (TPM) x, channel n. TPM1C2SC would be the status and control register for channel 2 of timer 1.
16.3.1
TPM Status and Control Register (TPMxSC)
TPMxSC contains the overow status ag and control bits used to congure the interrupt enable, TPM conguration, clock source, and prescale factor. These controls relate to all channels within this timer module.
7 6 5 4 3 2 1 0
R W Reset
TOF TOIE 0 0 0 0 0 0 0 0 0 CPWMS CLKSB CLKSA PS2 PS1 PS0
Figure 16-7. TPM Status and Control Register (TPMxSC) Table 16-2. TPMxSC Field Descriptions
Field 7 TOF Description Timer overow ag. This read/write ag is set when the TPM counter resets to 0x0000 after reaching the modulo value programmed in the TPM counter modulo registers. Clear TOF by reading the TPM status and control register when TOF is set and then writing a logic 0 to TOF. If another TPM overow occurs before the clearing sequence is complete, the sequence is reset so TOF would remain set after the clear sequence was completed for the earlier TOF. This is done so a TOF interrupt request cannot be lost during the clearing sequence for a previous TOF. Reset clears TOF. Writing a logic 1 to TOF has no effect. 0 TPM counter has not reached modulo value or overow 1 TPM counter has overowed Timer overow interrupt enable. This read/write bit enables TPM overow interrupts. If TOIE is set, an interrupt is generated when TOF equals one. Reset clears TOIE. 0 TOF interrupts inhibited (use for software polling) 1 TOF interrupts enabled Center-aligned PWM select. When present, this read/write bit selects CPWM operating mode. By default, the TPM operates in up-counting mode for input capture, output compare, and edge-aligned PWM functions. Setting CPWMS recongures the TPM to operate in up/down counting mode for CPWM functions. Reset clears CPWMS. 0 All channels operate as input capture, output compare, or edge-aligned PWM mode as selected by the MSnB:MSnA control bits in each channels status and control register. 1 All channels operate in center-aligned PWM mode.
6 TOIE
5 CPWMS
Table 16-2. TPMxSC Field Descriptions (continued)

Field Description
43 Clock source selects. As shown in Table 16-3, this 2-bit eld is used to disable the TPM system or select one of CLKS[B:A] three clock sources to drive the counter prescaler. The xed system clock source is only meaningful in systems with a PLL-based or FLL-based system clock. When there is no PLL or FLL, the xed-system clock source is the same as the bus rate clock. The external source is synchronized to the bus clock by TPM module, and the xed system clock source (when a PLL or FLL is present) is synchronized to the bus clock by an on-chip synchronization circuit. When a PLL or FLL is present but not enabled, the xed-system clock source is the same as the bus-rate clock. 20 PS[2:0] Prescale factor select. This 3-bit eld selects one of 8 division factors for the TPM clock input as shown in Table 16-4. This prescaler is located after any clock source synchronization or clock source selection so it affects the clock source selected to drive the TPM system. The new prescale factor will affect the clock source on the next system clock cycle after the new value is updated into the register bits.
Table 16-3. TPM-Clock-Source Selection

CLKSB:CLKSA 00 01 10 11 TPM Clock Source to Prescaler Input No clock selected (TPM counter disable) Bus rate clock Fixed system clock External source
Table 16-4. Prescale Factor Selection

PS2:PS1:PS0 000 001 010 011 100 101 110 111 TPM Clock Source Divided-by 1 2 4 8 16 32 64 128
16.3.2
TPM-Counter Registers (TPMxCNTH:TPMxCNTL)
The two read-only TPM counter registers contain the high and low bytes of the value in the TPM counter. Reading either byte (TPMxCNTH or TPMxCNTL) latches the contents of both bytes into a buffer where they remain latched until the other half is read. This allows coherent 16-bit reads in either big-endian or little-endian order which makes this more friendly to various compiler implementations. The coherency mechanism is automatically restarted by an MCU reset or any write to the timer status/control register (TPMxSC).
Reset clears the TPM counter registers. Writing any value to TPMxCNTH or TPMxCNTL also clears the TPM counter (TPMxCNTH:TPMxCNTL) and resets the coherency mechanism, regardless of the data involved in the write.
7 6 5 4 3 2 1 0
R W Reset
Bit 15
14
13
12
11
10
Bit 8
Any write to TPMxCNTH clears the 16-bit counter 0 0 0 0 0 0 0 0
Figure 16-8. TPM Counter Register High (TPMxCNTH)

7 6 5 4 3 2 1 0
R W Reset
Bit 7
Bit 0
Any write to TPMxCNTL clears the 16-bit counter 0 0 0 0 0 0 0 0
Figure 16-9. TPM Counter Register Low (TPMxCNTL)
When BDM is active, the timer counter is frozen (this is the value that will be read by user); the coherency mechanism is frozen such that the buffer latches remain in the state they were in when the BDM became active, even if one or both counter halves are read while BDM is active. This assures that if the user was in the middle of reading a 16-bit register when BDM became active, it will read the appropriate value from the other half of the 16-bit value after returning to normal execution. In BDM mode, writing any value to TPMxSC, TPMxCNTH or TPMxCNTL registers resets the read coherency mechanism of the TPMxCNTH:L registers, regardless of the data involved in the write.
16.3.3
TPM Counter Modulo Registers (TPMxMODH:TPMxMODL)
The read/write TPM modulo registers contain the modulo value for the TPM counter. After the TPM counter reaches the modulo value, the TPM counter resumes counting from 0x0000 at the next clock, and the overow ag (TOF) becomes set. Writing to TPMxMODH or TPMxMODL inhibits the TOF bit and overow interrupts until the other byte is written. Reset sets the TPM counter modulo registers to 0x0000 which results in a free running timer counter (modulo disabled). Writing to either byte (TPMxMODH or TPMxMODL) latches the value into a buffer and the registers are updated with the value of their write buffer according to the value of CLKSB:CLKSA bits, so: If (CLKSB:CLKSA = 0:0), then the registers are updated when the second byte is written If (CLKSB:CLKSA not = 0:0), then the registers are updated after both bytes were written, and the TPM counter changes from (TPMxMODH:TPMxMODL - 1) to (TPMxMODH:TPMxMODL). If the TPM counter is a free-running counter, the update is made when the TPM counter changes from 0xFFFE to 0xFFFF The latching mechanism may be manually reset by writing to the TPMxSC address (whether BDM is active or not).
When BDM is active, the coherency mechanism is frozen (unless reset by writing to TPMxSC register) such that the buffer latches remain in the state they were in when the BDM became active, even if one or both halves of the modulo register are written while BDM is active. Any write to the modulo registers bypasses the buffer latches and directly writes to the modulo register while BDM is active.
7 6 5 4 3 2 1 0
R Bit 15 W Reset 0 0 0 0 0 0 0 0 14 13 12 11 10 9 Bit 8
Figure 16-10. TPM Counter Modulo Register High (TPMxMODH)

7 6 5 4 3 2 1 0
R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0
Figure 16-11. TPM Counter Modulo Register Low (TPMxMODL)
Reset the TPM counter before writing to the TPM modulo registers to avoid confusion about when the rst counter overow will occur.
16.3.4
TPM Channel n Status and Control Register (TPMxCnSC)
TPMxCnSC contains the channel-interrupt-status ag and control bits used to congure the interrupt enable, channel conguration, and pin function.
7 6 5 4 3 2 1 0
R W Reset
CHnF CHnIE 0 0 0 0 0 0 0 MSnB MSnA ELSnB ELSnA
Figure 16-12. TPM Channel n Status and Control Register (TPMxCnSC)
Table 16-5. TPMxCnSC Field Descriptions

Field 7 CHnF Description Channel n ag. When channel n is an input-capture channel, this read/write bit is set when an active edge occurs on the channel n pin. When channel n is an output compare or edge-aligned/center-aligned PWM channel, CHnF is set when the value in the TPM counter registers matches the value in the TPM channel n value registers. When channel n is an edge-aligned/center-aligned PWM channel and the duty cycle is set to 0% or 100%, CHnF will not be set even when the value in the TPM counter registers matches the value in the TPM channel n value registers. A corresponding interrupt is requested when CHnF is set and interrupts are enabled (CHnIE = 1). Clear CHnF by reading TPMxCnSC while CHnF is set and then writing a logic 0 to CHnF. If another interrupt request occurs before the clearing sequence is complete, the sequence is reset so CHnF remains set after the clear sequence completed for the earlier CHnF. This is done so a CHnF interrupt request cannot be lost due to clearing a previous CHnF. Reset clears the CHnF bit. Writing a logic 1 to CHnF has no effect. 0 No input capture or output compare event occurred on channel n 1 Input capture or output compare event on channel n Channel n interrupt enable. This read/write bit enables interrupts from channel n. Reset clears CHnIE. 0 Channel n interrupt requests disabled (use for software polling) 1 Channel n interrupt requests enabled Mode select B for TPM channel n. When CPWMS=0, MSnB=1 congures TPM channel n for edge-aligned PWM mode. Refer to the summary of channel mode and setup controls in Table 16-6. Mode select A for TPM channel n. When CPWMS=0 and MSnB=0, MSnA congures TPM channel n for input-capture mode or output compare mode. Refer to Table 16-6 for a summary of channel mode and setup controls. Note: If the associated port pin is not stable for at least two bus clock cycles before changing to input capture mode, it is possible to get an unexpected indication of an edge trigger. Edge/level select bits. Depending upon the operating mode for the timer channel as set by CPWMS:MSnB:MSnA and shown in Table 16-6, these bits select the polarity of the input edge that triggers an input capture event, select the level that will be driven in response to an output compare match, or select the polarity of the PWM output. Setting ELSnB:ELSnA to 0:0 congures the related timer pin as a general purpose I/O pin not related to any timer functions. This function is typically used to temporarily disable an input capture channel or to make the timer pin available as a general purpose I/O pin when the associated timer channel is set up as a software timer that does not require the use of a pin.
6 CHnIE 5 MSnB 4 MSnA
32 ELSnB ELSnA
Table 16-6. Mode, Edge, and Level Selection

CPWMS X MSnB:MSnA XX ELSnB:ELSnA 00 Mode Conguration
Pin not used for TPM - revert to general purpose I/O or other peripheral control
Table 16-6. Mode, Edge, and Level Selection

CPWMS 0 MSnB:MSnA 00 ELSnB:ELSnA 01 10 11 01 01 10 11 1X 10 X1 1 XX 10 X1 Center-aligned PWM Edge-aligned PWM Output compare Mode Input capture Conguration Capture on rising edge only Capture on falling edge only Capture on rising or falling edge Toggle output on compare Clear output on compare Set output on compare High-true pulses (clear output on compare) Low-true pulses (set output on compare) High-true pulses (clear output on compare-up) Low-true pulses (set output on compare-up)
16.3.5
TPM Channel Value Registers (TPMxCnVH:TPMxCnVL)
These read/write registers contain the captured TPM counter value of the input capture function or the output compare value for the output compare or PWM functions. The channel registers are cleared by reset.
7 6 5 4 3 2 1 0
R Bit 15 W Reset 0 0 0 0 0 0 0 0 14 13 12 11 10 9 Bit 8
Figure 16-13. TPM Channel Value Register High (TPMxCnVH)

7 6 5 4 3 2 1 0
R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0
Figure 16-14. TPM Channel Value Register Low (TPMxCnVL)
In input capture mode, reading either byte (TPMxCnVH or TPMxCnVL) latches the contents of both bytes into a buffer where they remain latched until the other half is read. This latching mechanism also resets
(becomes unlatched) when the TPMxCnSC register is written (whether BDM mode is active or not). Any write to the channel registers will be ignored during the input capture mode. When BDM is active, the coherency mechanism is frozen (unless reset by writing to TPMxCnSC register) such that the buffer latches remain in the state they were in when the BDM became active, even if one or both halves of the channel register are read while BDM is active. This assures that if the user was in the middle of reading a 16-bit register when BDM became active, it will read the appropriate value from the other half of the 16-bit value after returning to normal execution. The value read from the TPMxCnVH and TPMxCnVL registers in BDM mode is the value of these registers and not the value of their read buffer. In output compare or PWM modes, writing to either byte (TPMxCnVH or TPMxCnVL) latches the value into a buffer. After both bytes are written, they are transferred as a coherent 16-bit value into the timer-channel registers according to the value of CLKSB:CLKSA bits and the selected mode, so: If (CLKSB:CLKSA = 0:0), then the registers are updated when the second byte is written. If (CLKSB:CLKSA not = 0:0 and in output compare mode) then the registers are updated after the second byte is written and on the next change of the TPM counter (end of the prescaler counting). If (CLKSB:CLKSA not = 0:0 and in EPWM or CPWM modes), then the registers are updated after the both bytes were written, and the TPM counter changes from (TPMxMODH:TPMxMODL - 1) to (TPMxMODH:TPMxMODL). If the TPM counter is a free-running counter then the update is made when the TPM counter changes from 0xFFFE to 0xFFFF. The latching mechanism may be manually reset by writing to the TPMxCnSC register (whether BDM mode is active or not). This latching mechanism allows coherent 16-bit writes in either big-endian or little-endian order which is friendly to various compiler implementations. When BDM is active, the coherency mechanism is frozen such that the buffer latches remain in the state they were in when the BDM became active even if one or both halves of the channel register are written while BDM is active. Any write to the channel registers bypasses the buffer latches and directly write to the channel register while BDM is active. The values written to the channel register while BDM is active are used for PWM & output compare operation once normal execution resumes. Writes to the channel registers while BDM is active do not interfere with partial completion of a coherency sequence. After the coherency mechanism has been fully exercised, the channel registers are updated using the buffered values written (while BDM was not active) by the user.
16.4
All TPM functions are associated with a central 16-bit counter which allows exible selection of the clock source and prescale factor. There is also a 16-bit modulo register associated with the main counter. The CPWMS control bit chooses between center-aligned PWM operation for all channels in the TPM (CPWMS=1) or general purpose timing functions (CPWMS=0) where each channel can independently be congured to operate in input capture, output compare, or edge-aligned PWM mode. The CPWMS control bit is located in the main TPM status and control register because it affects all channels within the TPM and inuences the way the main counter operates. (In CPWM mode, the counter changes to an up/down mode rather than the up-counting mode used for general purpose timer functions.)
The following sections describe the main counter and each of the timer operating modes (input capture, output compare, edge-aligned PWM, and center-aligned PWM). Because details of pin operation and interrupt activity depend upon the operating mode, these topics will be covered in the associated mode explanation sections.
16.4.1
Counter
All timer functions are based on the main 16-bit counter (TPMxCNTH:TPMxCNTL). This section discusses selection of the clock source, end-of-count overow, up-counting vs. up/down counting, and manual counter reset.
16.4.1.1
Counter Clock Source
The 2-bit eld, CLKSB:CLKSA, in the timer status and control register (TPMxSC) selects one of three possible clock sources or OFF (which effectively disables the TPM). See Table 16-3. After any MCU reset, CLKSB:CLKSA=0:0 so no clock source is selected, and the TPM is in a very low power state. These control bits may be read or written at any time and disabling the timer (writing 00 to the CLKSB:CLKSA eld) does not affect the values in the counter or other timer registers.
Table 16-7. TPM Clock Source Selection

CLKSB:CLKSA 00 01 10 11 TPM Clock Source to Prescaler Input No clock selected (TPM counter disabled) Bus rate clock Fixed system clock External source
The bus rate clock is the main system bus clock for the MCU. This clock source requires no synchronization because it is the clock that is used for all internal MCU activities including operation of the CPU and buses. In MCUs that have no PLL and FLL or the PLL and FLL are not engaged, the xed system clock source is the same as the bus-rate-clock source, and it does not go through a synchronizer. When a PLL or FLL is present and engaged, a synchronizer is required between the crystal divided-by two clock source and the timer counter so counter transitions will be properly aligned to bus-clock transitions. A synchronizer will be used at chip level to synchronize the crystal-related source clock to the bus clock. The external clock source may be connected to any TPM channel pin. This clock source always has to pass through a synchronizer to assure that counter transitions are properly aligned to bus clock transitions. The bus-rate clock drives the synchronizer; therefore, to meet Nyquist criteria even with jitter, the frequency of the external clock source must not be faster than the bus rate divided-by four. With ideal clocks the external clock can be as fast as bus clock divided by four. When the external clock source shares the TPM channel pin, this pin should not be used for other channel timing functions. For example, it would be ambiguous to congure channel 0 for input capture when the TPM channel 0 pin was also being used as the timer external clock source. (It is the users responsibility to avoid such settings.) The TPM channel could still be used in output compare mode for software timing functions (pin controls set not to affect the TPM channel pin).
16.4.1.2
Counter Overow and Modulo Reset
An interrupt ag and enable are associated with the 16-bit main counter. The ag (TOF) is a software-accessible indication that the timer counter has overowed. The enable signal selects between software polling (TOIE=0) where no hardware interrupt is generated, or interrupt-driven operation (TOIE=1) where a static hardware interrupt is generated whenever the TOF ag is equal to one. The conditions causing TOF to become set depend on whether the TPM is congured for center-aligned PWM (CPWMS=1). In the simplest mode, there is no modulus limit and the TPM is not in CPWMS=1 mode. In this case, the 16-bit timer counter counts from 0x0000 through 0xFFFF and overows to 0x0000 on the next counting clock. TOF becomes set at the transition from 0xFFFF to 0x0000. When a modulus limit is set, TOF becomes set at the transition from the value set in the modulus register to 0x0000. When the TPM is in center-aligned PWM mode (CPWMS=1), the TOF ag gets set as the counter changes direction at the end of the count value set in the modulus register (that is, at the transition from the value set in the modulus register to the next lower count value). This corresponds to the end of a PWM period (the 0x0000 count value corresponds to the center of a period).
16.4.1.3
Counting Modes
The main timer counter has two counting modes. When center-aligned PWM is selected (CPWMS=1), the counter operates in up/down counting mode. Otherwise, the counter operates as a simple up counter. As an up counter, the timer counter counts from 0x0000 through its terminal count and then continues with 0x0000. The terminal count is 0xFFFF or a modulus value in TPMxMODH:TPMxMODL. When center-aligned PWM operation is specied, the counter counts up from 0x0000 through its terminal count and then down to 0x0000 where it changes back to up counting. Both 0x0000 and the terminal count value are normal length counts (one timer clock period long). In this mode, the timer overow ag (TOF) becomes set at the end of the terminal-count period (as the count changes to the next lower count value).
16.4.1.4
Manual Counter Reset
The main timer counter can be manually reset at any time by writing any value to either half of TPMxCNTH or TPMxCNTL. Resetting the counter in this manner also resets the coherency mechanism in case only half of the counter was read before resetting the count.
16.4.2
Channel Mode Selection
Provided CPWMS=0, the MSnB and MSnA control bits in the channel n status and control registers determine the basic mode of operation for the corresponding channel. Choices include input capture, output compare, and edge-aligned PWM.
16.4.2.1
Input Capture Mode
With the input-capture function, the TPM can capture the time at which an external event occurs. When an active edge occurs on the pin of an input-capture channel, the TPM latches the contents of the TPM counter into the channel-value registers (TPMxCnVH:TPMxCnVL). Rising edges, falling edges, or any edge may be chosen as the active edge that triggers an input capture. In input capture mode, the TPMxCnVH and TPMxCnVL registers are read only. When either half of the 16-bit capture register is read, the other half is latched into a buffer to support coherent 16-bit accesses in big-endian or little-endian order. The coherency sequence can be manually reset by writing to the channel status/control register (TPMxCnSC). An input capture event sets a ag bit (CHnF) which may optionally generate a CPU interrupt request. While in BDM, the input capture function works as congured by the user. When an external event occurs, the TPM latches the contents of the TPM counter (which is frozen because of the BDM mode) into the channel value registers and sets the ag bit.
16.4.2.2
Output Compare Mode
With the output-compare function, the TPM can generate timed pulses with programmable position, polarity, duration, and frequency. When the counter reaches the value in the channel-value registers of an output-compare channel, the TPM can set, clear, or toggle the channel pin.
In output compare mode, values are transferred to the corresponding timer channel registers only after both 8-bit halves of a 16-bit register have been written and according to the value of CLKSB:CLKSA bits, so: If (CLKSB:CLKSA = 0:0), the registers are updated when the second byte is written If (CLKSB:CLKSA not = 0:0), the registers are updated at the next change of the TPM counter (end of the prescaler counting) after the second byte is written. The coherency sequence can be manually reset by writing to the channel status/control register (TPMxCnSC). An output compare event sets a ag bit (CHnF) which may optionally generate a CPU-interrupt request.
16.4.2.3
Edge-Aligned PWM Mode
This type of PWM output uses the normal up-counting mode of the timer counter (CPWMS=0) and can be used when other channels in the same TPM are congured for input capture or output compare functions. The period of this PWM signal is determined by the value of the modulus register (TPMxMODH:TPMxMODL) plus 1. The duty cycle is determined by the setting in the timer channel register (TPMxCnVH:TPMxCnVL). The polarity of this PWM signal is determined by the setting in the ELSnA control bit. 0% and 100% duty cycle cases are possible. The output compare value in the TPM channel registers determines the pulse width (duty cycle) of the PWM signal (Figure 16-15). The time between the modulus overow and the output compare is the pulse width. If ELSnA=0, the counter overow forces the PWM signal high, and the output compare forces the PWM signal low. If ELSnA=1, the counter overow forces the PWM signal low, and the output compare forces the PWM signal high.
OVERFLOW PERIOD PULSE WIDTH TPMxCHn OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE OVERFLOW OVERFLOW
Figure 16-15. PWM Period and Pulse Width (ELSnA=0)
When the channel value register is set to 0x0000, the duty cycle is 0%. 100% duty cycle can be achieved by setting the timer-channel register (TPMxCnVH:TPMxCnVL) to a value greater than the modulus setting. This implies that the modulus setting must be less than 0xFFFF in order to get 100% duty cycle. Because the TPM may be used in an 8-bit MCU, the settings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to any of the registers TPMxCnVH and TPMxCnVL, actually write to buffer registers. In edge-aligned PWM mode, values are transferred to the corresponding timer-channel registers according to the value of CLKSB:CLKSA bits, so: If (CLKSB:CLKSA = 0:0), the registers are updated when the second byte is written If (CLKSB:CLKSA not = 0:0), the registers are updated after the both bytes were written, and the TPM counter changes from (TPMxMODH:TPMxMODL - 1) to (TPMxMODH:TPMxMODL). If
the TPM counter is a free-running counter then the update is made when the TPM counter changes from 0xFFFE to 0xFFFF.
16.4.2.4
Center-Aligned PWM Mode
This type of PWM output uses the up/down counting mode of the timer counter (CPWMS=1). The output compare value in TPMxCnVH:TPMxCnVL determines the pulse width (duty cycle) of the PWM signal while the period is determined by the value in TPMxMODH:TPMxMODL. TPMxMODH:TPMxMODL should be kept in the range of 0x0001 to 0x7FFF because values outside this range can produce ambiguous results. ELSnA will determine the polarity of the CPWM output. pulse width = 2 x (TPMxCnVH:TPMxCnVL) period = 2 x (TPMxMODH:TPMxMODL); TPMxMODH:TPMxMODL=0x0001-0x7FFF If the channel-value register TPMxCnVH:TPMxCnVL is zero or negative (bit 15 set), the duty cycle will be 0%. If TPMxCnVH:TPMxCnVL is a positive value (bit 15 clear) and is greater than the (non-zero) modulus setting, the duty cycle will be 100% because the duty cycle compare will never occur. This implies the usable range of periods set by the modulus register is 0x0001 through 0x7FFE (0x7FFF if you do not need to generate 100% duty cycle). This is not a signicant limitation. The resulting period would be much longer than required for normal applications. TPMxMODH:TPMxMODL=0x0000 is a special case that should not be used with center-aligned PWM mode. When CPWMS=0, this case corresponds to the counter running free from 0x0000 through 0xFFFF, but when CPWMS=1 the counter needs a valid match to the modulus register somewhere other than at 0x0000 in order to change directions from up-counting to down-counting. The output compare value in the TPM channel registers (times 2) determines the pulse width (duty cycle) of the CPWM signal (Figure 16-16). If ELSnA=0, a compare occurred while counting up forces the CPWM output signal low and a compare occurred while counting down forces the output high. The counter counts up until it reaches the modulo setting in TPMxMODH:TPMxMODL, then counts down until it reaches zero. This sets the period equal to two times TPMxMODH:TPMxMODL.
COUNT= 0 OUTPUT COUNT= COMPARE TPMxMODH:TPMxMODL (COUNT DOWN) OUTPUT COMPARE (COUNT UP) COUNT= TPMxMODH:TPMxMODL
TPMxCHn PULSE WIDTH 2 x TPMxCnVH:TPMxCnVL PERIOD 2 x TPMxMODH:TPMxMODL
Figure 16-16. CPWM Period and Pulse Width (ELSnA=0)
Center-aligned PWM outputs typically produce less noise than edge-aligned PWMs because fewer I/O pin transitions are lined up at the same system clock edge. This type of PWM is also required for some types of motor drives.
Input capture, output compare, and edge-aligned PWM functions do not make sense when the counter is operating in up/down counting mode so this implies that all active channels within a TPM must be used in CPWM mode when CPWMS=1. The TPM may be used in an 8-bit MCU. The settings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to any of the registers TPMxMODH, TPMxMODL, TPMxCnVH, and TPMxCnVL, actually write to buffer registers. In center-aligned PWM mode, the TPMxCnVH:L registers are updated with the value of their write buffer according to the value of CLKSB:CLKSA bits, so: If (CLKSB:CLKSA = 0:0), the registers are updated when the second byte is written If (CLKSB:CLKSA not = 0:0), the registers are updated after the both bytes were written, and the TPM counter changes from (TPMxMODH:TPMxMODL - 1) to (TPMxMODH:TPMxMODL). If the TPM counter is a free-running counter, the update is made when the TPM counter changes from 0xFFFE to 0xFFFF. When TPMxCNTH:TPMxCNTL=TPMxMODH:TPMxMODL, the TPM can optionally generate a TOF interrupt (at the end of this count). Writing to TPMxSC cancels any values written to TPMxMODH and/or TPMxMODL and resets the coherency mechanism for the modulo registers. Writing to TPMxCnSC cancels any values written to the channel value registers and resets the coherency mechanism for TPMxCnVH:TPMxCnVL.
16.5
16.5.1
Reset Overview
General
The TPM is reset whenever any MCU reset occurs.
16.5.2
Description of Reset Operation
Reset clears the TPMxSC register which disables clocks to the TPM and disables timer overow interrupts (TOIE=0). CPWMS, MSnB, MSnA, ELSnB, and ELSnA are all cleared which congures all TPM channels for input-capture operation with the associated pins disconnected from I/O pin logic (so all MCU pins related to the TPM revert to general purpose I/O pins).
16.6
16.6.1
Interrupts
General
The TPM generates an optional interrupt for the main counter overow and an interrupt for each channel. The meaning of channel interrupts depends on each channels mode of operation. If the channel is congured for input capture, the interrupt ag is set each time the selected input capture edge is recognized. If the channel is congured for output compare or PWM modes, the interrupt ag is set each time the main timer counter matches the value in the 16-bit channel value register.
All TPM interrupts are listed in Table 16-8 which shows the interrupt name, the name of any local enable that can block the interrupt request from leaving the TPM and getting recognized by the separate interrupt processing logic.
Table 16-8. Interrupt Summary
Interrupt TOF Local Enable TOIE Source Counter overow Description Set each time the timer counter reaches its terminal count (at transition to next count value which is usually 0x0000) An input capture or output compare event took place on channel n
CHnF
CHnIE
Channel event
The TPM module will provide a high-true interrupt signal. Vectors and priorities are determined at chip integration time in the interrupt module so refer to the users guide for the interrupt module or to the chips complete documentation for details.
16.6.2
Description of Interrupt Operation
For each interrupt source in the TPM, a ag bit is set upon recognition of the interrupt condition such as timer overow, channel-input capture, or output-compare events. This ag may be read (polled) by software to determine that the action has occurred, or an associated enable bit (TOIE or CHnIE) can be set to enable hardware interrupt generation. While the interrupt enable bit is set, a static interrupt will generate whenever the associated interrupt ag equals one. The users software must perform a sequence of steps to clear the interrupt ag before returning from the interrupt-service routine. TPM interrupt ags are cleared by a two-step process including a read of the ag bit while it is set (1) followed by a write of zero (0) to the bit. If a new event is detected between these two steps, the sequence is reset and the interrupt ag remains set after the second step to avoid the possibility of missing the new event.
16.6.2.1
Timer Overow Interrupt (TOF) Description
The meaning and details of operation for TOF interrupts varies slightly depending upon the mode of operation of the TPM system (general purpose timing functions versus center-aligned PWM operation). The ag is cleared by the two step sequence described above. 16.6.2.1.1 Normal Case
Normally TOF is set when the timer counter changes from 0xFFFF to 0x0000. When the TPM is not congured for center-aligned PWM (CPWMS=0), TOF gets set when the timer counter changes from the terminal count (the value in the modulo register) to 0x0000. This case corresponds to the normal meaning of counter overow.
16.6.2.1.2
Center-Aligned PWM Case
When CPWMS=1, TOF gets set when the timer counter changes direction from up-counting to down-counting at the end of the terminal count (the value in the modulo register). In this case the TOF corresponds to the end of a PWM period.
16.6.2.2
Channel Event Interrupt Description
The meaning of channel interrupts depends on the channels current mode (input-capture, output-compare, edge-aligned PWM, or center-aligned PWM). 16.6.2.2.1 Input Capture Events
When a channel is congured as an input capture channel, the ELSnB:ELSnA control bits select no edge (off), rising edges, falling edges or any edge as the edge which triggers an input capture event. When the selected edge is detected, the interrupt ag is set. The ag is cleared by the two-step sequence described in Section 16.6.2, Description of Interrupt Operation. 16.6.2.2.2 Output Compare Events
When a channel is congured as an output compare channel, the interrupt ag is set each time the main timer counter matches the 16-bit value in the channel value register. The ag is cleared by the two-step sequence described Section 16.6.2, Description of Interrupt Operation. 16.6.2.2.3 PWM End-of-Duty-Cycle Events
For channels congured for PWM operation there are two possibilities. When the channel is congured for edge-aligned PWM, the channel ag gets set when the timer counter matches the channel value register which marks the end of the active duty cycle period. When the channel is congured for center-aligned PWM, the timer count matches the channel value register twice during each PWM cycle. In this CPWM case, the channel ag is set at the start and at the end of the active duty cycle period which are the times when the timer counter matches the channel value register. The ag is cleared by the two-step sequence described Section 16.6.2, Description of Interrupt Operation.
16.7
The Differences from TPM v2 to TPM v3
1. Write to TPMxCNTH:L registers (Section 16.3.2, TPM-Counter Registers (TPMxCNTH:TPMxCNTL)) [SE110-TPM case 7] Any write to TPMxCNTH or TPMxCNTL registers in TPM v3 clears the TPM counter (TPMxCNTH:L) and the prescaler counter. Instead, in the TPM v2 only the TPM counter is cleared in this case. 2. Read of TPMxCNTH:L registers (Section 16.3.2, TPM-Counter Registers (TPMxCNTH:TPMxCNTL)) In TPM v3, any read of TPMxCNTH:L registers during BDM mode returns the value of the TPM counter that is frozen. In TPM v2, if only one byte of the TPMxCNTH:L registers was read before the BDM mode became active, then any read of TPMxCNTH:L registers during
BDM mode returns the latched value of TPMxCNTH:L from the read buffer instead of the frozen TPM counter value. This read coherency mechanism is cleared in TPM v3 in BDM mode if there is a write to TPMxSC, TPMxCNTH or TPMxCNTL. Instead, in these conditions the TPM v2 does not clear this read coherency mechanism. 3. Read of TPMxCnVH:L registers (Section 16.3.5, TPM Channel Value Registers (TPMxCnVH:TPMxCnVL)) In TPM v3, any read of TPMxCnVH:L registers during BDM mode returns the value of the TPMxCnVH:L register. In TPM v2, if only one byte of the TPMxCnVH:L registers was read before the BDM mode became active, then any read of TPMxCnVH:L registers during BDM mode returns the latched value of TPMxCNTH:L from the read buffer instead of the value in the TPMxCnVH:L registers. This read coherency mechanism is cleared in TPM v3 in BDM mode if there is a write to TPMxCnSC. Instead, in this condition the TPM v2 does not clear this read coherency mechanism. 4. Write to TPMxCnVH:L registers Input Capture Mode (Section 16.4.2.1, Input Capture Mode) In this mode the TPM v3 does not allow the writes to TPMxCnVH:L registers. Instead, the TPM v2 allows these writes. Output Compare Mode (Section 16.4.2.2, Output Compare Mode) In this mode and if (CLKSB:CLKSA not = 0:0), the TPM v3 updates the TPMxCnVH:L registers with the value of their write buffer at the next change of the TPM counter (end of the prescaler counting) after the second byte is written. Instead, the TPM v2 always updates these registers when their second byte is written. The following procedure can be used in the TPM v3 to verify if the TPMxCnVH:L registers were updated with the new value that was written to these registers (value in their write buffer). ... write the new value to TPMxCnVH:L; read TPMxCnVH and TPMxCnVL registers; while (the read value of TPMxCnVH:L is different from the new value written to TPMxCnVH:L) begin read again TPMxCnVH and TPMxCnVL; end ... In this point, the TPMxCnVH:L registers were updated, so the program can continue and, for example, write to TPMxC0SC without cancelling the previous write to TPMxCnVH:L registers. Edge-Aligned PWM (Section 16.4.2.3, Edge-Aligned PWM Mode) In this mode and if (CLKSB:CLKSA not = 00), the TPM v3 updates the TPMxCnVH:L registers with the value of their write buffer after that the both bytes were written and when the
TPM counter changes from (TPMxMODH:L - 1) to (TPMxMODH:L). If the TPM counter is a free-running counter, then this update is made when the TPM counter changes from $FFFE to $FFFF. Instead, the TPM v2 makes this update after that the both bytes were written and when the TPM counter changes from TPMxMODH:L to $0000. Center-Aligned PWM (Section 16.4.2.4, Center-Aligned PWM Mode) In this mode and if (CLKSB:CLKSA not = 00), the TPM v3 updates the TPMxCnVH:L registers with the value of their write buffer after that the both bytes were written and when the TPM counter changes from (TPMxMODH:L - 1) to (TPMxMODH:L). If the TPM counter is a free-running counter, then this update is made when the TPM counter changes from $FFFE to $FFFF. Instead, the TPM v2 makes this update after that the both bytes were written and when the TPM counter changes from TPMxMODH:L to (TPMxMODH:L - 1). 5. Center-Aligned PWM (Section 16.4.2.4, Center-Aligned PWM Mode) TPMxCnVH:L = TPMxMODH:L [SE110-TPM case 1] In this case, the TPM v3 produces 100% duty cycle. Instead, the TPM v2 produces 0% duty cycle. TPMxCnVH:L = (TPMxMODH:L - 1) [SE110-TPM case 2] In this case, the TPM v3 produces almost 100% duty cycle. Instead, the TPM v2 produces 0% duty cycle. TPMxCnVH:L is changed from 0x0000 to a non-zero value [SE110-TPM case 3 and 5] In this case, the TPM v3 waits for the start of a new PWM period to begin using the new duty cycle setting. Instead, the TPM v2 changes the channel output at the middle of the current PWM period (when the count reaches 0x0000). TPMxCnVH:L is changed from a non-zero value to 0x0000 [SE110-TPM case 4] In this case, the TPM v3 nishes the current PWM period using the old duty cycle setting. Instead, the TPM v2 nishes the current PWM period using the new duty cycle setting. 6. Write to TPMxMODH:L registers in BDM mode (Section 16.3.3, TPM Counter Modulo Registers (TPMxMODH:TPMxMODL)) In the TPM v3 a write to TPMxSC register in BDM mode clears the write coherency mechanism of TPMxMODH:L registers. Instead, in the TPM v2 this coherency mechanism is not cleared when there is a write to TPMxSC register. 7. Update of EPWM signal when CLKSB:CLKSA = 00 In the TPM v3 if CLKSB:CLKSA = 00, then the EPWM signal in the channel output is not update (it is frozen while CLKSB:CLKSA = 00). Instead, in the TPM v2 the EPWM signal is updated at the next rising edge of bus clock after a write to TPMxCnSC register. The Figure 0-1 and Figure 0-2 show when the EPWM signals generated by TPM v2 and TPM v3 after the reset (CLKSB:CLKSA = 00) and if there is a write to TPMxCnSC register.
EPWM mode TPMxMODH:TPMxMODL = 0x0007 TPMxCnVH:TPMxCnVL = 0x0005
RESET (active low) BUS CLOCK TPMxCNTH:TPMxCNTL 00 00 00 10 10 0 1 2 3 4 5 6 01 7 0 1 2 ...
CLKSB:CLKSA BITS MSnB:MSnA BITS ELSnB:ELSnA BITS TPMv2 TPMxCHn TPMv3 TPMxCHn CHnF BIT (in TPMv2 and TPMv3)
Figure 0-1. Generation of high-true EPWM signal by TPM v2 and v3 after the reset
EPWM mode TPMxMODH:TPMxMODL = 0x0007 TPMxCnVH:TPMxCnVL = 0x0005
RESET (active low) BUS CLOCK TPMxCNTH:TPMxCNTL 00 00 00 10 01 0 1 2 3 4 5 6 01 7 0 1 2 ...
CLKSB:CLKSA BITS MSnB:MSnA BITS ELSnB:ELSnA BITS TPMv2 TPMxCHn TPMv3 TPMxCHn CHnF BIT (in TPMv2 and TPMv3)
Figure 0-2. Generation of low-true EPWM signal by TPM v2 and v3 after the reset
The following procedure can be used in TPM v3 (when the channel pin is also a port pin) to emulate the high-true EPWM generated by TPM v2 after the reset.
... congure the channel pin as output port pin and set the output pin; congure the channel to generate the EPWM signal but keep ELSnB:ELSnA as 00; congure the other registers (TPMxMODH, TPMxMODL, TPMxCnVH, TPMxCnVL, ...); congure CLKSB:CLKSA bits (TPM v3 starts to generate the high-true EPWM signal, however TPM does not control the channel pin, so the EPWM signal is not available); wait until the TOF is set (or use the TOF interrupt); enable the channel output by conguring ELSnB:ELSnA bits (now EPWM signal is available); ...

17.1 Introduction
Development support systems in the HCS08 include the background debug controller (BDC) and the on-chip debug module (DBG). The BDC provides a single-wire debug interface to the target MCU that provides a convenient interface for programming the on-chip Flash and other nonvolatile memories. The BDC is also the primary debug interface for development and allows non-intrusive access to memory data and traditional debug features such as CPU register modify, breakpoints, and single instruction trace commands. In the HCS08 Family, address and data bus signals are not available on external pins (not even in test modes). Debug is done through commands fed into the target MCU via the single-wire background debug interface. The debug module provides a means to selectively trigger and capture bus information so an external development system can reconstruct what happened inside the MCU on a cycle-by-cycle basis without having external access to the address and data signals.
17.1.1
Forcing Active Background
The method for forcing active background mode depends on the specic HCS08 derivative. For the MC9S08DZ60, you can force active background after a power-on reset by holding the BKGD pin low as the device exits the reset condition. You can also force active background by driving BKGD low immediately after a serial background command that writes a one to the BDFR bit in the SBDFR register. If no debug pod is connected to the BKGD pin, the MCU will always reset into normal operating mode.
17.1.2
Features
Features of the BDC module include: Single pin for mode selection and background communications BDC registers are not located in the memory map SYNC command to determine target communications rate Non-intrusive commands for memory access Active background mode commands for CPU register access GO and TRACE1 commands BACKGROUND command can wake CPU from stop or wait modes One hardware address breakpoint built into BDC Oscillator runs in stop mode, if BDC enabled COP watchdog disabled while in active background mode Features of the ICE system include: Two trigger comparators: Two address + read/write (R/W) or one full address + data + R/W Flexible 8-word by 16-bit FIFO (rst-in, rst-out) buffer for capture information: Change-of-ow addresses or Event-only data Two types of breakpoints: Tag breakpoints for instruction opcodes Force breakpoints for any address access Nine trigger modes: Basic: A-only, A OR B Sequence: A then B Full: A AND B data, A AND NOT B data Event (store data): Event-only B, A then event-only B Range: Inside range (A address B), outside range (address < A or address > B)
17.2
Background Debug Controller (BDC)
All MCUs in the HCS08 Family contain a single-wire background debug interface that supports in-circuit programming of on-chip nonvolatile memory and sophisticated non-intrusive debug capabilities. Unlike debug interfaces on earlier 8-bit MCUs, this system does not interfere with normal application resources. It does not use any user memory or locations in the memory map and does not share any on-chip peripherals. BDC commands are divided into two groups: Active background mode commands require that the target MCU is in active background mode (the user program is not running). Active background mode commands allow the CPU registers to be read or written, and allow the user to trace one user instruction at a time, or GO to the user program from active background mode.
Non-intrusive commands can be executed at any time even while the users program is running. Non-intrusive commands allow a user to read or write MCU memory locations or access status and control registers within the background debug controller.
Typically, a relatively simple interface pod is used to translate commands from a host computer into commands for the custom serial interface to the single-wire background debug system. Depending on the development tool vendor, this interface pod may use a standard RS-232 serial port, a parallel printer port, or some other type of communications such as a universal serial bus (USB) to communicate between the host PC and the pod. The pod typically connects to the target system with ground, the BKGD pin, RESET, and sometimes VDD. An open-drain connection to reset allows the host to force a target system reset, which is useful to regain control of a lost target system or to control startup of a target system before the on-chip nonvolatile memory has been programmed. Sometimes VDD can be used to allow the pod to use power from the target system to avoid the need for a separate power supply. However, if the pod is powered separately, it can be connected to a running target system without forcing a target system reset or otherwise disturbing the running application program.
BKGD 1 NO CONNECT 3 NO CONNECT 5 2 GND 4 RESET 6 VDD
Figure 17-1. BDM Tool Connector
17.2.1
BKGD Pin Description
BKGD is the single-wire background debug interface pin. The primary function of this pin is for bidirectional serial communication of active background mode commands and data. During reset, this pin is used to select between starting in active background mode or starting the users application program. This pin is also used to request a timed sync response pulse to allow a host development tool to determine the correct clock frequency for background debug serial communications. BDC serial communications use a custom serial protocol rst introduced on the M68HC12 Family of microcontrollers. This protocol assumes the host knows the communication clock rate that is determined by the target BDC clock rate. All communication is initiated and controlled by the host that drives a high-to-low edge to signal the beginning of each bit time. Commands and data are sent most signicant bit rst (MSB rst). For a detailed description of the communications protocol, refer to Section 17.2.2, Communication Details. If a host is attempting to communicate with a target MCU that has an unknown BDC clock rate, a SYNC command may be sent to the target MCU to request a timed sync response signal from which the host can determine the correct communication speed. BKGD is a pseudo-open-drain pin and there is an on-chip pullup so no external pullup resistor is required. Unlike typical open-drain pins, the external RC time constant on this pin, which is inuenced by external capacitance, plays almost no role in signal rise time. The custom protocol provides for brief, actively driven speedup pulses to force rapid rise times on this pin without risking harmful drive level conicts. Refer to Section 17.2.2, Communication Details, for more detail.
When no debugger pod is connected to the 6-pin BDM interface connector, the internal pullup on BKGD chooses normal operating mode. When a debug pod is connected to BKGD it is possible to force the MCU into active background mode after reset. The specic conditions for forcing active background depend upon the HCS08 derivative (refer to the introduction to this Development Support section). It is not necessary to reset the target MCU to communicate with it through the background debug interface.
17.2.2
Communication Details
The BDC serial interface requires the external controller to generate a falling edge on the BKGD pin to indicate the start of each bit time. The external controller provides this falling edge whether data is transmitted or received. BKGD is a pseudo-open-drain pin that can be driven either by an external controller or by the MCU. Data is transferred MSB rst at 16 BDC clock cycles per bit (nominal speed). The interface times out if 512 BDC clock cycles occur between falling edges from the host. Any BDC command that was in progress when this timeout occurs is aborted without affecting the memory or operating mode of the target MCU system. The custom serial protocol requires the debug pod to know the target BDC communication clock speed. The clock switch (CLKSW) control bit in the BDC status and control register allows the user to select the BDC clock source. The BDC clock source can either be the bus or the alternate BDC clock source. The BKGD pin can receive a high or low level or transmit a high or low level. The following diagrams show timing for each of these cases. Interface timing is synchronous to clocks in the target BDC, but asynchronous to the external host. The internal BDC clock signal is shown for reference in counting cycles.
Figure 17-2 shows an external host transmitting a logic 1 or 0 to the BKGD pin of a target HCS08 MCU. The host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge to where the target perceives the beginning of the bit time. Ten target BDC clock cycles later, the target senses the bit level on the BKGD pin. Typically, the host actively drives the pseudo-open-drain BKGD pin during host-to-target transmissions to speed up rising edges. Because the target does not drive the BKGD pin during the host-to-target transmission period, there is no need to treat the line as an open-drain signal during this period.
BDC CLOCK (TARGET MCU)
HOST TRANSMIT 1
HOST TRANSMIT 0 10 CYCLES
EARLIEST START OF NEXT BIT
SYNCHRONIZATION UNCERTAINTY PERCEIVED START OF BIT TIME
TARGET SENSES BIT LEVEL
Figure 17-2. BDC Host-to-Target Serial Bit Timing
Figure 17-3 shows the host receiving a logic 1 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long enough for the target to recognize it (at least two target BDC cycles). The host must release the low drive before the target MCU drives a brief active-high speedup pulse seven cycles after the perceived start of the bit time. The host should sample the bit level about 10 cycles after it started the bit time.
HOST DRIVE TO BKGD PIN
HIGH-IMPEDANCE
TARGET MCU SPEEDUP PULSE HIGH-IMPEDANCE PERCEIVED START OF BIT TIME R-C RISE BKGD PIN
HIGH-IMPEDANCE
10 CYCLES 10 CYCLES HOST SAMPLES BKGD PIN
Figure 17-3. BDC Target-to-Host Serial Bit Timing (Logic 1)
Figure 17-4 shows the host receiving a logic 0 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the target HCS08 nishes it. Because the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 BDC clock cycles, then briey drives it high to speed up the rising edge. The host samples the bit level about 10 cycles after starting the bit time.
HOST DRIVE TO BKGD PIN
HIGH-IMPEDANCE
TARGET MCU DRIVE AND SPEED-UP PULSE PERCEIVED START OF BIT TIME
SPEEDUP PULSE
BKGD PIN 10 CYCLES 10 CYCLES
HOST SAMPLES BKGD PIN
Figure 17-4. BDM Target-to-Host Serial Bit Timing (Logic 0)
17.2.3
BDC Commands
BDC commands are sent serially from a host computer to the BKGD pin of the target HCS08 MCU. All commands and data are sent MSB-rst using a custom BDC communications protocol. Active background mode commands require that the target MCU is currently in the active background mode while non-intrusive commands may be issued at any time whether the target MCU is in active background mode or running a user application program. Table 17-1 shows all HCS08 BDC commands, a shorthand description of their coding structure, and the meaning of each command. Coding Structure Nomenclature This nomenclature is used in Table 17-1 to describe the coding structure of the BDC commands. Commands begin with an 8-bit hexadecimal command code in the host-to-target direction (most signicant bit rst) / = separates parts of the command d = delay 16 target BDC clock cycles AAAA = a 16-bit address in the host-to-target direction RD = 8 bits of read data in the target-to-host direction WD = 8 bits of write data in the host-to-target direction RD16 = 16 bits of read data in the target-to-host direction WD16 = 16 bits of write data in the host-to-target direction SS = the contents of BDCSCR in the target-to-host direction (STATUS) CC = 8 bits of write data for BDCSCR in the host-to-target direction (CONTROL) RBKP = 16 bits of read data in the target-to-host direction (from BDCBKPT breakpoint register) WBKP = 16 bits of write data in the host-to-target direction (for BDCBKPT breakpoint register)
Table 17-1. BDC Command Summary

Command Mnemonic SYNC ACK_ENABLE ACK_DISABLE BACKGROUND READ_STATUS WRITE_CONTROL READ_BYTE READ_BYTE_WS READ_LAST WRITE_BYTE WRITE_BYTE_WS READ_BKPT WRITE_BKPT GO TRACE1 TAGGO READ_A READ_CCR READ_PC READ_HX READ_SP READ_NEXT READ_NEXT_WS WRITE_A WRITE_CCR WRITE_PC WRITE_HX WRITE_SP WRITE_NEXT WRITE_NEXT_WS
1
Active BDM/ Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM n/a1 D5/d D6/d 90/d E4/SS C4/CC
Coding Structure
Description Request a timed reference pulse to determine target BDC communication speed Enable acknowledge protocol. Refer to Freescale document order no. HCS08RMv1/D. Disable acknowledge protocol. Refer to Freescale document order no. HCS08RMv1/D. Enter active background mode if enabled (ignore if ENBDM bit equals 0) Read BDC status from BDCSCR Write BDC controls in BDCSCR Read a byte from target memory Read a byte and report status Re-read byte from address just read and report status Write a byte to target memory Write a byte and report status Read BDCBKPT breakpoint register Write BDCBKPT breakpoint register Go to execute the user application program starting at the address currently in the PC Trace 1 user instruction at the address in the PC, then return to active background mode Same as GO but enable external tagging (HCS08 devices have no external tagging pin) Read accumulator (A) Read condition code register (CCR) Read program counter (PC) Read H and X register pair (H:X) Read stack pointer (SP) Increment H:X by one then read memory byte located at H:X Increment H:X by one then read memory byte located at H:X. Report status and data. Write accumulator (A) Write condition code register (CCR) Write program counter (PC) Write H and X register pair (H:X) Write stack pointer (SP) Increment H:X by one, then write memory byte located at H:X Increment H:X by one, then write memory byte located at H:X. Also report status.
E0/AAAA/d/RD E1/AAAA/d/SS/RD E8/SS/RD C0/AAAA/WD/d C1/AAAA/WD/d/SS E2/RBKP C2/WBKP 08/d 10/d 18/d 68/d/RD 69/d/RD 6B/d/RD16 6C/d/RD16 6F/d/RD16 70/d/RD 71/d/SS/RD 48/WD/d 49/WD/d 4B/WD16/d 4C/WD16/d 4F/WD16/d 50/WD/d 51/WD/d/SS
The SYNC command is a special operation that does not have a command code.
The SYNC command is unlike other BDC commands because the host does not necessarily know the correct communications speed to use for BDC communications until after it has analyzed the response to the SYNC command. To issue a SYNC command, the host: Drives the BKGD pin low for at least 128 cycles of the slowest possible BDC clock (The slowest clock is normally the reference oscillator/64 or the self-clocked rate/64.) Drives BKGD high for a brief speedup pulse to get a fast rise time (This speedup pulse is typically one cycle of the fastest clock in the system.) Removes all drive to the BKGD pin so it reverts to high impedance Monitors the BKGD pin for the sync response pulse The target, upon detecting the SYNC request from the host (which is a much longer low time than would ever occur during normal BDC communications): Waits for BKGD to return to a logic high Delays 16 cycles to allow the host to stop driving the high speedup pulse Drives BKGD low for 128 BDC clock cycles Drives a 1-cycle high speedup pulse to force a fast rise time on BKGD Removes all drive to the BKGD pin so it reverts to high impedance The host measures the low time of this 128-cycle sync response pulse and determines the correct speed for subsequent BDC communications. Typically, the host can determine the correct communication speed within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent.
17.2.4
BDC Hardware Breakpoint
The BDC includes one relatively simple hardware breakpoint that compares the CPU address bus to a 16-bit match value in the BDCBKPT register. This breakpoint can generate a forced breakpoint or a tagged breakpoint. A forced breakpoint causes the CPU to enter active background mode at the rst instruction boundary following any access to the breakpoint address. The tagged breakpoint causes the instruction opcode at the breakpoint address to be tagged so that the CPU will enter active background mode rather than executing that instruction if and when it reaches the end of the instruction queue. This implies that tagged breakpoints can only be placed at the address of an instruction opcode while forced breakpoints can be set at any address. The breakpoint enable (BKPTEN) control bit in the BDC status and control register (BDCSCR) is used to enable the breakpoint logic (BKPTEN = 1). When BKPTEN = 0, its default value after reset, the breakpoint logic is disabled and no BDC breakpoints are requested regardless of the values in other BDC breakpoint registers and control bits. The force/tag select (FTS) control bit in BDCSCR is used to select forced (FTS = 1) or tagged (FTS = 0) type breakpoints. The on-chip debug module (DBG) includes circuitry for two additional hardware breakpoints that are more exible than the simple breakpoint in the BDC module.
17.3
On-Chip Debug System (DBG)
Because HCS08 devices do not have external address and data buses, the most important functions of an in-circuit emulator have been built onto the chip with the MCU. The debug system consists of an 8-stage FIFO that can store address or data bus information, and a exible trigger system to decide when to capture bus information and what information to capture. The system relies on the single-wire background debug system to access debug control registers and to read results out of the eight stage FIFO. The debug module includes control and status registers that are accessible in the users memory map. These registers are located in the high register space to avoid using valuable direct page memory space. Most of the debug modules functions are used during development, and user programs rarely access any of the control and status registers for the debug module. The one exception is that the debug system can provide the means to implement a form of ROM patching. This topic is discussed in greater detail in Section 17.3.6, Hardware Breakpoints.
17.3.1
Comparators A and B
Two 16-bit comparators (A and B) can optionally be qualied with the R/W signal and an opcode tracking circuit. Separate control bits allow you to ignore R/W for each comparator. The opcode tracking circuitry optionally allows you to specify that a trigger will occur only if the opcode at the specied address is actually executed as opposed to only being read from memory into the instruction queue. The comparators are also capable of magnitude comparisons to support the inside range and outside range trigger modes. Comparators are disabled temporarily during all BDC accesses. The A comparator is always associated with the 16-bit CPU address. The B comparator compares to the CPU address or the 8-bit CPU data bus, depending on the trigger mode selected. Because the CPU data bus is separated into a read data bus and a write data bus, the RWAEN and RWA control bits have an additional purpose, in full address plus data comparisons they are used to decide which of these buses to use in the comparator B data bus comparisons. If RWAEN = 1 (enabled) and RWA = 0 (write), the CPUs write data bus is used. Otherwise, the CPUs read data bus is used. The currently selected trigger mode determines what the debugger logic does when a comparator detects a qualied match condition. A match can cause: Generation of a breakpoint to the CPU Storage of data bus values into the FIFO Starting to store change-of-ow addresses into the FIFO (begin type trace) Stopping the storage of change-of-ow addresses into the FIFO (end type trace)
17.3.2
Bus Capture Information and FIFO Operation
The usual way to use the FIFO is to setup the trigger mode and other control options, then arm the debugger. When the FIFO has lled or the debugger has stopped storing data into the FIFO, you would read the information out of it in the order it was stored into the FIFO. Status bits indicate the number of words of valid information that are in the FIFO as data is stored into it. If a trace run is manually halted by writing 0 to ARM before the FIFO is full (CNT = 1:0:0:0), the information is shifted by one position and
the host must perform ((8 CNT) 1) dummy reads of the FIFO to advance it to the rst signicant entry in the FIFO. In most trigger modes, the information stored in the FIFO consists of 16-bit change-of-ow addresses. In these cases, read DBGFH then DBGFL to get one coherent word of information out of the FIFO. Reading DBGFL (the low-order byte of the FIFO data port) causes the FIFO to shift so the next word of information is available at the FIFO data port. In the event-only trigger modes (see Section 17.3.5, Trigger Modes), 8-bit data information is stored into the FIFO. In these cases, the high-order half of the FIFO (DBGFH) is not used and data is read out of the FIFO by simply reading DBGFL. Each time DBGFL is read, the FIFO is shifted so the next data value is available through the FIFO data port at DBGFL. In trigger modes where the FIFO is storing change-of-ow addresses, there is a delay between CPU addresses and the input side of the FIFO. Because of this delay, if the trigger event itself is a change-of-ow address or a change-of-ow address appears during the next two bus cycles after a trigger event starts the FIFO, it will not be saved into the FIFO. In the case of an end-trace, if the trigger event is a change-of-ow, it will be saved as the last change-of-ow entry for that debug run. The FIFO can also be used to generate a prole of executed instruction addresses when the debugger is not armed. When ARM = 0, reading DBGFL causes the address of the most-recently fetched opcode to be saved in the FIFO. To use the proling feature, a host debugger would read addresses out of the FIFO by reading DBGFH then DBGFL at regular periodic intervals. The rst eight values would be discarded because they correspond to the eight DBGFL reads needed to initially ll the FIFO. Additional periodic reads of DBGFH and DBGFL return delayed information about executed instructions so the host debugger can develop a prole of executed instruction addresses.
17.3.3
Change-of-Flow Information
To minimize the amount of information stored in the FIFO, only information related to instructions that cause a change to the normal sequential execution of instructions is stored. With knowledge of the source and object code program stored in the target system, an external debugger system can reconstruct the path of execution through many instructions from the change-of-ow information stored in the FIFO. For conditional branch instructions where the branch is taken (branch condition was true), the source address is stored (the address of the conditional branch opcode). Because BRA and BRN instructions are not conditional, these events do not cause change-of-ow information to be stored in the FIFO. Indirect JMP and JSR instructions use the current contents of the H:X index register pair to determine the destination address, so the debug system stores the run-time destination address for any indirect JMP or JSR. For interrupts, RTI, or RTS, the destination address is stored in the FIFO as change-of-ow information.
17.3.4
Tag vs. Force Breakpoints and Triggers
Tagging is a term that refers to identifying an instruction opcode as it is fetched into the instruction queue, but not taking any other action until and unless that instruction is actually executed by the CPU. This distinction is important because any change-of-ow from a jump, branch, subroutine call, or interrupt causes some instructions that have been fetched into the instruction queue to be thrown away without being executed.
A force-type breakpoint waits for the current instruction to nish and then acts upon the breakpoint request. The usual action in response to a breakpoint is to go to active background mode rather than continuing to the next instruction in the user application program. The tag vs. force terminology is used in two contexts within the debug module. The rst context refers to breakpoint requests from the debug module to the CPU. The second refers to match signals from the comparators to the debugger control logic. When a tag-type break request is sent to the CPU, a signal is entered into the instruction queue along with the opcode so that if/when this opcode ever executes, the CPU will effectively replace the tagged opcode with a BGND opcode so the CPU goes to active background mode rather than executing the tagged instruction. When the TRGSEL control bit in the DBGT register is set to select tag-type operation, the output from comparator A or B is qualied by a block of logic in the debug module that tracks opcodes and only produces a trigger to the debugger if the opcode at the compare address is actually executed. There is separate opcode tracking logic for each comparator so more than one compare event can be tracked through the instruction queue at a time.
17.3.5
Trigger Modes
The trigger mode controls the overall behavior of a debug run. The 4-bit TRG eld in the DBGT register selects one of nine trigger modes. When TRGSEL = 1 in the DBGT register, the output of the comparator must propagate through an opcode tracking circuit before triggering FIFO actions. The BEGIN bit in DBGT chooses whether the FIFO begins storing data when the qualied trigger is detected (begin trace), or the FIFO stores data in a circular fashion from the time it is armed until the qualied trigger is detected (end trigger). A debug run is started by writing a 1 to the ARM bit in the DBGC register, which sets the ARMF ag and clears the AF and BF ags and the CNT bits in DBGS. A begin-trace debug run ends when the FIFO gets full. An end-trace run ends when the selected trigger event occurs. Any debug run can be stopped manually by writing a 0 to ARM or DBGEN in DBGC. In all trigger modes except event-only modes, the FIFO stores change-of-ow addresses. In event-only trigger modes, the FIFO stores data in the low-order eight bits of the FIFO. The BEGIN control bit is ignored in event-only trigger modes and all such debug runs are begin type traces. When TRGSEL = 1 to select opcode fetch triggers, it is not necessary to use R/W in comparisons because opcode tags would only apply to opcode fetches that are always read cycles. It would also be unusual to specify TRGSEL = 1 while using a full mode trigger because the opcode value is normally known at a particular address. The following trigger mode descriptions only state the primary comparator conditions that lead to a trigger. Either comparator can usually be further qualied with R/W by setting RWAEN (RWBEN) and the corresponding RWA (RWB) value to be matched against R/W. The signal from the comparator with optional R/W qualication is used to request a CPU breakpoint if BRKEN = 1 and TAG determines whether the CPU request will be a tag request or a force request.
A-Only Trigger when the address matches the value in comparator A A OR B Trigger when the address matches either the value in comparator A or the value in comparator B A Then B Trigger when the address matches the value in comparator B but only after the address for another cycle matched the value in comparator A. There can be any number of cycles after the A match and before the B match. A AND B Data (Full Mode) This is called a full mode because address, data, and R/W (optionally) must match within the same bus cycle to cause a trigger event. Comparator A checks address, the low byte of comparator B checks data, and R/W is checked against RWA if RWAEN = 1. The high-order half of comparator B is not used. In full trigger modes it is not useful to specify a tag-type CPU breakpoint (BRKEN = TAG = 1), but if you do, the comparator B data match is ignored for the purpose of issuing the tag request to the CPU and the CPU breakpoint is issued when the comparator A address matches. A AND NOT B Data (Full Mode) Address must match comparator A, data must not match the low half of comparator B, and R/W must match RWA if RWAEN = 1. All three conditions must be met within the same bus cycle to cause a trigger. In full trigger modes it is not useful to specify a tag-type CPU breakpoint (BRKEN = TAG = 1), but if you do, the comparator B data match is ignored for the purpose of issuing the tag request to the CPU and the CPU breakpoint is issued when the comparator A address matches. Event-Only B (Store Data) Trigger events occur each time the address matches the value in comparator B. Trigger events cause the data to be captured into the FIFO. The debug run ends when the FIFO becomes full. A Then Event-Only B (Store Data) After the address has matched the value in comparator A, a trigger event occurs each time the address matches the value in comparator B. Trigger events cause the data to be captured into the FIFO. The debug run ends when the FIFO becomes full. Inside Range (A Address B) A trigger occurs when the address is greater than or equal to the value in comparator A and less than or equal to the value in comparator B at the same time. Outside Range (Address < A or Address > B) A trigger occurs when the address is either less than the value in comparator A or greater than the value in comparator B.
17.3.6
Hardware Breakpoints
The BRKEN control bit in the DBGC register may be set to 1 to allow any of the trigger conditions described in Section 17.3.5, Trigger Modes, to be used to generate a hardware breakpoint request to the CPU. TAG in DBGC controls whether the breakpoint request will be treated as a tag-type breakpoint or a force-type breakpoint. A tag breakpoint causes the current opcode to be marked as it enters the instruction queue. If a tagged opcode reaches the end of the pipe, the CPU executes a BGND instruction to go to active background mode rather than executing the tagged opcode. A force-type breakpoint causes the CPU to nish the current instruction and then go to active background mode. If the background mode has not been enabled (ENBDM = 1) by a serial WRITE_CONTROL command through the BKGD pin, the CPU will execute an SWI instruction instead of going to active background mode.
17.4
Register Denition
This section contains the descriptions of the BDC and DBG registers and control bits. Refer to the high-page register summary in the device overview chapter of this data sheet for the absolute address assignments for all DBG registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header le is used to translate these names into the appropriate absolute addresses.
17.4.1
BDC Registers and Control Bits
The BDC has two registers: The BDC status and control register (BDCSCR) is an 8-bit register containing control and status bits for the background debug controller. The BDC breakpoint match register (BDCBKPT) holds a 16-bit breakpoint match address. These registers are accessed with dedicated serial BDC commands and are not located in the memory space of the target MCU (so they do not have addresses and cannot be accessed by user programs). Some of the bits in the BDCSCR have write limitations; otherwise, these registers may be read or written at any time. For example, the ENBDM control bit may not be written while the MCU is in active background mode. (This prevents the ambiguous condition of the control bit forbidding active background mode while the MCU is already in active background mode.) Also, the four status bits (BDMACT, WS, WSF, and DVF) are read-only status indicators and can never be written by the WRITE_CONTROL serial BDC command. The clock switch (CLKSW) control bit may be read or written at any time.
17.4.1.1
BDC Status and Control Register (BDCSCR)
This register can be read or written by serial BDC commands (READ_STATUS and WRITE_CONTROL) but is not accessible to user programs because it is not located in the normal memory map of the MCU.
7 6 5 4 3 2 1 0
R ENBDM W Normal Reset Reset in Active BDM: 0 1
BDMACT BKPTEN 0 1 0 0 FTS 0 0 CLKSW 0 1
WS
WSF
DVF
0 0
0 0
0 0
Figure 17-5. BDC Status and Control Register (BDCSCR) Table 17-2. BDCSCR Register Field Descriptions
Field 7 ENBDM Description Enable BDM (Permit Active Background Mode) Typically, this bit is written to 1 by the debug host shortly after the beginning of a debug session or whenever the debug host resets the target and remains 1 until a normal reset clears it. 0 BDM cannot be made active (non-intrusive commands still allowed) 1 BDM can be made active to allow active background mode commands Background Mode Active Status This is a read-only status bit. 0 BDM not active (user application program running) 1 BDM active and waiting for serial commands BDC Breakpoint Enable If this bit is clear, the BDC breakpoint is disabled and the FTS (force tag select) control bit and BDCBKPT match register are ignored. 0 BDC breakpoint disabled 1 BDC breakpoint enabled Force/Tag Select When FTS = 1, a breakpoint is requested whenever the CPU address bus matches the BDCBKPT match register. When FTS = 0, a match between the CPU address bus and the BDCBKPT register causes the fetched opcode to be tagged. If this tagged opcode ever reaches the end of the instruction queue, the CPU enters active background mode rather than executing the tagged opcode. 0 Tag opcode at breakpoint address and enter active background mode if CPU attempts to execute that instruction 1 Breakpoint match forces active background mode at next instruction boundary (address need not be an opcode) Select Source for BDC Communications Clock CLKSW defaults to 0, which selects the alternate BDC clock source. 0 Alternate BDC clock source 1 MCU bus clock
6 BDMACT 5 BKPTEN
4 FTS
3 CLKSW
Table 17-2. BDCSCR Register Field Descriptions (continued)

Field 2 WS Description Wait or Stop Status When the target CPU is in wait or stop mode, most BDC commands cannot function. However, the BACKGROUND command can be used to force the target CPU out of wait or stop and into active background mode where all BDC commands work. Whenever the host forces the target MCU into active background mode, the host should issue a READ_STATUS command to check that BDMACT = 1 before attempting other BDC commands. 0 Target CPU is running user application code or in active background mode (was not in wait or stop mode when background became active) 1 Target CPU is in wait or stop mode, or a BACKGROUND command was used to change from wait or stop to active background mode Wait or Stop Failure Status This status bit is set if a memory access command failed due to the target CPU executing a wait or stop instruction at or about the same time. The usual recovery strategy is to issue a BACKGROUND command to get out of wait or stop mode into active background mode, repeat the command that failed, then return to the user program. (Typically, the host would restore CPU registers and stack values and re-execute the wait or stop instruction.) 0 Memory access did not conict with a wait or stop instruction 1 Memory access command failed because the CPU entered wait or stop mode Data Valid Failure Status This status bit is not used in the MC9S08DZ60 Series because it does not have any slow access memory. 0 Memory access did not conict with a slow memory access 1 Memory access command failed because CPU was not nished with a slow memory access
1 WSF
0 DVF
17.4.1.2
BDC Breakpoint Match Register (BDCBKPT)
This 16-bit register holds the address for the hardware breakpoint in the BDC. The BKPTEN and FTS control bits in BDCSCR are used to enable and congure the breakpoint logic. Dedicated serial BDC commands (READ_BKPT and WRITE_BKPT) are used to read and write the BDCBKPT register but is not accessible to user programs because it is not located in the normal memory map of the MCU. Breakpoints are normally set while the target MCU is in active background mode before running the user application program. For additional information about setup and use of the hardware breakpoint logic in the BDC, refer to Section 17.2.4, BDC Hardware Breakpoint.
17.4.2
System Background Debug Force Reset Register (SBDFR)
This register contains a single write-only control bit. A serial background mode command such as WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are ignored. Reads always return 0x00.
R W Reset
0 BDFR1
1
BDFR is writable only through serial background mode debug commands, not from user programs.
Figure 17-6. System Background Debug Force Reset Register (SBDFR) Table 17-3. SBDFR Register Field Description
Field 0 BDFR Description Background Debug Force Reset A serial active background mode command such as WRITE_BYTE allows an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from a user program.
17.4.3
DBG Registers and Control Bits
The debug module includes nine bytes of register space for three 16-bit registers and three 8-bit control and status registers. These registers are located in the high register space of the normal memory map so they are accessible to normal application programs. These registers are rarely if ever accessed by normal user application programs with the possible exception of a ROM patching mechanism that uses the breakpoint logic.
17.4.3.1
Debug Comparator A High Register (DBGCAH)
This register contains compare value bits for the high-order eight bits of comparator A. This register is forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.
17.4.3.2
Debug Comparator A Low Register (DBGCAL)
This register contains compare value bits for the low-order eight bits of comparator A. This register is forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.
17.4.3.3
Debug Comparator B High Register (DBGCBH)
This register contains compare value bits for the high-order eight bits of comparator B. This register is forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.
17.4.3.4
Debug Comparator B Low Register (DBGCBL)
This register contains compare value bits for the low-order eight bits of comparator B. This register is forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.
17.4.3.5
Debug FIFO High Register (DBGFH)
This register provides read-only access to the high-order eight bits of the FIFO. Writes to this register have no meaning or effect. In the event-only trigger modes, the FIFO only stores data into the low-order byte of each FIFO word, so this register is not used and will read 0x00. Reading DBGFH does not cause the FIFO to shift to the next word. When reading 16-bit words out of the FIFO, read DBGFH before reading DBGFL because reading DBGFL causes the FIFO to advance to the next word of information.
17.4.3.6
Debug FIFO Low Register (DBGFL)
This register provides read-only access to the low-order eight bits of the FIFO. Writes to this register have no meaning or effect. Reading DBGFL causes the FIFO to shift to the next available word of information. When the debug module is operating in event-only modes, only 8-bit data is stored into the FIFO (high-order half of each FIFO word is unused). When reading 8-bit words out of the FIFO, simply read DBGFL repeatedly to get successive bytes of data from the FIFO. It isnt necessary to read DBGFH in this case. Do not attempt to read data from the FIFO while it is still armed (after arming but before the FIFO is lled or ARMF is cleared) because the FIFO is prevented from advancing during reads of DBGFL. This can interfere with normal sequencing of reads from the FIFO. Reading DBGFL while the debugger is not armed causes the address of the most-recently fetched opcode to be stored to the last location in the FIFO. By reading DBGFH then DBGFL periodically, external host software can develop a prole of program execution. After eight reads from the FIFO, the ninth read will return the information that was stored as a result of the rst read. To use the proling feature, read the FIFO eight times without using the data to prime the sequence and then begin using the data to get a delayed picture of what addresses were being executed. The information stored into the FIFO on reads of DBGFL (while the FIFO is not armed) is the address of the most-recently fetched opcode.
17.4.3.7
Debug Control Register (DBGC)
This register can be read or written at any time.

7 6 5 4 3 2 1 0
R DBGEN W Reset 0 0 0 0 0 0 0 0 ARM TAG BRKEN RWA RWAEN RWB RWBEN
Figure 17-7. Debug Control Register (DBGC) Table 17-4. DBGC Register Field Descriptions
Field 7 DBGEN 6 ARM Description Debug Module Enable Used to enable the debug module. DBGEN cannot be set to 1 if the MCU is secure. 0 DBG disabled 1 DBG enabled Arm Control Controls whether the debugger is comparing and storing information in the FIFO. A write is used to set this bit (and ARMF) and completion of a debug run automatically clears it. Any debug run can be manually stopped by writing 0 to ARM or to DBGEN. 0 Debugger not armed 1 Debugger armed Tag/Force Select Controls whether break requests to the CPU will be tag or force type requests. If BRKEN = 0, this bit has no meaning or effect. 0 CPU breaks requested as force type requests 1 CPU breaks requested as tag type requests Break Enable Controls whether a trigger event will generate a break request to the CPU. Trigger events can cause information to be stored in the FIFO without generating a break request to the CPU. For an end trace, CPU break requests are issued to the CPU when the comparator(s) and R/W meet the trigger requirements. For a begin trace, CPU break requests are issued when the FIFO becomes full. TRGSEL does not affect the timing of CPU break requests. 0 CPU break requests not enabled 1 Triggers cause a break request to the CPU R/W Comparison Value for Comparator A When RWAEN = 1, this bit determines whether a read or a write access qualies comparator A. When RWAEN = 0, RWA and the R/W signal do not affect comparator A. 0 Comparator A can only match on a write cycle 1 Comparator A can only match on a read cycle Enable R/W for Comparator A Controls whether the level of R/W is considered for a comparator A match. 0 R/W is not used in comparison A 1 R/W is used in comparison A R/W Comparison Value for Comparator B When RWBEN = 1, this bit determines whether a read or a write access qualies comparator B. When RWBEN = 0, RWB and the R/W signal do not affect comparator B. 0 Comparator B can match only on a write cycle 1 Comparator B can match only on a read cycle Enable R/W for Comparator B Controls whether the level of R/W is considered for a comparator B match. 0 R/W is not used in comparison B 1 R/W is used in comparison B
5 TAG
4 BRKEN
3 RWA
2 RWAEN 1 RWB
0 RWBEN
17.4.3.8
Debug Trigger Register (DBGT)
This register can be read any time, but may be written only if ARM = 0, except bits 4 and 5 are hard-wired to 0s.
7 6 5 4 3 2 1 0
R TRGSEL W Reset 0 0 BEGIN
0 TRG3 TRG2 0 TRG1 0 TRG0 0
Figure 17-8. Debug Trigger Register (DBGT) Table 17-5. DBGT Register Field Descriptions
Field 7 TRGSEL Description Trigger Type Controls whether the match outputs from comparators A and B are qualied with the opcode tracking logic in the debug module. If TRGSEL is set, a match signal from comparator A or B must propagate through the opcode tracking logic and a trigger event is only signalled to the FIFO logic if the opcode at the match address is actually executed. 0 Trigger on access to compare address (force) 1 Trigger if opcode at compare address is executed (tag) Begin/End Trigger Select Controls whether the FIFO starts lling at a trigger or lls in a circular manner until a trigger ends the capture of information. In event-only trigger modes, this bit is ignored and all debug runs are assumed to be begin traces. 0 Data stored in FIFO until trigger (end trace) 1 Trigger initiates data storage (begin trace) Select Trigger Mode Selects one of nine triggering modes, as described below. 0000 A-only 0001 A OR B 0010 A Then B 0011 Event-only B (store data) 0100 A then event-only B (store data) 0101 A AND B data (full mode) 0110 A AND NOT B data (full mode) 0111 Inside range: A address B 1000 Outside range: address < A or address > B 1001 1111 (No trigger)
6 BEGIN
3:0 TRG[3:0]
17.4.3.9
Debug Status Register (DBGS)
This is a read-only status register.

7 6 5 4 3 2 1 0
R W Reset
AF
BF
ARMF
CNT3
CNT2
CNT1
CNT0
Figure 17-9. Debug Status Register (DBGS) Table 17-6. DBGS Register Field Descriptions
Field 7 AF Description Trigger Match A Flag AF is cleared at the start of a debug run and indicates whether a trigger match A condition was met since arming. 0 Comparator A has not matched 1 Comparator A match Trigger Match B Flag BF is cleared at the start of a debug run and indicates whether a trigger match B condition was met since arming. 0 Comparator B has not matched 1 Comparator B match Arm Flag While DBGEN = 1, this status bit is a read-only image of ARM in DBGC. This bit is set by writing 1 to the ARM control bit in DBGC (while DBGEN = 1) and is automatically cleared at the end of a debug run. A debug run is completed when the FIFO is full (begin trace) or when a trigger event is detected (end trace). A debug run can also be ended manually by writing 0 to ARM or DBGEN in DBGC. 0 Debugger not armed 1 Debugger armed FIFO Valid Count These bits are cleared at the start of a debug run and indicate the number of words of valid data in the FIFO at the end of a debug run. The value in CNT does not decrement as data is read out of the FIFO. The external debug host is responsible for keeping track of the count as information is read out of the FIFO. 0000 Number of valid words in FIFO = No valid data 0001 Number of valid words in FIFO = 1 0010 Number of valid words in FIFO = 2 0011 Number of valid words in FIFO = 3 0100 Number of valid words in FIFO = 4 0101 Number of valid words in FIFO = 5 0110 Number of valid words in FIFO = 6 0111 Number of valid words in FIFO = 7 1000 Number of valid words in FIFO = 8
6 BF
5 ARMF
3:0 CNT[3:0]

A.1 Introduction
This section contains the most accurate electrical and timing information for the MC9S08DZ60 Series of microcontrollers available at the time of publication.
A.2
Parameter Classication
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classication is used and the parameters are tagged accordingly in the tables where appropriate:
Table A-1. Parameter Classications P C
Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations. NOTE The classication is shown in the column labeled C in the parameter tables where appropriate.
A.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specied in Table A-2 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical elds; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD).
Table A-2. Absolute Maximum Ratings
Num 1 2 3 4 5
1
Rating Supply voltage Input voltage Instantaneous maximum current (applies to all port pins)1, 2, 3 Maximum current into VDD Storage temperature Single pin limit
Symbol VDD VIn ID IDD Tstg
Value 0.3 to + 5.8 0.3 to VDD + 0.3 25 120 55 to +150
Unit V V mA mA C
Input must be current limited to the value specied. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins are internally clamped to V SS and VDD. 3 Power supply must maintain regulation within operating V DD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may ow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low which would reduce overall power consumption.
A.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and it is user-determined rather than being controlled by the MCU design. In order to take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small.
Table A-3. Thermal Characteristics

Num 1 C D Operating temperature range (packaged) 2 3 T D Maximum Junction Temperature1 Thermal resistance2 Single-layer board 64-pin LQFP 48-pin LQFP 32-pin LQFP Four-Layer board 64-pin LQFP 48-pin LQFP 32-pin LQFP
1
Rating
Symbol
Value 40 to 125 40 to 105 40 to 85 135
Unit
Temp. Code M V C
TA TJ
C C
JA JA JA
69 75 80
C/W C/W C/W
JA JA JA
51 51 52
C/W C/W C/W
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air ow, power dissipation of other components on the board, and board thermal resistance. 2 Junction to Ambient Natural Convection
The average chip-junction temperature (TJ) in C can be obtained from:

TJ = TA + (PD JA) Eqn. A-1
where: TA = Ambient temperature, C JA = Package thermal resistance, junction-to-ambient, C/W PD = Pint + PI/O Pint = IDD VDD, Watts chip internal power PI/O = Power dissipation on input and output pins user determined For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is:
PD = K (TJ + 273C) Eqn. A-2
Solving equations 1 and 2 for K gives:

K = PD (TA + 273C) + JA (PD)2 Eqn. A-3
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations 1 and 2 iteratively for any value of TA.
A.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge. Qualication tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. All ESD testing is in conformity with AEC-Q100 Stress Test Qualication for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM) and the Charge Device Model (CDM). A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification.
Table A-4. ESD and Latch-up Test Conditions
Model Series Resistance Human Body Storage Capacitance Number of Pulse per pin Minimum input voltage limit Latch-up Maximum input voltage limit 7.5 V Description Symbol R1 C Value 1500 100 3 2.5 V Unit
pF
Table A-5. ESD and Latch-Up Protection Characteristics

Num 1 2 3 Rating Human Body Model (HBM) Charge Device Model (CDM) Latch-up Current at TA = 125C Symbol VHBM VCDM ILAT Min +/- 2000 +/- 500 +/- 100 Max Unit V V mA
A.6
DC Characteristics
This section includes information about power supply requirements, I/O pin characteristics, and power supply current in various operating modes.
Table A-6. DC Characteristics
Num 1 C Characteristic Symbol VDD 5 V, ILoad = 2 mA 3 V, ILoad = 0.6 mA 5 V, ILoad = 0.4 mA VOH Condition Min 2.7 VDD 1.5 VDD 1.5 VDD 0.8 Typ1 0.1 Max 5.5 -100 -60 1.5 1.5 0.8 0.8 1.5 1.5 0.8 0.8 100 60 0.35 x VDD 1 V mV A mA V mA V Unit V
Operating Voltage P C C Output high C voltage P C C C All I/O pins, high-drive strength All I/O pins, low-drive strength
3 V, ILoad = 0.24 mA VDD 0.8 5 V, ILoad = 10 mA VDD 1.5 3 V, ILoad = 3 mA 5 V, ILoad = 2 mA 3 V, ILoad = 0.4 mA VDD 1.5 VDD 0.8 VDD 0.8 0 0 0 0 0.65 x VDD 0.06 x VDD VIn = VDD or VSS
C Output high current P C C Output low C voltage P C C C
Max total IOH for all ports
IOHT
5V 3V 5 V, ILoad = 2 mA 3 V, ILoad = 0.6 mA 5 V, ILoad = 0.4 mA
All I/O pins, low-drive strength
VOL
3 V, ILoad = 0.24 mA 5 V, ILoad = 10 mA 3 V, ILoad = 3 mA 5 V, ILoad = 2 mA 3 V, ILoad = 0.4 mA
All I/O pins, high-drive strength
5 6 7 8 9
C Output low current
Max total IOL for all ports
IOLT VIH VIL Vhys
5V 3V 5V 5V
C Input high voltage; all digital inputs C Input low voltage; all digital inputs C Input hysteresis Input leakage P current (Per pin) all input only pins Hi-Z (off-state) leakage current (per pin) all input/output Pullup resistors (or Pulldown2 resistors when enabled) Input Capacitance, all pins
|IIn| |IOZ|
RPU, RPD
VIn = VDD or VSS
0.1
10
11
P C
5V 3V
20 20
45 45 0.6
65 k 65 8 1.0 pF V
12 13
CIn VRAM MC9S08DZ60 Series Data Sheet, Rev. 4
D RAM retention voltage
Freescale Semiconductor
373
Table A-6. DC Characteristics (continued)

Num 14 15 C Characteristic
3 4
Symbol VPOR tPOR VLVD1
Condition
Min 0.9 10
Typ1 1.4
Max 2.0
Unit V s
D POR re-arm voltage D POR re-arm time
16
Low-voltage detection threshold high range P VDD falling VDD rising Low-voltage detection threshold low range P VDD falling VDD rising Low-voltage warning threshold high range 1 C VDD falling VDD rising Low-voltage warning threshold high range 0 P VDD falling VDD rising Low-voltage warning threshold low range 1 P VDD falling VDD rising Low-voltage warning threshold low range 0 C VDD falling VDD rising Low-voltage inhibit reset/recover T hysteresis dc injection current 5, 6, 7, 8 Single pin limit
3.9 4.0 VLVD0 2.48 2.54 VLVW3 4.5 4.6 VLVW2 4.2 4.3 VLVW1 2.84 2.90 VLVW0 2.66 2.72 Vhys 5V 3V VIN > VDD IIC VIN < VSS VIN > VDD VIN < VSS 0 0 0 0 1.19
4.0 4.1
4.1 4.2
17
2.56 2.62
2.64 2.70
18
4.6 4.7
4.7 4.8
19
4.3 4.4
4.4 4.5
20
2.92 2.98
3.00 3.06
21
2.74 2.80 100 60 1.20
2.82 2.88 2 0.2 25 5 1.21
22
mV
23
D Total MCU limit, includes sum of all stressed pins Bandgap Voltage Reference C Factory trimmed at VDD = 5.0 V, Temp = 25C
mA
VBG V
24
1 2 3 4 5
Typical values are measured at 25C. Characterized, not tested When a pin interrupt is congured to detect rising edges, pulldown resistors are used in place of pullup resistors. Maximum is highest voltage that POR is guaranteed. Simulated, not tested Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may ow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low which (would reduce overall power consumption). All functional non-supply pins are internally clamped to VSS and VDD. MC9S08DZ60 Series Data Sheet, Rev. 4
374
Freescale Semiconductor

7
Input must be current limited to the value specied. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 8 PTE1 does not have a clamp diode to VDD. Do not drive PTE1 above VDD.
A.7
Supply Current Characteristics

Table A-7. Supply Current Characteristics
Num C C 1 C P 2 C P 3 C P4 P4 P 4 P C C C C P4 P4 P 5 P C C C C Stop2 mode supply current Parameter Run supply current3 measured at (CPU clock = 2 MHz, fBus = 1 MHz) Run supply current measured at (CPU clock = 16 MHz, fBus = 8 MHz) Run supply current3 measured at (CPU clock = 40 MHz, fBus = 20 MHz) Stop3 mode supply current
3
Symbol
VDD (V) 5
Typical1 3 2.8 7.7 7.4 15 14
Max2 7.5
Unit
RIDD
mA 3 5 7.4 11.4 mA 3 5 11.2 24 mA 3 23
RIDD
RIDD
40 C (C, V, & M sufx) 25 C (All parts) 105 C (V sufx only) 125 C (M sufx only) 40 C (C, V, & M sufx) 25 C (All parts) 105 C (V sufx only) 125 C (M sufx only) 3 S3IDD 5
0.9 1.0 26 62 0.8 0.9 21 52
39 90 32 80 A
40 C (C, V, & M sufx) 25 C (All parts) 105 C (V sufx only) 125 C (M sufx only) 40 C (C, V, & M sufx) 25 C (All parts) 105 C (V sufx only) 125 C (M sufx only) 3 S2IDD 5
0.8 0.9 25 46 0.7 0.8 20 40
37 70 30 60 A
Table A-7. Supply Current Characteristics (continued)

Num C Parameter RTC adder to stop2 or stop35, 25C 6 C 3 LVD adder to stop3 (LVDE = LVDSE = 1) 7 C 3 Adder to stop3 for oscillator enabled6 (IRCLKEN = 1 and IREFSTEN = 1 or ERCLKEN = 1 and EREFSTEN = 1) 5 3 90 5 5 5 300 110 nA A A A A Symbol VDD (V) 5 Typical1 300 Max2 Unit nA
8
1 2 3 4
5 6
Typicals are measured at 25C, unless otherwise noted. Maximum values in this column apply for the full operating temperature range of the device unless otherwise noted. All modules except ADC active, MCG congured for FBE, and does not include any dc loads on port pins Stop currents are tested in production for 25C on all parts. Tests at other temperatures depend upon the part number sufx and maturity of the product. Freescale may eliminate a test insertion at a particular temperature from the production test ow once sufcient data has been collected and is approved. Most customers are expected to nd that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait mode. Values given under the following conditions: low range operation (RANGE = 0), low power mode (HGO = 0).
A.8
Num 1 2 3 4 5 6 7
Analog Comparator (ACMP) Electricals

Table A-8. Analog Comparator Electrical Specications
C D D D D D D Supply voltage Supply current (active) Analog input voltage Analog input offset voltage Analog Comparator hysteresis Analog input leakage current Analog Comparator initialization delay Rating Symbol VDD IDDAC VAIN VAIO VH IALKG tAINIT 3.0 - Min 2.7 VSS 0.3 Typical 20 20 6.0 - Max 5.5 35 VDD 40 20.0 1.0 1.0 Unit V A V mV mV A s
A.9
ADC Characteristics
Table A-9. 12-bit ADC Operating Conditions
Characteristic Supply voltage
Conditions Absolute Delta to VDD (VDD-VDDAD)2
Symb VDDAD VDDAD VSSAD
Min 2.7 -100 -100
Typ1 0 0
Max 5.5 +100 +100
Unit V mV mV
Comment
Ground voltage
Delta to VSS (VSS-VSSAD)2
Table A-9. 12-bit ADC Operating Conditions (continued)

Characteristic Ref Voltage High Conditions Symb VREFH Min 2.7 Typ1 VDDAD Max VDDAD Unit V Comment Applicable in only 64-pin packages {VREFH < VDDAD characterized but not production test} Not Applicable in 64-pin packages (only 32- and 48-pin packages)
Ref Voltage Low
VREFL
VSSAD
VSSAD
VSSAD
Input Voltage Input Capacitance Input Resistance Analog Source Resistance 12 bit mode fADCK > 4MHz fADCK < 4MHz 10 bit mode fADCK > 4MHz fADCK < 4MHz 8 bit mode (all valid fADCK) ADC Conversion Clock Freq.
1
VADIN CADIN RADIN RAS
VREFL
4.5 3
VREFH 5.5 5
V pF k k External to MCU
fADCK 0.4 0.4
2 5 5 10 10 8.0 4.0 MHz
High Speed (ADLPC=0) Low Power (ADLPC=1)
Typical values assume VDDAD = 5.0V, Temp = 25C, fADCK=1.0MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 DC potential difference.
Appendix A Electrical Characteristics SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZAS RAS Pad leakage due to input protection
ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN
ADC SAR ENGINE
+
VADIN VAS
CAS
RADIN INPUT PIN
RADIN
INPUT PIN
RADIN CADIN
INPUT PIN
Figure A-1. ADC Input Impedance Equivalency Diagram
Table A-10. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD)

Characteristic Supply Current Conditions ADLPC=1 ADLSMP=1 ADCO=1 ADLPC=1 ADLSMP=0 ADCO=1 ADLPC=0 ADLSMP=1 ADCO=1 ADLPC=0 ADLSMP=0 ADCO=1 Stop, Reset, Module Off High Speed (ADLPC=0) Low Power (ADLPC=1) P C T Symb IDD + IDDAD IDD + IDDAD IDD + IDDAD IDD + IDDAD IDD + IDDAD fADACK Min Typ1 133 Max Unit A Comment ADC current only ADC current only ADC current only ADC current only ADC current only tADACK = 1/fADACK
Supply Current
218
Supply Current
327
Supply Current
0.582
mA
Supply Current ADC Asynchronous Clock Source
2 1.25
0.011 3.3 2
1 5 3.3
A MHz
Table A-10. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued)
Characteristic Conversion Time (Including sample time) Sample Time Conditions Short Sample (ADLSMP=0) Long Sample (ADLSMP=1) Short Sample (ADLSMP=0) Long Sample (ADLSMP=1) Total Unadjusted Error 12 bit mode 10 bit mode 8 bit mode Differential Non-Linearity 12 bit mode 10 bit mode3 8 bit mode3 Integral Non-Linearity 12 bit mode 10 bit mode 8 bit mode Zero-Scale Error 12 bit mode 10 bit mode 8 bit mode Full-Scale Error 12 bit mode 10 bit mode 8 bit mode Quantization Error 12 bit mode 10 bit mode 8 bit mode Input Leakage Error 12 bit mode 10 bit mode 8 bit mode Temp Sensor Slope Temp Sensor Voltage
1
C D
Symb tADC
Min
Typ1 20 40 3.5 23.5 3.0 1 0.5 1.75 0.5 0.3 1.5 0.5 0.3 1.5 0.5 0.5 1 0.5 0.5 -1 to 0 1 0.2 0.1 3.266 3.638 1.396
Max 10 2.5 1.0 4.0 1.0 0.5 4.0 1.0 0.5 6.0 1.5 0.5 4.0 1 0.5 -1 to 0 0.5 0.5 10.0 2.5 1
Unit ADCK cycles ADCK cycles LSB2
Comment See Table 10-13 for conversion time variances
tADS
T P T T P T T T T T P T T T T D
ETUE
Includes quantization
DNL
LSB2
INL
LSB2
EZS
LSB2
VADIN = VSSAD
EFS
LSB2
VADIN = VDDAD
EQ
LSB2
EIL
LSB2
Pad leakage4 * RAS
-40C 25C 25C 125C 25C
mV/C
VTEMP25
Typical values assume VDDAD = 5.0V, Temp = 25C, fADCK=1.0MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 1 LSB = (V N REFH - VREFL)/2

3 4
Monotonicity and No-Missing-Codes guaranteed in 10 bit and 8 bit modes Based on input pad leakage current. Refer to pad electricals.
A.10
Num C
External Oscillator (XOSC) Characteristics

Table A-11. Oscillator Electrical Specications (Temperature Range = 40 to 125C Ambient)
Rating Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1 Low range (RANGE = 0) C High range (RANGE = 1) FEE or FBE mode High range (RANGE = 1) PEE or PBE mode
2 3
Symbol flo fhi-l fhi-pll fhi-hgo fhi-lp C1 C2 RF
Min 32 1 1 1 1
Typ1
Max 38.4 5 16 16 8
Unit kHz MHz MHz MHz MHz
High range (RANGE = 1, HGO = 1) BLPE mode High range (RANGE = 1, HGO = 0) BLPE mode 2 Load capacitors Feedback resistor 3 Low range (32 kHz to 100 kHz) High range (1 MHz to 16 MHz) Series resistor Low range, low gain (RANGE = 0, HGO = 0) Low range, high gain (RANGE = 0, HGO = 1) 4 High range, low gain (RANGE = 1, HGO = 0) High range, high gain (RANGE = 1, HGO = 1) 8 MHz 4 MHz 1 MHz Crystal start-up time
4 t t
See crystal or resonator manufacturers recommendation. 10 1 0 100 0 0 0 0 0 10 20 k M M
RS
Low range, low gain (RANGE = 0, HGO = 0) 5 T Low range, high gain (RANGE = 0, HGO = 1) High range, low gain (RANGE = 1, HGO = 0)5 High range, high gain (RANGE = 1, HGO = 1)4 Square wave input clock frequency (EREFS = 0, ERCLKEN = 1) 6 T FEE or FBE mode 2 PEE or PBE mode BLPE mode
1 2 3 t
CSTL-LP
200 400 5 15
ms
CSTL-HGO t CSTH-LP
CSTH-HGO
0.03125 fextal 1 0
5 16 40 MHz
Typical data was characterized at 3.0 V, 25C or is recommended value. When MCG is configured for FEE or FBE mode, the input clock source must be divisible using RDIV to within the range of 31.25 kHz to 39.0625 kHz. 3 When MCG is congured for PEE or PBE mode, input clock source must be divisible using RDIV to within the range of 1 MHz to 2 MHz. 4 This parameter is characterized and not tested on each device. Proper PC board layout procedures must be followed to achieve specications. This data will vary based upon the crystal manufacturer and board design. The crystal should be characterized by the crystal manufacturer. 5 4 MHz crystal.
MCU EXTAL XTAL RS
RF
C1
Crystal or Resonator
C2
A.11
Num C 1 2 3 4 5 6 7 8 9 P P P
MCG Specications
Table A-12. MCG Frequency Specications (Temperature Range = 40 to 125C Ambient)
Rating Internal reference frequency - factory trimmed at VDD = 5 V and temperature = 25 C Average internal reference frequency untrimmed 1 Average internal reference frequency - user trimmed
1
Symbol fint_ft fint_ut fint_t tirefst fdco_ut fdco_t fdco_res_t fdco_res_t fdco_t fdco_t tl_acquire tpll_acquire CJitter fvco fpll_ref fpll_cycjit_2ms fpll_maxjit_2ms
Min 25 31.25 25.6 32
Typical 31.25 32.7 60 33.48 0.1 0.2 + 0.5 -1.0 0.5 0.02 0.5904 0.001
Max 41.66 39.0625 100 42.66 40 0.2 0.4 2 1 1 1 0.2 55.0 2.0
Unit kHz kHz kHz us MHz MHz %fdco %fdco %fdco %fdco ms ms %fdco MHz MHz %fpll %fpll
D Internal reference startup time DCO output frequency range - untrimmed value provided for reference: fdco_ut = 1024 X fint_ut P DCO output frequency range - trimmed C C P Resolution of trimmed DCO output frequency at xed voltage and temperature (using FTRIM) Resolution of trimmed DCO output frequency at xed voltage and temperature (not using FTRIM) Total deviation of trimmed DCO output frequency over voltage and temperature
10 11 12 13 14 15 16 17
Total deviation of trimmed DCO output frequency C over xed voltage and temperature range of 0 - 70 C C FLL acquisition time 2 D PLL acquisition time 3 C Long term Jitter of DCO output clock (averaged over 2ms interval) 4
7.0 1.0
D VCO operating frequency D PLL reference frequency range T T RMS frequency variation of a single clock cycle measured 2 ms after reference edge.5 Maximum frequency variation averaged over 2 ms window.
Table A-12. MCG Frequency Specications (Temperature Range = 40 to 125C Ambient) (continued)
Num C 18 19 20 21 22 23 T T Rating RMS frequency variation of a single clock cycle measured 625 ns after reference edge.6 Maximum frequency variation averaged over 625 ns window. Symbol fpll_cycjit_625ns fpll_maxjit_625ns Dlock Dunl tl_lock tpll_lock floc_low Min 1.49 4.47 Typical 0.5664 0.113 Max 2.98 5.97 tl_acquire+ 1075(1/fint_t) tpll_acquire+ 1075(1/fpll_ref) Unit %fpll %fpll % % s s
D Lock entry frequency tolerance 7 D Lock exit frequency tolerance 8 D Lock time - FLL D Lock time - PLL Loss of external clock minimum frequency D RANGE = 0 Loss of external clock minimum frequency D RANGE = 1
24
(3/5) x fint
kHz
25
1 2
floc_high
(16/5) x fint
kHz
5 6 7
TRIM register at default value (0x80) and FTRIM control bit at default value (0x0). This specication applies to any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specication assumes it is already running. This specication applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specication assumes it is already running. Jitter is the average deviation from the programmed frequency measured over the specied interval at maximum fBUS. Measurements are made with the device powered by ltered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval. Jitter measurements are based upon a 40MHz MCGOUT clock frequency. In some specications, this value is described as long term accuracy of PLL output clock (averaged over 2 ms) with symbol fpll_jitter_2ms. The parameter is unchanged, but the description has been changed for clarication purposes. In some specications, this value is described as Jitter of PLL output clock measured over 625 ns with symbol fpll_jitter_625ns. The parameter is unchanged, but the description has been changed for clarication purposes. Below Dlock minimum, the MCG is guaranteed to enter lock. Above Dlock maximum, the MCG will not enter lock. But if the MCG is already in lock, then the MCG may stay in lock. Below Dunl minimum, the MCG will not exit lock if already in lock. Above Dunl maximum, the MCG is guaranteed to exit lock.
A.12
AC Characteristics
This section describes ac timing characteristics for each peripheral system.
A.12.1
Nu m 1 2 3 4 5 6 7
Control Timing
Table A-13. Control Timing
C Rating Bus frequency (tcyc = 1/fBus) Internal low-power oscillator period External reset pulse width2 Reset low drive3 Active background debug mode latch setup time Active background debug mode latch hold time IRQ/PIAx/ PIBx/PIDx pulse width Asynchronous path2 Synchronous path3 Port rise and fall time Low output drive (PTxDS = 0) (load = 50 pF)4 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) Port rise and fall time High output drive (PTxDS = 1) (load = 50 pF)4 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) Symbol fBus tLPO textrst trstdrv tMSSU tMSH tILIH, tIHIL Min dc 1.5 x tcyc 34 x tcyc 25 25 100 1.5 tcyc Typical1 1500 Max 20 Unit MHz s ns ns ns ns ns
D/ P T D D D D D
tRise, tFall
40 75
ns
tRise, tFall
11 35
ns
Typical data was characterized at 5.0 V, 25C unless otherwise stated. This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to override reset requests from internal sources. 3 When any reset is initiated, internal circuitry drives the RESET pin low for about 34 cycles of t . After POR reset, the bus cyc clock frequency changes to the untrimmed DCO frequency (freset = (fdco_ut)/4) because TRIM is reset to 0x80 and FTRIM is reset to 0; and there is an extra divide-by-two because BDIV is reset to 0:1. After other resets, trim stays at the pre-reset value. 4 Timing is shown with respect to 20% V DD and 80% VDD levels. Temperature range 40C to 125C.
2
textrst RESET PIN
Figure A-2. Reset Timing
BKGD/MS
RESET tMSH tMSSU
Figure A-3. Active Background Debug Mode Latch Timing
tIHIL PIAx/PIBx/PIDx
IRQ/PIAx/PIBx/PIDx tILIH
Figure A-4. Pin Interrupt Timing
A.12.2
Timer/PWM
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock.
Table A-14. TPM Input Timing
Num 1 2 3 4 5 C D D D Rating External clock frequency External clock period External clock high time External clock low time Input capture pulse width Symbol fTCLK tTCLK tclkh tclkl tICPW Min dc 4 1.5 1.5 1.5 Max fBus/4 Unit MHz tcyc tcyc tcyc tcyc
tTCLK tclkh
TPMxCHn tclkl
Figure A-5. Timer External Clock
tICPW TPMxCHn
TPMxCHn tICPW
Figure A-6. Timer Input Capture Pulse
A.12.3
MSCAN
Table A-15. MSCAN Wake-up Pulse Characteristics
Num C 1 2
Rating
Symbol tWUP tWUP
Min 5
Typ
Max 2
Unit s s
D MSCAN Wake-up dominant pulse ltered D MSCAN Wake-up dominant pulse pass
A.12.4
SPI
Table A-16. SPI Electrical Characteristic
Num1 1 C Cycle time D Enable lead time 2 D Enable lag time 3 D Master Slave Clock (SPSCK) high time Master and Slave Clock (SPSCK) low time Master and Slave Data setup time (inputs) 6 D Data hold time (inputs) 7 8 9 10 D D D D Access time, slave3 Disable time, slave4 Master Slave Master Slave Master Slave Master Slave tSCK tSCK 2 4 1/2 2048 Rating2 Symbol Min Max Unit tcyc tcyc
Table A-16 and Figure A-7 through Figure A-10 describe the timing requirements for the SPI system.
1/2
tLead tLead tLag tLag tSCKH tSCKL tSI(M) tSI(S) tHI(M) tHI(S) tA tdis tSO tSO tHO tHO fop fop
tSCK tSCK tSCK tSCK

ns ns ns ns
1/2
1/2
4 5
D D
(1/2 tSCK) 25 (1/2 tSCK) 25 30 30
30 30 0 25 25
40 40
ns ns ns ns ns ns
Data setup time (outputs) Master Slave Data hold time (outputs)
11
D Operating frequency5
Master Slave
10 10
ns ns
12
1
Master Slave
fBus/2048 dc
5 fBus/4
MHz
Refer to Figure A-7 through Figure A-10. All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output pins. 3 Time to data active from high-impedance state. 4 Hold time to high-impedance state. 5 Maximum baud rate must be limited to 5 MHz due to pad input characteristics.
2
Appendix A Electrical Characteristics SS1 (OUTPUT) 2 SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) 6 MISO (INPUT) MSB IN2 10 MOSI (OUTPUT) MSB OUT2 7 BIT 6 . . . 1 10 BIT 6 . . . 1 LSB OUT LSB IN 11 1 5 4 3
5 4
NOTES: 1. SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure A-7. SPI Master Timing (CPHA = 0)
SS(1) (OUTPUT) 1 2 SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) MISO (INPUT) 10 MOSI (OUTPUT) MSB OUT(2) 5 4 5 4 6 7 MSB IN(2) BIT 6 . . . 1 11 BIT 6 . . . 1 LSB OUT LSB IN 3
NOTES: 1. SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure A-8. SPI Master Timing (CPHA = 1)
Appendix A Electrical Characteristics SS (INPUT) 1 SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 8 MISO (OUTPUT) SLAVE 6 MOSI (INPUT)
NOTE:
3 5
5 4 10 MSB OUT 7 MSB IN BIT 6 . . . 1 LSB IN BIT 6 . . . 1 11 SLAVE LSB OUT SEE NOTE 9
1. Not defined but normally MSB of character just received
Figure A-9. SPI Slave Timing (CPHA = 0)
SS (INPUT) 1 2 SCK (CPOL = 0) (INPUT) SCK (CPOL = 1) (INPUT) MISO (OUTPUT) SEE NOTE 8 MOSI (INPUT) 5 4 5 4 10 SLAVE 6 MSB IN MSB OUT 7 BIT 6 . . . 1 LSB IN 11 BIT 6 . . . 1 SLAVE LSB OUT 9 3
NOTE: 1. Not defined but normally LSB of character just received
Figure A-10. SPI Slave Timing (CPHA = 1)
A.13
Flash and EEPROM
This section provides details about program/erase times and program-erase endurance for the Flash and EEPROM memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see Chapter 4, Memory.
Table A-17. Flash and EEPROM Characteristics
Num 1 C Rating Supply voltage for program/erase Supply voltage for read operation 0 < fBus < 8 MHz 0 < fBus < 20 MHz Internal FCLK frequency1 Internal FCLK period (1/FCLK) Byte program time (random location)(2) Byte program time (burst mode)(2) Page erase time2 Mass erase time(2) Flash Program/erase endurance3 TL to TH = 40C to + 125C T = 25C EEPROM Program/erase endurance3 TL to TH = 40C to + 0C TL to TH = 0C to + 125C T = 25C Data retention4 Symbol Vprog/erase VRead Min 2.7 Typical Max 5.5 Unit V
2.7
5.5
3 4 5 6 7 8
fFCLK tFcyc tprog tBurst tPage tMass
150 5 9 4 4000 20,000
200 6.67
kHz s tFcyc tFcyc tFcyc tFcyc
nFLPE
10,000
100,000
cycles
10
nEEPE
10,000 50,000 15
100,000 100
cycles
11
1 2
tD_ret
years
The frequency of this clock is controlled by a software setting. These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 3 Typical endurance for Flash and EEPROM is based on the intrinsic bit cell performance. For additional information on how Freescale Semiconductor denes typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory. 4 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25C using the Arrhenius equation. For additional information on how Freescale Semiconductor denes typical data retention, please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.
A.14
EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a signicant role in EMC performance. The system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specically targeted at optimizing EMC performance.
A.14.1
Radiated Emissions
Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller are measured in a TEM cell in two package orientations (North and East). For more detailed information concerning the evaluation results, conditions and setup, please refer to the EMC Evaluation Report for this device. The maximum radiated RF emissions of the tested conguration in all orientations are less than or equal to the reported emissions levels.
Table A-18. Radiated Emissions for 3M05C Mask Set
Parameter Symbol VRE_TEM Conditions VDD = 5 TA = +25oC 64 LQFP Frequency 0.15 50 MHz 50 150 MHz 150 500 MHz 500 1000 MHz IEC Level SAE Level
1
fosc/fCPU
Level1 (Max) 18 18
Unit dBV
Radiated emissions, electric eld Conditions -
16 MHz Crystal 20 MHz Bus
13 7 L 2
Data based on qualication test results.

NOTE This chapter refers to S08TPM version 2, which applies to the 3M05C and older mask sets of this device. )M74K and newer mask set devices use S08TPM version 3. If your device uses mask 0M74K or newer, please refer to Chapter 16, Timer Pulse-Width Modulator (S08TPMV3) for information pertaining to that module. The TPM uses one input/output (I/O) pin per channel, TPMxCHn where x is the TPM number (for example, 1 or 2) and n is the channel number (for example, 04). The TPM shares its I/O pins with general-purpose I/O port pins (refer to the Pins and Connections chapter for more information).
B.0.1
Features
The TPM has the following features: Each TPM may be congured for buffered, center-aligned pulse-width modulation (CPWM) on all channels Clock sources independently selectable per TPM (multiple TPMs device) Selectable clock sources (device dependent): bus clock, xed system clock, external pin Clock prescaler taps for divide by 1, 2, 4, 8, 16, 32, 64, or 128 16-bit free-running or up/down (CPWM) count operation 16-bit modulus register to control counter range Timer system enable One interrupt per channel plus a terminal count interrupt for each TPM module (multiple TPMs device) Channel features: Each channel may be input capture, output compare, or buffered edge-aligned PWM Rising-edge, falling-edge, or any-edge input capture trigger Set, clear, or toggle output compare action Selectable polarity on PWM outputs
B.0.2
Block Diagram
Figure B-1 shows the structure of a TPM. Some MCUs include more than one TPM, with various numbers of channels.
BUSCLK XCLK TPMxCLK SYNC
CLOCK SOURCE SELECT OFF, BUS, XCLK, EXT
PRESCALE AND SELECT DIVIDE BY 1, 2, 4, 8, 16, 32, 64, or 128
CLKSB CPWMS MAIN 16-BIT COUNTER
CLKSA
PS2
PS1
PS0
COUNTER RESET 16-BIT COMPARATOR TPMxMODH:TPMxMODL CHANNEL 0 16-BIT COMPARATOR TPMxC0VH:TPMxC0VL 16-BIT LATCH MS0B MS0A CH0IE CH0F ELS0B ELS0A
TOF TOIE
INTERRUPT LOGIC
PORT LOGIC
TPMxCH0
INTERRUPT LOGIC
INTERNAL BUS
ELS1B
ELS1A
TPMxCH1
MS1B
MS1A
CH1IE
...
... CHANNEL n 16-BIT COMPARATOR TPMxCnVH:TPMxCnVL 16-BIT LATCH MSnB MSnA CHnIE CHnF ELSnB ELSnA
...
PORT LOGIC
TPMxCHn
INTERRUPT LOGIC
Figure B-1. TPM Block Diagram
The central component of the TPM is the 16-bit counter that can operate as a free-running counter, a modulo counter, or an up-/down-counter when the TPM is congured for center-aligned PWM. The TPM counter (when operating in normal up-counting mode) provides the timing reference for the input capture, output compare, and edge-aligned PWM functions. The timer counter modulo registers, TPMxMODH:TPMxMODL, control the modulo value of the counter. (The values 0x0000 or 0xFFFF effectively make the counter free running.) Software can read the counter value at any time without affecting the counting sequence. Any write to either byte of the TPMxCNT counter resets the counter regardless of the data value written.
All TPM channels are programmable independently as input capture, output compare, or buffered edge-aligned PWM channels.
B.1
When any pin associated with the timer is congured as a timer input, a passive pullup can be enabled. After reset, the TPM modules are disabled and all pins default to general-purpose inputs with the passive pullups disabled.
B.1.1
External TPM Clock Sources
When control bits CLKSB:CLKSA in the timer status and control register are set to 1:1, the prescaler and consequently the 16-bit counter for TPMx are driven by an external clock source, TPMxCLK, connected to an I/O pin. A synchronizer is needed between the external clock and the rest of the TPM. This synchronizer is clocked by the bus clock so the frequency of the external source must be less than one-half the frequency of the bus rate clock. The upper frequency limit for this external clock source is specied to be one-fourth the bus frequency to conservatively accommodate duty cycle and phase-locked loop (PLL) or frequency-locked loop (FLL) frequency jitter effects. On some devices the external clock input is shared with one of the TPM channels. When a TPM channel is shared as the external clock input, the associated TPM channel cannot use the pin. (The channel can still be used in output compare mode as a software timer.) Also, if one of the TPM channels is used as the external clock input, the corresponding ELSnB:ELSnA control bits must be set to 0:0 so the channel is not trying to use the same pin.
B.1.2
TPMxCHn TPMx Channel n I/O Pins
Each TPM channel is associated with an I/O pin on the MCU. The function of this pin depends on the conguration of the channel. In some cases, no pin function is needed so the pin reverts to being controlled by general-purpose I/O controls. When a timer has control of a port pin, the port data and data direction registers do not affect the related pin(s). See the Pins and Connections chapter for additional information about shared pin functions.
B.2
Register Denition
The TPM includes: An 8-bit status and control register (TPMxSC) A 16-bit counter (TPMxCNTH:TPMxCNTL) A 16-bit modulo register (TPMxMODH:TPMxMODL) Each timer channel has: An 8-bit status and control register (TPMxCnSC) A 16-bit channel value register (TPMxCnVH:TPMxCnVL) Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all TPM registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header le is used to translate these names into the appropriate absolute addresses.
B.2.1
Timer Status and Control Register (TPMxSC)
TPMxSC contains the overow status ag and control bits that are used to congure the interrupt enable, TPM conguration, clock source, and prescale divisor. These controls relate to all channels within this timer module.
7 6 5 4 3 2 1 0
R W Reset
TOF TOIE 0 0 CPWMS 0 CLKSB 0 CLKSA 0 PS2 0 PS1 0 PS0 0
Figure B-2. Timer Status and Control Register (TPMxSC) Table B-1. TPMxSC Register Field Descriptions
Field 7 TOF Description Timer Overow Flag This ag is set when the TPM counter changes to 0x0000 after reaching the modulo value programmed in the TPM counter modulo registers. When the TPM is congured for CPWM, TOF is set after the counter has reached the value in the modulo register, at the transition to the next lower count value. Clear TOF by reading the TPM status and control register when TOF is set and then writing a 0 to TOF. If another TPM overow occurs before the clearing sequence is complete, the sequence is reset so TOF would remain set after the clear sequence was completed for the earlier TOF. Reset clears TOF. Writing a 1 to TOF has no effect. 0 TPM counter has not reached modulo value or overow 1 TPM counter has overowed Timer Overow Interrupt Enable This read/write bit enables TPM overow interrupts. If TOIE is set, an interrupt is generated when TOF equals 1. Reset clears TOIE. 0 TOF interrupts inhibited (use software polling) 1 TOF interrupts enabled Center-Aligned PWM Select This read/write bit selects CPWM operating mode. Reset clears this bit so the TPM operates in up-counting mode for input capture, output compare, and edge-aligned PWM functions. Setting CPWMS recongures the TPM to operate in up-/down-counting mode for CPWM functions. Reset clears CPWMS. 0 All TPMx channels operate as input capture, output compare, or edge-aligned PWM mode as selected by the MSnB:MSnA control bits in each channels status and control register 1 All TPMx channels operate in center-aligned PWM mode Clock Source Select As shown in Table B-2, this 2-bit eld is used to disable the TPM system or select one of three clock sources to drive the counter prescaler. The external source and the XCLK are synchronized to the bus clock by an on-chip synchronization circuit. Prescale Divisor Select This 3-bit eld selects one of eight divisors for the TPM clock input as shown in Table B-3. This prescaler is located after any clock source synchronization or clock source selection, so it affects whatever clock source is selected to drive the TPM system.
6 TOIE
5 CPWMS
4:3 CLKS[B:A] 2:0 PS[2:0]
Table B-2. TPM Clock Source Selection

CLKSB:CLKSA 0:0 0:1 1:0 1:1
1
TPM Clock Source to Prescaler Input No clock selected (TPMx disabled) Bus rate clock (BUSCLK) Fixed system clock (XCLK) External source (TPMxCLK)1,2
The maximum frequency that is allowed as an external clock is one-fourth of the bus frequency. 2 If the external clock input is shared with channel n and is selected as the TPM clock source, the corresponding ELSnB:ELSnA control bits should be set to 0:0 so channel n does not try to use the same pin for a conicting function.
Table B-3. Prescale Divisor Selection

PS2:PS1:PS0 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 TPM Clock Source Divided-By 1 2 4 8 16 32 64 128
B.2.2
Timer Counter Registers (TPMxCNTH:TPMxCNTL)
The two read-only TPM counter registers contain the high and low bytes of the value in the TPM counter. Reading either byte (TPMxCNTH or TPMxCNTL) latches the contents of both bytes into a buffer where they remain latched until the other byte is read. This allows coherent 16-bit reads in either order. The coherency mechanism is automatically restarted by an MCU reset, a write of any value to TPMxCNTH or TPMxCNTL, or any write to the timer status/control register (TPMxSC). Reset clears the TPM counter registers.
7 6 5 4 3 2 1 0
R W Reset
Bit 15
14
13
12
11
10
Bit 8
Any write to TPMxCNTH clears the 16-bit counter. 0 0 0 0 0 0 0 0
Figure B-3. Timer Counter Register High (TPMxCNTH)
R W Reset
Bit 7
Bit 0
Any write to TPMxCNTL clears the 16-bit counter. 0 0 0 0 0 0 0 0
Figure B-4. Timer Counter Register Low (TPMxCNTL)
When background mode is active, the timer counter and the coherency mechanism are frozen such that the buffer latches remain in the state they were in when the background mode became active even if one or both bytes of the counter are read while background mode is active.
B.2.3
Timer Counter Modulo Registers (TPMxMODH:TPMxMODL)
The read/write TPM modulo registers contain the modulo value for the TPM counter. After the TPM counter reaches the modulo value, the TPM counter resumes counting from 0x0000 at the next clock (CPWMS = 0) or starts counting down (CPWMS = 1), and the overow ag (TOF) becomes set. Writing to TPMxMODH or TPMxMODL inhibits TOF and overow interrupts until the other byte is written. Reset sets the TPM counter modulo registers to 0x0000, which results in a free-running timer counter (modulo disabled).
7 6 5 4 3 2 1 0
R Bit 15 W Reset 0 0 0 0 0 0 0 0 14 13 12 11 10 9 Bit 8
Figure B-5. Timer Counter Modulo Register High (TPMxMODH)
R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0
Figure B-6. Timer Counter Modulo Register Low (TPMxMODL)
It is good practice to wait for an overow interrupt so both bytes of the modulo register can be written well before a new overow. An alternative approach is to reset the TPM counter before writing to the TPM modulo registers to avoid confusion about when the rst counter overow will occur.
B.2.4
Timer Channel n Status and Control Register (TPMxCnSC)
TPMxCnSC contains the channel interrupt status ag and control bits that are used to congure the interrupt enable, channel conguration, and pin function.
7 6 5 4 3 2 1 0
R CHnF W Reset 0 0 0 0 0 0 CHnIE MSnB MSnA ELSnB ELSnA
Figure B-7. Timer Channel n Status and Control Register (TPMxCnSC) Table B-4. TPMxCnSC Register Field Descriptions
Field 7 CHnF Description Channel n Flag When channel n is congured for input capture, this ag bit is set when an active edge occurs on the channel n pin. When channel n is an output compare or edge-aligned PWM channel, CHnF is set when the value in the TPM counter registers matches the value in the TPM channel n value registers. This ag is seldom used with center-aligned PWMs because it is set every time the counter matches the channel value register, which correspond to both edges of the active duty cycle period. A corresponding interrupt is requested when CHnF is set and interrupts are enabled (CHnIE = 1). Clear CHnF by reading TPMxCnSC while CHnF is set and then writing a 0 to CHnF. If another interrupt request occurs before the clearing sequence is complete, the sequence is reset so CHnF would remain set after the clear sequence was completed for the earlier CHnF. This is done so a CHnF interrupt request cannot be lost by clearing a previous CHnF. Reset clears CHnF. Writing a 1 to CHnF has no effect. 0 No input capture or output compare event occurred on channel n 1 Input capture or output compare event occurred on channel n Channel n Interrupt Enable This read/write bit enables interrupts from channel n. Reset clears CHnIE. 0 Channel n interrupt requests disabled (use software polling) 1 Channel n interrupt requests enabled Mode Select B for TPM Channel n When CPWMS = 0, MSnB = 1 congures TPM channel n for edge-aligned PWM mode. For a summary of channel mode and setup controls, refer to Table B-5. Mode Select A for TPM Channel n When CPWMS = 0 and MSnB = 0, MSnA congures TPM channel n for input capture mode or output compare mode. Refer to Table B-5 for a summary of channel mode and setup controls. Edge/Level Select Bits Depending on the operating mode for the timer channel as set by CPWMS:MSnB:MSnA and shown in Table B-5, these bits select the polarity of the input edge that triggers an input capture event, select the level that will be driven in response to an output compare match, or select the polarity of the PWM output. Setting ELSnB:ELSnA to 0:0 congures the related timer pin as a general-purpose I/O pin unrelated to any timer channel functions. This function is typically used to temporarily disable an input capture channel or to make the timer pin available as a general-purpose I/O pin when the associated timer channel is set up as a software timer that does not require the use of a pin.
6 CHnIE 5 MSnB 4 MSnA 3:2 ELSn[B:A]
Table B-5. Mode, Edge, and Level Selection

CPWMS X 0 MSnB:MSnA XX 00 ELSnB:ELSnA 00 01 10 11 01 00 01 10 11 1X 10 X1 1 XX 10 X1 Edge-aligned PWM Center-aligned PWM Output compare Mode Conguration
Pin not used for TPM channel; use as an external clock for the TPM or revert to general-purpose I/O Input capture Capture on rising edge only Capture on falling edge only Capture on rising or falling edge Software compare only Toggle output on compare Clear output on compare Set output on compare High-true pulses (clear output on compare) Low-true pulses (set output on compare) High-true pulses (clear output on compare-up) Low-true pulses (set output on compare-up)
If the associated port pin is not stable for at least two bus clock cycles before changing to input capture mode, it is possible to get an unexpected indication of an edge trigger. Typically, a program would clear status ags after changing channel conguration bits and before enabling channel interrupts or using the status ags to avoid any unexpected behavior.
B.2.5
Timer Channel Value Registers (TPMxCnVH:TPMxCnVL)
These read/write registers contain the captured TPM counter value of the input capture function or the output compare value for the output compare or PWM functions. The channel value registers are cleared by reset.
7 6 5 4 3 2 1 0
R Bit 15 W Reset 0 0 0 0 0 0 0 0 14 13 12 11 10 9 Bit 8
Figure B-8. Timer Channel Value Register High (TPMxCnVH)
R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0
Figure B-9. Timer Channel Value Register Low (TPMxCnVL)
In input capture mode, reading either byte (TPMxCnVH or TPMxCnVL) latches the contents of both bytes into a buffer where they remain latched until the other byte is read. This latching mechanism also resets (becomes unlatched) when the TPMxCnSC register is written. In output compare or PWM modes, writing to either byte (TPMxCnVH or TPMxCnVL) latches the value into a buffer. When both bytes have been written, they are transferred as a coherent 16-bit value into the timer channel value registers. This latching mechanism may be manually reset by writing to the TPMxCnSC register. This latching mechanism allows coherent 16-bit writes in either order, which is friendly to various compiler implementations.
B.3
All TPM functions are associated with a main 16-bit counter that allows exible selection of the clock source and prescale divisor. A 16-bit modulo register also is associated with the main 16-bit counter in the TPM. Each TPM channel is optionally associated with an MCU pin and a maskable interrupt function. The TPM has center-aligned PWM capabilities controlled by the CPWMS control bit in TPMxSC. When CPWMS is set to 1, timer counter TPMxCNT changes to an up-/down-counter and all channels in the associated TPM act as center-aligned PWM channels. When CPWMS = 0, each channel can independently be congured to operate in input capture, output compare, or buffered edge-aligned PWM mode. The following sections describe the main 16-bit counter and each of the timer operating modes (input capture, output compare, edge-aligned PWM, and center-aligned PWM). Because details of pin operation and interrupt activity depend on the operating mode, these topics are covered in the associated mode sections.
B.3.1
Counter
All timer functions are based on the main 16-bit counter (TPMxCNTH:TPMxCNTL). This section discusses selection of the clock source, up-counting vs. up-/down-counting, end-of-count overow, and manual counter reset. After any MCU reset, CLKSB:CLKSA = 0:0 so no clock source is selected and the TPM is inactive. Normally, CLKSB:CLKSA would be set to 0:1 so the bus clock drives the timer counter. The clock source for the TPM can be selected to be off, the bus clock (BUSCLK), the xed system clock (XCLK), or an external input. The maximum frequency allowed for the external clock option is one-fourth the bus rate. Refer to Section B.2.1, Timer Status and Control Register (TPMxSC) and Table B-2 for more information about clock source selection. When the microcontroller is in active background mode, the TPM temporarily suspends all counting until the microcontroller returns to normal user operating mode. During stop mode, all TPM clocks are stopped; therefore, the TPM is effectively disabled until clocks resume. During wait mode, the TPM continues to operate normally. The main 16-bit counter has two counting modes. When center-aligned PWM is selected (CPWMS = 1), the counter operates in up-/down-counting mode. Otherwise, the counter operates as a simple up-counter.
As an up-counter, the main 16-bit counter counts from 0x0000 through its terminal count and then continues with 0x0000. The terminal count is 0xFFFF or a modulus value in TPMxMODH:TPMxMODL. When center-aligned PWM operation is specied, the counter counts upward from 0x0000 through its terminal count and then counts downward to 0x0000 where it returns to up-counting. Both 0x0000 and the terminal count value (value in TPMxMODH:TPMxMODL) are normal length counts (one timer clock period long). An interrupt ag and enable are associated with the main 16-bit counter. The timer overow ag (TOF) is a software-accessible indication that the timer counter has overowed. The enable signal selects between software polling (TOIE = 0) where no hardware interrupt is generated, or interrupt-driven operation (TOIE = 1) where a static hardware interrupt is automatically generated whenever the TOF ag is 1. The conditions that cause TOF to become set depend on the counting mode (up or up/down). In up-counting mode, the main 16-bit counter counts from 0x0000 through 0xFFFF and overows to 0x0000 on the next counting clock. TOF becomes set at the transition from 0xFFFF to 0x0000. When a modulus limit is set, TOF becomes set at the transition from the value set in the modulus register to 0x0000. When the main 16-bit counter is operating in up-/down-counting mode, the TOF ag gets set as the counter changes direction at the transition from the value set in the modulus register and the next lower count value. This corresponds to the end of a PWM period. (The 0x0000 count value corresponds to the center of a period.) Because the HCS08 MCU is an 8-bit architecture, a coherency mechanism is built into the timer counter for read operations. Whenever either byte of the counter is read (TPMxCNTH or TPMxCNTL), both bytes are captured into a buffer so when the other byte is read, the value will represent the other byte of the count at the time the rst byte was read. The counter continues to count normally, but no new value can be read from either byte until both bytes of the old count have been read. The main timer counter can be reset manually at any time by writing any value to either byte of the timer count TPMxCNTH or TPMxCNTL. Resetting the counter in this manner also resets the coherency mechanism in case only one byte of the counter was read before resetting the count.
B.3.2
Channel Mode Selection
Provided CPWMS = 0 (center-aligned PWM operation is not specied), the MSnB and MSnA control bits in the channel n status and control registers determine the basic mode of operation for the corresponding channel. Choices include input capture, output compare, and buffered edge-aligned PWM.
B.3.2.1
Input Capture Mode
With the input capture function, the TPM can capture the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the TPM latches the contents of the TPM counter into the channel value registers (TPMxCnVH:TPMxCnVL). Rising edges, falling edges, or any edge may be chosen as the active edge that triggers an input capture. When either byte of the 16-bit capture register is read, both bytes are latched into a buffer to support coherent 16-bit accesses regardless of order. The coherency sequence can be manually reset by writing to the channel status/control register (TPMxCnSC).
An input capture event sets a ag bit (CHnF) that can optionally generate a CPU interrupt request.
B.3.2.2
Output Compare Mode
With the output compare function, the TPM can generate timed pulses with programmable position, polarity, duration, and frequency. When the counter reaches the value in the channel value registers of an output compare channel, the TPM can set, clear, or toggle the channel pin. In output compare mode, values are transferred to the corresponding timer channel value registers only after both 8-bit bytes of a 16-bit register have been written. This coherency sequence can be manually reset by writing to the channel status/control register (TPMxCnSC). An output compare event sets a ag bit (CHnF) that can optionally generate a CPU interrupt request.
B.3.2.3
Edge-Aligned PWM Mode
This type of PWM output uses the normal up-counting mode of the timer counter (CPWMS = 0) and can be used when other channels in the same TPM are congured for input capture or output compare functions. The period of this PWM signal is determined by the setting in the modulus register (TPMxMODH:TPMxMODL). The duty cycle is determined by the setting in the timer channel value register (TPMxCnVH:TPMxCnVL). The polarity of this PWM signal is determined by the setting in the ELSnA control bit. Duty cycle cases of 0 percent and 100 percent are possible. As Figure B-10 shows, the output compare value in the TPM channel registers determines the pulse width (duty cycle) of the PWM signal. The time between the modulus overow and the output compare is the pulse width. If ELSnA = 0, the counter overow forces the PWM signal high and the output compare forces the PWM signal low. If ELSnA = 1, the counter overow forces the PWM signal low and the output compare forces the PWM signal high.
OVERFLOW PERIOD PULSE WIDTH OVERFLOW OVERFLOW
TPMxC
OUTPUT COMPARE
OUTPUT COMPARE
OUTPUT COMPARE
Figure B-10. PWM Period and Pulse Width (ELSnA = 0)
When the channel value register is set to 0x0000, the duty cycle is 0 percent. By setting the timer channel value register (TPMxCnVH:TPMxCnVL) to a value greater than the modulus setting, 100% duty cycle can be achieved. This implies that the modulus setting must be less than 0xFFFF to get 100% duty cycle. Because the HCS08 is a family of 8-bit MCUs, the settings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to either register, TPMxCnVH or TPMxCnVL, write to buffer registers. In edge-PWM mode, values are transferred to the corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have been written and
the value in the TPMxCNTH:TPMxCNTL counter is 0x0000. (The new duty cycle does not take effect until the next full period.)
B.3.3
Center-Aligned PWM Mode
This type of PWM output uses the up-/down-counting mode of the timer counter (CPWMS = 1). The output compare value in TPMxCnVH:TPMxCnVL determines the pulse width (duty cycle) of the PWM signal and the period is determined by the value in TPMxMODH:TPMxMODL. TPMxMODH:TPMxMODL should be kept in the range of 0x0001 to 0x7FFF because values outside this range can produce ambiguous results. ELSnA will determine the polarity of the CPWM output.
pulse width = 2 x (TPMxCnVH:TPMxCnVL) period = 2 x (TPMxMODH:TPMxMODL); for TPMxMODH:TPMxMODL = 0x00010x7FFF Eqn. 17-1
Eqn. 17-2
If the channel value register TPMxCnVH:TPMxCnVL is zero or negative (bit 15 set), the duty cycle will be 0%. If TPMxCnVH:TPMxCnVL is a positive value (bit 15 clear) and is greater than the (nonzero) modulus setting, the duty cycle will be 100% because the duty cycle compare will never occur. This implies the usable range of periods set by the modulus register is 0x0001 through 0x7FFE (0x7FFF if generation of 100% duty cycle is not necessary). This is not a signicant limitation because the resulting period is much longer than required for normal applications. TPMxMODH:TPMxMODL = 0x0000 is a special case that should not be used with center-aligned PWM mode. When CPWMS = 0, this case corresponds to the counter running free from 0x0000 through 0xFFFF, but when CPWMS = 1 the counter needs a valid match to the modulus register somewhere other than at 0x0000 in order to change directions from up-counting to down-counting. Figure B-11 shows the output compare value in the TPM channel registers (multiplied by 2), which determines the pulse width (duty cycle) of the CPWM signal. If ELSnA = 0, the compare match while counting up forces the CPWM output signal low and a compare match while counting down forces the output high. The counter counts up until it reaches the modulo setting in TPMxMODH:TPMxMODL, then counts down until it reaches zero. This sets the period equal to two times TPMxMODH:TPMxMODL.
COUNT = 0 COUNT = OUTPUT COMPARE (COUNT DOWN) OUTPUT COMPARE (COUNT UP) COUNT =
TPMxMODH:TPMx
TPMxMODH:TPMx
TPM1C
PULSE WIDTH
2x 2x
PERIOD
Figure B-11. CPWM Period and Pulse Width (ELSnA = 0)
Center-aligned PWM outputs typically produce less noise than edge-aligned PWMs because fewer I/O pin transitions are lined up at the same system clock edge. This type of PWM is also required for some types of motor drives.
Because the HCS08 is a family of 8-bit MCUs, the settings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to any of the registers, TPMxMODH, TPMxMODL, TPMxCnVH, and TPMxCnVL, actually write to buffer registers. Values are transferred to the corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have been written and the timer counter overows (reverses direction from up-counting to down-counting at the end of the terminal count in the modulus register). This TPMxCNT overow requirement only applies to PWM channels, not output compares. Optionally, when TPMxCNTH:TPMxCNTL = TPMxMODH:TPMxMODL, the TPM can generate a TOF interrupt at the end of this count. The user can choose to reload any number of the PWM buffers, and they will all update simultaneously at the start of a new period. Writing to TPMxSC cancels any values written to TPMxMODH and/or TPMxMODL and resets the coherency mechanism for the modulo registers. Writing to TPMxCnSC cancels any values written to the channel value registers and resets the coherency mechanism for TPMxCnVH:TPMxCnVL.
B.4
TPM Interrupts
The TPM generates an optional interrupt for the main counter overow and an interrupt for each channel. The meaning of channel interrupts depends on the mode of operation for each channel. If the channel is congured for input capture, the interrupt ag is set each time the selected input capture edge is recognized. If the channel is congured for output compare or PWM modes, the interrupt ag is set each time the main timer counter matches the value in the 16-bit channel value register. See the Resets, Interrupts, and System Conguration chapter for absolute interrupt vector addresses, priority, and local interrupt mask control bits. For each interrupt source in the TPM, a ag bit is set on recognition of the interrupt condition such as timer overow, channel input capture, or output compare events. This ag may be read (polled) by software to verify that the action has occurred, or an associated enable bit (TOIE or CHnIE) can be set to enable hardware interrupt generation. While the interrupt enable bit is set, a static interrupt will be generated whenever the associated interrupt ag equals 1. It is the responsibility of user software to perform a sequence of steps to clear the interrupt ag before returning from the interrupt service routine.
B.4.1
Clearing Timer Interrupt Flags
TPM interrupt ags are cleared by a 2-step process that includes a read of the ag bit while it is set (1) followed by a write of 0 to the bit. If a new event is detected between these two steps, the sequence is reset and the interrupt ag remains set after the second step to avoid the possibility of missing the new event.
B.4.2
Timer Overow Interrupt Description
The conditions that cause TOF to become set depend on the counting mode (up or up/down). In up-counting mode, the 16-bit timer counter counts from 0x0000 through 0xFFFF and overows to 0x0000 on the next counting clock. TOF becomes set at the transition from 0xFFFF to 0x0000. When a modulus limit is set, TOF becomes set at the transition from the value set in the modulus register to 0x0000. When the counter is operating in up-/down-counting mode, the TOF ag gets set as the counter changes direction
at the transition from the value set in the modulus register and the next lower count value. This corresponds to the end of a PWM period. (The 0x0000 count value corresponds to the center of a period.)
B.4.3
Channel Event Interrupt Description
The meaning of channel interrupts depends on the current mode of the channel (input capture, output compare, edge-aligned PWM, or center-aligned PWM). When a channel is congured as an input capture channel, the ELSnB:ELSnA control bits select rising edges, falling edges, any edge, or no edge (off) as the edge that triggers an input capture event. When the selected edge is detected, the interrupt ag is set. The ag is cleared by the 2-step sequence described in Section B.4.1, Clearing Timer Interrupt Flags. When a channel is congured as an output compare channel, the interrupt ag is set each time the main timer counter matches the 16-bit value in the channel value register. The ag is cleared by the 2-step sequence described in Section B.4.1, Clearing Timer Interrupt Flags.
B.4.4
PWM End-of-Duty-Cycle Events
For channels that are congured for PWM operation, there are two possibilities: When the channel is congured for edge-aligned PWM, the channel ag is set when the timer counter matches the channel value register that marks the end of the active duty cycle period. When the channel is congured for center-aligned PWM, the timer count matches the channel value register twice during each PWM cycle. In this CPWM case, the channel ag is set at the start and at the end of the active duty cycle, which are the times when the timer counter matches the channel value register. The ag is cleared by the 2-step sequence described in Section B.4.1, Clearing Timer Interrupt Flags.

C.1 Ordering Information
This section contains ordering information for MC9S08DZ60 Series devices. Example of the device numbering system:
MC 9 S08 DZ Status (MC = Fully Qualified) (S = Auto Qualified) Memory (9 = Flash-based) Core Family Approximate Flash size in KB 60 F1 M XX
Package designator (see Table C-2) Temperature range (C = 40C to 85C) (V = 40C to 105C) (M = 40C to 125C) Mast Set Identifier Only appears for Auto Qualified part numbers beginning with S F1 = 1M74K mask set
C.1.1
MC9S08DZ60 Series Devices

Table C-1. Devices in the MC9S08DZ60 Series
Memory Device Number FLASH MC9S08DZ60 MC9S08DZ48 MC9S08DZ32 MC9S08DZ16
1
Available Packages1 EEPROM 2048 1536 1024 512 48-LQFP, 32-LQFP 64-LQFP, 48-LQFP, 32-LQFP
RAM 4096 3072 2048 1024
60,032 49,152 33,792 16,896
See Table C-2 for package information.
C.2
Mechanical Drawings
The following pages are mechanical drawings for the packages described in the following table:
Table C-2. Package Descriptions

Pin Count 64 48 32 Type Low Quad Flat Package Low Quad Flat Package Low Quad Flat Package Abbreviation LQFP LQFP LQFP Designator LH LF LC Document No. 98ASS23234W 98ASH00962A 98ASH70029A
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MC9S08DZ60 MC9S08DZ48 MC9S08DZ32 MC9S08DZ16

MC9S08DZ60 Rev. 4 6/2008

MC9S08DZ60 Series Features

Clock Source Options

MC9S08DZ60 Data Sheet

MC9S08DZ60 Rev. 4 6/2008

MC9S08DZ60 Series Data Sheet, Rev. 4 6 Freescale Semiconductor

MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 7

Chapter 1 Device Overview

Chapter 2 Pins and Connections

Chapter 3 Modes of Operation

Chapter 5 Resets, Interrupts, and General System Control

Chapter 6 Parallel Input/Output Control

Chapter 7 Central Processor Unit (S08CPUV3)

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1)

Chapter 9 Analog Comparator (S08ACMPV3)

9.2 9.3 9.4

Chapter 10 Analog-to-Digital Converter (S08ADC12V1)

Chapter 11 Inter-Integrated Circuit (S08IICV2)

Chapter 12 Freescale Controller Area Network (S08MSCANV1)

Chapter 13 Serial Peripheral Interface (S08SPIV3)

Chapter 14 Serial Communications Interface (S08SCIV4)

Chapter 15 Real-Time Counter (S08RTCV1)

MC9S08DZ60 Series Data Sheet, Rev. 4 16 Freescale Semiconductor

Title Chapter 16 Timer Pulse-Width Modulator (S08TPMV3)

Chapter 17 Development Support

Appendix A Electrical Characteristics

Appendix B Timer Pulse-Width Modulator (TPMV2)

Appendix C Ordering Information and Mechanical Drawings

MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 19

Chapter 1 Device Overview

Devices in the MC9S08DZ60 Series

MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 21

Chapter 1 Device Overview

Table 1-1. MC9S08DZ60 Series Features by MCU and Pin Count

MC9S08DZ60 60032 4096 2048 64 yes 24 48 yes

MC9S08DZ32 33792 2048 1024 48 yes1 16 32 no 10

MC9S08DZ16 16896 1024 512 48 yes1 16 32 no 10

ACMP2O is not available.

MCU Block Diagram

Figure 1-1 is the MC9S08DZ60 Series system-level block diagram.

MC9S08DZ60 Series Data Sheet, Rev. 4 22 Freescale Semiconductor

Chapter 1 Device Overview

Figure 1-1. MC9S08DZ60 Block Diagram

MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 23

USER RAM MC9S08DZ60 = 4K

6-CHANNEL TIMER/PWM MODULE (TPM1)

TPM1CH5 TPM1CH0 6 TPM1CLK

Chapter 1 Device Overview

Table 1-2 provides the functional version of the on-chip modules.

3M05C and older masks have TPM version 2.

System Clock Distribution

MC9S08DZ60 Series Data Sheet, Rev. 4 24 Freescale Semiconductor

MCGFFCLKVALID MCG MCGFFCLK

MCGOUT MCGLCLK XOSC CPU

Figure 1-2. MC9S08DZ60 System Clock Distribution Diagram

MC9S08DZ60 Series Data Sheet, Rev. 4 Freescale Semiconductor 25

Chapter 1 Device Overview

MC9S08DZ60 Series Data Sheet, Rev. 4 26 Freescale Semiconductor

Chapter 2 Pins and Connections