Course Topics

Module# Topics
Module-1 Basic structures of Computers: Computer Architecture vs. Computer Organization,
Functional units, Operational concepts, Registers, Bus Structure, Performance
Consideration, SPEC rating.
Module-2 Memory location and addresses, Big-endian and Little-endian representation, Instruction
format, Instruction set Architecture, RISC vs. CISC, Addressing modes, Instruction
Sequencing, Subroutines.
Module-3 Binary Arithmetic: Addition and subtraction of signed numbers, Design of fast adders,
Multiplication of positive numbers, Signed operand multiplication, Fast multiplication,
Integer division, Representation of floating point numbers.
Module-4 Memory System: Basic Concepts, Speed, Size and cost, Cache memory concepts, Cache
memory mapping techniques, Performance consideration; Virtual memory concepts,
Translation look-aside buffer, Replacement techniques, Secondary Storage.
Module-5 Basic Processing Units: Fundamental concepts, Execution cycle, Single-Bus and Multi-Bus
Organization, Execution of complete instruction, Hardwired control, Micro programmed
control, Accessing I/O devices.
Memory location and addresses
(Chapter 2)
• Memory location and addresses
• Memory consists of many millions of storage cells (flip-flops).
• Each cell can store a bit of information i.e. 0 or 1 (Figure 2.1).
• Data is usually accessed in n-bit groups.
• Each group of n bits is referred to as a word of information, and
n is called the word length.
• The word length can vary from 8 to 64 bits.
• A unit of 8 bits is called a byte.
• Accessing the memory to store or retrieve a single item of
information (word/byte) requires distinct addresses for each item
location.
 Memory Words and Locations
• If the address is of k bits, then 2k = no. of addressable locations.
• So 2k addresses constitute the address-space of the computer.
• For example, a 24-bit address generates an address-space of 224 locations (16 MB) (1M=220).
• It is customary to use numbers from 0 through 2k-1 as the addresses of successive-locations in the memory
32-bit word length example
Memory Words and Locations
BYTE-ADDRESSABILITY
• It is impractical to assign distinct addresses to
individual bit locations in the memory.
• The most practical assignment is to have successive
addresses refer to successive byte locations in the
memory – byte-addressable memory.
• In byte-addressable memory, successive addresses
refer to successive byte locations in the memory.
• Byte locations have addresses 0, 1, 2. . . . .
• If the word-length is 32 bits, successive words are
located at addresses 0, 4, 8. . with each word having
4 bytes.
BIG-ENDIAN & LITTLE-ENDIAN ASSIGNMENTS

• There are two ways in which byte-addresses are arranged

1) Big-Endian: Lower byte-addresses are used for the more
significant bytes of the word.
2) Little-Endian: Lower byte-addresses are used for the less
significant bytes of the word
• In both cases, byte-addresses 0, 4, 8. . . . . are taken as the
addresses of successive words in the memory.
WORD ALIGNMENT
• Words are said to be Aligned in memory if they begin at a byte-
address that is a multiple of the number of bytes in a word.
• For example,
 If the word length is 16(2 bytes), aligned words begin at
byte-addresses 0, 2, 4 . . . . .
 If the word length is 32(4 bytes), aligned words begin at
byte-addresses 0, 4, 8, 16 . . . . .
• Words are said to have Unaligned Addresses, if they begin at
an arbitrary byte-address.
ACCESSING NUMBERS, CHARACTERS & CHARACTERS
STRINGS
• A number usually occupies one word.
• It can be accessed in the memory by specifying its word address.
• Similarly, individual characters can be accessed by their byte-
address.

There are two ways to indicate the length of the string:

1) A special control character with the meaning "end of string"
can be used as the last character in the string.
2) A separate memory word location or register can contain a
number indicating the length of the string in bytes.
MEMORY OPERATIONS
• Two memory operations are:
1) Load (Read/Fetch) &
2) Store (Write).

• The Load operation transfers a copy of the contents of a specific memory-location to

the processor.

• The memory contents remain unchanged.

• Steps for Load operation:

1) Processor sends the address of the desired location to the memory.
2) Processor issues “read” signal to memory to fetch the data.
3) Memory reads the data stored at that address.
4) Memory sends the read data to the processor.
Store operation
• The Store operation transfers the information from the register to the
specified memory location.
• This will destroy the original contents of that memory-location.
Steps for Store operation are:
1) Processor sends the address of the memory-location where it
wants to store data.
2) Processor issues “write” signal to memory to store the data.
3) Content of register (MDR) is written into the specified memory
location.
Instruction Set Architecture
• An Instruction Set Architecture (ISA) is part of the abstract
model of a computer that defines how the CPU is controlled
by the software.
• The ISA acts as an interface between the hardware and the
software, specifying both what the processor is capable of
doing as well as how it gets done.
• The ISA defines the supported data types, the registers, how
the hardware manages main memory which instructions a
microprocessor can execute, addressing modes etc.
Instructions
• A computer must have instructions capable of performing 4 types of
operations:
1) Data transfers between the memory and the registers (MOV,
PUSH, POP, XCHG).
2) Arithmetic and logic operations on data (ADD, SUB, MUL, DIV,
AND, OR, NOT).
3) Program sequencing and control (CALL,EOT, LOOP, INT).
4) I/0 transfers (IN, OUT).
Register Transfer Notation (RTN)
• Identify a location by a symbolic name standing for its hardware
binary address (LOC, R0,…)
• Contents of a location are denoted by placing square brackets around
the name of the location (R1←[LOC], R3 ←[R1]+[R2])
• The possible locations in which transfer of information occurs are:
1) Memory-location
2) Processor register
3) Registers in I/O device.
Register Transfer Notation (RTN)

Location Hardware Binary Example Description

Address
Memory LOC, PLACE, NUM R1 ← [LOC] Contents of memory location LOC
are transferred in to register R1.
Processor R0, R1, R2 R3 ← [R1] + Add the contents of register R1 &
Register [R2] R2 and places their sum into R3.
I/O Registers DATAIN, DATAOUT R1 ← Contents of memory I/O register
[DATAIN] DATAIN are transferred in to
register R1.
Assembly Language Notation
• To represent machine instructions and programs, assembly language
format is used

Assembly Lang Description

Format
Load R2, LOC the contents of memory location LOC are
transferred into processor register R2
Add R4, R2, R3 adds the contents of registers R2 and R3,
and places their sum into register R4
 Basic Instruction Formats

Instruction Syntax Example Description

Type
Three Opcode Destination,Source1,Source2 ADD C,A,B Add the contents of memory-locations A
Address & B. Then, place the result into location
C.
Two Address Opcode Destination, Source ADD A,B Add the contents of memory-locations A
& B. Then, place the result into location
A, replacing the original contents of this
location.
One Address Opcode Source/Destination ADD B Add contents of memory- location B to
contents of accumulator register & place
sum back into accumulator.
Zero Address Opcode [no Source / Destination] ADD Add top two elements of the STACK &
place sum back at the top of the STACK
Types of Computer Organization
• Two types : RISC and CISC
• RISC (Reduced Instruction Set Computers)
• Each instruction occupies exactly one word in memory.
• All operands needed to execute a given operation specified by an instruction are
already in processor registers.
• This approach is conducive to the “pipelined” execution of instruction.
• Memory operands are accessed only using Load and Store instructions.
• The restriction that each instruction must fit into a single word reduces the
complexity.
• CISC (Complex Instruction Set Computers)
• Instructions may span more than one word of memory.
• It may specify more complicated operations.
• Difficult to implement “pipelined” execution of instruction.
Types of CPU Organization
• Single Accumulator
• Result usually goes to the Accumulator
• Accumulator has to be saved to memory quite often
• General Register
• Registers hold operands thus reduce memory traffic
• Register bookkeeping
• Stack
• Operands and result are always in the stack
CPU Organization type mapped to Instruction types
Instruction types CPU Organization type

Three-Address Instructions General Register

Two-Address Instructions General Register

One-Address Instructions Single Accumulator

Zero-Address Instructions Stack

Instruction Formats
• Three-Address Instructions
• ADD R1, R2, R3 R1 ← R2 + R3
• Two-Address Instructions
• ADD R1, R2 R1 ← R1 + R2
• One-Address Instructions
• ADD M AC ← AC + M[AR]
• Zero-Address Instructions
• ADD TOS ← TOS + (TOS – 1)
• RISC Instructions
• Lots of registers. Memory is restricted to Load & Store

Opcode Operand(s) or Address(es)

 Instruction Formats Example -1.
Example: Evaluate (A+B)  (C+D)
• Three-Address
1. ADD R1, A, B; R1 ← M[A] + M[B]
2. ADD R2, C, D; R2 ← M[C] + M[D]
3. MUL X, R1, R2; M[X] ← R1  R2
 Instruction Formats Example -2
Example: Evaluate (A+B)  (C+D)
• Two-Address
1. MOV R1, A; R1 ← M[A]
2. ADD R1, B; R1 ← R1 + M[B]
3. MOV R2, C; R2 ← M[C]
4. ADD R2, D; R2 ← R2 + M[D]
5. MUL R1, R2; R1 ← R1  R2
6. MOV X, R1; M[X] ← R1
 Instruction Formats Example -3
Example: Evaluate (A+B)  (C+D)
• One-Address
1. LOAD A; AC ← M[A]
2. ADD B; AC ← AC + M[B]
3. STORE T; M[T] ← AC
4. LOAD C; AC ← M[C]
5. ADD D; AC ← AC + M[D]
6. MUL T; AC ← AC  M[T]
7. STORE X; M[X] ← AC
 Instruction Formats Example -4
Example: Evaluate (A+B)  (C+D)
• Zero-Address
1. PUSH A; TOS ← A
2. PUSH B; TOS ← B
3. ADD; TOS ← (A + B)
4. PUSH C; TOS ← C
5. PUSH D; TOS ← D
6. ADD; TOS ← (C + D)
7. MUL; TOS ← (C+D)(A+B)
8. POP X; M[X] ← TOS
Instruction Formats Example -5
Example: Evaluate (A+B)  (C+D)
• RISC
1. LOAD R1, A ; R1 ← M[A]
2. LOAD R2, B ; R2 ← M[B]
3. LOAD R3, C ; R3 ← M[C]
4. LOAD R4, D ; R4 ← M[D]
5. ADD R1, R1, R2 ; R1 ← R1 + R2
6. ADD R3, R3, R4 ; R3 ← R3 + R4
7. MUL R1, R1, R3 ; R1 ← R1  R3
8. STORE X, R1 ; M[X] ← R1

Note: Add is a three-operand, or a three-address, instruction of the form

Add destination, source1, source2
Advantage of Using Registers in RISC
• Registers are faster
• Shorter instructions
• The number of registers is smaller (e.g. 32 registers need 5 bits)
• Potential speedup
• Minimize the frequency with which data is moved back and forth
between the memory and processor registers.
Phases in instruction execution

• Different architectures uses different number (3, 4 or 5) of phases for

instruction execution.
• In a RISC machine, an instruction execution uses the following five
phases in general
• IF = Instruction Fetch,
• ID = Instruction Decode,
• EX = Execute,
• MEM = Memory access,
• WB = Register write back.

IF ID EX MEM WB
Instruction Execution & Straight Line Sequencing
• The program is executed as follows:
1) Initially, the address of the first instruction is loaded into PC .
2) Then, the processor control circuits use the information in the
PC to fetch and execute.
3) During the execution of each instruction, PC is incremented by 4
(assuming word size = 4 bytes) to point to next instruction.

• Instructions, one at a time, in the order of increasing addresses. This is

called Straight-Line sequencing
Straight Line Sequencing Example
Program (straight line sequence) Explanation

• Consider the program for adding a list of n numbers.

• The Address of the memory-locations containing the n

numbers are symbolically given as NUM1,NUM2…..NUMn.

• Separate Add instruction is used to add each number

to the contents of register R2.

• After all the numbers have been added, the result is

placed in memory-location SUM.
 Branching
• Consider the task of adding a list of “n” numbers.

• Number of entries in the list “n” is stored in

memory-location N.

• Register R2 is used as a counter to determine the

number of times the loop is executed.

• Content-location N is loaded into register R2 at

the beginning of the program.

• The Loop is a straight line sequence of

instructions executed as many times as needed.
The loop starts at location LOOP and ends at the
instruction ‘Branch_if_[R2]>0 LOOP’.
• During each pass,

→ address of the next list entry is determined and

→ that entry is fetched and added to R3.

• The instruction Subtract R2, R2, #1 reduces the contents of

R2 by 1 each time through the loop.

• Then Branch Instruction loads a new value into the program

counter. As a result, the processor fetches and executes the
instruction at this new address called the LOOP.

• A Conditional Branch Instruction causes a branch only if a

specified condition is satisfied.

• If the condition is not satisfied, the PC is incremented in the

normal way, and the next instruction in sequential address
order is fetched and executed.
ADDRESSING MODES
• The different ways for specifying the locations of operands in an
instruction are known as addressing modes.
IMPLEMENTATION OF VARIABLE AND
CONSTANTS

• Variable is represented by allocating a memory-location to hold its

value.
• Thus, the value can be changed as needed using appropriate
instructions.
• There are 2 accessing modes to access the variables:
1) Register Mode
2) Absolute Mode
Register Mode
• The operand is the contents of a register.
• The name (or address) of the register is given in the instruction.
• Registers are used as temporary storage locations where the data in a
register are accessed.
For example,
Move R2, R1 ;
This instruction copies content of register R1 into register R2.
Absolute (Direct) Mode
• The operand is in a memory-location.
• The address of memory-location is given explicitly in the instruction.
• The absolute mode can represent global variables in the program.
For example, Move R2, LOC;
The instruction copies content of memory-location LOC into register R2.
Immediate Mode
The operand is given explicitly in the instruction.
For example, the instruction
Move R0, #200 ; places the value 200 in register R0.
• The immediate mode is only used to specify the value of a source-
operand (can’t be used as destination in an operation).

Indirection and Pointers

Instruction does not give the operand or its address explicitly.
Instead, the instruction provides information from which the new
address of the operand can be determined.
This address is called Effective Address (EA) of the operand.
Indirect Mode
• The effective address of the
operand is the contents of a
register that is specified in the
instruction.
• The register (or memory-location)
that contains the address of an
operand is called a Pointer.
• Example: Load R2, (R5)

•To execute the Load instruction, the processor uses the value B, which is in
register R5, as the effective address of the operand.
•It requests a Read operation to fetch the contents of location B in the
memory.
•The value from the memory is the desired operand, which the processor
loads into register R2.
INDEXING AND ARRAYS
Index mode
•The effective address of the operand is generated by adding a constant
value to the contents of a register.
•We will refer to the register used in this mode as the index register.
•We indicate the Index mode symbolically as
X(Ri)
where X denotes a constant signed integer value contained in the
instruction and Ri is the name of the register involved.
•The effective address of the operand is given by
EA = X + [Ri]
Relative Mode
• This is similar to index-mode with one difference:
• The effective-address is determined using the PC in place of the general
purpose register Ri.
• The operation is indicated as X(PC).
• X(PC) denotes an effective-address of the operand which is X locations
above or below the current contents of PC.
• Since the addressed-location is identified "relative" to the PC, the name
Relative mode is associated with this type of addressing.
• This mode is used commonly in conditional branch instructions.
• An instruction such as
Branch > 0 LOOP ;
Causes program execution to go to the branch target location
identified by name LOOP if branch condition is satisfied
Auto Increment Mode
• Effective-address of operand is contents of a register
specified in the instruction
• Accessing the operand, the contents of this register are
automatically incremented to point to the next item in a list.
• Implicitly, the increment amount is 1/2/4 depending on the
size of operand.
• This mode is denoted as (Ri)+ ; where Ri = pointer-register.
Add R1, (R2)+ // OR R1 = R1 +M[R2]
R2 = R2 + d
Useful for stepping through arrays in a loop. R2 – start of array d – size of an element
Auto Decrement Mode
• The contents of a register specified in the instruction are first
automatically decremented and are then used as the effective-
address of the operand.
• This mode is denoted as -(Ri) ;where Ri = pointer-register.
• Auto increment and decrement modes can be used together to
implement an important data structure called a stack.
Add R1,-(R2)
//OR R2 = R2-d
R1 = R1 + M[R2]
Question 1
An instruction is stored at location 300 with its address field at location 301. The
address field has the value 400. A processor register R1 contains the number
200.Evaluate the effective address if the addressing mode of the instruction is

(i) Direct addressing mode

(iii) Relative addressing mode

(iv)Register indirect addressing mode

(v) Index addressing mode with R1 as the index register
Question 2
• What do mean by addressing mode? Why it is used?
Registers R1 and R2 of a computer contains the decimal
values 1200 and 4600. What is the effective address of
the memory operand in each of the following
instruction.